Semiconductor device provided with a reference voltage circuit

Abstract

The present application suppresses threshold voltage shift in a high-temperature storage test of a semiconductor device provided with a reference voltage circuit using an enhancement-mode transistor having a gate electrode of P-type polysilicon. As a semiconductor device provided with a reference voltage circuit, it has an enhancement-mode transistor having a first gate electrode of P-type polysilicon and a depletion-mode transistor having a second gate electrode of N-type polysilicon, the enhancement-mode transistor has a non-water-permeable film partially provided so as to cover the first gate electrode via an interlayer insulating film on the upper portion of the first gate electrode, and a nitride film provided so as to cover the periphery of the non-water-permeable film, the nitride film having a larger opening than the first gate electrode and a smaller opening than the non-water-permeable film, and the depletion-mode transistor has a nitride film directly provided on the interlayer insulating film on the upper portion of the second gate electrode, the nitride film covering the depletion-mode transistor without a gap.

Description

Technical Field

[0001] The present invention relates to a semiconductor device having a reference voltage circuit having an N-type MOS transistor having a P-type gate electrode. Background Technology

[0002] It is possible to use two N-type MOS transistors (enhancement-mode and depletion-mode) to construct a reference voltage circuit that outputs a certain voltage in response to changes in the power supply voltage.

[0003] In reference voltage circuits, it is generally required to suppress temperature-induced fluctuations in the output voltage. Therefore, as shown in Patent Document 1, a method exists where, in the two N-type MOS transistors (enhancement-mode and depletion-mode) constituting the reference voltage circuit (Vref circuit), the impurity concentration in the channel region is made the same. Simultaneously, regarding the conductivity type of the polysilicon constituting the gate electrode, the previously identical N-type polysilicon is used, except that the gate electrode of the enhancement-mode transistor is made of P-type polysilicon. Utilizing the difference in work function resulting from the difference in the conductivity type of the gate electrode, a difference is set between the threshold voltage (Vth) of the enhancement-mode MOS transistor with P-type conductivity polysilicon as its gate electrode and the depletion-mode MOS transistor with N-type conductivity polysilicon as its gate electrode, thereby generating a reference voltage.

[0004] In this case, the impurity concentration in the channel region is the same, so the effect of temperature change on the threshold voltage of the two transistors also becomes the same, which can suppress the variation of the reference voltage obtained from the difference in the threshold voltage of the two transistors.

[0005] Hereinafter, a gate electrode made of polysilicon with P-type conductivity will be referred to as a P-type gate electrode, a gate electrode made of polysilicon with N-type conductivity will be referred to as an N-type gate electrode, a MOS transistor having polysilicon containing P-type conductivity as its gate electrode will be referred to as a P-type gate electrode MOS transistor, and a MOS transistor having polysilicon containing N-type conductivity as its gate electrode will be referred to as an N-type gate electrode MOS transistor. Furthermore, a Vref circuit constructed using P-type and N-type gate electrode MOS transistors will be referred to as a Vref circuit utilizing dissimilar gates.

[0006] Prior technology literature [Patent Documents] [Patent Document 1] Japanese Patent Application Publication No. 2008-293409. Summary of the Invention

[0007] [The problem the invention aims to solve] In one of the accelerated tests conducted to evaluate the reliability of Vref circuits utilizing dissimilar gates—namely, the high-temperature placement test—where environmental conditions more stringent than actual use are set, it was observed that P-gate MOS transistors sometimes exhibit threshold voltage shifts. This shift in the reference voltage causes a change in IC characteristics during long-term reliability testing. The effect of hydrogen can be cited as one cause of threshold voltage shift. However, although this threshold voltage shift is minute, ranging from a few millivolts, it is not negligible in applications requiring high stability of the reference voltage derived from the threshold voltage.

[0008] Therefore, the present invention aims to provide a semiconductor device having a reference voltage circuit that utilizes a transistor structure capable of suppressing threshold voltage shifts generated in a P-type gate electrode MOS transistor during high-temperature placement tests.

[0009] [Solution to the problem] To address the aforementioned issues, the semiconductor device with a reference voltage circuit according to embodiments of the present invention is configured as follows: The semiconductor device with a reference voltage circuit includes an enhancement-mode MOS transistor having a first gate electrode of polysilicon with a P-type conductivity type and a depletion-mode MOS transistor having a second gate electrode of polysilicon with an N-type conductivity type. The enhancement-mode MOS transistor has a non-permeable film partially disposed by covering the first gate electrode via an interlayer insulating film disposed above the first gate electrode, and a nitride film disposed to cover the periphery of the non-permeable film, having an opening larger than the first gate electrode and smaller than the non-permeable film when viewed from above. The depletion-mode MOS transistor has a nitride film directly disposed on the interlayer insulating film disposed above the second gate electrode, covering the depletion-mode MOS transistor without gaps when viewed from above.

[0010] [The effects of the invention] Regarding the semiconductor device with a reference voltage circuit according to the present invention, in a P-type gate electrode MOS transistor, the nitride film, which serves as a protective film and is the primary cause of hydrogen diffusion (a major cause of threshold voltage shift during high-temperature storage tests), is removed from the top of the P-type gate electrode, thereby suppressing hydrogen diffusion and inhibiting interface state changes caused by high-temperature storage. Even without process modifications, IC characteristic variations can be easily suppressed. The area where the nitride film is removed is localized, and the area below the removed opening is a non-permeable membrane, thus effectively suppressing moisture intrusion and eliminating concerns about decreased reliability. Attached Figure Description

[0011] Figure 1 This is a top view of a semiconductor device with a reference voltage circuit according to the first embodiment of the present invention.

[0012] Figure 2 It is along Figure 1 A schematic diagram of the cross section along section line A.

[0013] Figure 3 It is along Figure 1 A schematic diagram of the cross section along section line B.

[0014] Figure 4 This is an equivalent circuit diagram of the reference voltage circuit according to the first embodiment.

[0015] Figure 5 This is a comparison chart of the offset during the high-temperature placement test.

[0016] Figure 6 This is a schematic cross-sectional view of a semiconductor device with a reference voltage circuit according to the second embodiment of the present invention.

[0017] Figure 7 This is a schematic cross-sectional view of a semiconductor device with a reference voltage circuit according to the third embodiment of the present invention. Detailed Implementation

[0018] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0019] Figure 1 This is a top view of a semiconductor device having the reference voltage circuit according to the first embodiment of the present invention. Figure 2 It is along Figure 1 A cross-sectional view of section line A. Figure 3 It is along Figure 1 A schematic diagram of the cross section along section line B.

[0020] like Figure 1 As shown, the semiconductor device 100 with a reference voltage circuit includes an enhancement-type MOS transistor 1 and a depletion-type MOS transistor 2. Both the enhancement-type MOS transistor 1 and the depletion-type MOS transistor 2 are N-type, sometimes referred to as N-channel.

[0021] like Figure 2 and Figure 3As shown, an enhancement-mode MOS transistor 1 is disposed on the surface of a P-type well 8 disposed on an N-type substrate 7, with a source 9A and a drain 9B, both of which are N-type high-concentration layers, sandwiched between a P-type gate electrode 3 disposed via a gate oxide film. An intermediate insulating film 10 is disposed covering the P-type gate electrode 3, and a first metal wiring 11 is disposed on the intermediate insulating film 10. An interlayer insulating film 12 is disposed covering the first metal wiring 11, and a water-impermeable film 5 is partially disposed thereon covering the P-type gate electrode 3. The water-impermeable film 5 is covered from the periphery of the opening 6 to the outside by a final protective film 13 disposed on the interlayer insulating film 12, but the opening 6 disposed on the upper surface of the water-impermeable film 5 is not covered by the final protective film 13. The final protective film 13 has an opening 6 in the water-impermeable film 5, exposing the surface of the water-impermeable film 5.

[0022] As from Figure 1 As can be seen from a top view, the impermeable membrane 5 covers the entire surface of the P-type gate electrode 3, and is therefore larger than the P-type gate electrode 3. In addition, the opening 6 is made larger than the P-type gate electrode 3 so as to include the entire surface of the P-type gate electrode 3 on its inner side, but since the opening 6 is located inside the impermeable membrane 5, it is smaller than the impermeable membrane 5.

[0023] like Figure 2 As shown, the depletion-type MOS transistor 2 is disposed on the surface of another P-type well 8, different from the P-type well 8 on which the enhancement-type MOS transistor 1 is disposed, and is disposed on an N-type substrate 7. A source 9C and a drain 9D, both having high-concentration N-type layers, are sandwiched between an N-type gate electrode 4 disposed via a gate oxide film. An intermediate insulating film 10 is disposed covering the N-type gate electrode 4, and a first metal wiring 11 is disposed on the intermediate insulating film 10. An interlayer insulating film 12 is disposed covering the first metal wiring 11, and a final protective film 13 disposed on the interlayer insulating film 12 covers the entire surface. The final protective film 13 covering the depletion-type MOS transistor 2 does not have an opening 6, thus the depletion-type MOS transistor 2 is completely covered by the final protective film 13 without gaps.

[0024] like Figure 1 As shown, the drain 9B of the enhancement-type MOS transistor 1 is connected to the source 9C of the depletion-type MOS transistor 2 via the first metal wiring 11. The P-type gate electrode 3 of the enhancement-type MOS transistor 1 and the N-type gate electrode 4 of the depletion-type MOS transistor 2 are also connected via the same metal wiring to achieve the same potential. Typically, the source 9A of the enhancement-type MOS transistor 1 is connected to a wiring at ground potential, and the drain 9D of the depletion-type MOS transistor 2 is connected to a wiring at power supply potential via the first metal wiring 11.

[0025] Figure 4 It means to use Figures 1 to 3This is an equivalent circuit diagram of the reference voltage circuit portion of a semiconductor device with a reference voltage circuit, as illustrated. It includes an enhancement-mode MOS transistor 1 and a depletion-mode MOS transistor 2 connected in series, with the source of the enhancement-mode MOS transistor 1 connected to ground potential V. SS The drain of depletion-type MOS transistor 2 is connected to the power supply potential V. DD The reference voltage V is output from the connection point of enhancement-mode MOS transistor 1 and depletion-mode MOS transistor 2. ref .

[0026] Next, a method for manufacturing a semiconductor device having the aforementioned reference voltage circuit will be described. The enhancement-mode MOS transistor and depletion-mode MOS transistor constituting the reference voltage circuit are respectively disposed near the surface of an N-type silicon substrate or individually formed separately in an N-type well. After forming the element separation region using LOCOS or STI, a gate oxide film is formed, and a polysilicon film serving as the gate electrode is deposited. After the polysilicon film is deposited to a thickness of 100 nm-400 nm, impurity ion implantation is performed in the following manner: for example, BF2 is ion implanted into the gate electrode region of the enhancement-mode MOS transistor to form P-type polysilicon, and phosphorus is ion implanted into the gate electrode region of the depletion-mode MOS transistor to form N-type polysilicon. Thereafter, the polysilicon is patterned, processed, and a gate electrode is formed.

[0027] Next, after forming an intermediate insulating film covering the gate electrode and forming contact holes, a metal film is formed to become the first metal wiring layer. Afterward, an interlayer insulating film and the required number of multilayer wiring layers are formed.

[0028] A non-permeable layer is formed on the topmost layer of the multilayer wiring. In its configuration, it is laid out and patterned in a way that covers the gate electrode in at least the enhancement-type MOS transistor constituting the reference voltage circuit, thus becoming a non-permeable film. Not only can a non-permeable film be configured on the gate electrode of the enhancement-type MOS transistor, but it can also be configured on the gate electrode of the depletion-type MOS transistor.

[0029] As a waterproof layer, it can be a metal wiring layer that serves as the top layer. Alternatively, it can be made without metal, using amorphous silicon formed by sputtering.

[0030] After the impermeable layer is patterned, a final protective film is formed. The final protective film can be a single-layer plasma nitride film or a two-layer structure consisting of an oxide film and a plasma nitride film. Since the hydrogen contained in the plasma nitride film is released and trapped as an interface state during the high-temperature placement test, the portion of the final protective film on the impermeable membrane disposed on the gate electrode of the aforementioned reference voltage circuit is etched and removed. This process prevents hydrogen from diffusing from the plasma nitride film located directly above the P-type gate electrode, thus suppressing the total amount of diffusing hydrogen.

[0031] Figure 5 It will be by Figures 1 to 4 The graph shows a comparison between the offset exhibited by the semiconductor device with a reference voltage circuit in a high-temperature placement test and the offset in a conventional semiconductor device with a reference voltage circuit. It can be seen that if the offset in the conventional structure is set to 1, the offset in the structure according to the first embodiment is reduced to 0.6. From this comparison result, it can be seen that by disposing a non-water-permeable film covering the P-type gate electrode 3 above the enhancement-type MOS transistor 1, and providing an opening formed by removing the final protective film disposed thereon, i.e., the plasma nitriding film, the threshold voltage offset in the high-temperature placement test can be suppressed.

[0032] Figure 6 This is a cross-sectional schematic diagram of a semiconductor device with a reference voltage circuit according to the second embodiment of the present invention. The difference from the first embodiment is the presence of a polyimide film 15 covering the final protective film 13 disposed above the reference voltage circuit. The non-permeable film 5 is impermeable to water, but there is a possibility that water may penetrate from the interface between the non-permeable film 5 and the final protective film 13 around the periphery covered by the final protective film 13. Water, unlike hydrogen, causes corrosion, so preventing water intrusion is also important in semiconductor devices. Therefore, a device is configured such that a polyimide film 15, disposed on the final protective film 13, seamlessly covers the opening 6 located on the surface of the non-permeable film 5, thereby suppressing water intrusion from the interface between the non-permeable film 5 and the final protective film 13. Since polyimide exhibits hydrophobicity, it has the effect of delaying water intrusion.

[0033] Figure 7This is a cross-sectional schematic diagram of a semiconductor device equipped with a reference voltage circuit according to the third embodiment of the present invention. The difference from the first embodiment is that a film of corrosion-resistant oxide is present on the surface of the impermeable film 5, which forms the bottom of the opening 6. In the first embodiment, examples of the impermeable film 5 include those using a metal wiring layer or amorphous silicon deposited by sputtering. When using a metal wiring layer, the opening makes corrosion due to moisture or other factors possible in the impermeable film 5. Therefore, by providing a film 16 of corrosion-resistant oxide that at least seamlessly covers the surface of the impermeable film 5, which forms the bottom of the opening, the impermeable film 5 is prevented from corroding, thereby improving the reliability of the semiconductor device against corrosion.

[0034] Examples of corrosion-resistant oxide films 16 include alumina (alumina: Al2O3) and ceramics, which are metal oxides. In the case of an impermeable membrane 5 with aluminum as the main component, alumina can be formed by oxidation in an oxygen atmosphere or anodic oxidation. Ceramic films can be formed by coating to create a thin film with a ceramic component as the main body. These oxides have high corrosion resistance and can be formed at relatively low temperatures, thus enabling their use in semiconductor devices.

[0035] Furthermore, the opening 6 must be configured to be at least longer than the width of the first channel in the width direction and cover the first channel region. However, the opening 6 may also be shorter than the length of the first channel in the length direction and be located inside the first channel region.

[0036] The main cause is believed to be the change in interface states due to high-temperature storage, originating from the desorption of hydrogen from the oxidation process located in the region with low bonding between the gate insulating film and the semiconductor substrate. This low-bonding region is particularly concentrated at the boundary between the device separation region and the channel region. Therefore, the opening 6 sufficiently covers this region, thereby suppressing hydrogen intrusion from the nitride film acting as a protective layer and inhibiting the binding and desorption of hydrogen present in the low-bonding region.

[0037] On the other hand, dangling bonds in silicon, generated by processes such as plasma etching during gate electrode formation, tend to be non-uniform at the boundary between the channel region and the source / drain region. These dangling bonds are not terminated by hydrogen but act as fixed charges, tending to increase the threshold voltage. Therefore, actively promoting hydrogen intrusion from the nitride film, which acts as a protective film, suppresses the rise or deviation of the threshold voltage, thereby stabilizing the reference voltage output by the reference voltage circuit. Therefore, the opening 6 can also be configured to be shorter than the length of the first channel in the first channel length direction and positioned inside the first channel region to promote hydrogen intrusion.

[0038] [Symbol Explanation] 1. N-channel enhancement-mode transistor 2. N-channel depletion-type transistor 3. Gate electrode made of P-type polycrystalline silicon (P-type gate electrode) 4. Gate electrode made of N-type polysilicon (N-type gate electrode) 5. Non-permeable membrane 6. Located at the opening of the final protective film. 7. N-type substrate 8. P-type trap 9A, 9C. N-type high-concentration layer (source electrode) 9B, 9D. N-type high-concentration layer (drain electrode) 10. Intermediate insulating film 11. First metal wiring 12. Interlayer insulating film 13. Final protective film 14. Component separation insulating film 15. Polyimide film 16. Non-permeable membrane.

Claims

1. A semiconductor device having a reference voltage circuit, wherein the reference voltage circuit comprises an enhancement-mode MOS transistor and a depletion-mode MOS transistor. The enhancement-mode MOS transistor has: a first channel region having a first channel length direction and a first channel width direction; and polysilicon covering the first channel region as a P-type gate electrode and having a P-type conductivity type. The depletion-type MOS transistor comprises: a second channel region having a second channel length direction and a second channel width direction; and polysilicon covering the second channel region as an N-type gate electrode and having an N-type conductivity type, characterized in that... The enhanced MOS transistor has: A non-permeable membrane, partially disposed and covering the P-type gate electrode via an interlayer insulating film disposed on top of the P-type gate electrode; and a nitride membrane, which, when viewed from above, includes the P-type gate electrode and has an opening configured to be smaller than that of the non-permeable membrane, disposed in a manner to cover the periphery of the non-permeable membrane. The depletion-type MOS transistor has: A nitride film that is directly disposed on the interlayer insulating film disposed on the top of the N-type gate electrode and covers the depletion-type MOS transistor without gaps when viewed from above.

2. The semiconductor device with a reference voltage circuit according to claim 1, characterized in that, The opening is longer than the width of the first channel in the width direction and shorter than the length of the first channel in the length direction.

3. A semiconductor device having a reference voltage circuit, wherein the reference voltage circuit comprises an enhancement-mode MOS transistor and a depletion-mode MOS transistor. The enhancement-mode MOS transistor uses polycrystalline silicon with P-type conductivity as its P-type gate electrode. The depletion-type MOS transistor is characterized by being situated in polycrystalline silicon with N-type conductivity, serving as an N-type gate electrode. The enhanced MOS transistor has: A non-permeable membrane is provided partially by covering the P-type gate electrode with an interlayer insulating film disposed on top of the P-type gate electrode; and a nitride membrane is provided to cover the periphery of the non-permeable membrane, having an opening that is larger than the P-type gate electrode and smaller than the non-permeable membrane when viewed from above. The depletion-type MOS transistor has: A nitride film that is directly disposed on the interlayer insulating film disposed on the top of the N-type gate electrode and covers the depletion-type MOS transistor without gaps when viewed from above.

4. The semiconductor device having a reference voltage circuit according to any one of claims 1 to 3, characterized in that, The impermeable membrane is the uppermost wiring layer.

5. The semiconductor device comprising a reference voltage circuit according to any one of claims 1 to 3, characterized in that, The impermeable membrane is amorphous silicon.

6. The semiconductor device comprising a reference voltage circuit according to any one of claims 1 to 3, characterized in that, It also has a polyimide film covering the final protective film, the polyimide film seamlessly covering the openings disposed on the surface of the impermeable membrane of the final protective film.

7. The semiconductor device comprising a reference voltage circuit according to any one of claims 1 to 3, characterized in that, It also has a membrane of corrosion-resistant oxides that covers the surface of the impermeable membrane without gaps.

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