Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the forming method comprising: providing a substrate, the substrate comprising an initial substrate, the substrate comprising a first region and a second region; etching the initial substrate of the first region to form a first fin; forming a first protective layer conformally covering the first fin; after forming the first protective layer, etching the initial substrate of the second region to form a second fin; and forming a second protective layer conformally covering the second fin. Embodiments of the present application take a direction perpendicular to the extension direction of the second fin as a lateral direction, so that the lateral dimension of the second fin is not easily reduced, and a gate structure is subsequently formed across the second fin. The second fin covered by the gate structure serves as a channel region. When the semiconductor structure is in operation, the migration rate of carriers in the channel is easily up to the design requirement. In addition, the second fin is not easily dislocated, and the formation quality of the second fin is higher, which is beneficial to improve the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the smaller feature size, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens. Therefore, the gate structure's control over the channel becomes worse, and it becomes increasingly difficult to pinch off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, to reduce the impact of short-channel effects, semiconductor processes have gradually transitioned from planar MOSFETs to three-dimensional transistors with higher efficiency, such as FinFETs. In FinFETs, the gate structure can control the ultrathin body (fin) from at least both sides. Compared with planar MOSFETs, the gate structure has stronger control over the channel and can effectively suppress short-channel effects. Furthermore, FinFETs have better compatibility with existing integrated circuit manufacturing processes compared to other devices.

[0004] The quality of fin formation has a significant impact on the performance of semiconductor structures. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the formation quality of the fins and optimizing the electrical performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate, the substrate including a first region and a second region; a first fin located on the substrate in the first region; a second fin located on the substrate in the second region; an isolation layer located on the substrate where the first and second fins are exposed, and covering a portion of the sidewalls of the first and second fins; a first protective layer located between the first fin and the isolation layer; and a second protective layer located between the second fin and the isolation layer, and the second protective layer is also located between the isolation layer in the first region and the isolation layer in the second region.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including an initial substrate, the substrate including a first region and a second region; etching the initial substrate of the first region to form a first fin; forming a first protective layer conformally covering the first fin; after forming the first protective layer, etching the initial substrate of the second region to form a second fin; and forming a second protective layer conformally covering the second fin.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] In the semiconductor structure formation method provided by the embodiments of the present invention, a substrate is provided, the substrate including an initial substrate, the substrate including a first region and a second region; the initial substrate of the first region is etched to form a first fin; a first protective layer is formed to conformally cover the first fin; after forming the first protective layer, the initial substrate of the second region is etched to form a second fin, the remaining initial substrate serving as a substrate; a second protective layer is formed to conformally cover the second fin; an isolation layer is formed on the substrate exposed by the first and second fins, the isolation layer covering a portion of the sidewalls of the first and second fins; and the first and second protective layers above the isolation layer are removed. In this embodiment of the invention, compared to directly forming fins on the first and second regions, conformally covering the fins with a first protective layer, then removing the first protective layer in the second region, forming a second protective layer on the fins in the second region, and then forming an isolation layer covering a portion of the thickness of the fins after forming the second protective layer, and removing the first and second protective layers higher than the isolation layer, the step of removing the first protective layer in the second region is eliminated. Therefore, the sidewalls of the second fin are less likely to be accidentally damaged. With the extension direction perpendicular to the second fin as the lateral direction, the lateral dimension of the second fin is less likely to decrease. Subsequently, a gate structure spanning the second fin is formed, and the second fin covered by the gate structure serves as the channel region. Consequently, during semiconductor structure operation, the carrier migration rate in the channel easily meets design requirements, which is beneficial for optimizing the electrical performance of the semiconductor structure. Furthermore, it avoids disrupting the stress balance between the second fin and the first protective layer during the step of removing the first protective layer on the second fin. The second fin is less prone to dislocations, and the formation quality of the second fin is higher, which is beneficial for improving the electrical performance of the semiconductor structure. Attached Figure Description

[0010] Figures 1 to 7 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0011] Figure 8This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0012] Figures 9 to 19 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0013] The semiconductor structures currently being formed still suffer from poor performance. This paper analyzes the reasons for this poor performance by examining a semiconductor structure formation method.

[0014] Figures 1 to 7 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0015] like Figure 1 As shown, a substrate is provided, the substrate including a first region I and a second region II, the first region I being used to form an NMOS and the second region II being used to form a PMOS, the substrate including a substrate 10 and fins located on the substrate 10, the fins located in the first region I being designated as first fins 1, and the fins located in the second region II being designated as second fins 2, the second fins 2 including a bottom fin 21 and a top fin 22 located on the bottom fin 21, the fins being lateral, parallel to the surface of the substrate 10 and perpendicular to the extension direction of the fins.

[0016] Specifically, the first fin 1 is made of silicon, the bottom fin 21 is made of silicon, and the top fin 22 is made of silicon germanide.

[0017] like Figure 2 As shown, a first protective material layer 3 is conformally covered on the substrate 10 and the fin.

[0018] like Figure 3 As shown, a first shielding layer 4 is formed that covers the first region I and exposes the second region II.

[0019] like Figure 4 As shown, the first protective material layer 3 in the second region II is removed using the first shielding layer 4 as a mask, and the remaining first protective material layer 3 in the first region I serves as the first protective layer 5; after the first protective layer 5 is formed, the first shielding layer 4 is removed.

[0020] like Figure 5 As shown, a second protective layer 6 is formed on the first protective layer 5 and the second fin 2.

[0021] like Figure 6 As shown, an insulating material layer 7 is formed on the substrate 10 exposed at the fin.

[0022] like Figure 7As shown, the isolation material layer 7 with a partial thickness is etched to form an isolation layer 8, the top surface of which is higher than or flush with the bottom surface of the top fin 22.

[0023] Subsequently, a gate structure spanning the second fin 2, that is, a gate structure spanning part of the top fin 22, is formed on the isolation layer 8. The top fin 22 covered by the gate structure serves as a channel region. During the process of removing the first protective layer 5 of the second region using the first shielding layer 4 as a mask, the sidewalls of the second fin 2 are easily damaged. In other words, the sidewalls of the top fin 22 are easily damaged, resulting in a reduction in the lateral dimension of the top fin 22. If the lateral dimension of the top fin 22 does not meet the design requirements, the electrical performance of the semiconductor structure will be poor. Furthermore, during the formation of the first protective layer 5, a stress balance is achieved between the first protective layer 5 and the second fin 2. During the process of removing the first protective layer 5 from the surface of the second fin 2 using an isotropic etching process, the stress balance between the second fin 2 and the first protective layer 5 will be disrupted. After removing the first protective layer 5, dislocations are more likely to occur in the second fin 2. The higher the formation quality of the second fin 2, the worse the electrical performance of the semiconductor structure will be.

[0024] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including an initial substrate, the substrate including a first region and a second region; etching the initial substrate in the first region to form a first fin; forming a first protective layer conformally covering the first fin; after forming the first protective layer, etching the initial substrate in the second region to form a second fin, the remaining initial substrate serving as a substrate; forming a second protective layer conformally covering the second fin; forming an isolation layer on the substrate exposed by the first and second fins, the isolation layer covering a portion of the sidewalls of the first and second fins; and removing the first and second protective layers above the isolation layer. In this embodiment of the invention, compared to directly forming fins on a first region and a second region, conformally covering the fins with a first protective layer, then removing the first protective layer in the second region, forming a second protective layer on the first protective layer in the first region and the fins in the second region, and then forming an isolation layer covering a portion of the thickness of the fins after forming the second protective layer, and removing the first and second protective layers higher than the isolation layer, the step of removing the first protective layer in the second region is eliminated. Therefore, the sidewalls of the second fin are less likely to be accidentally damaged. With the extension direction perpendicular to the second fin as the lateral direction, the lateral dimension of the second fin is less likely to decrease. Subsequently, a gate structure spanning the second fin is formed, and the second fin covered by the gate structure serves as the channel region. Correspondingly, when the semiconductor structure is working, the carrier migration rate in the channel easily meets the design requirements, which is beneficial for optimizing the electrical performance of the semiconductor structure. Furthermore, it avoids disrupting the stress balance between the second fin and the first protective layer during the step of removing the first protective layer on the second fin. The second fin is less prone to dislocations, and the formation quality of the second fin is higher, which is beneficial for improving the electrical performance of the semiconductor structure.

[0025] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0026] Accordingly, embodiments of the present invention also provide a semiconductor structure. (See reference...) Figure 8 The diagram shows a schematic representation of an embodiment of a semiconductor structure.

[0027] The semiconductor structure includes: a substrate 213, which includes a first region I and a second region II; a first fin 205 located on the substrate 213 in the first region I; a second fin 209 located on the substrate 213 in the second region II; an isolation layer 212 located on the substrate 213 where the first fin 205 and the second fin 209 are exposed, and covering a portion of the sidewalls of the first fin 205 and the second fin 209; a first protective layer 207 located between the first fin 205 and the isolation layer 212; and a second protective layer 210 located between the second fin 209 and the isolation layer 212, and the second protective layer 210 is also located between the isolation layer 212 in the first region I and the isolation layer 212 in the second region II.

[0028] The method for forming the semiconductor structure includes: providing a substrate, the substrate including an initial substrate, the substrate including a first region I and a second region II; etching the initial substrate of the first region I to form a first fin 205; forming a first protective layer 207 conformally covering the first fin 205; after forming the first protective layer 207, etching the initial substrate of the second region II to form a second fin 209, the remaining initial substrate serving as a substrate 213; forming a second protective layer 210 conformally covering the second fin 209; forming an isolation layer 212 on the substrate 213 exposed by the first fin 205 and the second fin 209, the isolation layer 212 covering a portion of the sidewalls of the first fin 205 and the second fin 209; and removing the first protective layer 207 and the second protective layer 210 above the isolation layer 212. In this embodiment of the invention, compared to directly forming the fin on the first and second regions, conformally covering the fin with a first protective layer, then removing the first protective layer in the second region, forming a second protective layer on the fin in the second region, and then forming an isolation layer covering a portion of the fin's thickness after forming the second protective layer, and removing the first and second protective layers higher than the isolation layer, the sidewalls of the second fin 209 are less likely to be accidentally damaged. With the extension direction of the second fin 209 perpendicular to its lateral direction, the lateral dimension of the second fin 209 is less likely to decrease, facilitating subsequent formation... The gate structure spanning the second fin 209, with the second fin 209 covered by the gate structure serving as a channel region, allows the carrier migration rate in the channel to easily meet design requirements during semiconductor structure operation, which is beneficial for optimizing the electrical performance of the semiconductor structure. In addition, it avoids disrupting the stress balance between the second fin 209 and the first protective layer 207 during the step of removing the first protective layer 207 on the second fin 209. The second fin 209 is less prone to dislocations, and the formation quality of the second fin 209 is high, which is beneficial for improving the electrical performance of the semiconductor structure.

[0029] The substrate 213 is used to provide a process platform for the subsequent formation of semiconductor structures. In this embodiment, the first region I is used to form a PMOS (Positive Channel Metal Oxide Semiconductor), in which holes are the charge carriers when the PMOS is working; the second region II is used to form an NMOS (Negative Channel Metal Oxide Semiconductor), in which electrons are the charge carriers when the NMOS is working.

[0030] In this embodiment, the first fin portion 205 includes a bottom fin portion 2051 and a top fin portion 2052 located on the bottom fin portion 2051.

[0031] Specifically, the material of the top fin 2052 includes one or more of germanium, silicon germanide, gallium arsenide, indium gallium arsenide, and indium phosphide. In this embodiment, the material of the top fin 2052 includes silicon germanide.

[0032] In this embodiment, the material of the bottom fin 2051 includes silicon. In other embodiments, the bottom fin may also be silicon on an insulator or germanium on an insulator.

[0033] The material of the top fin 2052 includes silicon germanide, that is, the molar volume percentage of germanium in the top fin 2052 is higher than that in the bottom fin 2051. Because germanium atoms are larger than silicon atoms, when the bottom fin 2051 with a lower germanium concentration comes into contact with the top fin 2052 with a higher germanium concentration, compressive stress will be generated in the top fin 2052 and tensile stress will be generated in the bottom fin 2051. The compressive stress in the top fin 2052 is beneficial to improving the carrier mobility in the PMOS.

[0034] With the extension direction perpendicular to the first fin 205 as the lateral direction, during the formation of the semiconductor structure, the first protective layer 207 is used to protect the surface of the first fin 205 from oxidation, so that the lateral dimension of the first fin 205 is not easily reduced. Subsequently, a gate structure spanning the first fin 205 is formed. When the semiconductor structure is working, because the lateral dimension of the first fin 205 is large, the carrier migration rate in the channel is high.

[0035] Specifically, the material of the first protective layer 207 includes one or more of silicon, silicon nitride, silicon oxynitride, silicon carbide nitride, boron nitride, aluminum nitride, boron silicon nitride, and boron silicon carbide. In this embodiment, silicon nitride is a commonly used dielectric material in the process, and silicon nitride can provide compressive stress to the first fin 205. After the gate structure is subsequently formed, source and drain doped layers are formed in the first fin 205 on both sides of the gate structure. When the semiconductor structure is working, the first protective layer 207 and the source and drain doped layers can jointly provide compressive stress to the channel, increasing the carrier migration rate in the channel.

[0036] It should be noted that the first protective layer 207 should not be too thick or too thin. If the first protective layer 207 is too thick, it will require excessive processing time to form, resulting in low formation efficiency. Since the first fin 205 has a slender structure, if the first protective layer 207 is too thick, the pressure exerted on the first fin 205 will be excessive, causing it to bend or tilt, and adjacent fins to easily bridge, leading to poor electrical performance of the semiconductor structure. If the first protective layer 207 is too thin, it will not effectively prevent the first fin 205 from contacting external oxygen during subsequent semiconductor structure formation, making the surface of the first fin 205 still easily oxidized. Consequently, the lateral dimension of the first fin 205 exposed by the isolation layer 212 will be smaller. During semiconductor structure operation, the carrier migration rate in the channel of the first fin 205 will be lower than the design value, failing to meet process requirements and resulting in poor electrical performance of the semiconductor structure. In this embodiment, the thickness of the first protective layer 207 is 1.5 nanometers to 10 nanometers.

[0037] It should be noted that the first protective layer 207 is typically formed using atomic layer deposition or chemical vapor deposition. Therefore, the first protective layer 207 is also located between the substrate 213 and the isolation layer 212 in the first region I.

[0038] The second protective layer 210 is used to protect the surface of the second fin 209 from oxidation and to prevent the lateral dimension of the second fin 209 from shrinking. In the subsequent formation of a gate structure across the second fin 209, when the semiconductor structure is working, the lateral dimension of the second fin 209 is large, resulting in a higher carrier migration rate in the channel.

[0039] Specifically, the material of the second protective layer 210 includes one or more of silicon oxide, silicon carbide, and aluminum oxide.

[0040] It should be noted that the second protective layer 210 should not be too thick or too thin. If the second protective layer 210 is too thick, it will take too much processing time to form the second protective layer 210, resulting in low formation efficiency. The second fin 209 has a slender structure. If the second protective layer 210 is too thick, the pressure of the second protective layer 210 on the second fin 209 will be too great, and the second fin 209 will be prone to bending or tilting. Adjacent second fins 209 will be prone to bridging together, resulting in poor electrical performance of the semiconductor structure. If the second protective layer 210 is too thin, it cannot effectively prevent the second fin 209 from contacting external oxygen during the semiconductor structure formation process, making the surface of the second fin still easily oxidized. In the step of removing the second protective layer 210 that exposes the isolation layer 212, the lateral dimension of the second fin 209 exposed by the isolation layer 212 is small. During semiconductor structure operation, the carrier migration rate in the channel of the second fin 209 is less than the design value, failing to meet process requirements and resulting in poor electrical performance of the semiconductor structure. In this embodiment, the thickness of the second protective layer 210 is 1.5 nanometers to 10 nanometers.

[0041] It should be noted that the second protective layer 210 is typically formed using atomic layer deposition or chemical vapor deposition. Therefore, the second protective layer 210 is also located between the substrate 213 and the isolation layer 212 in the second region II.

[0042] The isolation layer 212 is prepared for the subsequent formation of the isolation layer of the first region I.

[0043] In this embodiment, the material of the isolation layer 212 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the isolation layer 212, and the removal process of silicon oxide is simple.

[0044] In this embodiment, the isolation layer 212 covers the bottom fin portion 2051 and a portion of the thickness of the top fin portion 2052 of the first region I. The first fin portion 205 and the second fin portion 209 exposed in the isolation layer 212 serve as effective fin portions. Subsequently, a gate structure spanning the effective fin portions of the first fin portion 205 and the second fin portion 209 is formed on the isolation layer 212. When the semiconductor structure is in operation, the channel is located in the effective fin portion.

[0045] Figures 9 to 19 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0046] refer to Figure 9A substrate is provided, the substrate including an initial substrate 100, the substrate including a first region I and a second region II.

[0047] The substrate is used to provide a process platform for the subsequent formation of semiconductor structures. In this embodiment, the first region I is used to form a PMOS (Positive Channel Metal Oxide Semiconductor), in which holes are the charge carriers when the PMOS is working; the second region II is used to form an NMOS (Negative Channel Metal Oxide Semiconductor), in which electrons are the charge carriers when the NMOS is working.

[0048] The initial substrate 100 of the first region I includes: a first semiconductor layer 101 and a second semiconductor layer 102 located on the first semiconductor layer 101; the initial substrate 100 of the second region II includes: a first semiconductor layer 101, the top of the first semiconductor layer 101 of the second region II being flush with the top of the second semiconductor layer 102.

[0049] In this embodiment, the material of the first semiconductor layer 101 includes silicon. In other embodiments, the first semiconductor layer may also be silicon-on-insulator or germanium-on-insulator.

[0050] Specifically, the material of the second semiconductor layer 102 includes one or more of germanium, silicon germanide, gallium arsenide, indium gallium arsenide, and indium phosphide. In this embodiment, the material of the second semiconductor layer 102 includes silicon germanide.

[0051] In other embodiments, the germanium in the second semiconductor layer may also have multiple concentrations.

[0052] In this embodiment, the step of providing a substrate includes: forming a first semiconductor material layer (not shown in the figure) in the first region I and the second region II; etching a portion of the thickness of the first semiconductor material layer in the first region I to form a substrate trench (not shown in the figure), with the remaining first semiconductor material layer serving as the first semiconductor layer 101; and forming a second semiconductor layer 102 in the substrate trench, with the first semiconductor layer 101 and the second semiconductor layer 102 serving as the substrate.

[0053] It should be noted that, in the step of providing the substrate, a top mask layer 103 is formed on the initial substrate 100.

[0054] The top mask layer 103 serves as an etching mask for subsequent etching of the initial substrate 100 to form the fin.

[0055] Specifically, the top mask layer 103 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron carbide. In this embodiment, the top mask layer 103 includes silicon nitride.

[0056] It should be noted that, in this embodiment, a bottom mask layer 104 is also formed between the top mask layer 103 and the fin 101.

[0057] In this embodiment, the bottom mask layer 104 is made of silicon oxide. The bottom mask layer 104 is used to reduce the stress between the top mask layer 103 and the initial substrate 100, making the top mask layer 103 less likely to fall off and avoiding the problem of dislocation caused by direct contact between the top mask layer 103 and the initial substrate 100.

[0058] refer to Figure 10 and Figure 11 The initial substrate 100 of the first region I is etched to form the first fin 105 (e.g., Figure 11 (As shown).

[0059] The initial substrate 100 of the first region I is etched to form a first fin 105. Subsequently, a first protective layer is formed to conformally cover the first fin 105. After the second fin is formed in the second region II, a second protective layer is formed to conformally cover the second fin. Compared to directly forming fins on the first region I and the second region II, conformally covering the fins with a first protective layer, and then removing the first protective layer on the fins in the second region II, and then forming the second protective layer on the first protective layer in the first region I and the fins in the second region II, this method eliminates the step of removing the first protective layer on the second fin, thus ensuring the second fin is perpendicular to the first fin. The extension direction is lateral, and the sidewalls of the second fin are not easily damaged, making it difficult to reduce the lateral size of the second fin. Subsequently, a gate structure is formed across the second fin. The second fin covered by the gate structure serves as a channel region. Accordingly, when the semiconductor structure is working, the migration rate of charge carriers in the channel can easily meet the design requirements, which is beneficial to optimizing the electrical performance of the semiconductor structure. In addition, it also avoids breaking the stress balance between the second fin and the first protective layer during the step of removing the first protective layer on the second fin. The second fin is less prone to dislocation, and the formation quality of the second fin is high, which is beneficial to improving the electrical performance of the semiconductor structure.

[0060] Subsequently, an isolation layer is formed covering part of the sidewall of the first fin 105. The first fin 105 above the isolation layer is an active fin. When the semiconductor structure is working, the first fin 105 above the isolation layer is a channel region. Subsequently, a gate structure spanning the first fin 105 is formed on the isolation layer.

[0061] In this embodiment, the first fin portion 105 includes a bottom fin portion 1051 and a top fin portion 1052 located on the bottom fin portion 1051. In this embodiment, the material of the bottom fin portion 1051 is silicon; the material of the top fin portion 1052 includes one or more of silicon germanide, germanium, gallium arsenide, indium gallium arsenide, and indium phosphide.

[0062] In this embodiment, the top fin 1052 is made of silicon germanide, and the bottom fin 1051 is made of silicon. That is, the molar volume percentage of germanium in the top fin 1052 is higher than that in the bottom fin 1051. This is because germanium atoms are larger than silicon atoms. When the bottom fin 1051, with its lower germanium concentration, comes into contact with the top fin 1052, which has a higher germanium concentration, compressive stress is generated in the top fin 1052, which is beneficial for improving carrier mobility in the PMOS.

[0063] Specifically, the step of etching the initial substrate 100 of the first region I to form the first fin 105 includes: forming a shielding layer 106 that covers the second region II and exposes the first region I; and etching the initial substrate 100 using the top mask layer 103 of the first region I as a mask to form the first fin 105.

[0064] In this embodiment, the initial substrate 100 is etched using a dry etching process with the top mask layer 103 as a mask to form the first fin 105. The dry etching process has anisotropic etching characteristics, good control over the etching profile, and can achieve fairly accurate pattern transformation, which is beneficial for ensuring that the morphology of the first fin 105 meets process requirements. Furthermore, using a dry etching process allows for precise control of the height of the first fin 105.

[0065] It should be noted that during the step of etching to form the first fin 105, the bottom mask layer 104 is also etched, so that during the etching of the initial substrate 100, the top mask layer 103 and the bottom mask layer 104 together serve as etching masks for etching the initial substrate 100. In this embodiment, after the first fin 105 is formed, the top mask layer 103 is etched away.

[0066] In the step of forming the first fin 105, the shielding layer 106 protects the initial substrate 100 of the second region II from being easily etched.

[0067] The shielding layer 106 is made of a material that can shield the initial substrate 100 of the second region I and is easily removable. Specifically, the material of the shielding layer 106 includes organic materials.

[0068] The method for forming the semiconductor structure further includes: after forming the first fin 105, removing the shielding layer 106.

[0069] The shielding layer 106 is removed so that the organic materials in the shielding layer 106 are less likely to contaminate the machine.

[0070] refer to Figure 12 A first protective layer 107 is formed to cover the first fin portion 105 in a conformal manner.

[0071] With the extension direction perpendicular to the first fin 105 as the lateral direction, during the formation of the semiconductor structure, the first protective layer 107 is used to protect the surface of the first fin 105 from oxidation, so that the lateral dimension of the first fin 105 is not easily reduced. Subsequently, a gate structure is formed across the first fin 105. When the semiconductor structure is working, because the lateral dimension of the first fin 105 is large, the carrier migration rate in the channel is high.

[0072] It should be noted that the first protective layer 107 also conformally covers the bottom mask layer 104 on top of the first fin 105.

[0073] It should be noted that in the step of forming a first protective layer 107 that conformally covers the first fin 105, the first protective layer 107 also conformally covers the initial substrate 100 of the second region II.

[0074] Specifically, the material of the first protective layer 107 includes one or more of silicon, silicon nitride, silicon oxynitride, silicon carbide nitride, boron nitride, aluminum nitride, boron silicon nitride, and boron silicon carbide. In this embodiment, silicon nitride is used, which is a commonly used dielectric material in the process, and silicon nitride can provide compressive stress to the first fin 105. After the gate structure is subsequently formed, source and drain doped layers are formed in the first fin 105 on both sides of the gate structure. When the semiconductor structure is working, the first protective layer 107 and the source and drain doped layers can jointly provide compressive stress to the channel, increasing the migration rate of charge carriers in the channel.

[0075] In this embodiment, the first protective layer 107 is formed using atomic layer deposition (ALD). ALD involves multiple ALD cycles, which improves the thickness uniformity of the first protective layer 107, enabling it to conformally cover the sidewalls, top, and initial substrate 100 of the first fin 105. Furthermore, ALD offers good gap-filling and step coverage, further enhancing the conformal coverage of the first protective layer 107. In other embodiments, chemical vapor deposition (CVD) can also be used to form the first protective layer.

[0076] It should be noted that in the step of forming the first protective layer 107 that conformally covers the first fin 105, the first protective layer 107 should not be too thick or too thin. If the first protective layer 107 is too thick, it will require too much processing time to form, resulting in low formation efficiency. Since the first fin 105 is a tall and slender structure, if the first protective layer 107 is too thick, the pressure exerted by the first protective layer 107 on the first fin 105 will be too great, causing the first fin 105 to bend or tilt, and adjacent first fins 105 to easily bridge together, resulting in poor electrical performance of the semiconductor structure. If the first protective layer 107 is too thin, during the subsequent semiconductor structure formation process, the first protective layer 107 cannot effectively block the first fin 105 from contact with external oxygen, causing the surface of the first fin 105 to still be easily oxidized. Consequently, the lateral dimension of the first fin 105 is easily reduced, and when the semiconductor structure is working, the carrier migration rate in the channel is less than the design value, failing to meet process requirements and resulting in poor electrical performance of the semiconductor structure. In this embodiment, the thickness of the first protective layer 107 is 1.5 nanometers to 10 nanometers.

[0077] refer to Figure 13 and Figure 14 The method for forming the semiconductor structure includes: after forming the first protective layer and before forming the second fin, forming a first isolation material layer 108 covering the first protective layer 107 in the first region I.

[0078] The first isolation material layer 108 covers the first protective layer 107. During the subsequent etching of the initial substrate 100 of the second region II using the top mask layer 103 as a mask to form the second fin, the first isolation material layer 108 protects the first protective layer 107 from damage. Correspondingly, the protective layer 107 protects the sidewalls of the first fin 105 from oxidation, ensuring that the lateral dimensions of the first fin 105 meet process requirements. Furthermore, the first isolation material layer 108 also prepares for the subsequent formation of the isolation layer in the first region I.

[0079] In this embodiment, the material of the first isolation material layer 108 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the first isolation material layer 108. In addition, the removal process of silicon oxide is simple, which facilitates the subsequent etching of the first isolation material layer 108 to form an isolation layer.

[0080] The step of forming the first isolation material layer 108 includes: forming a first isolation material film 114 covering the first fin 105 and the second region II top mask layer 103; etching back a portion of the thickness of the first isolation material film 114 to form the first isolation material layer 108, wherein the first isolation material layer 108 exposes the top mask layer 103 of the second region II.

[0081] In this embodiment, the first isolation material film 114 is formed using a flowable chemical vapor deposition (FCVD) process. The flowable chemical vapor deposition process has good filling capabilities, which helps reduce the probability of voids and other defects forming within the first isolation material film 114, thereby improving the film quality of the first isolation material layer 108.

[0082] In this embodiment, a maskless dry etching process is used to etch back a portion of the thickness of the first isolation material film 114 to form the first isolation material layer 108. The step of etching the portion of the thickness of the first isolation material film 114 using the maskless dry etching process eliminates the need for a photomask, reducing the process cost of forming the first isolation material layer 108. Furthermore, in the step of etching the portion of the thickness of the first isolation material film 114 using the maskless dry etching process, the first protective layer 109 on the sidewall of the top mask layer 103 is less likely to be damaged, and consequently, the sidewall of the top mask layer 103 is less likely to be damaged, making it less likely that the lateral dimension of the top mask layer 103 will decrease, and consequently, the lateral dimension of the subsequently formed second fin will not decrease.

[0083] In this embodiment, during the process of etching back a portion of the thickness of the first isolation material film 114 to form the first isolation material layer 108, the etching selectivity ratio of the first isolation material film 114 to the first protective layer 107 is greater than 5, so the first protective layer 107 is not easily damaged, and correspondingly, the top mask layer 103 covered by the first protective layer 107 is not easily damaged.

[0084] The first isolation material layer 108 exposes the top mask layer 103 of the second region II, in preparation for subsequent etching of the initial substrate 100 of the second region II using the top mask layer 103 as a mask to form the second fin.

[0085] In this embodiment, the method for forming the semiconductor structure further includes: after forming the first isolation material layer 108, etching the initial substrate 100 of the second region II, and before forming the second fin, removing the first protective layer 107 of the second region II.

[0086] Removing the first protective layer 107 from the second region II can prevent the first protective layer 107 on the sidewall of the top mask layer 103 from serving together with the top mask layer 103 as the etching mask for etching the initial substrate 100 of the second region II, thus making the lateral dimension of the second fin less likely to be too large.

[0087] In this embodiment, a wet etching process is used to remove the first protective layer 107 of the second region II. The wet etching process has isotropic etching characteristics, and simultaneously etches the first protective layer 107 on the top and sidewalls of the top mask layer 103 and the surface of the bottom mask layer 104, making it less likely for the first protective layer 107 of the second region II to remain.

[0088] In this embodiment, the material of the first protective layer 107 is silicon nitride. The corresponding wet etching solution includes phosphoric acid.

[0089] In other embodiments, in the step of forming a first protective layer that conformally covers the first fin, the first protective layer also conformally covers the top mask layer of the second region; in the subsequent process of forming the second fin, the initial substrate of the second region II is etched using the top mask layer and the first protective layer as masks to form the second fin.

[0090] The second fin is formed by etching the initial substrate of the second region II using the top mask layer and the first protective layer as a mask. The lateral dimension of the second fin is larger than that of the first fin. Subsequently, a gate structure spanning the second fin is formed. When the semiconductor structure is working, it is beneficial to improve the migration rate of charge carriers in the channel of the second region.

[0091] refer to Figure 15 The initial substrate 100 of the second region II is etched to form the second fin 109.

[0092] Subsequently, an isolation layer is formed covering part of the sidewall of the second fin 109. The second fin 109 above the isolation layer is an active fin. When the semiconductor structure is working, the second fin 109 above the isolation layer is a channel region. Subsequently, a gate structure spanning the second fin 109 is formed on the isolation layer.

[0093] In this embodiment, the material of the second fin 109 includes silicon.

[0094] In this embodiment, using the top mask layer 103 as a mask, a dry etching process is employed to etch the initial substrate 100 of the second region to form the second fin 109. The dry etching process possesses anisotropic etching characteristics, offering good control over the etching profile and enabling highly accurate pattern transformation, which is beneficial for ensuring that the morphology of the second fin 109 meets process requirements. Furthermore, the use of a dry etching process facilitates precise control over the height of the second fin 109.

[0095] It should be noted that in the step of etching to form the second fin 109, the bottom mask layer 104 is also etched, so that during the etching of the initial substrate 100, the top mask layer 103 and the bottom mask layer 104 together serve as the etching mask for etching the initial substrate 100. In this embodiment, after the second fin 109 is formed, the top mask layer 103 is etched away.

[0096] It should be noted that after the second fin 109 is formed, the first semiconductor layer located below the first fin 105 and the second fin 109 serves as the substrate 113.

[0097] It should be noted that in this embodiment, the first fin 105 is formed first and the second fin 109 is formed later. The first fin 105 and the second fin 109 are formed in different steps, which can make the lateral dimensions and heights of the first fin 105 and the second fin 109 different according to process requirements.

[0098] refer to Figure 16 This forms a second protective layer 110 that conforms to the shape and covers the second fin portion 109.

[0099] In this embodiment, after the first fin 105 is formed in the first region I, a first protective layer 107 is formed to conformally cover the first fin 105. After the second fin 109 is formed in the second region II, a second protective layer 110 is formed to conformally cover the second fin 109. Compared to the case where the fins are formed directly in the first region I and the second region II, the first protective layer 107 is conformally covered on the fins, and then the first protective layer 107 on the fins in the second region II is removed, and the second protective layer 110 is formed on the first protective layer 107 in the first region I and the fins in the second region II, the removal of the first protective layer 107 on the second fin 109 is omitted. Step 7 makes it difficult to reduce the lateral dimension of the second fin 109. Subsequently, a gate structure is formed across the second fin 109. The second fin 109 covered by the gate structure serves as a channel region. Accordingly, when the semiconductor structure is working, the migration rate of charge carriers in the channel can easily meet the design requirements, which is beneficial to optimizing the electrical performance of the semiconductor structure. In addition, it also avoids breaking the stress balance between the second fin 109 and the first protective layer 107 in the step of removing the first protective layer 107 on the second fin 109. The second fin 109 is less prone to dislocations, and the formation quality of the second fin is high, which is beneficial to improving the electrical performance of the semiconductor structure.

[0100] The second protective layer 110 is used to protect the surface of the second fin 109 from oxidation and to prevent the lateral dimension of the second fin 109 from shrinking. Subsequently, a gate structure is formed across the second fin 109. When the semiconductor structure is working, because the lateral dimension of the second fin 109 is large, the migration rate of charge carriers in the channel is high.

[0101] It should be noted that the second protective layer 110 also conformally covers the bottom mask layer 104 on top of the second fin 109.

[0102] It should be noted that during the process of forming the second protective layer 110 that conformally covers the second fin 109, the second protective layer 110 also conformally covers the first isolation material layer 108 of the first region I.

[0103] Specifically, the material of the second protective layer 110 includes one or more of silicon oxide, silicon carbide, and aluminum oxide.

[0104] In this embodiment, the second protective layer 110 is formed using atomic layer deposition (ALD). ALD involves multiple ALD cycles, which improves the thickness uniformity of the second protective layer 110, enabling it to conformally cover the sidewalls and top of the second fin 109 and the sidewalls and top of the first insulating material layer 108 in the first region I. Furthermore, ALD offers good gap-filling performance and step coverage, thereby enhancing the conformal coverage capability of the second protective layer 110. In other embodiments, chemical vapor deposition (CVD) can also be used to form the second protective layer.

[0105] It should be noted that in the step of forming the second protective layer 110 that conformally covers the second fin 109, the second protective layer 110 should not be too thick or too thin. If the second protective layer 110 is too thick, it will take too much processing time to form the second protective layer 110, resulting in low formation efficiency. Since the second fin 109 has a slender structure, if the second protective layer 110 is too thick, the pressure of the second protective layer 110 on the second fin 109 will be too great, making the second fin 109 prone to bending or tilting, and adjacent second fins 109 prone to bridging together, resulting in poor electrical performance of the semiconductor structure. If the second protective layer 110 is too thin, it will not effectively prevent the second fin 109 from contacting external oxygen during the subsequent semiconductor structure formation process. This will cause the surface of the second fin 109 to remain easily oxidized, resulting in a reduction in the lateral dimension of the second fin 109 during semiconductor structure formation. Consequently, the carrier migration rate in the channel will be lower than the design value during semiconductor structure operation, failing to meet process requirements and leading to poor electrical performance of the semiconductor structure. In this embodiment, the thickness of the second protective layer 110 is 1.5 nanometers to 10 nanometers.

[0106] refer to Figure 17 The method for forming the semiconductor structure includes: after forming the second protective layer 110, forming a second isolation material layer 111 covering the second protective layer 110.

[0107] The second isolation material layer 111 is then etched in preparation for forming the isolation layer of the second region II.

[0108] In this embodiment, the material of the second isolation material layer 111 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the second isolation material layer 111. In addition, the removal process of silicon oxide is simple, which facilitates the subsequent etching of the second isolation material layer 111 to form an isolation layer.

[0109] In this embodiment, the second isolation material layer 111 is formed using a flowable chemical vapor deposition (FCVD) process. The flowable chemical vapor deposition process has good filling capabilities, which helps reduce the probability of voids and other defects forming within the second isolation material layer 111, thereby improving the film quality of the second isolation material layer 111.

[0110] It should be noted that the second insulating material layer 111 also covers the first insulating material layer 108 of the first region I. Therefore, the top surface of the second insulating material layer 111 in the first region I is easily flush with the top surface of the second insulating material layer 111 in the second region II.

[0111] In the subsequent etching of the first isolation material layer 108 and the second isolation material layer 111 of a certain thickness to form an isolation layer, it is easy to make the isolation layer of the first region I and the isolation layer of the second region II have the same height. Correspondingly, the height of the first fin and the second fin exposed in the isolation layer are the same. Correspondingly, the height of the effective fin of the first region I and the height of the effective fin of the second region II are the same. When the semiconductor structure is working, the channel is located in the effective fin, which is beneficial to improving the uniformity of the semiconductor structure.

[0112] refer to Figure 18 and Figure 19 The first isolation material layer 108 and the second isolation material layer 111, which are partially etched, form an isolation layer 112, which covers part of the sidewalls of the first fin 105 and the second fin 109.

[0113] The isolation layer 112 is used for electrical isolation of adjacent fins.

[0114] The steps of forming the isolation layer 112 include: removing the first isolation material layer 108, the second isolation material layer 111, and the bottom mask layer 104 above the first fin 105 and the second fin 109 using a planarization process; etching back a portion of the thickness of the first isolation material layer 108 and the second isolation material layer 111, and the remaining first isolation material layer 108 and the second isolation material layer 111 serve as the isolation layer 112.

[0115] In this embodiment, the planarization process includes chemical mechanical polishing (CMP). CMP is a global surface planarization technique that can remove the first isolation material layer 108, the second isolation material layer 111, and the bottom mask layer 104 above the first fin 105 and the second fin 109, while minimizing the height difference between the top surface of the first isolation material layer 108 in the first region I and the top surface of the second isolation material layer 111 in the second region II.

[0116] In this embodiment, a dry etching process is used to etch the first isolation material layer 108 and the second isolation material layer 111 to form an isolation layer 112. The dry etching process has anisotropic etching characteristics, which is beneficial for precisely controlling the removal thickness of the first isolation material layer 108 and the second isolation material layer 111, so that the height of the isolation layer 112 meets the process requirements.

[0117] The method for forming the semiconductor structure further includes: after forming the isolation layer 112, removing the first protective layer 107 and the second protective layer 110 that are higher than the isolation layer 112.

[0118] In this embodiment, an isotropic etching process is used to remove the first protective layer 107 and the second protective layer 110, which are higher than the isolation layer 112. Specifically, the isotropic etching process includes a wet etching process. Wet etching is an isotropic etching process, which has a high etching rate, is simple to operate, and has low process cost.

[0119] The semiconductor structure described in this embodiment can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0120] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising an initial substrate, the substrate comprising a first region and a second region; The initial substrate in the first region is etched to form the first fin; A first protective layer is formed to conformally cover the first fin. After forming the first protective layer, the initial substrate in the second region is etched to form the second fin; A second protective layer is formed to conformally cover the second fin. The method for forming the semiconductor structure includes: after forming the first protective layer and before forming the second fin, forming a first isolation material layer covering the first protective layer in the first region; the method for forming the semiconductor structure includes: after forming the second protective layer, forming a second isolation material layer covering the second protective layer, the second isolation material layer also covering the first isolation material layer in the first region; etching a portion of the thickness of the first isolation material layer and the second isolation material layer to form an isolation layer, the isolation layer covering a portion of the sidewalls of the first fin and the second fin.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first protective layer includes one or more of silicon, silicon nitride, silicon oxynitride, silicon carbide, boron nitride, aluminum nitride, boron silicon nitride, and boron silicon carbide.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming a first protective layer that conformally covers the first fin, the thickness of the first protective layer is 1.5 nanometers to 10 nanometers.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first protective layer is formed using atomic layer deposition or chemical vapor deposition.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming a first protective layer that conformally covers the first fin, the first protective layer also conformally covers the initial substrate of the second region; The method for forming the semiconductor structure further includes: after forming the first protective layer, etching the initial substrate of the second region, and before forming the second fin, removing the first protective layer of the second region.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The first protective layer in the second region is removed using a wet etching process.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, a top mask layer is formed on the initial substrate; In the step of forming a first protective layer that conformally covers the first fin, the first protective layer also conformally covers the top mask layer of the second region; In the step of etching the initial substrate in the second region to form the second fin, the initial substrate is etched using the first protective layer and the top mask layer as masks.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The second protective layer is formed using chemical vapor deposition or atomic layer deposition.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The steps for the second protective layer include one or more of silicon oxide, silicon carbide, and aluminum oxide.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming a second protective layer that conformally covers the second fin, the thickness of the second protective layer is 1.5 nanometers to 10 nanometers.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first and second isolation material layers are etched using a dry etching process to form an isolation layer.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first region is used to form a PMOS; The first fin includes a base fin and a top fin located on the base fin.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The material of the bottom fin is silicon; The material of the top fin includes one or more of silicon germanide, germanium, gallium arsenide, indium gallium arsenide, and indium phosphide.

14. A semiconductor structure, characterized in that, The semiconductor structure is formed using the method for forming a semiconductor structure according to any one of claims 1 to 13, wherein the semiconductor structure comprises: A substrate, the substrate comprising a first region and a second region; A first fin is located on the substrate in the first region; The second fin is located on the substrate in the second region; An isolation layer is located on the substrate exposed by the first and second fins, and covers part of the sidewalls of the first and second fins; A first protective layer is located between the first fin and the isolation layer; A second protective layer is located between the second fin and the isolation layer, and the second protective layer is also located between the isolation layer of the first region and the isolation layer of the second region. The material of the second protective layer is different from that of the first protective layer.

15. The semiconductor structure as described in claim 14, characterized in that, The material of the first protective layer includes one or more of silicon, silicon nitride, silicon oxynitride, silicon carbide, boron nitride, aluminum nitride, boron silicon nitride, and boron silicon carbide.

16. The semiconductor structure as claimed in claim 14, characterized in that, The material of the second protective layer includes one or more of silicon oxide, silicon carbide, and aluminum oxide.

17. The semiconductor structure as claimed in claim 14, characterized in that, The first region is used to form a PMOS; the first fin includes a bottom fin and a top fin located on the bottom fin, and the insulating layer covers the bottom fin and a portion of the thickness of the top fin.

18. The semiconductor structure as claimed in claim 17, characterized in that, The bottom fin is made of silicon, and the top fin is made of silicon germanide, germanium, gallium arsenide, indium gallium arsenide, and indium phosphide.

19. The semiconductor structure as claimed in claim 14, characterized in that, The material of the isolation layer includes one or two of silicon oxide, silicon nitride, and silicon oxynitride.

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