Integrated circuit including a full wraparound gate transistor

Abstract

An integrated circuit includes: a memory cell block comprising a plurality of bit cells; and an input / output (I / O) block including a plurality of gate-all-around (GAA) transistors connected to the bit cells, wherein the I / O block includes a plurality of active regions disposed apart from each other in a first direction, each of the plurality of active regions extending in a second direction perpendicular to the first direction, and wherein a GAA transistor is formed therein; a plurality of power rails disposed apart from each other in the first direction and configured to supply power to the GAA transistors; and a plurality of signal lines disposed between the power rails and configured to provide signals to the GAA transistors, wherein a first number of bit cells in the bit cells are connected to a second number of GAA transistors formed in the active regions, and the second number is greater than twice the first number.

Description

Technical Field

[0001] This disclosure relates to integrated circuits, and more specifically, to integrated circuits including all-around gate transistors. Background Technology

[0002] To improve the price competitiveness of memory devices, it is necessary to reduce the size of semiconductor elements. However, reducing the size of semiconductor elements can lead to single-channel effects. To address this issue, a fin field-effect transistor (FinFET) has been developed, in which the gate surrounds three sides of the channel. In addition, a gate-all-around (GAA) transistor, such as a nanosheet transistor or a nanowire transistor, has been developed, in which the gate surrounds four sides of each nanosheet channel.

[0003] Meanwhile, FinFETs can adjust the performance and size of memory devices including FinFETs based on the number of fins. However, GAA transistors require an increase in the number of nanosheets or nanowires to enhance the performance of memory devices including GAA transistors. As the number of nanosheets or nanowires in GAA transistors increases, the size of the memory device increases, the integration density of the semiconductor device deteriorates, and price competitiveness also weakens. Summary of the Invention

[0004] This disclosure provides an integrated circuit including a gate-all-around (GAA) transistor with high integration density and a design method thereof.

[0005] According to one embodiment, an integrated circuit is provided, comprising: a memory cell block including a plurality of bit cells; and an input / output (I / O) block including a plurality of GAA transistors connected to the bit cells, wherein the I / O block includes a plurality of active regions disposed apart from each other in a first direction, each of the plurality of active regions extending in a second direction perpendicular to the first direction, and wherein a GAA transistor is formed therein; a plurality of power rails disposed apart from each other in the first direction and configured to provide power to the GAA transistors; and a plurality of signal lines disposed between the power rails and configured to provide signals to the GAA transistors, wherein a first number of bit cells are connected to a second number of GAA transistors formed in the active regions, and the second number is greater than twice the first number.

[0006] According to one embodiment, an integrated circuit is provided, comprising: a first number of bit cells disposed in a first direction; and a front-end cell region configured to correspond to the first number of bit cells and adjacent to the first number of bit cells in a second direction perpendicular to the first direction, wherein the front-end cell region includes: a second number of active regions separated from each other in the first direction, each active region extending in the second direction; a plurality of logic cells including GAA transistors formed in the active regions; and a plurality of power rails configured to provide power to the logic cells, wherein the second number is three times the first number.

[0007] According to one embodiment, an integrated circuit is provided, comprising: a first number of bit cells disposed in a first direction; a second number of active regions separated from each other in the first direction, extending in a second direction perpendicular to the first direction, and configured to correspond to the first number of bit cells; a front-end cell region including a plurality of logic cells configured to be adjacent to the first number of bit cells in the second direction; a back-end cell region including a plurality of logic cells configured to be adjacent to the plurality of logic cells in the front-end cell region in the second direction; and a plurality of power rails separated from each other in the first direction, each of the plurality of power rails extending in the second direction and formed to be interrupted at a boundary between the front-end cell region and the back-end cell region, wherein the second number is three times the first number, and the plurality of logic cells in the front-end cell region and the plurality of logic cells in the back-end cell region include a plurality of multi-bridge channel transistors formed in the second number of active regions. Attached Figure Description

[0008] The embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0009] Figure 1 This is a layout diagram of an integrated circuit according to one embodiment;

[0010] Figure 2 This is a block diagram illustrating an integrated circuit according to one embodiment;

[0011] Figure 3 This is a layout diagram of an integrated circuit according to one embodiment;

[0012] Figure 4 According to one embodiment Figure 3 A sectional view of line A-A';

[0013] Figure 5 According to one embodiment Figure 3 A sectional view of line B-B';

[0014] Figure 6 This is a layout diagram for interpreting bit cell groups and input / output (I / O) groups according to one embodiment;

[0015] Figure 7 and Figure 8 This illustrates an embodiment. Figure 6 The circuit diagram of the logic unit;

[0016] Figure 9 According to one embodiment Figure 6 Layout diagram of enlarged region C;

[0017] Figure 10 The figure shows a circuit diagram of a display unit according to one embodiment;

[0018] Figure 11 This is a flowchart illustrating a method for manufacturing an integrated circuit according to one embodiment;

[0019] Figure 12 This is a flowchart illustrating an example of a method for designing an integrated circuit according to one embodiment;

[0020] Figure 13 This is a block diagram illustrating a system-on-a-chip (SoC) according to one embodiment; and

[0021] Figure 14 This is a block diagram illustrating a computing system including a memory for storing programs according to one embodiment. Detailed Implementation

[0022] Various embodiments will be described below with reference to the accompanying drawings. The embodiments described herein are exemplary embodiments, and therefore the inventive concept is not limited thereto, and can be implemented in various other forms. In the following, the horizontal direction on the plane of the layout drawing is defined as the first direction X, the vertical direction on the plane of the layout drawing is defined as the second direction Y, and the direction substantially perpendicular to the layout drawing is defined as the third direction Z. Therefore, the second direction Y can represent a direction perpendicular to the first direction X. Directions indicated by arrows in the drawings and their opposites are described as the same direction. The above definitions of directions are the same for all drawings. For ease of explanation, only some of these are shown in the accompanying drawings of this specification.

[0023] Each embodiment provided in the following description does not exclude the association with one or more features in other examples or embodiments provided herein or not provided herein but consistent with the inventive concept. For example, even if a matter described in a particular example is not described in a different example, that matter may be understood to be related to or in conjunction with that different example, unless otherwise mentioned in its description. Furthermore, it should be understood that all descriptions of principles, aspects, examples, and particular embodiments are intended to include their structural and functional equivalents. Additionally, these equivalents should be understood to include not only currently well-known equivalents but also equivalents developed in the future, i.e., all devices invented to perform the same function, regardless of their structure.

[0024] As used here, when a statement such as "at least one" follows an element in a column, it modifies the entire column, not individual elements within that column. For example, the statement "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0025] It will be understood that when an element or layer is referred to as being "above," "over," "on," "below," "under," "connected to," or "attached to" another element or layer, it can be directly above, above, above, below, under, connected to, or attached to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "directly above," "directly above," "directly on," "directly below," "directly under," "directly connected to," or "directly attached to," there are no intermediate elements or layers.

[0026] Figure 1 This is a layout diagram of an integrated circuit according to one embodiment. In detail, Figure 1 The layout diagram illustrates a memory device 10 included in an integrated circuit. In some embodiments, the integrated circuit may store data based on externally provided commands and addresses, and the memory device 10 may be a stand-alone memory device. Additionally, in some embodiments, the integrated circuit may include another element for writing data to or reading data from the memory device 10, and the memory device 10 may be an embedded memory device.

[0027] like Figure 1As shown, the storage device 10 may include a memory cell block 11, an input / output (I / O) block 13, a row driver 14, and a control block 15. The memory cell block 11 may include a plurality of bit cells 12 accessed by word lines and bit lines, respectively. In some embodiments, the bit cells 12 may be volatile memory cells, such as static random access memory (SRAM) cells or dynamic random access memory (DRAM) cells. In some embodiments, the bit cells 12 may be non-volatile memory cells, such as flash memory cells or resistive random access memory (RRAM) cells. Embodiments of the inventive concept will be described primarily with reference to SRAM cells, but are not limited thereto.

[0028] refer to Figure 1 I / O block 13 can be positioned adjacent to memory cell block 11 in the second direction Y. I / O block 13 can perform write or read operations. Row driver 14 can be positioned adjacent to memory cell block 11 in the first direction X. Row driver 14 can be positioned among multiple memory cell blocks 11. Row driver 14 can access bit cell 12 via word lines. Control block 15 is positioned adjacent to I / O block 13 in the first direction X and adjacent to row driver 14 in the second direction Y. Control block 15 can be positioned among I / O blocks 13. Control block 15 can send signals for performing write or read operations. (See later for further details.) Figure 2 Describes storage cell block 11, I / O block 13, row driver 14, and control block 15.

[0029] Figure 2 This is a block diagram illustrating an integrated circuit according to one embodiment. In detail, Figure 2 The block diagram is for understanding Figure 1 The layout diagram indicates the memory device 10 included in the integrated circuit.

[0030] refer to Figure 2 The storage device 10 can receive a command CMD, an address ADDR, a clock signal CLK, write data DATA_IN, and read data DATA_OUT. For example, the storage device 10 can receive a command CMD (which may be called a write command), an address (which may be called a write address), and write data DATA_IN to indicate a write operation, and store the write data DATA_IN in the area corresponding to that address in the storage cell block 11. Additionally, the storage device 10 can receive a command CMD (which may be called a read command) and an address (which may be called a read address) to indicate a read operation, and output the read data DATA_OUT stored in the area corresponding to that address in the storage cell block 11 to the outside.

[0031] The storage cell block 11 may include a plurality of bit cells 12. Each bit cell 12 may be connected to one of a plurality of word lines WL and at least one of a plurality of bit lines BL.

[0032] Row driver 14 can be connected to memory cell block 11 via multiple word lines (WL). Row driver 14 can activate one of the word lines (WL) based on the row address (ROW). Therefore, memory cells connected to the activated word line can be selected from the memory cells. In other words, row driver 14 can select any one of the word lines (WL).

[0033] Control block 15 can receive commands CMD, address ADDR, and clock signal CLK, and generate row address ROW, column address COL, read signal CTR1, and write signal CTR2. For example, control block 15 can identify a read command by decoding command CMD and generate row address ROW, column address COL, and read signal CTR1 for reading data DATA_OUT. Similarly, control block 15 can identify a write command by decoding command CMD and generate row address ROW, column address COL, and write signal CTR2 for writing data DATA_IN.

[0034] I / O block 13 may include bit line precharge circuit 13-1, column driver 13-2, read circuit 13-3, and write circuit 13-4.

[0035] Bit line precharge circuit 13-1 can be connected to memory cell block 11 via multiple bit lines BL. Bit line precharge circuit 13-1 can precharge bit lines BL. Bit lines BL may include bit lines connected to both ends of the memory cell and bitline bars complementary to the bit lines.

[0036] Column driver 13-2 can be connected to bit line precharge circuit 13-1 via bit line BL. Column driver 13-2 can select at least one bit line from bit lines BL based on column address COL. Based on selecting at least one bit line from bit lines BL, bit cells 12 connected to the selected bit line can be selected from bit cells 12. The at least one bit line may include a first bit line BL1 and a second bit line BL2 complementary to the first bit line BL1. The first bit line BL1 and the second bit line BL2 can be connected to both ends of the bit cell 12 of the memory cell block 11. (See later...) Figure 10 Describe the connection relationship between bit cell 12 and the first and second bit lines BL1 and BL2.

[0037] During a read operation, read circuit 13-3 can sense the current and / or voltage received through bit line BL to identify the value stored in the bit cell 12 of the selected word line, i.e., connected to the active word line, and output read data DATA_OUT based on the identified value. Read circuit 13-3 can be connected to column driver 13-2 through at least one bit line of BL. This at least one bit line may include a first bit line BL1 and a second bit line BL2. Read circuit 13-3 can receive a read signal CTR1 from control block 15. Read circuit 13-3 may include a sense amplifier.

[0038] During a write operation, write circuit 13-4 can apply current and / or voltage to bit line BL based on the write data DATA_IN, and write a value to bit cell 12 connected to the active word line, i.e., the selected word line. Write circuit 13-4 can be connected to column driver 13-2 via at least one bit line of BL. This at least one bit line may include a first bit line BL1 and a second bit line BL2. Write circuit 13-4 can receive write signal CTR2 from control block 15.

[0039] Figure 3 This is a layout diagram of an integrated circuit according to one embodiment. In detail, Figure 3 The layout for explaining bit cell group G1 and corresponding I / O group G2 in the XY plane is shown. Bit cell group G1 and I / O group G2 may be repeated multiple times in the first direction X, and only one bit cell group G1 and one I / O group G2 are shown for explanation purposes.

[0040] refer to Figure 3 The bit cell group G1 may include a plurality of bit cells 12-1 to 12-4. The bit cell group G1 may include a first number of bit cells. For example, the first number may be four. In this embodiment, four bit cells 12-1 to 12-4 are shown, but the embodiment is not limited thereto. The first bit cell 12-1, the second bit cell 12-2, the third bit cell 12-3, and the fourth bit cell 12-4 may be arranged adjacent to each other in a first direction. The bit cell group G1 may be included in the storage cell block 11. Figure 1 The storage cell block 11 may include multiple bit cell groups G1. The bit cell groups G1 may be repeatedly arranged in the first direction.

[0041] I / O group G2 may include multiple active regions A1 to A12, multiple power rails PR1 to PR7, multiple gate electrodes GT, and multiple GAA patterns GP.

[0042] Specifically, I / O group G2 may include active regions A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, and A12. Active regions A1 to A12 may be separated from each other in a first direction X. Each of active regions A1 to A12 may extend in a second direction Y. Each of active regions A1 to A12 may extend continuously in the second direction Y within I / O group G2. Active regions A1 to A12 may form an active region group. Integrated circuit 1 may include a plurality of transistors, and transistors may be formed in active regions A1 to A12. Each of active regions A1 to A12 may be an N-type active region in which N-type transistors are formed or a P-type active region in which P-type transistors are formed.

[0043] In this specification, the transistor may be described hereinafter as a gate-all-around FET (GAAFET), but may have any structure. For example, the transistor may include a fin FET (FinFET) formed by a gate electrode and an active pattern extending in a fin shape. The transistor may also include a multi-bridge channel FET (MBCFET) formed by a gate electrode and a plurality of nanosheets extending parallel to each other. The transistor may also include a fork FET having a structure in which the nanosheets for the P-type transistor are separated from the nanosheets for the N-type transistor by dielectric walls, and thus the N-type and P-type transistors are closer to each other. The transistor may also include a vertical FET (VFET) having a structure in which the nanosheets for the P-type transistor are separated from the nanosheets for the N-type transistor by dielectric walls, and thus the N-type and P-type transistors are closer to each other. Figure 3 A transistor consists of source / drain regions separated from each other along the Z-axis and a gate electrode surrounding the channel region. Transistors can include not only FETs, such as complementary FETs (CFETs), negative FETs (NCFETs), or carbon nanotube FETs (CNTs), but also bipolar junction transistors or three-dimensional transistors.

[0044] Multiple gate electrodes GT can be disposed separately from each other in the second direction Y and extend in the first direction X. Therefore, the gate electrodes GT can partially overlap with the active regions A1 to A12. The gate electrodes GT can have a structure corresponding to the gate terminal of the transistor included in integrated circuit 1. The gate electrodes GT can be located below power rails PR1 to PR7.

[0045] Power rails PR1, PR2, PR3, PR4, PR5, PR6, and PR7 can be separately arranged in the first direction X, and each can extend in the second direction Y. Power rails PR1 to PR7 can be formed on the same wiring layer. Each of power rails PR1 to PR7 can be arranged adjacent to one side of active areas A1 to A12. Active areas A1 to A12 can be arranged between power rails PR1 to PR7. Every two active areas A1 to A12 can be arranged between adjacent power rails PR1 to PR7. Power rails PR1 to PR7 can form a power rail group. This embodiment is not limited to... Figure 3 and with Figure 3 Unlike other regions, three or more of the active regions A1 to A12 can be positioned between adjacent power rails PR1 to PR7. Power rails PR1 to PR7 can apply voltage to the transistors formed in the active regions A1 to A12.

[0046] The GAA pattern GP can be located on the active regions A1 to A12. The GAA pattern GP can partially overlap with the gate electrode GT. The GAA pattern GP can be formed at the intersection of the active regions A1 to A12 and the gate electrode GT. The GAA pattern GP can be separated from each other in a first direction X to extend in a second direction Y. The GAA pattern GP can extend discontinuously in the second direction Y. The GAA pattern GP can include multiple nanosheets. In this case, the transistor can include a GAAFET formed by nanosheets and a gate electrode. The GAAFET can include an MBCFET. The MBCFET can include a MOS transistor. The transistor can also include a fork FET, each fork FET having a structure in which the nanosheets for the P-type transistor are separated from the nanosheets for the N-type transistor by dielectric walls and thus the N-type transistor and the P-type transistor are closer to each other. The planar shape of each GAA pattern GP is shown as a quadrilateral, but is not limited thereto.

[0047] Although not shown in the diagram, signal lines can be configured between power rails PR1 and PR7. A signal line group can be configured within an I / O group G2. (Refer to...) Figure 6 Describe the signal line.

[0048] I / O group G2 can correspond to bit unit group G1. Bit units 12-1 to 12-4 can include a first number of bit units, and active regions A1 to A12 can include a second number of active regions. The first and second numbers can be integers equal to or greater than 1. The second number can be greater than twice the first number. For example, the second number can be three times the first number. For example, the first number is two, and the second number is six. For example, the first number is four, and the second number is 12, such as... Figure 3As shown. In another embodiment, the first number can be four, and the second number can be greater than 12. The first number of bit cells can be connected to transistors formed in the second number of active regions. Since the second number is formed to be more than twice the first number, transistors can be additionally disposed while keeping the width of the gate electrode GT in the second direction Y constant. Therefore, the distance between transistors can be reduced.

[0049] I / O group G2 can be included in Figure 1 In I / O block 13. Figure 1 The I / O block 13 may include multiple I / O groups G2. The I / O groups G2 may be repeatedly arranged in the first direction X. In other words, Figure 1 The I / O block 13 may include a first active region group containing a second number of active regions and a second active region group containing a second number of active regions, and the first active region group may be adjacent to the second active region group in the first direction X. The first active region group and the second active region group may correspond to different bit cell groups G1 that are arranged adjacent to each other in the first direction X. Additionally, Figure 1 The I / O block 13 may include a first power rail group and a first signal line group formed on a first active area group, and a second power rail group and a second signal line group formed on a second active area group. The layout of the first active area group may be the same as the layout of the second active area group, the layout of the first power rail group may be the same as the layout of the second power rail group, and the layout of the first signal line group may be the same as the layout of the second signal line group.

[0050] In this embodiment, since the bit cell group G1, comprising four bit cells 12-1 to 12-4, corresponds to the I / O group G2, comprising 12 active regions A1 to A12, the first active region A1 to the third active region A3 can correspond to the first bit cell 12-1. Because transistors can be formed in the portion where the active regions A1 to A12 intersect with the gate electrode GT, at least three transistors can be connected to one bit cell.

[0051] In this embodiment, as the number of transistors that can be connected to a single bit cell increases, semiconductor devices and integrated circuits including such semiconductor devices can be provided. Due to the increased device density, the parasitic capacitance and resistance of the transistors included in the semiconductor device can be reduced. This increased device density also improves price competitiveness.

[0052] Furthermore, since the interval D between the active regions A1 and A12 is constant, the pattern of the active regions A1 to A12 can be simplified. Therefore, defects that may occur during the manufacturing process can be prevented or reduced.

[0053] Figure 4 It is based on Figure 3A sectional view of line A-A'. Figure 5 It is based on Figure 3 A sectional view along line B-B'. In detail, Figure 3 Integrated circuit 1 may include GAA transistors, and Figure 4 and Figure 5 It is used to explain in Figure 3 A cross-sectional view of the multi-bridge channel (MBC) transistor 100 formed in the active regions A1 to A12. Therefore, details are omitted. Figure 3 Power rails PR1 to PR7.

[0054] refer to Figure 4 The MBC transistor 100 may include a plurality of finned active regions FA protruding from a substrate 102 and extending in a second direction Y, and a plurality of nanosheet stacked structures NSS facing the top surface 104 of the finned active regions FA at locations separated from the top surface 104 of the finned active regions FA. The finned active regions FA can represent Figure 3 Multiple active regions A1 to A12.

[0055] A trench T restricting the finned active region FA can be formed in a substrate 102. The substrate 102 may include conductive regions, such as doped wells or structures. The trench T may be filled with a shallow trench isolation (STI) film 114. The STI film 114 may include an insulating material. The level of the top surface 104 of the finned active region FA may be the same as or similar to the level of the top surface of the STI film 114.

[0056] The nanosheet stacked structure NSS can be separated from the top surface 104 of the fin active region FA. The nanosheet stacked structure NSS may include nanosheets N1, N2, and N3 extending parallel to the top surface of the fin active region FA. Nanosheets N1, N2, and N3 may be sequentially stacked one after another on the top surface 104 of the fin active region FA, and each may have a channel region. In this embodiment, a configuration is shown in which nanosheets N1, N2, and N3, along with the gate structure 150, are formed on a fin active region FA, and three nanosheets N1, N2, and N3 are stacked in each nanosheet stacked structure, but this is not a limitation. A case is shown where the planar shape of the nanosheet stacked structure NSS is approximately rectangular, but this is not a limitation. Depending on the planar shape of the fin active region FA and the gate structure 150, the nanosheet stacked structure NSS can have various planar shapes. Nanosheets N1, N2, and N3 may be formed from the same material as the substrate 102.

[0057] Gate structure 150 may extend along a first direction X on fin-type active region FA. Gate structure 150 may be formed to cover nanosheet stacked structure NSS and surround at least a portion of nanosheets N1, N2, and N3. Gate structure 150 may include a main gate portion 150M configured to cover the top surface of nanosheet stacked structure NSS, and a plurality of sub-gate portions 150S formed between the top surface of fin-type active region FA and nanosheet N1 and between nanosheets N1, N2, and N3. Main gate portion 150M and sub-gate portions 150S may be connected to each other. The thickness of each sub-gate portion 150S may be less than the thickness of main gate portion 150M.

[0058] A gate dielectric film 145 can be formed between the nanosheet stacked structure NSS and the gate structure 150. An interlayer insulating film 174 can be formed on the gate structure 150.

[0059] refer to Figure 5 The source / drain region SD can be formed on the upper part of the fin-type active region FA. The source / drain region SD can be connected to the ends of adjacent nanosheets N1, N2, and N3. An insulating pad 134, a first insulating spacer 136 on the insulating pad 134, and a protective film 138 on the first insulating spacer 136 can be formed on the sidewall of the gate structure 150 on the nanosheet stacked structure NSS. The insulating pad 134, the first insulating spacer 136, and the protective film 138 can be disposed on the sidewall of the main gate portion 150M. In another embodiment, the protective film 138 can be omitted.

[0060] A second insulating spacer 140 can be formed on at least some sidewalls of the sub-gate portion 150S. The second insulating spacer 140 can be disposed between nanosheets N1, N2, and N3. The second insulating spacer 140 can be disposed between the sub-gate portion 150S and the source / drain region SD.

[0061] The buffer semiconductor layer 106 can be disposed on the two sidewalls of the sub-gate portion 150S closest to the fin active region FA. The buffer semiconductor layer 106 can also be disposed on the top surface 104 of the fin active region FA. The buffer semiconductor layer 106 can be formed of a material different from that of the fin active region FA.

[0062] Contact plug 190 can be connected to the source / drain region SD. Contact plug 190 can penetrate the interlayer insulating film 174 and the protective film 138 to connect to the source / drain region SD.

[0063] Figure 6 This is a layout diagram for explaining bit cell groups and I / O groups according to one embodiment. Figure 6 The bit cell groups and I / O groups shown can be used with Figure 3The bit cell group G1 and I / O group G2 shown are the same. Therefore, with Figures 1 to 3 The same reference numerals in the accompanying drawings indicate the same parts, and repeated descriptions of them are omitted.

[0064] refer to Figure 6 Bit unit group G1 can refer to a group of a first number of bit units. In this embodiment, the first number can be four. The first number of bit units can be arranged in a first direction X. Bit unit group G1 can be included in... Figure 1 In the storage cell block 11. In this embodiment, the bit cell group G1 is shown as including four bit cells, but is not limited thereto.

[0065] I / O group G2 can correspond to bit cell group G1. In other words, one I / O group G2 can correspond to one bit cell group G1. Bit cell group G1 and I / O group G2 can be repeated in the first direction X.

[0066] I / O group G2 can be divided into a front-end cell area FC and a back-end cell area BC. The front-end cell area FC is adjacent to the bit cell group G1 in the second direction Y. The back-end cell area BC is adjacent to the front-end cell area FC in the second direction Y.

[0067] I / O group G2 may include a plurality of active regions A1 to A12 that are separated from each other in a first direction X and extend in a second direction Y. Each of the active regions A1 to A12 may extend continuously in the second direction Y. In other words, each of the active regions A1 to A12 may be continuous above the boundary RB of the front-end unit region FC and the rear-end unit region BC. Active regions A1 to A12 may include a second number of active regions. The second number may be an integer greater than twice the first number. In this embodiment, the second number may be 12. Therefore, active regions A1 to A12 may include 12 active regions. However, the implementation is not limited to this, and the second number may be an integer equal to or greater than 12.

[0068] Power rails PR1 to PR7 can be configured to have active regions A1 to A12 therebetween. Each pair of active regions A1 to A12 can be located between adjacent power rails PR1 to PR7. For example, a first active region A1 and a second active region A2 can be separated from each other along a first direction between the first power rail PR1 and the second power rail PR2. Power rails PR1 to PR7 can apply voltage to transistors formed in the active regions A1 to A12. At least one of power rails PR1 to PR7 can be formed to be interrupted at the boundary RB between the front-end cell region FC and the back-end cell region BC. In this embodiment, all power rails PR1 to PR7 can be formed to be interrupted at the boundary RB between the front-end cell region FC and the back-end cell region BC. When the boundary RB between the front-end cell region FC and the back-end cell region BC can be referred to as the first boundary, and the boundary of the back-end cell region BC located opposite to the first boundary is referred to as the second boundary, at least one of power rails PR1 to PR7 can be continuously formed from the first boundary to the second boundary. In other words, at least one of the power rails PR1 to PR7 can extend continuously in the second direction Y within the rear-end cell region BC. In this embodiment, the power rails PR1 to PR7 can be uninterrupted within the rear-end cell region BC.

[0069] Signal lines can be positioned between power rails PR1 to PR7. These signal lines can apply signals to transistors formed in active regions A1 to A12. Every five signal lines can be positioned between adjacent power rails PR1 to PR7. For example, signal lines S1, S2, S3, S4, and S5 can be separated from each other in the first direction X between the sixth power rail PR6 and the seventh power rail PR7. Signal lines S1 to S5 can be formed to have different lengths. Signal lines S1 to S5 can be arranged differently as needed. The signal lines included in an I / O group G2 can form a signal line group.

[0070] The front-end cell area FC and the back-end cell area BC can include various logic units. Logic units can include transistors formed in active areas A1 to A12. Logic units can have a symmetrical layout on both sides. Logic units can include switches, inverters, etc. Logic units can be respectively arranged in multiple columns C1, C2, C3, C4, C5, and C6. Logic units can occupy different areas within I / O group G2. The number and type of logic units included in I / O group G2 are not limited to this embodiment. Logic units can receive power from power rails PR1 to PR7 and input or output signals through signal lines. In another embodiment, logic units can include standard units. Standard units can have a structure conforming to predetermined specifications.

[0071] In this embodiment, the front-end cell region FC may include logic cells adjacent to the bit cell group G1 in the second direction Y. Because the bit cell group G1 may include... Figure 1 Therefore, the front-end cell region FC can include logic cells adjacent to the memory cell block 11 in the second direction Y. Each logic cell in the front-end cell region FC can include a switch adjustment unit WMIV, a write switch WM, a power gating cell PG, a capacitance measurement transistor CAP, and a dummy unit DM.

[0072] The logic units in the front-end cell region FC can have a symmetrical layout. For example, multiple switch adjustment units (WMIVs) disposed in the front-end cell region FC can be arranged symmetrically on both sides. The symmetrical layout of the logic units in the front-end cell region FC ensures stable operation. That is, because the logic units in the front-end cell region FC are symmetrical, stable operation is possible. For example, since the switch adjustment units (WMIVs) can have a symmetrical layout, the time it takes for a signal to be transmitted to the switch adjustment units (WMIVs) can be the same. Therefore, signal accuracy can be improved. This embodiment discloses that each logic unit in the front-end cell region FC includes a switch adjustment unit (WMIV), a write switch (WM), a power gating unit (PG), a capacitance measurement transistor (CAP), and a dummy unit (DM), but is not limited thereto, and other logic units can be disposed in the front-end cell region FC.

[0073] The switching adjustment unit WMIV can be located adjacent to the bit cell group G1 in the second direction Y. The switching adjustment unit WMIV can include two active regions. For example, the switching adjustment unit WMIV can include a first active region A1 and a second active region A2. Four switching adjustment units WMIV can be located in one I / O group G2.

[0074] The write switch WM can be positioned adjacent to the switch adjustment unit WMIV in the second direction Y. The write switch WM may include two active regions. For example, the write switch WM may include a second active region A2 and a third active region A3. Four write switches WM can be configured in one I / O group G2. The write switches WM can be electrically connected to the switch adjustment unit WMIV. The write switches WM may not include any of the power rails PR1 to PR7. By positioning the switch adjustment unit WMIV, instead of the write switches WM, closer to the bit cell group G1, the distance between the write switches WM and the switch adjustment unit WMIV is shortened, thus reducing errors in the signal. Therefore, write operations can be performed stably.

[0075] A power gating unit PG can be positioned adjacent to the switch regulating unit WMIV in the second direction Y and adjacent to the write switch WM in the first direction X. The power gating unit PG may include an active region. For example, the power gating unit PG may include a first active region A1. Four power gating units PG can be configured in one I / O group G2. The power gating units PG may not be electrically connected to the write switch WM and the switch regulating unit WMIV.

[0076] The capacitance measuring transistor CAP and the dummy unit DM can be positioned adjacent to the switch adjustment unit WMIV in the first direction X and adjacent to the write switch WM in the second direction Y. The capacitance measuring transistor CAP can measure the capacitance of the transistor formed in the active regions A1 to A12. The dummy unit DM may not include a transistor and is configured to stably perform I / O operations.

[0077] The back-end cell region BC may include logic cells adjacent to the logic cells in the front-end cell region FC in the second direction Y. The back-end cell region BC may include multiple different logic cells. For example, logic cells may include switches, inverters, etc. The logic cells or combinations of logic cells disposed in the back-end cell region BC may be configured as sense amplifiers, write drivers, or level shifters. The logic cells in the back-end cell region BC may have a symmetrical layout on both sides.

[0078] Figure 6 Region C is used to explain the pathways set in I / O group G2, and will be referenced later. Figure 9 describe.

[0079] Figure 7 This is a circuit diagram based on one embodiment, showing... Figure 6 The power gating unit is shown in the logic unit.

[0080] refer to Figure 7 The power-gated unit PG may include a transistor. As mentioned above, the transistor may be a GAAFET. The transistor may be an MBCFET. The power-gated unit PG may include a P-type field-effect transistor (PFET). The power-gated unit PG can supply power to the bit line BL according to the first write signal CTR21.

[0081] Figure 8 This is a circuit diagram based on one embodiment, showing... Figure 6 The logic unit shown includes the switch adjustment unit WMIV and the write switch WM.

[0082] refer to Figure 8The switching adjustment unit WMIV and the write switch WM can be electrically connected to each other. The switching adjustment unit WMIV may include an inverter IV. Therefore, the switching adjustment unit WMIV can invert the second write signal CTR22. The write switch WM can be controlled by the switching adjustment unit WMIV.

[0083] The write switch WM may include two transistors. As mentioned above, the transistors may be GAAFETs. Alternatively, the transistors may be MBCFETs. The write switch WM may include two N-type field-effect transistors (NFETs). Both NFETs can receive the same signal. The write switch WM can receive a second write signal CTR22 inverted by the switch adjustment unit WMIV. The write switch WM can transmit write data to the first bit line BL1 and the second bit line BL2 according to the inverted second write signal CTR22. The second bit line BL2 may be complementary to the first bit line BL1. The first bit line BL1 and the second bit line BL2 may be connected to... Figure 6 At least one of the bit units included in the bit unit group G1.

[0084] Figure 9 According to one embodiment Figure 6 The layout diagram of enlarged area C is shown. In detail, Figure 9 This is a layout diagram used to explain the multiple pathways included in I / O group G2. (and...) Figure 6 The same reference numerals denote the same parts, and repeated descriptions of them are omitted. Additionally, in Figure 9 The trap is omitted in the text.

[0085] refer to Figure 9 The first path V1 can be located below signal lines S1' to S5'. The first path V1 can be connected to one of signal lines S1', S2', S3', S4', and S5'. Signal lines S1' to S5' can be connected to at least one path V1. The width of the first path V1 can be equal to or less than the width W1 of signal lines S1' to S5'.

[0086] The first path V1 and the second path V2 may be located below the first power rail PR1 and the second power rail PR2. The first power rail PR1 and the second power rail PR2 may be connected to at least one second path V2. The first power rail PR1 and the second power rail PR2 may be connected to at least one first path V1. The width of the second path V2 may be equal to or less than the width W2 of each of the first power rail PR1 and the second power rail PR2. The size of the second path V2 may be larger than the size of the first path V1. Because the width W2 of each of the first power rail PR1 and the second power rail PR2 is wider than the width W1 of the signal lines S1' to S5', the size of the second path V2 may be larger than the size of the first path V1.

[0087] The first path V1 and the second path V2 can be positioned at the same level, and the signal lines S1' to S5', the first power rail PR1, and the second power rail PR2 can be positioned above the first path V1 and the second path V2. The first power rail PR1 and the second power rail PR2 include the first path V1, which has a smaller size than the second path V2; therefore, the resistance of all first and second paths V1 and V2 can be reduced. Because the resistance of all first and second paths V1 and V2 is reduced, the performance of the integrated circuit, including I / O group G2, can be improved.

[0088] Figure 10 A circuit diagram for explaining a bit cell according to one embodiment is shown. Specifically, the bit cell may include... Figure 1 or Figure 2 In storage unit block 11, or it could be Figure 1 or Figure 2 Bit cell 12. In this embodiment, bit cell 12 may be an SRAM bit cell. In another embodiment, bit cell 12 may be a volatile memory cell such as a DRAM cell, or a non-volatile memory cell such as a flash memory cell or an RRAM cell.

[0089] refer to Figure 10 Bit unit 12 may include a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, a second pull-down transistor PD2, a first transmission transistor PA1, and a second transmission transistor PA2. The first pull-up transistor PU1 and the second pull-up transistor PU2 may be PFETs, and the first pull-down transistor PD1 and the second pull-down transistor PD2 may be NFETs.

[0090] The first pull-up transistor PU1 and the first pull-down transistor PD1 can be configured with the first inverter IV1. The gates of the first pull-down transistor PD1 and the first pull-up transistor PU1 can be connected to each other. The gates of the first pull-up transistor PU1 and the first pull-down transistor PD1 can correspond to the input terminals of the first inverter IV1. The first node N11 can correspond to the output terminal of the first inverter IV1.

[0091] The second pull-up transistor PU2 and the second pull-down transistor PD2 can be configured to power the second inverter IV2. The gates of the second pull-up transistor PU2 and the second pull-down transistor PD2 can be connected to each other. The connected gates of the second pull-up transistor PU2 and the second pull-down transistor PD2 can correspond to the input terminals of the second inverter IV2. The second node N12 can correspond to the output terminals of the second inverter IV2.

[0092] The first inverter IV1 and the second inverter IV2 can be combined with each other to configure a latching structure. The gates of the first pull-up transistor PU1 and the first pull-down transistor PD1 can be electrically connected to the second node N12, and the gates of the second pull-up transistor PU2 and the second pull-down transistor PD2 can be electrically connected to the first node N11. In other words, the input terminal of the first inverter IV1 can be connected to the output terminal of the second inverter IN2, and the input terminal of the second inverter IV2 can be connected to the output terminal of the first inverter IN1.

[0093] The source / drain of the first transfer transistor PA1 can be connected to the first node N11 and the first bit line BL1. The source / drain of the second transfer transistor PA2 can be connected to the second node N12 and the second bit line BL2. The second bit line BL2 can be complementary to the first bit line BL1. The gates of the first transfer transistor PA1 and the second transfer transistor PA2 can be electrically connected to the word line WL.

[0094] Figure 11 This is a flowchart illustrating a method for manufacturing an integrated circuit (IC) according to one embodiment.

[0095] refer to Figure 11 Unit library D12 may include information about items included in the library. Figure 6 Information about the logic units in I / O group G2. For example, this may include functional information, characteristic information, and layout information about the logic units. In this embodiment, the unit library D12 may include data such as D12_1 and D12_2 that define the layout of the logic units. Logic units may include standard units. Standard units may have a structure conforming to predetermined specifications.

[0096] In operation S10, a logic synthesis operation can be performed to generate netlist data D13 from RTL data D11. For example, a semiconductor design tool can generate netlist data D13, including bitstreams or netlists, by performing logic synthesis on RTL data D11 created in a hardware description language (HDL) using a reference cell library D12. HDL can include VHSIC hardware description language (VHDL), Verilog, etc. The cell library D12 can include information about the height of logic cells, the number of pins included in the logic cells, the number of tracks corresponding to the logic cells, etc. During logic synthesis, logic cells can be included in the integrated circuit by referring to the cell library D12.

[0097] In operation S20, a place and route (P&R) operation can be performed, in which place data D14 is generated from netlist data D13. P&R operation S20 may include multiple operations S21, S22, and S23.

[0098] In operation S21, operations for setting up logic cells can be performed. For example, a semiconductor design tool (e.g., a P&R tool) can set up multiple logic cells from netlist data D13 with reference to cell library D12. (See reference...) Figure 6 The logic units can be located in columns C1 to C6. Each logic unit can occupy a different area within I / O group G2. Each logic unit may include a switch regulating unit WMIV, a write switch WM, and a power gating unit PG located in the front-end unit area FC.

[0099] In operation S21, operations for setting the power rails can be performed.

[0100] In operation S22, operations for creating interconnects can be performed. Through these interconnect operations, the output and input pins of a logic unit can be electrically connected. A logic unit may include at least one path.

[0101] In operation S23, operations for generating layout data D14 can be performed. Layout data D14 may include geometric information about elements and interconnections. Layout data D14 may have a format such as GDSII.

[0102] In operation S30, optical proximity correction (OPC) can be performed on the layout data D14 to determine the pattern on the mask. In other words, distortions such as refraction caused by the properties of light can be corrected for the layout data D14 to form a pattern of the desired shape. In some embodiments, the layout of the integrated circuit can be modified restrictively in operation S30. This allows for optimization of the integrated circuit structure. Operation S30 can be referred to as design polishing.

[0103] In operation S40, operations for manufacturing a mask can be performed. At least one mask can be manufactured to form the pattern determined in operation S30. The mask may include a photomask.

[0104] In operation S50, operations for manufacturing integrated circuits can be performed. For example, multiple layers are patterned using at least one mask manufactured in operation S40, thus enabling the manufacture of integrated circuits. Figure 11 As shown, operation S50 may include operations S51 and S52.

[0105] In operation S51, front-end (FEOL) processes can be performed. FEOL processes refer to the operations of forming individual components on a substrate. Individual components can include transistors, capacitors, resistors, etc. FEOL processes can include wafer planarization, wafer cleaning, trench formation, well formation, gate line formation, and source and drain formation, etc.

[0106] In operation S52, back-end interconnect (BEOL) processes can be performed. BEOL processes can refer to operations used to interconnect independent components. For example, BEOL processes may include operations such as silicide gate, source, and drain regions, adding dielectrics, planarization, forming vias, adding metal layers, forming vias, and forming passivation layers.

[0107] After operating the S52, the packaged IC can be used as a component for various applications.

[0108] Figure 12 This is a flowchart illustrating an example of a method for designing an integrated circuit according to one embodiment. Figure 12 The method can be executed by a computing system including at least one processor, which executes a series of instructions. For example... Figure 12 As shown, the method for designing an IC may include operations S220, S240, and S260.

[0109] In operation S220, operations for acquiring input data can be performed. Input data may refer to data defining the integrated circuit and include the references mentioned above. Figure 11 A described netlist. A netlist may include information about the logic units and connections included in an integrated circuit.

[0110] In operation S240, P&R can be performed based on cell library D15. Operation S240 can correspond to Figure 11 Operation S21. Operation S240 may include multiple operations S242 and S244.

[0111] In operation S242, operations for setting up a logic unit having signal lines arranged along a predetermined track can be performed. For example, refer to... Figure 6 It can perform operations to set the switch regulating unit WMIV in the front-end unit area FC.

[0112] In operating the S244, the power rails can be configured. See the above reference. Figure 6 The power rails can be separated from each other in a first direction X and extend in a second direction Y. The power rails can be interrupted at the boundary between the front-end cell region FC and the rear-end cell region BC. The power rails in the rear-end cell region BC can be configured to extend continuously in the second direction Y.

[0113] In operation S260, operations for generating output data can be performed. The output data may refer to data defining the layout of the integrated circuit and includes the references mentioned above. Figure 11The layout data D14 is described. The output data can define the layout of an integrated circuit in which I / O patterns are set, the I / O patterns including a second number of active regions for each group of bit cells including a first number of bit cells.

[0114] Figure 13 This is a block diagram illustrating a system-on-a-chip (SOC) according to one embodiment. According to one embodiment, the SOC 200 is a semiconductor device and may include integrated circuits. The SOC 200 implements complex functional blocks, such as intellectual property (IP), that perform various functions within a single chip, and active regions, logic cells, and power rails, as provided in one embodiment, may be included in the functional blocks of the SOC 200, respectively.

[0115] refer to Figure 13 The SOC 200 may include a modem 202, a display controller 203, a memory 204, an external memory controller 205, a central processing unit (CPU) 206, a transaction unit 207, a power management integrated circuit (PMIC) 208, and a graphics processing unit (GPU) 209, and the functional blocks of the SOC 200 may communicate with each other via the system bus 201.

[0116] The CPU 206, which has full control over the operation of the SOC 200, can control the operation of other functional blocks (i.e., modem 202, display controller 203, memory 204, external memory controller 205, transaction unit 207, PMIC 208, and GPU 209). The modem 202 can demodulate externally received signals or modulate internally generated signals to transmit modulated signals externally. The external memory controller 205 can control the sending and receiving of data to and from external storage devices connected to the SOC 200. For example, programs and / or data stored in external storage devices can be provided to the CPU 206 or GPU 209 under the control of the external memory controller 205. The GPU 209 can execute program instructions related to graphics processing. The GPU 209 can receive graphics data through the external memory controller 205 and send the graphics data processed by the GPU 209 to the outside of the SOC 200 through the external memory controller 205. The transaction unit 207 can monitor the data transactions of each functional block, and the PMIC 208 can control the power supplied to each functional block according to the control of the transaction unit 207. The display controller 203 can control the display (or display device) outside the SOC 200 to transmit the data generated inside the SOC 200 to the display.

[0117] Memory 204 may include non-volatile memory, such as electrically erasable programmable read-only memory (EEPROM), flash memory, phase-change random access memory (PRAM), RRAM, nanofloating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), or ferroelectric random access memory (FRAM); and volatile memory, such as DRAM, SRAM, mobile DRAM, dual data rate synchronous dynamic random access memory (DDR SDRAM), low power DDR (LPDDR) SDRAM, graphics DDR (GDDR) SDRAM, or Rambus dynamic random access memory (RDRAM).

[0118] Figure 14 This is a block diagram illustrating a computing system including a memory for storing programs according to one embodiment. Methods for manufacturing integrated circuits (e.g., Figure 11 The method includes at least some of the operations and methods for designing integrated circuits (e.g., Figure 12 The operations included in the method can be executed by the computing system 300.

[0119] The computing system 300 can be a fixed computing system such as a desktop computer, workstation, or server, or a portable computing system such as a laptop computer. Figure 14 As shown, the computing system 300 may include a processor 301, an I / O device 302, a network interface 303, RAM 304, ROM 305, and a storage device 306. The processor 301, I / O device 302, network interface 303, RAM 304, ROM 305, and storage device 306 may be connected to a bus 307 or communicate with each other via the bus 307.

[0120] Processor 301 may be referred to as a processing unit and includes at least one core, such as a microprocessor, application processor (AP), digital signal processor (DSP), or GPU, capable of executing any instruction set (e.g., Intel Architecture (IA)-32, 64-bit Extended IA-32, x86-64, PowerPC, Sparc, MIPS, ARM, IA-64, etc.). For example, processor 301 may access memory, i.e., RAM 304 or ROM 305, via bus 307 and execute instructions stored in RAM 304 or ROM 305.

[0121] According to one embodiment, RAM 304 may store a program 304_1 or at least a portion thereof for manufacturing an integrated circuit, and program 304_1 enables processor 301 to perform operations for manufacturing an integrated circuit or at least a portion of operations included in a method for designing an integrated circuit. In other words, program 304_1 may include a plurality of instructions executable by processor 301, and the instructions included in program 304_1 enable processor 301 to perform operations including those referenced above, for example... Figure 11 and Figure 12 At least some of the operations in the flowchart described.

[0122] Even when the power supply to the computing system 300 is cut off, the storage device 306 will not lose the stored data. For example, the storage device 306 may include a non-volatile storage device, or a storage medium such as magnetic tape, optical disc, or magnetic disk. Additionally, the storage device 306 may be detachably attached to the computing system 300. According to one embodiment, the storage device 306 may store a program 304_1, and the program 304_1, or at least a portion thereof, may be loaded from the storage device 306 into RAM 304 before the processor 301 executes the program 304_1. Alternatively, the storage device 306 may store a file created in a programming language, or the program 304_1, or at least a portion thereof, created by a compiler from a file, may be loaded into RAM 304. Furthermore, the storage device 306 may store a database (DB) 306_1, and the database 306_1 may include information required for designing integrated circuits, for example, Figure 11 The unit library D12.

[0123] Storage device 306 can store data that has been processed by processor 301 or will be processed by processor 301. In other words, according to program 304_1, processor 301 can generate data by processing the data stored in storage device 306, or store the generated data in storage device 306. For example, storage device 306 can store... Figure 11 The RTL data D11, netlist data D13, and / or layout data D14.

[0124] I / O device 302 may include input devices, such as a keyboard or pointing device, and output devices, such as a display device or printer. For example, through I / O device 302, a user can trigger the execution of program 304_1 via processor 301 to input... Figure 11 The RTL data D11 and / or netlist data D13, and also check Figure 11 The layout data is D14.

[0125] Network interface 303 can provide access to networks outside computing system 300. For example, the network may include multiple computing systems and communication links, and the communication links may include wired links, optical links, wireless links, or any type of link.

[0126] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

[0127] This application is based on and claims priority to Korean Patent Application No. 10-2020-0147154 filed on November 5, 2020 and Korean Patent Application No. 10-2021-0032094 filed on March 11, 2021, the disclosures of which are incorporated herein by reference in their entirety.

Claims

1. An integrated circuit, comprising: A block of storage cells comprising multiple bit units; as well as The input / output block includes a plurality of fully encircled gate transistors connected to the bit cells. The input / output block includes: A plurality of active regions are disposed separately from each other in a first direction, each of the plurality of active regions extending in a second direction perpendicular to the first direction, and the all-around gate transistor is formed in the plurality of active regions; Multiple power rails, separated from each other in the first direction, are configured to provide power to the all-around gate transistor; and Multiple signal lines are disposed between the power rails and configured to provide signals to the all-around gate transistor. The first number of bit cells are connected to the all-around gate transistor formed in the second number of active regions in the active region, and The second quantity is more than twice the first quantity.

2. The integrated circuit of claim 1, wherein the second quantity is three times the first quantity, and Each pair of active regions is located between adjacent power rails in the power rail.

3. The integrated circuit according to claim 1, wherein the input / output block comprises: The front-end cell area adjacent to the storage cell block in the second direction; as well as The rear unit area adjacent to the front-end unit area in the second direction. The power rail is configured to break at the boundary between the front-end unit area and the rear-end unit area.

4. The integrated circuit according to claim 3, wherein the front-end cell region includes logic cells having a symmetrical layout on both sides.

5. The integrated circuit according to claim 3, wherein the front-end cell region comprises: A switch adjustment unit is disposed adjacent to the memory cell block in the second direction and configured to invert the write signal; as well as A write switch is disposed adjacent to the switch adjustment unit in the second direction and configured to transmit write data to at least one bit line connected to the bit unit.

6. The integrated circuit of claim 3, wherein at least one of the power rails is configured to be continuous in the second direction in the back-end cell region.

7. The integrated circuit according to claim 1, wherein the active region comprises: The first active region group includes the second number of active regions; as well as The second active region group is arranged adjacent to the first active region group and includes the second number of active regions. The power rail and the signal line include: The first power rail group and the first signal line group formed on the first active region group; and The second power rail group and the second signal line group are formed on the second active area group; The layout of the first active region group is the same as that of the second active region group. The layout of the first power rail group is the same as that of the second power rail group, and The layout of the first signal line group is the same as that of the second signal line group.

8. The integrated circuit according to claim 1, further comprising: A first path connected to the signal line; as well as A second path connected to the power rail. The size of the first channel is smaller than the size of the second channel.

9. The integrated circuit of claim 1, wherein the all-around gate transistor comprises a multi-bridge channel transistor.

10. The integrated circuit of claim 1, wherein the bit unit comprises a static random access memory bit unit.

11. An integrated circuit, comprising: A first number of bit units are set in the first direction; as well as The front-end cell area is configured to correspond to the first number of bit cells and is adjacent to the first number of bit cells in a second direction perpendicular to the first direction. The front-end unit area includes: A second number of active regions separated from each other in the first direction, each of the active regions extending in the second direction; Multiple logic cells, including all-around gate transistors formed in the active region; and Multiple power rails are configured to provide power to the logic unit. The second quantity is three times the first quantity.

12. The integrated circuit of claim 11, wherein the plurality of logic units are configured to have a bilaterally symmetrical layout.

13. The integrated circuit of claim 11, wherein each of the logic units comprises: A switch adjustment unit is disposed adjacent to the first number of bit units in the second direction and configured to invert the write signal; as well as A write switch is disposed adjacent to the switch adjustment unit in the second direction and configured to provide write data to a bit line connected to at least one of the bit units.

14. An integrated circuit, comprising: Four bit units are set in the first direction; Twelve active regions are separated from each other in the first direction, extend in a second direction perpendicular to the first direction, and are configured to correspond to the four bit cells; The front-end unit area includes a plurality of logic units arranged adjacent to the four bit units in the second direction; The back-end unit area includes multiple logical units, which are configured to be adjacent to the multiple logical units in the front-end unit area in the second direction; as well as A plurality of power rails, separated from each other in the first direction, each extending in the second direction and formed to be interrupted at the boundary between the front-end unit region and the rear-end unit region. The plurality of logic units in the front-end unit region and the plurality of logic units in the back-end unit region include a plurality of multi-bridge channel transistors formed in the 12 active regions.

15. The integrated circuit of claim 14, wherein the front-end cell region comprises: A switch adjustment unit is disposed adjacent to the four bit units in the second direction and configured to invert the write signal; as well as Multiple write switches are disposed adjacent to the switch adjustment unit in the second direction and configured to provide write data to a bit line connected to at least one of the bit units.

16. The integrated circuit of claim 15, wherein the front-end cell region further comprises: Multiple power gating units are configured to supply power to the bit unit, and The power gating unit is disposed adjacent to the switch adjustment unit in the second direction and adjacent to the write switch in the first direction.

17. The integrated circuit according to claim 14, wherein the plurality of logic units in the front-end cell region and the plurality of logic units in the back-end cell region are respectively formed in a bilaterally symmetrical layout.

18. The integrated circuit of claim 14, wherein every two active regions in the active region are disposed in the back-end cell region between adjacent power rails in the power rails.

19. The integrated circuit according to claim 14, wherein the four bit cells and the twelve active regions are repeatedly arranged in the first direction.

20. The integrated circuit of claim 14, wherein the bit unit comprises a static random access memory bit unit.

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