Method for manufacturing semiconductor device, semiconductor device, and storage system
By forming an alternating stacked structure of insulating dielectric layer and sacrificial layer on the substrate, and forming a step region at one end, removing part of the dielectric layer and the step region to expose the sacrificial layer, forming a groove and filling the oxide part, the problem of CT etching being difficult to stop on the metal layer is solved, and the stability of the contact hole and the etching are simplified.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YANGTZE MEMORY TECH CO LTD
- Filing Date
- 2022-01-24
- Publication Date
- 2026-07-31
AI Technical Summary
In existing technologies, as the number of 3D NAND stacked layers increases, it becomes increasingly difficult for CT etching to stop on the metal layer of the normal WL.
An alternating stacked insulating dielectric layer and sacrificial layer are formed on a substrate, and a stepped region is formed at one end. Part of the dielectric layer and the stepped region are removed to form a contact opening, exposing part of the sacrificial layer. Subsequently, a groove is formed on the sidewall of the contact opening and filled with oxide. Finally, a first filler material is filled into the contact opening to form a contact hole.
The CT etching process has been simplified, reducing the etching difficulty and enabling the contact holes to remain stably on the oxide layer, thus avoiding word line short circuits caused by thickening of the metal layer.
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Figure CN114446967B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductors, and more specifically, to a method for manufacturing a semiconductor device, a semiconductor device, a three-dimensional memory, and a memory system. Background Technology
[0002] As the number of stacked layers in 3D NAND increases, it becomes increasingly difficult for CT (Contact) etching to stop on the metal layer of normal WL (WordLine).
[0003] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention
[0004] The main objective of this application is to provide a method for fabricating a semiconductor device, a semiconductor device, a three-dimensional memory, and a storage system, in order to solve the problem in the prior art that it is difficult to control the CT etching to stop on the corresponding metal layer.
[0005] According to one aspect of the present invention, a method for fabricating a semiconductor device is provided, comprising: forming a stacked structure and a dielectric layer on a substrate, the stacked structure including an insulating dielectric layer and a sacrificial layer alternately stacked in a direction away from the substrate, one end of the stacked structure having a stepped region, and the dielectric layer covering the exposed surface of the stacked structure; removing a portion of the dielectric layer and a portion of the stepped region, forming a contact opening in the dielectric layer and the stepped region, the contact opening exposing at least a portion of the sacrificial layer; removing portions of the insulating dielectric layer and portions of the dielectric layer on both sides of the contact opening to form a plurality of grooves on the sidewalls of the contact opening; correspondingly forming oxide portions in each of the grooves, the oxide portions sealing the grooves; and filling the contact openings in which the oxide portions are formed with a first filler material to obtain a contact hole.
[0006] Optionally, forming oxide portions in each of the grooves includes: depositing polycrystalline silicon material on the inner wall of each of the grooves to form a plurality of polycrystalline silicon portions; oxidizing each of the polycrystalline silicon portions so that the oxidized polycrystalline silicon portions completely fill the grooves to obtain a plurality of oxide portions.
[0007] Optionally, polysilicon material is deposited on the inner wall of each of the grooves to form a plurality of polysilicon portions, including: forming a pre-polysilicon layer in the contact opening where the grooves are formed; removing the pre-polysilicon layer on the sidewall and bottom of the contact opening, and the remaining pre-polysilicon layer forming each of the polysilicon portions.
[0008] Optionally, after forming a stacked structure and a dielectric layer on a substrate, and before removing a portion of the dielectric layer and a portion of the step region, and forming contact openings in the dielectric layer and the step region, the method further includes: removing a portion of the dielectric layer and a portion of the step region, and forming a plurality of virtual channel holes in the dielectric layer and the step region, wherein the virtual channel holes are alternately arranged with the contact holes.
[0009] Optionally, forming a stacked structure and a dielectric layer on a substrate includes: forming a pre-stacked structure on the substrate, the pre-stacked structure including alternating layers of insulating dielectric layer and sacrificial layer; forming a channel via in the pre-stacked structure, the channel via extending through the substrate; forming the stepped region at the end of the pre-stacked structure to obtain the stacked structure; and forming the dielectric layer on the exposed surfaces of the channel via and the stacked structure.
[0010] Optionally, after filling the contact opening where the oxide portion is formed with a first filler material to obtain a contact hole, the method further includes: removing a portion of the dielectric layer and a portion of the stacked structure, forming a gate line slit in the dielectric layer and the stacked structure; replacing each of the sacrificial layers with a metal layer through the gate line slit; and filling the replaced gate line slit with a second filler material to obtain a gate line.
[0011] Optionally, after forming a stacked structure and a dielectric layer on the substrate, and before removing a portion of the dielectric layer and a portion of the step region, and forming contact openings in the dielectric layer and the step region, the method further includes: removing a portion of the dielectric layer and a portion of the stacked structure; forming a gate line slit in the dielectric layer and the stacked structure, the gate line slit extending through the substrate; replacing each of the sacrificial layers with a metal layer through the gate line slit; and filling the replaced gate line slit with a second filler material to obtain a gate line.
[0012] According to another aspect of the present invention, a semiconductor device is also provided, the semiconductor device being fabricated using the method described above.
[0013] According to another aspect of the present invention, a three-dimensional memory is also provided, including the aforementioned semiconductor device.
[0014] According to another aspect of the present invention, a storage system is also provided, including a storage controller and the three-dimensional memory, the three-dimensional memory being configured to store data, and the storage controller being coupled to the three-dimensional memory and configured to control the three-dimensional memory.
[0015] In an embodiment of the present invention, the method for fabricating a semiconductor device firstly involves sequentially forming a stacked structure and a dielectric layer on a substrate. The stacked structure includes alternating layers of insulating dielectric layers and sacrificial layers, and one end of the stacked structure has a stepped region. Then, a portion of the dielectric layer and a portion of the stepped region are removed to form a contact opening. The contact opening exposes at least a portion of the sacrificial layer, i.e., it is not necessary to control the contact opening to stop on the sacrificial layer corresponding to the stepped region. Subsequently, portions of the insulating dielectric layers on both sides of the contact opening and portions of the dielectric layers are removed to form multiple grooves on the sidewalls of the contact opening, exposing a portion of the upper surface of each insulating dielectric layer. Then, sealing oxide portions are formed in each of the grooves. Finally, a first filler material is filled into the contact opening where the oxide portions are formed to obtain a contact hole. Compared to the difficulty in controlling the CT etching to stop on the corresponding metal layer in existing technologies, the semiconductor device fabrication method of this application only requires exposing part of the sacrificial layer to form the contact opening, without stopping on the sacrificial layer corresponding to the step region. This ensures that the contact opening process is relatively easy to implement. Then, the dielectric layer on both sides of the contact opening is removed, and multiple grooves are formed on the sidewall of the contact opening. Finally, a sealing oxide portion is formed in the contact opening, and the contact opening is filled with a first filler material. This ensures that the obtained contact hole stops on the oxide portion while contacting the sacrificial layer, that is, each contact hole stops on the first step, thereby ensuring that the CT etching is less difficult. Attached Figure Description
[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:
[0017] Figures 1 to 3 Schematic diagrams of the structure of a semiconductor device according to one embodiment of this application are shown respectively;
[0018] Figure 4 A schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this application is shown;
[0019] Figures 5 to 24 The diagrams show the structural schematics obtained after each process step of the semiconductor device fabrication method according to embodiments of this application.
[0020] The above figures include the following reference numerals:
[0021] 10. Substrate; 20. Stacked structure; 30. Dielectric layer; 40. Contact opening; 50. Virtual channel via; 60. Channel via; 70. Gate line slit; 80. Gate line; 201. Insulating dielectric layer; 202. Sacrificial layer; 203. Step region; 204. Preparatory stacked structure; 205. Metal layer; 401. Groove; 402. Oxide portion; 403. Contact hole; 404. Polysilicon portion; 405. Preparatory polysilicon layer. Detailed Implementation
[0022] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.
[0023] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.
[0024] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0025] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.
[0026] To ensure that the CT etching stops on the corresponding metal layer of the WL, in some optional embodiments, such as Figure 1 as well as Figure 2As shown, the method of increasing the thickness of the sacrificial layer 202 in the CT etching region is used, and then the sacrificial layer 202 is replaced with a metal layer 205, resulting in a larger thickness of the metal layer 205 to increase the CT etching window. However, the inventors discovered that, as Figure 3 As shown, thickening the metal layer makes it easier for metal residue to form at the etching corners of the GL (Gate Line), which can lead to short circuits in the word line.
[0027] To address the problem of difficulty in controlling CT etching to stop on the corresponding metal layer, one embodiment of this application provides a method for fabricating a semiconductor device, a semiconductor device, a three-dimensional memory, and a storage system.
[0028] According to an embodiment of this application, a method for fabricating a semiconductor device is provided.
[0029] Figure 4 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application. For example... Figure 4 As shown, the method includes the following steps:
[0030] Step S101, as follows Figure 6 As shown, a stacked structure 20 and a dielectric layer 30 are formed on a substrate 10. The stacked structure 20 includes an insulating dielectric layer 201 and a sacrificial layer 202 that are alternately stacked in a direction away from the substrate. One end of the stacked structure 20 has a stepped region 203. The dielectric layer 30 covers the exposed surface of the stacked structure 20.
[0031] Step S102, as follows Figure 8 as well as Figure 19 As shown, a portion of the aforementioned dielectric layer 30 and a portion of the aforementioned step region are removed, and a contact opening 40 is formed in the aforementioned dielectric layer 30 and the aforementioned step region, the contact opening 40 exposing at least a portion of the aforementioned sacrificial layer 202.
[0032] Step S103, as follows Figure 9 as well as Figure 20 As shown, portions of the insulating dielectric layer 201 on both sides of the contact opening 40 and portions of the dielectric layer 30 are removed to form a plurality of grooves 401 on the sidewall of the contact opening 40.
[0033] Step S104, as follows Figure 12 as well as Figure 23 As shown, an oxide portion 402 is correspondingly formed in each of the above-mentioned grooves 401, and the oxide portion 402 seals the groove 401;
[0034] Step S105, as follows Figure 13 as well as Figure 24As shown, a first filler material is filled into the contact opening 40 where the oxide portion 402 is formed to obtain a contact hole 403.
[0035] In the above-described method for fabricating a semiconductor device, firstly, a stacked structure and a dielectric layer are sequentially formed on a substrate. The stacked structure includes alternating layers of insulating dielectric layers and sacrificial layers, and one end of the stacked structure has a stepped region. Then, a portion of the dielectric layer and a portion of the stepped region are removed to form a contact opening. The contact opening exposes at least a portion of the sacrificial layer, i.e., it is not necessary to control the contact opening to stop on the sacrificial layer corresponding to the stepped region. Next, portions of the insulating dielectric layers on both sides of the contact opening and portions of the dielectric layers are removed to form multiple grooves on the sidewalls of the contact opening, exposing a portion of the upper surface of each insulating dielectric layer. Then, sealing oxide portions are formed in each of the grooves. Finally, a first filler material is filled into the contact opening where the oxide portions are formed to obtain a contact hole. Compared to the problem in existing technologies where it is difficult to control the CT etching to stop on the corresponding metal layer, the semiconductor device fabrication method of this application only needs to expose part of the sacrificial layer to form the contact opening, without stopping on the sacrificial layer corresponding to the step region. This ensures that the contact opening process is easier to implement. Then, the dielectric layer on both sides of the contact opening is removed, and multiple grooves are formed on the sidewall of the contact opening. Finally, a sealing oxide portion is formed in the contact opening, and the contact opening is filled with a first filler material. This ensures that the obtained contact holes stop on the oxide portion when contacting the sacrificial layer, that is, each contact hole stops on the first step, thereby ensuring that the CT etching is less difficult.
[0036] It should be noted that each step in the above-described substrate formation embodiments can be implemented using feasible methods in the prior art. The substrate can be selected according to the actual needs of the device and may include silicon substrates, germanium substrates, silicon-germanium composites, SOI (Silicon on Insulator) substrates, or GOI (Germanium on Insulator) substrates. In other embodiments, the substrate may also be a substrate comprising other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, and may also be a stacked structure, such as Si / SiGe, or other epitaxial structures, such as SGOI (Sorganium on Silicon). Of course, other substrates feasible in the prior art may also be used.
[0037] It should be noted that, Figures 5 to 24In this context, X-cut refers to the structural diagram obtained by cutting a semiconductor device along the X direction, and Y-cut refers to the structural diagram obtained by cutting a semiconductor device along the Y direction. In this case, the X direction is perpendicular to the Y direction. Figures 5 to 24 It is obtained by splicing together cross-sectional views from two directions, with the splicing point marked by a dashed line. For example, the X direction can be the extension direction of the gate line slits, and the Y direction can be the arrangement direction of the gate line slits.
[0038] According to a specific embodiment of this application, oxide portions are correspondingly formed in each of the aforementioned grooves. It is understood that "corresponding" here refers to one groove corresponding to one oxide portion, including: such as... Figure 11 as well as Figure 22 As shown, polycrystalline silicon material is deposited on the inner wall of each of the aforementioned grooves 401 to form a plurality of polycrystalline silicon portions 404; as Figure 12 as well as Figure 23 As shown, each of the aforementioned polysilicon portions 404 is oxidized so that the oxidized polysilicon portions 404 completely fill the aforementioned grooves 401, resulting in multiple oxidized portions 402. Since polysilicon expands after oxidation, depositing polysilicon in the aforementioned grooves and then oxidizing it allows the oxidized silicon oxide portions to better fill the aforementioned grooves, sealing them off. This avoids the problem of voids in the grooves caused by directly depositing silicon oxide, which would affect the electrical performance of the device, thus ensuring better device performance. Furthermore, this embodiment further ensures that the contact holes all stop at the aforementioned oxidized portions, thereby further simplifying the fabrication process of the CT and further avoiding the problem in the prior art where it is difficult to control the CT etching to stop at the corresponding sacrificial tungsten layer.
[0039] To further simplify the process of sealing the aforementioned grooves, according to another specific embodiment of this application, polycrystalline silicon material is deposited on the inner wall of each of the aforementioned grooves to form multiple polycrystalline silicon portions, including: such as Figure 10 as well as Figure 21 As shown, a pre-formed polysilicon layer 405 is formed in the contact opening 40 where the aforementioned groove 401 is formed; as Figure 11 as well as Figure 22 As shown, the pre-existing polysilicon layer 405 on the sidewall and bottom of the contact opening 40 is removed, leaving only the pre-existing polysilicon layer 405 located in the groove. The remaining pre-existing polysilicon layer 405 forms each of the polysilicon portions 404. This further ensures that the oxidized polysilicon portions are sealed only at the corresponding groove, avoiding the problem of polysilicon material remaining at other locations of the contact opening, which would otherwise lead to sealing issues at other locations after oxidation.
[0040] According to another specific embodiment of this application, after forming a stacked structure and a dielectric layer on a substrate, before removing a portion of the dielectric layer and a portion of the step region, and before forming contact openings in the dielectric layer and the step region, the method further includes: Figure 7 As shown and Figure 8 As shown, a portion of the aforementioned dielectric layer 30 and a portion of the aforementioned stepped region 203 are removed, and a plurality of virtual channel holes 50 are formed in the aforementioned dielectric layer 30 and the aforementioned stepped region 203. The virtual channel holes 50 are alternately arranged with the aforementioned contact holes. The aforementioned virtual channel holes provide support to the aforementioned stepped region, avoiding problems such as tilting of the aforementioned stepped region during the formation of the contact opening.
[0041] According to a specific embodiment of this application, a stacked structure and a dielectric layer are formed on a substrate, including: Figure 5 As shown, a preliminary stacked structure 204 is formed on the substrate 10. The preliminary stacked structure 204 includes alternating layers of insulating dielectric layer 201 and sacrificial layer 202. A channel via 60 is formed in the preliminary stacked structure 204, and the channel via 60 penetrates to the substrate 10. Figure 6 As shown, the stepped region 203 is formed at the end of the pre-stacked structure 204 to obtain the stacked structure 20; the dielectric layer 30 is formed on the channel hole 60 and the exposed surface of the stacked structure 20.
[0042] According to another specific embodiment of this application, after filling the contact opening where the oxide portion is formed with a first filler material to obtain a contact hole, the method further includes: as follows: Figure 14 As shown, a portion of the dielectric layer 30 and a portion of the stacked structure are removed, and a gate line slit 70 is formed in the dielectric layer 30 and the stacked structure; as Figures 13 to 15 As shown, each of the sacrificial layers 202 is replaced with a metal layer 205 through the gate line slit 70; a second filler material is then filled into the replaced gate line slit 70 to obtain a gate line 80. In this embodiment, a gate line is obtained by first forming a contact hole, then forming a gate line slit, and finally replacing the sacrificial layer with a metal layer through the gate line slit and filling the gate line slit.
[0043] Specifically, the second filling material includes silicon oxide and polysilicon. The gate line is obtained by sequentially filling the gate line slit with silicon oxide and polysilicon material.
[0044] Of course, the method for forming the aforementioned metal layer is not limited to the method described above. According to another specific embodiment of this application, after forming a stacked structure and a dielectric layer on the substrate, before removing a portion of the aforementioned dielectric layer and a portion of the aforementioned step region, and before forming contact openings in the aforementioned dielectric layer and the aforementioned step region, the method further includes: Figure 16 As shown, a portion of the dielectric layer 30 and a portion of the stacked structure are removed, and a gate line slit 70 is formed in the dielectric layer 30 and the stacked structure, the gate line slit 70 extending to the substrate 10; as Figure 17 As shown, each of the sacrificial layers 202 is replaced with a metal layer 205 through the gate line slit 70; as Figure 18 As shown, the gate line 80 is obtained by filling the replaced gate line slit 70 with a second filler material. In this embodiment, the gate line slit is first formed, then the metal layer is replaced by the gate line slit and the slit is filled to obtain the gate line, and finally a contact hole is formed.
[0045] Regarding the fabrication of contact holes and gate lines, those skilled in the art can, according to the two specific embodiments described above, first form contact holes, then form gate line slits to obtain gate lines, thus achieving the desired result. Figure 15 The semiconductor device structure shown can also be obtained by first forming the gate line slit, then forming the contact hole after obtaining the gate line, resulting in a structure like the one described above. Figure 24 The semiconductor structure shown further ensures the flexibility of the entire fabrication process, making this fabrication method applicable to a variety of applications.
[0046] Depend on Figure 15 As can be seen, by forming the contact hole first and then the gate line, the metal material can completely fill the hole left after the contact hole is formed when the metal layer is formed. This results in a semiconductor device structure without internal holes, avoiding the diffusion of F ions in the metal material that could damage the device and ensuring more stable device performance.
[0047] The stepped region described above in this application can be formed by a single stacking and etching, or by multiple stacking and etching processes. The sacrificial layer and the insulating dielectric layer can be made of conventional materials in the prior art. In another specific embodiment of this application, the sacrificial layer is a silicon nitride layer, the insulating dielectric layer is a silicon oxide layer, and the materials of the first filler material and the metal layer include titanium nitride and tungsten.
[0048] These structural layers can be formed by one or more of molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), metal-organic vapor phase epitaxy (MOVPE), hydride vapor phase epitaxy (HVPE) and / or other known crystal growth processes.
[0049] According to another aspect of the present invention, a semiconductor device is also provided, which is manufactured using the method described above.
[0050] According to another aspect of the present invention, a three-dimensional memory is also provided, including the semiconductor device described above.
[0051] According to another aspect of the present invention, a storage system is also provided, including a storage controller and the aforementioned three-dimensional memory, wherein the three-dimensional memory is configured to store data, and the storage controller is coupled to the three-dimensional memory and configured to control the three-dimensional memory.
[0052] The aforementioned storage system includes a storage controller and a three-dimensional memory. The three-dimensional memory is configured to store data, and the storage controller is coupled to the three-dimensional memory and configured to control the three-dimensional memory. Compared to the problem in the prior art where it is difficult to control the CT etching to stop on the corresponding metal layer, the storage system of this application only needs to expose part of the sacrificial layer when forming the contact opening, without stopping on the sacrificial layer corresponding to the step region. This ensures that the contact opening process is easier to implement. Then, the dielectric layer on both sides of the contact opening is removed, and multiple grooves are formed on the sidewall of the contact opening. Finally, a sealing oxide portion is formed in the contact opening, and a first filler material is filled into the contact opening. This ensures that the obtained contact holes stop on the oxide portion when contacting the sacrificial layer, that is, each contact hole stops on the first step, thereby ensuring that the CT etching is less difficult.
[0053] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.
[0054] As can be seen from the above description, the embodiments of this application achieve the following technical effects:
[0055] 1) In the semiconductor device fabrication method described above in this application, firstly, a stacked structure and a dielectric layer are sequentially formed on a substrate. The stacked structure includes alternating layers of insulating dielectric layers and sacrificial layers, and one end of the stacked structure has a stepped region. Then, a portion of the dielectric layer and a portion of the stepped region are removed to form a contact opening. The contact opening exposes at least a portion of the sacrificial layer, i.e., it is not necessary to control the contact opening to stop on the sacrificial layer corresponding to the stepped region. Afterward, portions of the insulating dielectric layers on both sides of the contact opening and portions of the dielectric layers are removed to form a plurality of grooves on the sidewalls of the contact opening, exposing a portion of the upper surface of each insulating dielectric layer. Then, a sealing oxide portion is formed in each of the grooves. Finally, a first filler material is filled into the contact opening where the oxide portion is formed to obtain a contact hole. Compared to the problem in existing technologies where it is difficult to control the CT etching to stop on the corresponding metal layer, the semiconductor device fabrication method of this application only needs to expose part of the sacrificial layer to form the contact opening, without stopping on the sacrificial layer corresponding to the step region. This ensures that the contact opening process is easier to implement. Then, the dielectric layer on both sides of the contact opening is removed, and multiple grooves are formed on the sidewall of the contact opening. Finally, a sealing oxide portion is formed in the contact opening, and the contact opening is filled with a first filler material. This ensures that the obtained contact holes stop on the oxide portion when contacting the sacrificial layer, that is, each contact hole stops on the first step, thereby ensuring that the CT etching is less difficult.
[0056] 2) The storage system described in this application includes a storage controller and the aforementioned three-dimensional memory. The three-dimensional memory is configured to store data, and the storage controller is coupled to the three-dimensional memory and configured to control the three-dimensional memory. Compared to the problem in the prior art where it is difficult to control the CT etching to stop on the corresponding metal layer, the storage system described in this application only needs to expose part of the sacrificial layer when forming the contact opening, without stopping on the sacrificial layer corresponding to the step region. This ensures that the contact opening process is easier to implement. Then, the dielectric layer on both sides of the contact opening is removed, and multiple grooves are formed on the sidewall of the contact opening. Finally, a sealing oxide portion is formed in the contact opening, and a first filler material is filled into the contact opening. This ensures that the obtained contact holes stop on the oxide portion when contacting the sacrificial layer, that is, each contact hole stops on the first step, thereby ensuring that the CT etching is less difficult.
[0057] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A method of manufacturing a semiconductor device, characterized by, include: A stacked structure and a dielectric layer are formed on a substrate. The stacked structure includes an insulating dielectric layer and a sacrificial layer that are alternately stacked in a direction away from the substrate. One end of the stacked structure has a stepped region, and the dielectric layer covers the exposed surface of the stacked structure. A portion of the dielectric layer and a portion of the step region are removed, and contact openings are formed in the dielectric layer and the step region, the contact openings exposing at least a portion of the sacrificial layer; Remove portions of the insulating dielectric layer on both sides of the contact opening, as well as portions of the dielectric layer, to form a plurality of grooves on the sidewall of the contact opening; An oxide portion is formed correspondingly in each of the grooves, the oxide portion sealing the groove and sealing the contact opening; A first filler material is filled into the contact opening where the oxide portion is formed to obtain a contact hole.
2. The method of claim 1, wherein, Oxidation portions are correspondingly formed in each of the grooves, including: Polycrystalline silicon material is deposited on the inner wall of each of the grooves to form multiple polycrystalline silicon sections; Each of the polysilicon portions is oxidized so that the oxidized polysilicon portions completely fill the grooves, thereby obtaining a plurality of oxidized portions.
3. The method of claim 2, wherein, Polycrystalline silicon material is deposited on the inner wall of each of the grooves to form a plurality of polycrystalline silicon portions, including: A pre-formed polycrystalline silicon layer is formed in the contact opening where the groove is formed; Remove the pre-polysilicon layer from the sidewalls and bottom of the contact opening, and the remaining pre-polysilicon layer forms each of the polysilicon portions.
4. The method of claim 1, wherein, After forming a stacked structure and a dielectric layer on a substrate, and before removing a portion of the dielectric layer and a portion of the step region, and before forming contact openings in the dielectric layer and the step region, the method further includes: A portion of the dielectric layer and a portion of the step region are removed, and a plurality of virtual channel holes are formed in the dielectric layer and the step region, the virtual channel holes being alternately arranged with the contact holes.
5. The method of claim 1, wherein, A stacked structure and a dielectric layer are formed on the substrate, including: A pre-stacked structure is formed on the substrate, the pre-stacked structure comprising alternating layers of insulating dielectric layers and sacrificial layers; A channel hole is formed in the pre-stacked structure, the channel hole extending to the substrate; The stepped region is formed at the end of the pre-stacked structure to obtain the stacked structure; The dielectric layer is formed on the exposed surfaces of the channel holes and the stacked structure.
6. The method according to any one of claims 1 to 5, characterized in that, After filling the contact opening where the oxide portion is formed with a first filler material to obtain a contact hole, the method further includes: Remove a portion of the dielectric layer and a portion of the stacked structure to form a gate line slit in the dielectric layer and the stacked structure; Each of the sacrificial layers is replaced with a metal layer through the gate line slits; The gate line slits after replacement are filled with a second filler material to obtain a gate line.
7. The method according to any one of claims 1 to 5, characterized in that, After forming a stacked structure and a dielectric layer on a substrate, and before removing a portion of the dielectric layer and a portion of the step region, and before forming contact openings in the dielectric layer and the step region, the method further includes: A portion of the dielectric layer and a portion of the stacked structure are removed, and a gate line slit is formed in the dielectric layer and the stacked structure, the gate line slit extending into the substrate; Each of the sacrificial layers is replaced with a metal layer through the gate line slits; The gate line slits after replacement are filled with a second filler material to obtain a gate line.
8. A semiconductor device, characterized by comprising: The semiconductor device is manufactured using the method described in any one of claims 1 to 7.
9. A three-dimensional memory, comprising: Includes the semiconductor device as described in claim 8.
10. A storage system, characterized by The device includes a storage controller and the three-dimensional memory of claim 9, the three-dimensional memory being configured to store data, and the storage controller being coupled to the three-dimensional memory and configured to control the three-dimensional memory.