Semiconductor device and data storage system including the same

Abstract

A semiconductor device includes a gate electrode structure, a channel, a division pattern, an insulating pattern structure, a via, and a support structure. The gate electrode structure is on a substrate and includes gate electrodes stacked in a first direction perpendicular to the substrate. Each of the gate electrodes extends in a second direction parallel to the substrate. The channel extends through the gate electrode structure. The division pattern is at each of two sides of the gate electrode structure in a third direction parallel to the substrate. The insulating pattern structure extends through the gate electrode structure. The via extends through the insulating pattern structure. The support structure extends through the gate electrode structure between the insulating pattern structure and the division pattern. The support structure includes first and second extension portions that extend in the second and third directions, respectively.

Description

[0001] Cross-reference of related applications

[0002] Korean Patent Application No. 10-2020-0144339, filed on November 2, 2020, with the Korean Intellectual Property Office and entitled "Semiconductor Device and Massive Data Storage System Including the Same", is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments relate to semiconductor devices and massive data storage systems that include the semiconductor devices. Background Technology

[0004] Electronic systems, including data storage devices, can utilize high-capacity semiconductor devices capable of storing large amounts of data. Therefore, methods to increase the data storage capacity of semiconductor devices have been investigated. For example, semiconductor devices incorporating memory cells that can be stacked in three dimensions have been proposed. Summary of the Invention

[0005] An embodiment relates to a semiconductor device comprising: a gate electrode structure located on a substrate, the gate electrode structure including gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, each of the gate electrodes extending in a second direction parallel to the upper surface of the substrate; a channel extending through the gate electrode structure in the first direction; a dividing pattern located on each of two opposite sides of the gate electrode structure in a third direction, the third direction being parallel to the upper surface of the substrate and intersecting the second direction, the dividing pattern extending in the second direction; an insulating pattern structure extending through a portion of the gate electrode structure; a via extending through the insulating pattern structure in the first direction; and a support structure extending through a portion of the gate electrode structure between the insulating pattern structure and the dividing pattern in the first direction. The support structure may include: a first extension portion extending in the second direction in a plan view; and a second extension portion connected to the first extension portion, the second extension portion extending from the first extension portion in the third direction.

[0006] The embodiment relates to a semiconductor device, comprising: a lower circuit pattern on a substrate, the substrate including a cell array region and an extended region at least partially surrounding the cell array region; a common source plate (CSP) above the lower circuit pattern; a gate electrode structure on the CSP, the gate electrode structure including gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, each of the gate electrodes extending in a second direction parallel to the upper surface of the substrate; a memory channel structure extending on the cell array region through the gate electrode structure and contacting the upper surface of the CSP, the memory channel structure including: a channel extending in the first direction; and a charge storage structure located on an outer wall of the channel; and a dividing pattern located on each of two opposite sides of the gate electrode structure in a third direction, the third direction being parallel to the upper surface of the substrate. The substrate has an upper surface that intersects the second direction, and the dividing pattern extends in the second direction; an insulating pattern structure that extends on the CSP through a portion of the gate electrode structure; a via that extends in the first direction through the insulating pattern structure and the CSP, the via contacting and electrically connecting to one of the lower circuit patterns; a contact plug that extends in the first direction to contact the upper surface of the end of one of the gate electrodes in the second direction; a first support structure that extends in the first direction through the gate electrode structure and contacts the upper surface of the CSP, the first support structure being adjacent to the contact plug; and a second support structure that extends in the first direction through the portion of the gate electrode structure between the insulating pattern structure and the dividing pattern, and contacts the upper surface of the CSP. The second support structure may have a "C", "U", or "T" shape in a plan view.

[0007] The embodiment relates to a massive data storage system, comprising: a semiconductor device having: a memory cell structure including: a gate electrode structure located on a substrate, the gate electrode structure including gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, each of the gate electrodes extending in a second direction parallel to the upper surface of the substrate; a channel extending through the gate electrode structure in the first direction; a dividing pattern located on each of two sides of the gate electrode structure in a third direction, the third direction being parallel to the upper surface of the substrate and intersecting the second direction, the dividing pattern extending in the second direction; an insulating pattern structure extending through a portion of the gate electrode structure; and a via, in the... The device comprises: an insulating pattern structure extending in a first direction; a support structure extending in the first direction through the portion of the gate electrode structure between the insulating pattern structure and the dividing pattern; the support structure including a first extension portion extending in a second direction in a plan view, and including a second extension portion connected to the first extension portion, the second extension portion extending upward from the first extension portion in a third direction; peripheral circuit wiring configured to apply electrical signals to the memory cell structure; input / output pads electrically connected to the peripheral circuit wiring; and a controller electrically connected to the semiconductor device via the input / output pads, the controller being configured to control the semiconductor device. Attached Figure Description

[0008] The features will become clear to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 This is a schematic diagram illustrating an electronic system including semiconductor devices according to an example embodiment.

[0010] Figure 2 This is a schematic perspective view showing an electronic system including semiconductor devices according to an example embodiment.

[0011] Figure 3 and Figure 4 This is a schematic cross-sectional view showing a semiconductor package, which may include a semiconductor device according to an example embodiment.

[0012] Figures 5 to 39 These are plan and cross-sectional views illustrating a method of manufacturing a vertical memory device according to an example embodiment.

[0013] Figure 40 This is a plan view illustrating a semiconductor device according to an example embodiment, which may correspond to... Figure 34 .

[0014] Figure 41This is a plan view illustrating a semiconductor device according to an example embodiment, which may be... Figure 5 A plan view of region W in the diagram.

[0015] Figure 42A and Figure 42B This is a plan view illustrating a semiconductor device according to an example embodiment, which may be... Figure 10 The planar diagram of region Z in the diagram can correspond to... Figures 11 to 13 .

[0016] Figure 43 This illustrates the relationship between the fifth support structure 437 and the sixth support structure 438, as well as the reference. Figure 25 and Figure 26 A plan view illustrating the etching process of forming the second gap 560 by removing the fourth sacrificial pattern 325.

[0017] Figure 44 This is a cross-sectional view of a semiconductor device according to an example embodiment, which can correspond to Figure 34 .

[0018] Figure 45 This is a cross-sectional view of a semiconductor device according to an example embodiment, which can correspond to Figure 37 .

[0019] Figure 46 This is a cross-sectional view of a semiconductor device according to an example embodiment, which can correspond to Figure 37 .

[0020] Figure 47 This is a cross-sectional view of a semiconductor device according to an example embodiment, which can correspond to Figure 37 . Detailed Implementation

[0021] Figure 1 This is a schematic diagram illustrating an electronic system including semiconductor devices according to an example embodiment.

[0022] refer to Figure 1 Electronic system 1000 may include semiconductor device 1100 and controller 1200 electrically connected to semiconductor device 1100. Electronic system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, electronic system 1000 may be a solid-state drive (SSD) device, universal serial bus (USB) device, computing system, medical device, or communication device that may include one or more semiconductor devices 1100.

[0023] Semiconductor device 1100 may be a reference Figures 36 to 47The illustration describes a non-volatile memory device, such as a NAND flash memory device. Semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In the figure, the first structure 1100F is disposed below the second structure 1100S, but the embodiment is not limited thereto, and it may be disposed next to or on the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including decoder circuitry 1110, page buffer 1120, and logic circuitry 1130. The second structure 1100S may be a memory cell structure including: bit line BL, common source line CSL, word line WL, first upper gate line UL1 and second upper gate line UL2, first lower gate line LL1 and second lower gate line LL2, and a memory cell string CSTR between bit line BL and common source line CSL.

[0024] In the second structure 1100S, each memory cell string in the memory cell string CSTR may include: lower transistors LT1 and LT2, adjacent to the common source line CSL; upper transistors UT1 and UT2, adjacent to the bit line BL; and a plurality of memory cell transistors MCT, located between lower transistors LT1 and LT2 and upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary according to the example embodiment.

[0025] In the example embodiment, upper transistors UT1 and UT2 may include string select transistors, and lower transistors LT1 and LT2 may include ground select transistors. Lower gate lines LL1 and LL2 may be the gate electrodes of lower transistors LT1 and LT2, respectively. Word lines WL may be the gate electrodes of memory cell transistors MCT, respectively, and upper gate lines UL1 and UL2 may be the gate electrodes of upper transistors UT1 and UT2, respectively.

[0026] In an example embodiment, lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 that can be connected in series with each other. Upper transistors UT1 and UT2 may include a series select transistor UT1 and an upper erase control transistor UT2. At least one of the lower erase control transistors LT1 and UT2 may be used in an erase operation to erase data stored in the memory cell transistor MCT via gate-induced drain leakage (GIDL) phenomenon.

[0027] The common source line CSL, the first lower gate line LL1 and the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first connection wiring 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second connection wiring 1125 extending from the first structure 1100F to the second structure 1100S.

[0028] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations for at least one selected memory cell transistor (MCT) among a plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via input / output pads 1101 electrically connected to the logic circuit 1130. The input / output pads 1101 can be electrically connected to the logic circuit 1130 via input / output connection wiring 1135 extending from the first structure 1100F to the second structure 1100S.

[0029] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. The electronic system 1000 may include multiple semiconductor devices 1100, and in this case, the controller 1200 may control the multiple semiconductor devices 1100.

[0030] Processor 1210 can control the operation of electronic system 1000, including controller 1200. Processor 1210 can be operated by firmware and can control NAND controller 1220 to access semiconductor device 1100. NAND controller 1220 may include NAND interface 1221 for communicating with semiconductor device 1100. Through NAND interface 1221, control commands for controlling semiconductor device 1100, data to be written to memory cell transistors (MCTs) of semiconductor device 1100, data to be read from memory cell transistors (MCTs) of semiconductor device 1100, etc., can be transmitted. Host interface 1230 can provide communication between electronic system 1000 and external host. When a control command is received from external host through host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0031] Figure 2 This is a schematic perspective view showing an electronic system including semiconductor devices according to an example embodiment.

[0032] refer to Figure 2The electronic system 2000 may include a main substrate 2001, a controller 2002 mounted on the main substrate 2001, at least one semiconductor package 2003, and a dynamic random access memory (DRAM) device 2004. The semiconductor package 2003 and the DRAM device 2004 may be connected to the controller 2002 via wiring patterns 2005 on the main substrate 2001.

[0033] The main substrate 2001 may include a connector 2006 having multiple pins for connection to an external host. The number and arrangement of the multiple pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and the external host. In an example embodiment, the electronic system 2000 may communicate with the external host via one of the following: USB, PCI-Express, Serial Advanced Technology Attachment (SATA), M-Phy for Universal Flash Memory (UFS), etc. In an example embodiment, the electronic system 2000 may be operated by power supplied from the external host via the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) for distributing power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0034] The controller 2002 can write data to or read data from the semiconductor package 2003 and can improve the operating speed of the electronic system 2000.

[0035] DRAM device 2004 can be a buffer memory used to reduce the speed difference between semiconductor package 2003 for storing data and an external host. During control operations of semiconductor package 2003, DRAM device 2004 can be used as a cache memory and can provide space for temporary data storage. If electronic system 2000 includes DRAM device 2004, controller 2002 may also include a DRAM controller for controlling DRAM device 2004, in addition to a NAND controller for controlling semiconductor package 2003.

[0036] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a plurality of semiconductor chips 2200. Each semiconductor package in the first semiconductor package 2003a and the second semiconductor package 2003b may include: a package substrate 2100; a semiconductor chip 2200; a bonding layer 2300 disposed beneath the semiconductor chip 2200; a connection structure 2400 for electrically connecting the semiconductor chip 2200 to the package substrate 2100; and a molding layer 2500 covering the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0037] The package substrate 2100 may be a printed circuit board (PCB) having package-on-pads 2130. Each semiconductor chip 2200 may include input / output pads 2210. The input / output pads 2210 may correspond to... Figure 1 Input / output pads 1101. Each semiconductor chip 2200 may include: a gate electrode structure 3210; a memory channel structure 3220 extending through the gate electrode structure 3210; and a partitioning structure 3230 for partitioning the gate electrode structure 3210. Each semiconductor chip 2200 may include a reference... Figures 36 to 47 Explanation of semiconductor devices.

[0038] In an example embodiment, the connection structure 2400 may be a bonding wire for electrically connecting the input / output pads 2210 to the on-package pads 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via bonding wires and may be electrically connected to the on-package pads 2130 of the package substrate 2100. Alternatively, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, instead of the bonding wire connection structure 2400, the semiconductor chips 2200 may be electrically connected to each other via a connection structure including through-silicon vias (TSVs).

[0039] In an example embodiment, the controller 2002 and the semiconductor chip 2200 may be included in a single package. In an example embodiment, the controller 2002 and the semiconductor chip 2200 may be mounted on an insertion substrate different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be interconnected with each other via wiring on the insertion substrate.

[0040] Figure 3 and Figure 4 This is a schematic cross-sectional view showing a semiconductor package that may each include a semiconductor device according to an example embodiment. Figure 3 and Figure 4 It shows Figure 2 An example embodiment of the semiconductor package 2003 is shown, and it is illustrated. Figure 2 The cross-section taken along line I-I' of the semiconductor package 2003.

[0041] refer to Figure 3 In semiconductor packaging 2003, the packaging substrate 2100 can be a PCB. The packaging substrate 2100 may include: a substrate body portion 2120; and an upper pad 2130 (see reference). Figure 2 The upper pad 2130 is located on the upper surface of the substrate body portion 2120; the lower pad 2125 is located on or exposed through the lower surface of the substrate body portion 2120; and internal wiring 2135 is used to electrically connect the upper pad 2130 and the lower pad 2125 inside the substrate body portion 2120. The upper pad 2130 can be electrically connected to the connection structure 2400. The lower pad 2125 can be connected to the wiring pattern 2005 of the main substrate 2010 in the electronic system 2000 through the conductive connection portion 2800, such as... Figure 2 As shown in the diagram.

[0042] Each semiconductor chip 2200 may include: a semiconductor substrate 3010; and a first structure 3100 and a second structure 3200, stacked sequentially on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region, in which peripheral circuit wiring 3110 may be formed. The second structure 3200 may include: a common source line 3205; a gate electrode structure 3210 located on the common source line 3205; a memory channel structure 3220; and a partition structure 3230 (see reference). Figure 2 ), extending through the gate electrode structure 3210; bit line 3240, electrically connected to the memory channel structure 3220; and gate connection wiring 3235 (see reference). Figure 1 ), electrically connected to the word line WL of the gate electrode structure 3210.

[0043] The second structure 3200 may also include, for example: Figures 11 to 13 , Figure 34 ,as well as Figures 36 to 39 The first to third support structures 432, 434 and 436 are shown in the figure.

[0044] Each semiconductor chip 2200 may include via wiring 3245, which is electrically connected to the peripheral circuit wiring 3110 of the first structure 3100 and extends into the second structure 3200. The via wiring 3245 may be disposed outside the gate electrode structure 3210, and some via wiring 3245 may extend through the gate electrode structure 3210. Each semiconductor chip 2200 may also include input / output pads 2210 (see reference). Figure 2 The input / output pads are electrically connected to the peripheral circuit wiring 3110 of the first structure 3100.

[0045] refer to Figure 4 In a semiconductor package 2003A, each semiconductor chip 2200a may include: a semiconductor substrate 4010; a first structure 4100 located on the semiconductor substrate 4010; and a second structure 4200 located on the first structure 4100 and bonded to the first structure 4100 by a wafer bonding method.

[0046] The first structure 4100 may include a peripheral circuit region, in which peripheral circuit wiring 4110 and a first junction structure 4150 may be formed. The second structure 4200 may include: a common source line 4205; a gate electrode structure 4210 located between the common source line 4205 and the first structure 4100; a memory channel structure 4220; and a partitioning structure 3230 (see reference). Figure 2 ), extending through the gate electrode structure 4210; and the second junction structure 4250, electrically connected to the word line WL (refer to) of the memory channel structure 4220 and the gate electrode structure 4210. Figure 1 For example, the second junction structure 4250 is electrically connected to the bit line 4240 of the channel structure 4220 of the channel memory and electrically connected to the word line WL (see reference). Figure 1 The gate connection wiring 4235 is electrically connected to the memory channel structure 4220 and the word line WL (reference). Figure 1 The first joining structure 4150 of the first structure 4100 and the second joining structure 4250 of the second structure 4200 can contact each other to join together. The first joining structure 4150 and the second joining structure 4250 may include, for example, copper, and can be joined by copper-copper bonding.

[0047] The second structure 4200 may also include, for example: Figures 11 to 13 , Figure 34 ,as well as Figures 36 to 39 The first to third support structures 432, 434 and 436 are shown in the figure.

[0048] Each semiconductor chip 2200a may also include input / output pads 2210 (see reference). Figure 2The input / output pads are electrically connected to the peripheral circuit wiring 4110 of the first structure 4100.

[0049] Figure 3 Semiconductor chip 2200 and Figure 4 The semiconductor chips 2200a can be electrically connected to each other via the connection structure 2400 using a bonding wire method. However, in the example embodiment, such as those in the same semiconductor package... Figure 3 Semiconductor chip 2200 and Figure 4 Semiconductor chips such as the 2200a can be electrically connected to each other through a connection structure including TSV.

[0050] Figures 5 to 39 These are plan and cross-sectional views illustrating a method of manufacturing a vertical memory device according to an example embodiment. Specifically, Figures 5-6 , Figures 10-13 , Figure 17 , Figure 22 , Figure 29 , Figure 32 and Figure 34 It is a floor plan, and Figures 7-9 , Figures 14-16 , Figures 18-21 , Figures 23-28 , Figures 30-31 , Figure 33 ,as well as Figures 35-39 It is a cross-sectional view.

[0051] Figures 7-9 , Figures 14-15 , Figure 33 ,as well as Figures 35-36 These are cross-sectional views taken along line A-A' of the corresponding plan view. Figures 18-21 , Figures 23-25 , Figure 27 , Figure 30 and Figure 37 These are cross-sectional views taken along line B-B' of the corresponding plan view. Figure 16 , Figure 26 , Figure 28 , Figure 31 and Figure 38 These are cross-sectional views taken along line C-C' of the corresponding planar view. Figure 39 It is a cross-sectional view taken along line D-D' of the corresponding plan view. Figures 6 to 39 yes Figure 5 The graph of region X in the image. Figures 11 to 13 yes Figure 10 A magnified cross-sectional view of region Z in the image. Figure 15 yes Figure 14 A magnified cross-sectional view of region Y in the image.

[0052] In the following description (but not necessarily in the claims), a direction substantially perpendicular to the upper surface of the first substrate can be defined as a first direction D1, and two directions substantially parallel to the upper surface of the first substrate and intersecting each other can be defined as a second direction D2 and a third direction D3, respectively. In an example embodiment, the second direction D2 and the third direction D3 may be substantially perpendicular to each other.

[0053] refer to Figure 5 The substrate 100 may include a first region I and a second region II surrounding the first region I.

[0054] Substrate 100 may include silicon, germanium, silicon-germanium, or III-V compounds such as GaP, GaAs, and GaSb. In an example embodiment, substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. In an example embodiment, substrate 100 may be doped with p-type impurities (e.g., boron) or n-type impurities (e.g., phosphorus).

[0055] In the example embodiment, the first region I can be a cell array region, and the second region II can be a pad region or an extended region, and the first cell region I and the second cell region II can together form a cell region. Therefore, memory cells (each of which may include a gate electrode, a channel, and a charge storage structure) can be formed on the first region I of the substrate 100, and the contact plugs (for transmitting electrical signals to the pads of the memory cells and gate electrodes that are contact plugs) can be formed on the second region II of the substrate 100. In the figure, the second region II completely surrounds the first region I, but the embodiment is not limited to this. For example, the second region II may only be formed on both sides of the first region I in the second direction D2.

[0056] The substrate 100 may also include a third region surrounding the second region II, and an upper circuit pattern for applying electrical signals to memory cells via upper contact plugs may be formed on the third region of the substrate 100.

[0057] In the following description, only the structure in region X of the substrate 100, which partially includes the first region I and the second region II, will be described.

[0058] refer to Figure 6 and Figure 7 The lower circuit pattern can be formed on the substrate 100, and the first interlayer insulating layer 150 and the second interlayer insulating layer 170 can be formed on the substrate 100 to cover the lower circuit pattern.

[0059] The substrate 100 may include: a field region on which an isolation pattern 110 is formed; and a source region 101 on which no isolation pattern is formed. The isolation pattern 110 may be formed by a shallow trench isolation (STI) process and may include an oxide, such as silicon oxide.

[0060] In an example embodiment, the semiconductor device may have a peripheral upper cell (COP) structure. Therefore, a lower circuit pattern may be formed on the substrate 100, and memory cells, upper contact plugs, and the upper circuit pattern may be formed above the lower circuit pattern.

[0061] The lower circuit pattern may include, for example, transistors, lower contact plugs, lower wiring, lower vias, etc.

[0062] Together Figure 6 and Figure 7 Let's refer to each other. Figure 18 For example, a first transistor and a second transistor can be formed on a second region II and a first region I of the substrate 100, respectively. The first transistor may include a first lower gate structure 142 on the substrate 100, and the first region 102 and the second region 103 serve as source / drain regions of the active region 101 at the upper portion adjacent to the first lower gate structure 142. The second transistor may include a second lower gate structure 146 on the substrate 100, and the third region 106 and the fourth region 107 serve as source / drain regions of the active region 101 at the upper portion adjacent to the second lower gate structure 146.

[0063] The first lower gate structure 142 may include a first lower gate insulating pattern 122 and a first lower gate electrode 132 sequentially stacked on the substrate 100. The second lower gate structure 146 may include a second lower gate insulating pattern 126 and a second lower gate electrode 136 sequentially stacked on the substrate 100.

[0064] A first interlayer insulating layer 150 may be formed on the substrate 100 to cover the first transistor and the second transistor. It may include: a first lower contact plug 162, a second lower contact plug 163, a fourth lower contact plug 168, and a fifth lower contact plug 169, extending through the first interlayer insulating layer 150 to contact the first to fourth regions 102, 103, 106, and 107, respectively; and a third lower contact plug 164, extending through the first interlayer insulating layer 150 to contact the first lower gate electrode 132.

[0065] The first to fifth lower wirings 182, 183, 184, 188, and 189 can be formed on the first insulating interlayer 150 to contact the upper surfaces of the first to fifth lower contact plugs 162, 163, 164, 168, and 169, respectively. The first lower via 192, the sixth lower wiring 202, the third lower via 212, and the eighth lower wiring 222 can be stacked sequentially on the first lower wiring 182. The second lower via 196, the seventh lower wiring 206, the fourth lower via 216, and the ninth lower wiring 226 can be stacked sequentially on the fourth lower wiring 188.

[0066] The second interlayer insulating layer 170 may be formed on the first interlayer insulating layer 150 to cover the first to ninth lower wirings 182, 183, 184, 188, 189, 202, 206, 222 and 226 and the first to fourth lower vias 192, 194, 212 and 216.

[0067] Each element included in the lower circuit pattern can be formed by, for example, patterning and / or tessellation processes.

[0068] refer to Figure 8 The common source plate (CSP) 240, the first sacrificial layer structure 290 and the first support layer 300 can be sequentially formed on the second insulating interlayer 170.

[0069] CSP 240 may include polysilicon doped with, for example, n-type impurities. Alternatively, CSP 240 may include a metal silicide layer and a polysilicon layer doped with, for example, n-type impurities, stacked sequentially. The metal silicide layer may include, for example, tungsten silicide.

[0070] The first sacrificial layer structure 290 may include a first sacrificial layer 260, a second sacrificial layer 270, and a third sacrificial layer 280 sequentially stacked in the first direction D1. The first sacrificial layer 260 and the third sacrificial layer 280 may include oxides, such as silicon oxide. The second sacrificial layer 270 may include nitrides, such as silicon nitride.

[0071] The first support layer 300 may include a material that is etch-selective for the first to third sacrificial layers 260, 270, and 280, such as polysilicon doped with N-type impurities. A portion of the first support layer 300 may extend through the first sacrificial layer structure 290 to contact the upper surface of the CSP 240, which may form a first support pattern.

[0072] The insulating layer 310 and the fourth sacrificial layer 320 may be stacked alternately and repeatedly on the first support layer 300, so that a molded layer including the alternately stacked insulating layer 310 and the fourth sacrificial layer 320 may be formed on the first support layer 300. The insulating layer 310 may include an oxide, such as silicon oxide. The fourth sacrificial layer 320 may include a material that is etch-selective for the insulating layer 310, such as a nitride (e.g., silicon nitride).

[0073] Together Figure 8 Let's refer to each other. Figure 10 The first dividing pattern 330 can be formed through a portion of the bottommost fourth sacrificial layer 320. The first dividing pattern 330 can be formed on the second region II of the substrate 100 and can include an oxide, such as silicon oxide. In an example embodiment, multiple first dividing patterns 330 can be formed in each of the second direction D2 and the third direction D3.

[0074] refer to Figure 9 A photoresist pattern (not shown) can be formed on the uppermost insulating layer in insulating layer 310, and the uppermost insulating layer in insulating layer 310 and the uppermost fourth sacrificial layer in fourth sacrificial layer 320 can be etched using the photoresist pattern as an etching mask. Therefore, an insulating layer directly beneath the uppermost fourth sacrificial layer in fourth sacrificial layer 320 can be partially exposed.

[0075] A trimming process can be performed to reduce the area of ​​the photoresist pattern by a given ratio, and the uppermost insulating layer in insulating layer 310, the uppermost fourth sacrificial layer in fourth sacrificial layer 320, an exposed insulating layer in insulating layer 310, and a fourth sacrificial layer directly below the exposed insulating layer in fourth sacrificial layer 310 can be etched using a photoresist pattern with a reduced area. The trimming and etching processes can be performed alternately and repeatedly to form a molded portion with a stepped shape, the stepped shape comprising a plurality of stepped layers, each of the plurality of stepped layers comprising a fourth sacrificial layer 320 and an insulating layer 310 stacked sequentially.

[0076] In the following text, a "stepped layer" can be defined as having not only exposed portions of the fourth sacrificial layer 320 and the insulating layer 310 at the same level, but also unexposed portions, and the exposed portions can be defined as "steps". In an example embodiment, the steps can be arranged in the second direction D2. Alternatively, the steps can also be arranged in the third direction D3.

[0077] In the example embodiment, the lengths of the steps included in the molding section along the second direction D2 may be uniform, but some steps may be longer than others. Hereinafter, the shorter steps may be referred to as the first steps, and the longer steps as the second steps. Figure 9 Two second steps are shown. In the following text, steps may be represented by dashed lines in the diagram (see example...). Figure 10 ).

[0078] The molding portion can be formed on the first support layer 300 on the first region I and the second region II of the substrate 100, and the upper surface of the edge of the first support layer 300 can be exposed instead of being covered by the molding portion. The steps of the molding portion can be formed on the second region II of the substrate 100.

[0079] refer to Figures 10-11 as well as Figures 14-16 A third interlayer insulating layer 340 can be formed on the CSP 240 to cover the molded portion and the first support layer 300, and can be planarized until the upper surface of the uppermost insulating layer in the insulating layer 310 of the molded portion is exposed. Therefore, the sidewalls of the molded portion, the upper surface and sidewalls of the first support layer 300, and the sidewalls of the first sacrificial layer structure 290 can be covered by the third interlayer insulating layer 340. A fourth interlayer insulating layer 350 can be formed on the upper surface of the molded portion and the third interlayer insulating layer 340.

[0080] A channel hole extending in the first direction D1 can be formed through the fourth interlayer insulating layer 350, the molding portion, the first support layer 300, and the first sacrificial layer structure 290 on the first region I of the substrate 100 to expose the upper surface of the CSP 240. A first dummy channel hole and a second dummy channel hole extending in the first direction D1 can be formed through the third interlayer insulating layer 340 and the fourth interlayer insulating layer 350, a portion of the molding portion, the first support layer 300, and the first sacrificial layer structure 290 on the second region II of the substrate 100 to expose the upper surface of the CSP 240. In an example embodiment, a plurality of channel holes can be formed to be arranged in each of the second direction D2 and the third direction D3 on the first region I of the substrate 100, and a plurality of first dummy channel holes and a plurality of second dummy channel holes can be formed to be arranged in each of the second direction D2 and the third direction D3 on the second region II of the substrate 100.

[0081] In the example embodiment, the etching process can be performed using extreme ultraviolet (EUV) lithography, so the via and each of the first and second dummy vias can have various shapes. In the example embodiment, each of the vias and the first dummy via can have a shape such as circular, elliptical, rectangular, or rounded rectangle in a plan view, while the second dummy via can have a shape such as "C" or "U".

[0082] The vias, as well as the first dummy via and the second dummy via, can be formed simultaneously using the same etching process, or they can be formed sequentially using separate etching processes.

[0083] The charge storage structure layer and the channel layer can be sequentially formed on the sidewalls of the channel vias and the first and second dummy channel vias, the exposed upper surface of the CSP 240, and the upper surface of the fourth insulating interlayer 350. A fill layer can be formed on the channel layer to fill the channel vias and the first and second dummy channel vias. The fill layer, channel layer, and charge storage structure layer can be planarized until the upper surface of the fourth insulating interlayer 350 is exposed.

[0084] Therefore, the charge storage structure 390, the channel 400, and the filling pattern 410, stacked sequentially, can be formed on the channel hole. Furthermore, the first dummy charge storage structure 392, the first dummy channel 402, and the first dummy filling pattern 412, stacked sequentially, can be formed on the first dummy channel hole. Additionally, the second dummy charge storage structure 394, the second dummy channel 404, and the second dummy filling pattern 414, stacked sequentially, can be formed on the second dummy channel hole.

[0085] In an example embodiment, the charge storage structure 390 may include a tunnel insulating pattern 380, a charge storage pattern 370, and a first barrier pattern 360 sequentially stacked from the outer sidewall of the channel 400 in a horizontal direction substantially parallel to the upper surface of the substrate 100. The tunnel insulating pattern 380 and the first barrier pattern 360 may include oxides, such as silicon oxide. The charge storage pattern 370 may include nitrides, such as silicon nitride. The channel 400 may include, for example, polycrystalline silicon or monocrystalline silicon. The fill pattern 410 may include oxides, such as silicon oxide.

[0086] In the example embodiment, the first dummy charge storage structure 392 and the second dummy charge storage structure 394 may include the same material as the charge storage structure 390, the first dummy channel 402 and the second dummy channel 404 may include the same material as the channel 400, and the first dummy fill pattern 412 and the second dummy fill pattern 414 may include the same material as the fill pattern 410. Therefore, the first dummy charge storage structure 392 may include a first dummy tunnel insulation pattern, a first dummy charge storage pattern, and a first dummy barrier pattern stacked sequentially from the outer wall of the first dummy channel 402 in the horizontal direction. Furthermore, the second dummy charge storage structure 394 may include a second dummy tunnel insulation pattern, a second dummy charge storage pattern, and a second dummy barrier pattern stacked sequentially from the outer wall of the second dummy channel 404 in the horizontal direction.

[0087] The upper portion of the fill pattern 410 and the channel 400 can be removed to form a first trench, and a capping layer can be formed on the fill pattern 410, the channel 400, the charge storage structure 390, and the fourth insulating interlayer 350, and can be planarized until the upper surface of the fourth insulating interlayer 350 is exposed to form a capping pattern 420 filling the first trench. The capping pattern 420 may include, for example, polysilicon doped with impurities.

[0088] When the first groove is formed, the first dummy fill pattern 412 and the first dummy channel 402, as well as the second dummy fill pattern 414 and the second dummy channel 404, can also be removed to form the second groove and the third groove, respectively. When the cap pattern 420 is formed, the first dummy cap pattern 422 and the second dummy cap pattern 424 can also be formed in the second groove and the third groove, respectively. Therefore, the first dummy cap pattern 422 and the second dummy cap pattern 424 can include the same material as the cap pattern 420.

[0089] The filling pattern 410, channel 400, charge storage structure 390, and cap pattern 420 can form a memory channel structure 430, which can correspond to... Figure 3 The memory channel structure 3220 shown is... Figure 4 The memory channel structure 4220 shown is illustrated.

[0090] The first dummy fill pattern 412, the first dummy channel 402, the first dummy charge storage structure 392, and the first dummy cap pattern 422 can form the first dummy memory channel structure 432. The second dummy fill pattern 414, the second dummy channel 404, the second dummy charge storage structure 394, and the second dummy cap pattern 424 can form the second dummy memory channel structure 434.

[0091] The first dummy memory channel structure 432 and the second dummy memory channel structure 434 may not be used as memory channel structures for memory cells, but may instead support the molding portion. Therefore, they may be referred to as the first support structure 432 and the second support structure 434, respectively, in the following text.

[0092] In an example embodiment, each of the memory channel structure 430, the first support structure 432, and the second support structure 434 may have the shape of a pillar extending in a first direction D1. Each of the memory channel structure 430 and the first support structure 432 may have, in a plan view, a shape such as a circle, an ellipse, a rectangle, or a rounded rectangle with rounded corners, while the second support structure 434 may have, in a plan view, a shape such as a "C" or a "U".

[0093] In an example embodiment, a first support structure 432 can be formed by the first step of the molding section, and a second support structure 434 can be formed by the second step of the molding section. The first support structure 432 can be formed to be arranged in each of the first steps in each of the second direction D2 and the third direction D3, and can have different numbers and / or layouts.

[0094] The second support structure 434 can be configured to be arranged in each of the second and third directions, D2 and D3, in each of the second and third steps. For example... Figure 10 The diagram illustrates two columns of second support structures, one comprising two second support structures 434 disposed in the second direction D2 and the other comprising three second support structures 434 disposed in the second direction D2 and spaced apart from each other in the third direction D3. However, the embodiment is not limited to this, and the number and arrangement of the second support structures 434 in each column of the second support structures can vary.

[0095] The first support structure 432 can be formed to be adjacent to the second support structure 434 in the region of each second step. In some cases, the first support structure 432 may not be formed. For example... Figure 10 The diagram shows a plurality of first support structures 432 arranged in the second direction D2. However, the embodiment is not limited to this, and the number and arrangement of the first support structures 432 in the region of each second step can also vary.

[0096] refer to Figure 11In an example embodiment, in a plan view, the second support structure 434 may include: a first extension portion 434a extending in a second direction D2; and a second extension portion 434b extending from the first extension portion 434a in a third direction D3. The second extension portion 434b may extend from each of the opposite ends of the first extension portion 434a in the second direction D2 in the third direction D3.

[0097] refer to Figure 12 In the example embodiment, the third support structure 436 may be formed in a region of each second step of the molding section, instead of the second support structure 434. The number and layout of the third support structures 436 in each region of the second step may vary.

[0098] In an example embodiment, each of the third support structures 436 may have a "T" shape in a plan view. In the plan view, the third support structure 436 may include: a first extension 436a extending in a second direction D2; and a second extension 436b extending from the first extension 436a in a third direction D3. The second extension 436b may extend from the middle of the first extension 436a in the second direction D2.

[0099] refer to Figure 13 Both the second support structure 434 and the third support structure 436 can be formed in the region of each second step of the molding section. The number and arrangement of the second support structure 434 and the third support structure 436 in the region of each second step of the molding section can vary.

[0100] like Figures 10 to 13 As shown in the plan view, unlike the first support structure 432 in the first dummy channel hole, which can have a circular or rectangular shape, each of the second support structure 434 in the second dummy channel hole and the third support structure 436 in the third dummy channel hole can have a "C", "U" or "T" shape.

[0101] As the height of the molding section increases, some of the first dummy channel holes extending through the molding section may not expose the upper surface of the CSP 240, which can be referred to as an "opening failure". To prevent the opening failure, each of the first dummy channel holes can be enlarged, but this may cause adjacent first dummy channel holes to connect with each other, making it impossible for the first support structure 432 to be properly formed in the first dummy channel holes.

[0102] However, in the example embodiment, each of the second and third dummy channel holes may not have a circular or rectangular shape, but rather a bumpy shape, thus reducing unopened defects. When compared to ArF lithography, bumpy shapes, such as “C,” “U,” or “T” shapes (which are more complex than circular or rectangular shapes), can be more easily formed using EUV lithography, which uses relatively shorter wavelength EUV light as the light source. Therefore, the second and third dummy channel holes can be easily formed.

[0103] The photomask used to achieve the above shapes can be designed to have only "C", "U", and "T" shapes. However, the second and third dummy channel holes, which can be formed by etching the target layer using a photoresist pattern, can have "C", "U", or "T" shapes with rounded corners. This photoresist pattern can be formed using a photolithography process with a photomask.

[0104] refer to Figure 10 In an example embodiment, multiple channels 400 may be formed in each of the second direction D2 and the third direction D3 to form a channel array. In an example embodiment, the channel array may include: a first channel column 400a, including channels 400 arranged in the second direction D2; and a second channel column 400b, including channels 400 arranged in the second direction D2 and spaced apart from the first channel column 400a in the third direction D3. The channels 400 included in the first channel column 400a may be positioned at an acute angle relative to the channels 400 included in the second channel column 400b in either the second direction D2 or the third direction D3.

[0105] The first channel column 400a and the second channel column 400b can be arranged alternately and repeatedly in the third direction D3. In an example embodiment, five first channel columns 400a and four second channel columns 400b can be alternately arranged in the third direction D3, which can form a channel group. Hereinafter, the four channel columns arranged in the channel group can be referred to in sequence as the first channel column 400a, the second channel column 400b, the third channel column 400c, and the fourth channel column 400d, and the channel column in the middle of the channel group can be referred to as the fifth channel column 400e; the other four channel columns can be referred to as the first channel column 400a, the second channel column 400b, the third channel column 400c, and the fourth channel column 400d, respectively.

[0106] Two channel groups disposed on the third-party D3 can form a channel block. The memory cells, each including a channel 400, a charge storage structure 390, and a gate electrode, as described below, can also correspondingly define memory groups and memory blocks. Erasing operations can be performed on a block-by-block basis in the vertical memory device. Figure 10Two memory blocks are shown positioned on a third-party D3. Each memory block may include two memory groups positioned on a third-party D3.

[0107] Some layers of the fourth interlayer insulating layer 350, insulating layer 310, and fourth sacrificial layer 320 can be etched to form a first opening extending in the second direction D2, and a second dividing pattern 440 can be formed in the first opening. The second dividing pattern 440 can extend through some channels of the channels 400, such as the upper portion of the channel 400 included in the fifth channel column 400e in each channel group. Moreover, the second dividing pattern 440 can also extend through the fourth interlayer insulating layer 350, the fourth sacrificial layer in the upper two horizontal fourth sacrificial layers 320, and the insulating layer in the upper two horizontal insulating layers 310, and can also extend upward through the insulating layer 310 in the third horizontal insulating layer 310. The second dividing pattern 440 can extend in the second direction D2 on the first region I and the second region II of the substrate 100, and can extend through the upper two stepped layers of the molding portion. Therefore, the upper two horizontal fourth sacrificial layers 320 of the molding portion can be divided in the third direction D3 by the second dividing pattern 440.

[0108] refer to Figure 17 and Figure 18 The fifth interlayer insulating layer 450 can be formed on the fourth interlayer insulating layer 350, the cap pattern 420, and the second dividing pattern 440. The second opening 460 and the third opening 465 can be formed through the third to fifth interlayer insulating layers 340, 350, and 450, and the molding portion, by a dry etching process.

[0109] In an example embodiment, the second opening 460 may extend in a second direction D2 on the first region I and the second region II of the substrate 100, and may extend to opposite ends of the molded portion having a stepped shape in the second direction D2. In an example embodiment, a plurality of second openings 460 may be spaced apart from each other in a third direction D3. Therefore, the molded portion may be divided into multiple portions by the second openings 460 in the third direction D3. In an example embodiment, each of the second openings 460 may be formed between memory blocks. Therefore, the memory blocks may be divided by the second openings 460 to be spaced apart from each other in the third direction D3.

[0110] Once the second opening 460 is formed, the insulating layer 310 and the fourth sacrificial layer 320 of the molded portion can be divided into a first insulating pattern 315 and a fourth sacrificial pattern 325, both of which can extend in the second direction D2.

[0111] In an example embodiment, a third opening 465 may extend in a second direction D2 on a first region I of the substrate 100. A plurality of third openings 465 may be spaced apart from each other in the second direction D2 on a second region II of the substrate 100. The third openings 465 arranged in the second direction D2 may be formed between adjacent second openings in the second opening 460 in a third direction D3. In an example embodiment, third openings 465 may be formed between memory groups in each memory block of a memory block spaced apart by second openings 460. Therefore, memory groups may be spaced apart from each other in the third direction D3 by the third opening 465 of each memory block in the memory block.

[0112] However, as in, for example Figure 17 As shown, the third openings 465 may be spaced apart from each other in the second direction D2, and may differ from the second openings 460 that extend continuously in the second direction D2 to the opposite ends of the molding portion in the second direction D2, so that the memory groups in each memory block may not be completely divided by the third openings 465. In an example embodiment, the portion of the molding portion in the third openings 465 between adjacent third openings in the second direction D2 may partially overlap with the first dividing pattern 330 in the first direction D1.

[0113] The third opening 465 can extend continuously in the second direction D2 on the first region I of the substrate 100, and can extend to the opposite ends of the upper two stepped layers of the molding portion on the second region II of the substrate 100 in the second direction D2. Therefore, the upper two horizontal fourth sacrificial patterns 325 can be divided in the third direction D3 by the third opening 465 and the second dividing patterns 440 on the opposite sides of the third opening 465 in the third direction D3.

[0114] When the molding portion is divided in the third direction D3 to extend in the second direction D2 during the etching process used to form the second opening 460 and the third opening 465, the molding portion may not tilt or drop due to the first support structure to the third support structure 432, 434 and 436 and the memory channel structure 430 extending through it.

[0115] In an example embodiment, an etching process may be performed until the second opening 460 and the third opening 465 expose the upper surface of the first support layer 300 and extend further through the upper part of the first support layer 300.

[0116] The first spacer layer can be formed on the sidewalls of the second opening 460 and the third opening 465 and on the upper surface of the fifth insulating interlayer 450, and can be anisotropically etched thereon so that portions of the first spacer layer at the bottom of the second opening 460 and the third opening 465 can be removed to form the first spacer 470, as shown. Figure 19 As shown in the diagram. Therefore, the surface of the first support layer 300 can be partially exposed. The exposed first support layer 300 and a portion of the first sacrificial layer structure 140 beneath it can be removed to downwardly widen the second opening 460 and the third opening 465. Thus, the second opening 460 and the third opening 465 can expose the upper surface of the CSP 240 and further extend through the upper portion of the CSP 240.

[0117] In an example embodiment, the first spacer 470 may include, for example, undoped polysilicon. When the first sacrificial layer structure 290 is partially removed, the sidewalls of the second opening 460 and the third opening 465 may be covered by the first spacer 470, so the first insulating pattern 315 and the fourth sacrificial pattern 325 included in the molding portion may not need to be removed.

[0118] refer to Figure 19 The first sacrificial layer structure 290 exposed by the second opening 460 and the third opening 465 can be removed, for example, by a wet etching process to form the first gap 295. The wet etching process can be performed using, for example, hydrofluoric acid or phosphoric acid.

[0119] When the first gap 295 is formed, the lower portion of the first support layer 300 and the upper surface of the CSP 240 can be exposed. Furthermore, the sidewalls of the charge storage structure 390 can be partially exposed by the first gap 295, and the exposed sidewalls of the charge storage structure 390 can be removed to expose the outer sidewalls of the channel 400. Therefore, the charge storage structure 390 can be divided into: an upper portion extending through the molding portion to cover most of the outer sidewalls of the channel 400; and a lower portion covering the lower surface of the channel 400 on the CSP 240.

[0120] refer to Figure 20 After removing the first spacer 470, a channel connection layer can be formed on the sidewalls of the second opening 460 and the third opening 465, and in the first gap 295. A portion of the channel connection layer in the second opening 460 and the third opening 465 can be removed to form a channel connection pattern 480 in the first gap 295. Once the channel connection pattern 480 is formed, the channels 400 between adjacent second and third openings in the third direction D3 of the second opening 460 and the third opening 465—that is, the channels 400 included in each channel group—can be connected to each other. The channel connection pattern 480 can include, for example, polysilicon doped with n-type impurities or undoped polysilicon.

[0121] Air gap 485 can be formed in channel connection pattern 480.

[0122] refer to Figure 21The second sacrificial layer structure 520 and the third sacrificial layer structure 525 can be formed in the second opening 460 and the third opening 465, respectively.

[0123] The second sacrificial layer structure 520 and the third sacrificial layer structure 525 can be formed by the following operations: forming an etch stop layer and a second spacer layer sequentially on the sidewalls of the second opening 460 and the third opening 465 and on the exposed upper surface of the CSP 240; forming a fifth sacrificial layer on the second spacer layer to fill the second opening 460 and the third opening 465; and planarizing the fifth sacrificial layer, the second spacer layer and the etch stop layer until the upper surface of the fifth insulating interlayer 450 is exposed.

[0124] The second sacrificial layer structure 520 may include a first etch stop pattern 490, a second spacer 500, and a fifth sacrificial pattern 510 stacked in sequence. The third sacrificial layer structure 525 may include a second etch stop pattern 495, a third spacer 505, and a sixth sacrificial pattern 515 stacked in sequence.

[0125] The etch stop layer may include a material that is etch-selective for the fourth sacrificial pattern 325, such as an oxide (e.g., silicon oxide). The second spacer layer may include, for example, a nitride (e.g., silicon nitride). The fifth sacrificial layer may include, for example, polysilicon or silicon oxide.

[0126] refer to Figure 22 and Figure 23 The second support layer 530 can be formed on the fifth insulating interlayer layer 450, the second sacrificial layer structure 520, and the third sacrificial layer structure 525, and can be partially etched to form the fourth opening 540 and the fifth opening 545, respectively.

[0127] In an example embodiment, the fourth opening 540 may overlap with the second sacrificial layer structure 520 in the first direction D1. (See example...) Figure 22 The fourth opening 540 may extend continuously in the second direction D2 on the second region II of the substrate 100, and the plurality of fourth openings 540 may be spaced apart from each other in the second direction D2 on the first region I of the substrate 100. However, the embodiments are not limited thereto, and even on the second region II of the substrate 100, the plurality of fourth openings 540 may be spaced apart from each other in the second direction D2. In an example embodiment, the fourth opening 540 may have a width in the third direction D3 that is greater than the width of the second sacrificial layer structure 520; however, the embodiments are not limited thereto.

[0128] In an example embodiment, the fifth opening 545 may overlap with the third sacrificial layer structure 525 in the first direction D1. Therefore, a plurality of fifth openings 545 may be spaced apart from each other in the second direction D2 on the second region II of the substrate 100. Furthermore, even on the first region I of the substrate 100, a plurality of fifth openings 545 may be spaced apart from each other in the second direction D2 on the same third sacrificial layer structure 525. In an example embodiment, the fifth opening 545 may have a width in the third direction D3 greater than the width of the third sacrificial layer structure 525, but the embodiment is not limited to this.

[0129] In an example embodiment, the fourth opening 540 and the fifth opening 545 may be arranged in a z-shaped pattern on the first region I of the substrate 100 in the second direction D2. The fourth opening 540 and the fifth opening 545 may partially overlap each other in the third direction D3.

[0130] The second support layer 530 may include oxides, such as silicon oxide.

[0131] refer to Figure 24 The second sacrificial layer structure 520 and the third sacrificial layer structure 525 can be removed by etching through the fourth opening 540 and the fifth opening 545, so that the second opening 460 and the third opening 465 can be formed again.

[0132] As described above, the fourth opening 540 and the fifth opening 545 may not be fully exposed, but rather partially cover the upper surfaces of the second sacrificial layer structure 520 and the third sacrificial layer structure 525, respectively, on the first region I of the substrate 100. Therefore, even if the second opening 460 and the third opening 465 are re-formed by an etching process, the upper surfaces of the second sacrificial layer structure 520 and the third sacrificial layer structure 525 can still be at least partially covered by the second support layer 530. Thus, even if the upper surface of the molded portion is high and its extension length in the second direction D2 is large, the molded portion may not tilt or descend in the third direction D3, because the second support layer 530 at least partially covers the portions of the molded portion where the second opening 460 and the third opening 465 are formed.

[0133] Multiple third openings 465 may be spaced apart from each other in the second direction D2 on the second region II of the substrate 100, such that a portion of the molding portion remains between the third openings 465, and the first support structure to the third support structure 432, 434 and 436 extend through the molding portion, so that the molding portion may not tilt or descend in the third direction D3 due to this portion of the molding portion and the first support structure to the third support structure 432, 434 and 436.

[0134] In the example embodiment, the second sacrificial layer structure 520 and the third sacrificial layer structure 525 can be removed by a wet etching process.

[0135] An oxidation process can be performed on a layer structure including silicon and exposed by a second opening 460 and a third opening 465 to form a protective layer 550. In an example embodiment, when the oxidation process is performed, the protective layer 550 can be formed on the upper surface of the CSP 240 exposed by the second opening 460 and the third opening 465, the sidewalls of the channel connection pattern 480, and the sidewalls of the first support layer 300. The protective layer 550 may include, for example, silicon oxide.

[0136] refer to Figure 25 and Figure 26 The fourth sacrificial pattern 325 exposed by the second opening 460 and the third opening 465 can be removed to form a second gap 560 between the first insulating patterns 315. The outer walls of the charge storage structure 390 included in the memory channel structure 430, and the outer walls of the first dummy charge storage structure 392 and the second dummy charge storage structure 394 included in the first support structure 432 and the second support structure 434, can be partially exposed by the second gap 560, respectively.

[0137] In an example embodiment, the fourth sacrificial pattern 325 can be removed by a wet etching process using, for example, phosphoric acid (H3PO4) or sulfuric acid (H2SO4). The wet etching process can be performed through the second opening 460 and the third opening 465. The portion of the fourth sacrificial pattern 325 between the second opening 460 and the third opening 465 can be completely removed by an etching solution provided in two ways through both the second opening 460 and the third opening 465. However, the etching solution can be provided only through the second opening 460 (in the second region II of the substrate 100, in the region of the second opening 460 where no third opening 465 is formed between adjacent second openings in the third direction D3), so the fourth sacrificial pattern 325 may not be completely removed but partially retained, which can be referred to as the third insulating pattern 327. Furthermore, the portion of the first insulating pattern 315 that overlaps with the third insulating pattern 327 in the first direction D1 can be referred to as the second insulating pattern 317. The second insulating pattern 317 and the third insulating pattern 327, stacked alternately and repeatedly in the first direction D1, can form an insulating pattern structure 600.

[0138] The insulating pattern structure 600 may extend through a portion of the molded portion on the second region II of the substrate 100 and may have a rectangular, elliptical, circular shape, or a rectangular shape with recessed opposite sides in the second direction D2. In an example embodiment, the insulating pattern structure 600 may extend through a second step in each molded portion (which has a relatively large length in the second direction D2). In an example embodiment, a second support structure 434 and / or a third support structure 436 may be formed between each second opening in the second opening 460 and the insulating pattern structure 600, and a first support structure 432 may also be formed as described above.

[0139] refer to Figure 27 and Figure 28 The second barrier layer 570 may be formed on: the outer wall of the charge storage structure 390 exposed by the second opening 460 and the third opening 465; the outer walls of the first dummy charge storage structure 392 and the second dummy charge storage structure 394 included in the first support structure 432 and the second support structure 434 exposed by the second opening 460 and the third opening 465; the inner wall of the second gap 560; the surface of the first insulating pattern 315; the upper surface of the protective layer 550; the sidewalls and upper surface of the fifth insulating interlayer 450; and the sidewalls and upper surface of the second support layer 530.

[0140] A gate electrode layer may be formed on the second barrier layer 570. The gate electrode layer may include a gate barrier layer and a gate conductive layer stacked sequentially. The gate electrode layer may include a low-resistance metal, such as tungsten, titanium, tantalum, platinum, etc. The gate barrier layer may include a metal nitride, such as titanium nitride, tantalum nitride, etc. The second barrier layer 570 may include a metal oxide, such as aluminum oxide, hafnium oxide, zirconium oxide, etc.

[0141] The gate electrode layer can be partially removed to form the gate electrode in each of the second gaps 560. In an example embodiment, the gate electrode layer can be partially removed by a wet etching process. Therefore, the fourth sacrificial pattern 325 in the molded portion (which has a stepped shape including a fourth sacrificial pattern 325 and a first insulating pattern 315 stacked sequentially as a stepped layer) can be replaced by the gate electrode and a second barrier layer 570 covering the lower and upper surfaces of the gate electrode.

[0142] In an example embodiment, the gate electrode may extend in the second direction D2. A plurality of gate electrodes 109 may be spaced apart from each other in the first direction D1 to form a gate electrode structure. The gate electrodes may be stacked in a stepped shape, wherein the extension length in the second direction D2 decreases in a stepped manner from the lowest level to the highest level. The end of each gate electrode in the second direction D2 that does not overlap with the upper gate electrode in the first direction D1, i.e., the step of each step layer in the stepped layer, may be referred to as a pad. The gate electrode structure may include: a first pad having a relatively short length in the second direction D2; and a second pad having a relatively large length in the second direction D2. The number of first and second pads is not limited.

[0143] Multiple gate structures can be formed on the third direction D3. The gate electrode structures can be spaced apart from each other on the third direction D3 by the second opening 460. As described above, the third opening 465 may not extend to the opposite ends of the gate electrode structures on the second direction D2, but multiple third openings 465 can be spaced apart from each other on the second direction D2, so the gate electrode structures may not be separated by the third openings 465. However, one of the gate electrodes in the lowest horizontal direction can be separated on the third direction D3 by the third opening 465, the first dividing pattern 330, and the insulating pattern structure 600, and each of the gate electrodes in the upper two horizontal directions can be separated on the third direction D3 by the third opening 465 and the second dividing pattern 440.

[0144] In an example embodiment, the gate electrode structure may include a first gate electrode 752, a second gate electrode 754, and a third gate electrode 756 stacked sequentially in a first direction D1. In an example embodiment, the first gate electrode 752 may be used as a ground select line (GSL), the third gate electrode 756 may be used as a string select line (SSL), and the second gate electrode 754 may be formed at multiple horizontal positions between the first gate electrode 752 and the third gate electrode 756, and may be used as word lines respectively.

[0145] In an example embodiment, each memory block in the memory block between adjacent second openings in the second direction D2 within the second opening 460 may include two GSLs, one word line, and four SSLs at each level. However, the embodiment is not limited thereto.

[0146] refer to Figures 29 to 31 A third dividing pattern 580 filling the second opening 460 and the fourth opening 540, and a fourth dividing pattern 585 filling the third opening 465 and the fifth opening 545, can be formed on the second barrier layer 570 and can be planarized until the upper surface of the second support layer 530 is exposed. Therefore, the second barrier layer 570 can be transformed into the second barrier pattern 575.

[0147] The third dividing pattern 580 and the fourth dividing pattern 585 may include oxides, such as silicon oxide.

[0148] refer to Figure 32 and Figure 33 The first upper contact plug to the third upper contact plug 610, 620 and 622 can be formed by the second support layer 530, the third to fifth insulating interlayer layers 340, 350 and 450 on the second region II of the substrate 100 and the first insulating pattern 315.

[0149] The first to third upper contact plugs 610, 620, and 622 can respectively contact the pads of the third gate electrode 756, the second gate electrode 754, and the first gate electrode 752. In an example embodiment, each of the first to third upper contact plugs 610, 620, and 622 can be formed in the area surrounded by the first support structure 432 in each of the first and second pads of the gate electrode structure. For example, the first support structure 432 can be located at the vertices of a rectangle in a plan view, and each of the first to third upper contact plugs 610, 620, and 622 can be formed inside the rectangle. However, the number and arrangement of the first to third upper contact plugs 610, 620, and 622 are not limited to this. Figure 32 The quantities and layout shown.

[0150] refer to Figure 34 and Figure 35 The sixth insulating interlayer 630 may be formed on the second support layer 530 and the first upper contact plug to the third upper contact plug 610, 620 and 622.

[0151] Through-holes 650 can be formed by contacting the upper surface of the eighth lower wiring 222 through an insulating pattern structure 600, a first support layer 300, a channel connection pattern 480, a CSP 240, and a second insulating interlayer 170. Multiple through-holes 650 can be formed to be spaced apart from each other in the area where the insulating pattern structure 600 is formed. In the figure, six through-holes 650 are formed in each area, but the embodiment is not limited thereto.

[0152] A fourth insulating pattern 640 may be formed on the sidewall of the via 650 and may be electrically connected to the first support layer 300, the channel connection pattern 480, and the CSP 240. However, the via 650 may extend through the insulating pattern structure 600 (i.e., through the second insulating pattern 317 and the third insulating pattern 327) to electrically insulate it from the first gate electrode to the third gate electrodes 752, 754, and 756. Therefore, if additional insulating patterns are formed on the sidewall of the first support layer 300, the channel connection pattern 480, and the CSP 240, the fourth insulating pattern 640 may not be formed.

[0153] The first upper contact plugs to the third upper contact plugs 610, 620, and 622, and the through-hole 650 may include, for example, metal, metal nitride, metal silicide, etc. The fourth insulating pattern 640 may include oxides, such as silicon oxide.

[0154] A common source contact plug can also be formed by the portion of the first support layer 300 that is not covered by the gate electrode structure.

[0155] refer to Figures 36 to 39 The seventh insulating interlayer 660 can be formed on the sixth insulating interlayer 630, the fourth insulating pattern 640, and the through hole 650. The fourth upper contact plug 672, the fifth upper contact plug 674, the sixth upper contact plug, the seventh upper contact plug 680, and the eighth upper contact plug 690 can be formed.

[0156] The fourth upper contact plug 672, the fifth upper contact plug 674, and the sixth upper contact plug can extend through the sixth interlayer insulating layer 630 and the seventh interlayer insulating layer 660 to contact the upper surfaces of the first upper contact plugs to the third upper contact plugs 610, 620, and 622, respectively. The seventh upper contact plug 680 can extend through the seventh interlayer insulating layer 660 to contact the upper surface of the through hole 650. The eighth upper contact plug 690 can extend through the second support layer 530 and the fifth to seventh interlayer insulating layers 450, 630, and 660 to contact the upper surface of the cap pattern 420.

[0157] The eighth insulating interlayer 700 can be formed on the seventh insulating interlayer 660, the fourth upper contact plug 672 and the fifth upper contact plug 674, the sixth upper contact plug, the seventh upper contact plug 680 and the eighth upper contact plug 690.

[0158] A first upper wiring 712, a second upper wiring 714, a third upper wiring, a fourth upper wiring 720, and a fifth upper wiring 730 can be formed. The first upper wiring 712 and the second upper wiring 714 can contact the upper surfaces of the fourth upper contact plug 672 and the fifth upper contact plug 674. The third upper wiring can contact the upper surface of the sixth upper contact plug. The fourth upper wiring 720 and the fifth upper wiring 730 can contact the upper surfaces of the seventh upper contact plug 680 and the eighth upper contact plug 690, respectively.

[0159] In the example embodiment, the fifth upper wiring 730 may extend onto D3. Multiple fifth upper wirings 730 may be formed. The fifth upper wiring 730 may be used as a bit line. Alternatively, additional upper vias and a sixth upper wiring may be formed on the fifth upper wiring 730, and the sixth upper wiring may be used as a bit line.

[0160] The number and layout of the first upper wiring 712, the second upper wiring 714, the third upper wiring, and the fourth upper wiring 720 on the second region II of the substrate 100 can vary.

[0161] Semiconductor devices can be manufactured using the processes described above.

[0162] As described above, even with the formation of the second opening 460 and the third opening 465 (both extending through the molding in the second direction D2), the molding portion will not tilt or sag due to the extension of the first support structure to the third support structures 432, 434, and 436 through the molding portion. In the plan view, unlike the first support structure 432 which has a circular or rectangular shape, the second support structure 434 and the third support structure 436 can have an uneven shape (e.g., a "C", "U", or "T" shape), and can reduce the failure of unopened sections (wherein, the second and third dummy channel holes used to form the second and third support structures 434 and 436, respectively, do not expose the upper surface of the CSP 240). Therefore, the second support structure 434 and the third support structure 436, which respectively fill the second and third dummy channel holes, can stably support the molding portion.

[0163] Specifically, the dummy channel holes between the insulating pattern structure 600 and the second opening 460 may be prone to unopened failures. However, each dummy channel hole in the dummy channel holes can have an uneven shape, so that a second support structure 434 and a third support structure 436 with stable structures can be formed.

[0164] Semiconductor devices can have the following structural characteristics.

[0165] refer to Figure 34 as well as Figures 36 to 39The semiconductor device may include: a lower circuit pattern located on a substrate 100 including a first region I and a second region II at least partially surrounding the first region I; a CSP 240 located above the lower circuit pattern; a gate electrode structure including first to third gate electrodes 752, 754, and 756, each of the first to third gate electrodes 752, 754, and 756 extending in a second direction D2 and spaced apart from each other in a first direction D1 on the CSP 240; a memory channel structure 430 including a channel 400 extending in the first region I of the substrate 100 through the gate electrode structure in the first direction D1 to contact the upper surface of the CSP 240 and a charge storage structure 390 on the outer sidewall of the channel 400; a third dividing pattern 580 extending in the second direction D2 on each of the opposite sides of the gate electrode structure in the third direction D3; and an insulating pattern structure 600 extending through the CSP. A portion of the gate electrode structure on 240; a through-hole 650 extending in a first direction through the insulating pattern structure 600 and CSP 240 to contact and electrically connect to one of the lower circuit patterns; contact plugs 610, 620, and 622 extending in the first direction D1 to contact the ends (i.e., pads) of the first gate electrode to the third gate electrodes 752, 754, and 756 in the second direction D2; a first support structure 432 extending in the first direction D1 through the gate electrode structure to contact the upper surface of CSP 240, which may be adjacent to the contact plugs 610, 620, and 622; and a second or third support structure extending in the first direction D1 through the portion of the gate electrode structure between the insulating pattern structure 600 and the third dividing pattern 580.

[0166] Figure 40 This is a plan view illustrating a semiconductor device according to an example embodiment, which may correspond to... Figure 34 This semiconductor device can be used with Figure 34 as well as Figures 36 to 39 The semiconductor devices are basically the same or similar, except that some of the first support structures in the first support structure 432 are replaced by the fourth support structure 433.

[0167] refer to Figure 40 Some of the first support structures in the first support structure 432 can be replaced with a fourth support structure 433. The fourth support structure 433 can surround a first upper contact plug extending through each of the first and second pads of the gate electrode structure to each of the third upper contact plugs 610, 620, and 622. In an example embodiment, each fourth support structure 433 can have a “C” or “U” shape in a plan view.

[0168] like Figure 40As shown, the fourth support structure 433 may be formed on opposite sides of each of the first to third upper contact plugs 610, 620, and 622 in the third direction D3. Alternatively, the fourth support structure 433 may be formed on opposite sides of each of the first to third upper contact plugs 610, 620, and 622 in the second direction D2.

[0169] In the plan view, a fourth support structure 433 with a "C" or "U" shape can be formed instead of the first support structure 432 with a circular or rectangular shape. Therefore, a fourth dummy channel hole for forming the fourth support structure 433 can be formed to contact the upper surface of the CSP 240, so that the fourth support structure 433 can be formed in the fourth dummy channel hole to have a stable structure.

[0170] In other example embodiments, each of the fourth support structures 433 may have a shape other than a circle or rectangle in the plan view, instead of a "T". Alternatively, some of the fourth support structures 433 may have a "C" or "U" shape, while others may have a "T" shape in the plan view.

[0171] In other example embodiments, all of the first support structures 432 can be replaced with the fourth support structure 433.

[0172] Figure 41 This is a plan view illustrating a semiconductor device according to an example embodiment, which may be... Figure 5 A planar diagram of region W in the image. This semiconductor device can be used with... Figure 34 as well as Figures 36 to 39 The semiconductor devices are basically the same or similar, except that the insulating pattern structure 600, the through hole 650, and the first support structure 432 and the second support structure 434 can even be formed on the first region I of the substrate 100.

[0173] refer to Figure 41 An insulating pattern structure 600 may be formed between third dividing patterns 580, which may be formed between adjacent second openings 460 in a second opening 460 in a dummy region on a first region I of the substrate 100, in a third direction D3. A via 650 may extend through the insulating pattern structure 600 to electrically connect to a lower circuit pattern.

[0174] Furthermore, a first support structure 432 and a second support structure 434 may be formed between the insulating pattern structure 600 and the third dividing pattern 580, which may have a similar or identical layout to the first support structure 432 and the second support structure 434 in each second pad on the second region II of the substrate 100. In an example embodiment, a third support structure 436 may be formed instead of the second support structure 434, or both the second support structure 434 and the third support structure 436 may be formed.

[0175] Figure 42A and Figure 42B This is a plan view illustrating a semiconductor device according to an example embodiment, which may be... Figure 10 The planar diagram of region Z in the diagram can correspond to... Figures 11 to 13 This semiconductor device can be used with Figure 34 as well as Figures 36 to 39 The semiconductor devices are basically the same or similar, but include a fifth support structure 437 and a sixth support structure 438 that replace the second support structure 434.

[0176] refer to Figure 42A A fifth support structure 437 having a "C" or "U" shape and a sixth support structure 438 having a "2" or "5" shape can be formed between the third dividing pattern 580 and the insulating pattern structure 600 in the plan view. A first support structure 432 can also be formed.

[0177] In an example embodiment, the fifth support structure 437 may have a "C" or "U" shape, wherein the recess facing the third direction D3 extends in the second direction D2. Two sixth support structures 438 (each may have a "5" or "2" shape extending in the second direction D2 and may be arranged in a mirror-image manner spaced apart from each other in the second direction D2) are arranged such that the ends of the two sixth support structures 438 face the recess of the fifth support structure 437. The fifth support structure 437 and the sixth support structure 438 may be spaced apart from each other in the third direction D3.

[0178] In an example embodiment, the fifth support structure 437 may include: a first extension portion 437a extending in a second direction D2; and a second extension portion 437b extending from opposite ends of the first extension portion 437a in the second direction D2 in a third direction D3. Each of the second extension portions 437b may extend toward a corresponding sixth support structure 438.

[0179] In an example embodiment, the sixth support structure 438 may include a first extension 438a and a second extension 438c, which are spaced apart from each other in the third direction D3 and not aligned with each other in the second direction D2. Furthermore, the sixth support structure 438 may include a third extension 438b and a fourth extension 438d, spaced apart from each other in the second direction D2. The end of the first extension 438a in the second direction D2 may overlap with the corresponding end of the second extension 438c in the second direction D2 in the third direction D3. The fourth extension 438d may connect the ends of the first extension 438a and the second extension 438c, which may be adjacent to and overlap each other in the third direction D3. Each of the third extensions 438b may extend in the third direction D3 from the ends of the first extension 438a and the second extension 438c, which may be spaced apart from each other and may not overlap in the third direction D3.

[0180] In the example embodiment, a plurality of sixth support structures 438 may be spaced apart from each other in the second direction D2, and one of the third extension portions 438b of each of two adjacent sixth support structures 438 in the second direction D2 may face the first extension portion 437a of the fifth support structure 437 in the third direction D3.

[0181] refer to Figure 42B A fifth support structure 437, which has a "C" or "U" shape in the plan view, can be formed between the third dividing pattern 580 and the insulating pattern structure 600. A first support structure 432 can also be formed.

[0182] In an example embodiment, a plurality of fifth support structures 437 may be arranged in a second direction D2 to form a support structure column, and the first and second support structure columns may be spaced apart from each other in a third direction D3. The fifth support structures included in the first and second support structure columns may be arranged in a zigzag pattern, for example, overlapping alternately in the second direction D2. In an example embodiment, each second extension portion 437b of each fifth support structure 437 included in the first support structure column may extend toward a first extension portion 437a of a corresponding fifth support structure 437 in the second support structure column, and each second extension portion 437b of each fifth support structure 437 included in the second support structure column may extend toward a first extension portion 437a of a corresponding fifth support structure 437 in the first support structure column.

[0183] Because the second and third dummy channel holes used to form the second support structure 434 and the third support structure 436, the fifth and sixth dummy channel holes used to form the fifth support structure 437 and the sixth support structure 438 can have fewer unopened faults, thus the fifth support structure 437 and the sixth support structure 438 can have a stable structure.

[0184] For reference Figures 10 to 16 As shown, the fifth support structure 437 and the sixth support structure 438 can also be formed in the region of the second pad on the second region II of the substrate 100 where the first gate electrode 752, the second gate electrode 754 and the third gate electrode 756 are formed, or they can be formed in a dummy region on the first region I of the substrate 100, as shown in the reference. Figure 41 As explained.

[0185] Figure 43 This illustrates the relationship between the fifth support structure 437 and the sixth support structure 438, as well as the reference. Figure 25 and Figure 26 A plan view illustrating the etching process of forming the second gap 560 by removing the fourth sacrificial pattern 325.

[0186] refer to Figure 43 as well as Figure 25 and Figure 26 A wet etching process can be performed using an etching solution, thereby removing the fourth sacrificial pattern 325 through the second opening 460 and the third opening 465 to form the second gap 560.

[0187] The etching solution supplied from the second opening 460 along the third direction to D3 can move the same distance in both directions during the same time period, thereby removing the fourth sacrificial pattern 325. A first support structure 432 can be formed on one side of the second opening 460, and the etching solution can pass through... Figure 43 The first path P1 shown moves along the third direction D3. A fifth support structure 437 and a sixth support structure 438 can be formed on the other side of the second opening 460, and the etching solution can pass through... Figure 43 The second path P2 shown moves along the third direction D3.

[0188] like Figure 43As shown, the fifth support structure 437 and the sixth support structure 438 can be arranged adjacent to each other, so that the second path P2 through which the etching solution from the second opening 460 moves can be curved (e.g., meandering) due to the fifth support structure 437 and the sixth support structure 438. Therefore, the distance traveled by the etching solution through the second path P2 in the same amount of time can be smaller compared to the first path P1 through which the etching solution can move directly between the first support structures 432 from the second opening 460. Therefore, the second distance d2 from the second opening 460 to the insulating pattern structure 600 in the region including the fifth support structure 437 and the sixth support structure 438 (which can be formed in areas not reached by the etching solution) can be smaller than the first distance d1 from the second opening 460 to the insulating pattern structure 600 in the region including the first support structure 432.

[0189] Therefore, by replacing some of the first support structures in the first support structure 432 adjacent to the second opening 460 with the fifth support structure 437 and the sixth support structure 438, the length of the insulating pattern structure 600 between adjacent second openings 460 in the third direction D3 can be increased, which can increase the area of ​​the insulating pattern structure 600. Furthermore, the layout of the insulating pattern structure 600, as well as the second opening 460 and the third opening 465, can be adjusted. These features can be combined... Figure 42A The fifth support structure 437 and the sixth support structure 438 shown may be combined. Figure 42B It is obtained by the fifth support structure 437 shown.

[0190] Figure 44 This is a cross-sectional view illustrating a semiconductor device according to an example embodiment, which may correspond to... Figure 34 In addition to the fourth dividing pattern 585 and the insulating pattern structure 600, this semiconductor device can be coupled with... Figure 34 as well as Figures 36 to 39 The semiconductor devices are basically the same or similar.

[0191] refer to Figure 44 In the two memory blocks disposed on the third direction D3, the insulating pattern structure 600 and the via 650 extending through the insulating pattern structure 600 in the first direction D1 can be formed at each second pad of the gate electrode structure included in the first memory block, and a fourth dividing pattern 585 can be formed at each second pad of the gate electrode structure included in the second memory block, spaced apart from the fourth dividing pattern 585 at the first pad of the gate electrode structure.

[0192] A second support structure 434 and / or a third support structure 436 may be formed between the third partitioning pattern 580 and the insulating pattern structure 600 in the first memory block, while a first support structure 432 may be formed between the third partitioning pattern 580 and the fourth partitioning pattern 585 in the second memory block.

[0193] exist Figure 44 In the first memory block, two adjacent fourth partition patterns 585 on the third direction D3 are shown, but the embodiment is not limited to this. For example, if in the reference Figure 42A , Figure 42B and Figure 43 The area near the third dividing pattern 580 forms the fifth support structure 437 and the sixth support structure 438. Therefore, the insulating pattern structure 600 can have a large area, thus forming a unique fourth dividing pattern 585 between the third dividing patterns 580.

[0194] Typically, during the etching process that forms the second gap 560 by removing the fourth sacrificial pattern 325, in order to obtain the desired area of ​​the insulating pattern structure 600, the distance between the third dividing patterns 580 can be increased, taking into account the distance the etching solution travels along the third direction D3, so that two or more fourth dividing patterns 585 can be arranged. However, in the example embodiment, the fifth support structure 437 and the sixth support structure 438 can be arranged to reduce the travel distance of the etching solution, so that the insulating pattern structure 600 can have a sufficient area even without increasing the distance between the third dividing patterns 580. Therefore, the distance between the third dividing patterns 580 can be reduced, and the number of third dividing patterns 580 can be reduced.

[0195] Figure 45 This is a cross-sectional view illustrating a semiconductor device according to an example embodiment, which may correspond to... Figure 37 In addition to the memory channel structure 430, the channel connection pattern 480, and the first support layer 300, this semiconductor device can be coupled with... Figure 34 as well as Figures 36 to 39 The semiconductor devices are basically the same or similar.

[0196] The memory channel structure 430 may also include a semiconductor pattern 590 on the substrate 100. A charge storage structure 390, a channel 400, a fill pattern 410, and a cap pattern 420 may be formed on the semiconductor pattern 590.

[0197] Semiconductor pattern 590 may include, for example, monocrystalline silicon or polycrystalline silicon. In an example embodiment, the upper surface of semiconductor pattern 590 may be formed at a height between the lower and upper surfaces of the first insulating pattern 315 and the first gate electrode 752 and the second gate electrode 754. Charge storage structure 390 may have a cup-like shape with its central lower surface open (e.g., at the bottom of charge storage structure 390) and may contact the edge upper surface of semiconductor pattern 590. Channel 400 may have a cup-like shape (e.g., at the bottom of channel 400) and may contact the upper surface of the central semiconductor pattern 590. Therefore, channel 400 may be electrically connected to CSP 240 via semiconductor pattern 590.

[0198] It is not necessary to form a channel connection pattern 480 and a first support layer 300 between CSP 240 and the first gate electrode 752. In an example embodiment, one of the first insulating patterns 315 between the first gate electrode 752 and the second gate electrode 754 may have a greater thickness than the other first insulating patterns in the first insulating pattern 315 located in an upper layer.

[0199] Figure 46 This is a cross-sectional view of a semiconductor device according to an example embodiment, which can correspond to Figure 37 In addition to the memory channel structure 430, this semiconductor device can be used with... Figure 34 as well as Figures 36 to 39 The semiconductor devices are basically the same or similar.

[0200] The memory channel structure 430 may include a lower portion and an upper portion stacked sequentially. Each of the lower and upper portions may have a width that gradually increases from its bottom to its top. In an example embodiment, the lower surface of the upper portion of the memory channel structure 430 may have a smaller area than the area of ​​the upper surface of the lower portion of the memory channel structure 430.

[0201] exist Figure 46 In the memory channel structure 430, there are two parts, namely, a lower part and an upper part. However, the embodiments are not limited to this, and the memory channel structure 430 may include more than two parts. Each part of the memory channel structure 430 may have a width that gradually increases from its bottom to its top, and the area of ​​the lower surface of the upper part may be smaller than the area of ​​the upper surface of the lower part directly below the upper part.

[0202] Figure 47 This is a cross-sectional view of a semiconductor device according to an example embodiment, which can correspond to Figure 37 This semiconductor device can be used with Figure 34 as well as Figures 36 to 39The semiconductor devices are basically the same or similar, but the upper structure is inverted and a junction structure is formed. The lower circuit pattern can be similar to... Figure 4 The peripheral circuit wiring 4110 corresponds to this. The circuit structure, including the circuit pattern below, can be compared with... Figure 4 The first structure 4100 corresponds to this.

[0203] In an example embodiment, the ninth to twelfth interlayer insulating layers 800, 820, 840, and 860 may be stacked sequentially on the eighth lower wiring 222, the ninth lower wiring 226, and the second interlayer insulating layer 170. Furthermore, a first bonding pattern (extending through the ninth interlayer insulating layer 800 to contact the eighth lower wiring 222) and a second bonding pattern 810 (extending through the ninth interlayer insulating layer 800 to contact the ninth lower wiring 226) may be formed. Additionally, a third bonding pattern (extending through the tenth interlayer insulating layer 820 to contact the first bonding pattern) and a fourth bonding pattern 830 (extending through the tenth interlayer insulating layer 820 to contact the second bonding pattern 810) may be formed. The first and third bonding patterns, as well as the second and fourth bonding patterns 810 and 830, may comprise metals (e.g., copper, aluminum, etc.) and may be formed, for example, by a dual damascene process.

[0204] A seventh upper wiring (extending through the eleventh interlayer insulating layer 840 to contact the third bonding pattern) and an eighth upper wiring 850 (extending through the eleventh interlayer insulating layer 840 to contact the fourth bonding pattern 830) can be formed. A first upper via (extending through the twelfth interlayer insulating layer 860 to contact the seventh upper wiring) and a second upper via 870 (extending through the twelfth interlayer insulating layer 860 to contact the eighth upper wiring 850) can be formed.

[0205] At least some of the first upper wiring 712, the second upper wiring 714, the third upper wiring, the fourth upper wiring 720, the fifth upper wiring 730, and the sixth upper wiring can be electrically connected to the lower circuit pattern through the first and third bonding patterns or the second and fourth bonding patterns.

[0206] By summarizing and reviewing, it can be found that as the number of stacked memory cells in semiconductor devices increases, the molding portion used to form the memory cells may deform.

[0207] As described above, the embodiments can provide semiconductor devices with improved characteristics, and can provide massive data storage systems including semiconductor devices with improved characteristics. In the method of manufacturing a semiconductor device according to the example embodiment, a support structure for preventing deformation of the molding portion can be stably formed, and therefore the semiconductor device including the support structure can have better characteristics.

[0208] Example embodiments have been disclosed herein, and although specific terminology has been used, it is for descriptive purposes only and should be interpreted in a general descriptive sense, not for limiting purposes. In some instances, as will be appreciated by those skilled in the art upon which this application has been filed, features, characteristics, and / or elements described in connection with specific embodiments may be used alone or in combination with features, characteristics, and / or elements described in other embodiments, unless expressly stated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, comprising: A gate electrode structure is located on a substrate, the gate electrode structure including gate electrodes spaced apart from each other in a first direction perpendicular to the upper surface of the substrate, each of the gate electrodes extending in a second direction parallel to the upper surface of the substrate; A channel extends through the gate electrode structure in the first direction; A dividing pattern is located on each side of the gate electrode structure on opposite sides in a third direction, the third direction being parallel to the upper surface of the substrate and intersecting the second direction, the dividing pattern extending in the second direction; An insulating pattern structure extends through a portion of the gate electrode structure; A through-hole extends through the insulating pattern structure in the first direction; A first support structure extends through the gate electrode structure in the first direction; as well as The second support structure extends in the first direction through the portion of the gate electrode structure between the insulating pattern structure and the dividing pattern. The second support structure includes: The first extension portion extends in the second direction in the plan view; and A second extension portion is connected to the first extension portion, and the second extension portion extends upward from the first extension portion on the third party. Wherein, the first support structure is one of a plurality of first support structures arranged in a column of support structures extending in the second direction. The second support structure is one of a plurality of second support structures arranged as a first support structure column and a second support structure column, wherein the first support structure column and the second support structure column extend in the second direction and are spaced apart from each other in the third direction, and The first support structure column of the plurality of second support structures is arranged between the support structure column of the plurality of first support structures and the second support column of the plurality of second support structures.

2. The semiconductor device according to claim 1, wherein, The second extension extends upward from each of the opposite ends of the first extension in the second direction in the third direction.

3. The semiconductor device according to claim 1, wherein, The second extension extends upward from the middle of the first extension in the second direction in the third party.

4. The semiconductor device according to claim 1, wherein, The angles of each of the first and second extensions are rounded in the plan view.

5. The semiconductor device according to claim 1, wherein: The first support structure has a circular, elliptical, rectangular, or rounded rectangular shape.

6. The semiconductor device according to claim 5, further comprising: A contact plug extends in the first direction to contact the upper surface of the end of each of the gate electrodes in the second direction; as well as A third support structure extends through the gate electrode structure in the first direction, and the third support structure is adjacent to the contact plug. The third support structure has the same shape as the first support structure in the plan view.

7. The semiconductor device according to claim 1, wherein: The first support structure includes two third extension portions that extend in the second direction and are spaced apart from each other in the third direction. The first support structure includes three fourth extensions that extend upward from the third and are spaced apart from each other in the second direction. The two third extensions are not aligned with each other along the second direction. The corresponding ends of the two third extension portions in the second direction overlap each other in the third direction and are connected to each other by one of the fourth extension portions. The other two of the fourth extensions extend upward from the outer ends of the two third extensions in the second direction in the third direction.

8. The semiconductor device according to claim 7, wherein: The adjacent fourth extension of each of the plurality of first support structures faces the first extension in the third direction.

9. The semiconductor device according to claim 1, wherein: The second extension portion extends upward from each of the opposite ends of the first extension portion in the second direction in the third direction. The plurality of second support structures in the first support structure column and the second support structure column are arranged together in a z-shaped pattern in the second direction. The second extension portion in the first support structure column extends toward the second support structure column, and The second extension portion of the second support structure column extends toward the first support structure column.

10. The semiconductor device according to claim 1, wherein: The substrate includes a cell array region and an extended region that at least partially surrounds the cell array region; The gate electrode structure and the partitioning pattern are formed on the cell array region and the extended region. The channels are formed on the cell array region, and The insulating pattern structure, the through hole, and the second support structure are formed on the extended region and / or the unit array region.

11. The semiconductor device according to claim 1, wherein: The channel has a cup shape. The semiconductor device further includes: A charge storage structure is located on the outer wall of the channel; Filling pattern, filling the interior space formed by the channels; and A capping pattern is located on the channel and the filling pattern, the capping pattern contacting the inner wall of the charge storage structure, and The charge storage structure, the channel, the fill pattern, and the cap pattern form a memory channel structure extending in the first direction.

12. The semiconductor device according to claim 11, wherein, The second support structure includes: A virtual channel is provided, which has a cup shape and extends in the first direction; A dummy charge storage structure is located on the outer wall of the dummy channel; A dummy fill pattern is used to fill the internal space formed by the dummy channels; and A dummy cap pattern is located on the dummy channel and the dummy fill pattern, and the dummy cap pattern contacts the inner wall of the dummy charge storage structure. The dummy channel, the dummy charge storage structure, the dummy filling pattern, and the dummy cap pattern each comprise materials substantially the same as those used in the channel, the charge storage structure, the filling pattern, and the cap pattern.

13. The semiconductor device according to claim 1, wherein, The insulating pattern structure includes a first pattern and a second pattern, which are stacked alternately and repeatedly in the first direction, and the first pattern and the second pattern include different materials from each other.

14. A semiconductor device, comprising: The lower circuit pattern is located on a substrate, the substrate including a cell array region and an extended region at least partially surrounding the cell array region; The common source plate (CSP) is located above the lower circuit pattern; A gate electrode structure is located on the CSP, the gate electrode structure including gate electrodes spaced apart from each other in a first direction perpendicular to the upper surface of the substrate, each of the gate electrodes extending in a second direction parallel to the upper surface of the substrate; A memory channel structure extending through the gate electrode structure on the cell array region and contacting the upper surface of the CSP, the memory channel structure comprising: The channel extends in the first direction; and A charge storage structure is located on the outer wall of the channel; A dividing pattern is located on each side of the gate electrode structure on opposite sides in a third direction, the third direction being parallel to the upper surface of the substrate and intersecting the second direction, the dividing pattern extending in the second direction; An insulating pattern structure extends on the CSP through a portion of the gate electrode structure; A via extending in the first direction through the insulating pattern structure and the CSP, the via contacting and electrically connecting to one of the lower circuit patterns; A contact plug extends in the first direction to contact the upper surface of the end of one of the gate electrodes in the second direction; A first support structure extends in the first direction through the gate electrode structure and contacts the upper surface of the CSP, the first support structure being adjacent to the contact plug; and The second support structure extends in the first direction through the portion of the gate electrode structure between the insulating pattern structure and the dividing pattern, and contacts the upper surface of the CSP. The second support structure has a "C", "U" or "T" shape in the plan view.

15. The semiconductor device according to claim 14, wherein, The insulating pattern structure, the through hole, and the second support structure are formed on the extended region and / or the unit array region.

16. The semiconductor device of claim 14, further comprising: The third support structure between the dividing pattern and the second support structure has the same shape as the first support structure in the plan view.

17. The semiconductor device according to claim 14, wherein: The second support structure has a "C" or "U" shape in the plan view. The second support structure is one of a plurality of second support structures arranged as a first support structure column and a second support structure column, the first support structure column and the second support structure column extending in the second direction and spaced apart from each other in the third direction. The plurality of second support structures in the first support structure column and the second support structure column are arranged together in a z-shaped pattern in the second direction.

18. A massive data storage system, comprising: Semiconductor devices have: The memory cell structure includes: A gate electrode structure is located on a substrate, the gate electrode structure including gate electrodes spaced apart from each other in a first direction perpendicular to the upper surface of the substrate, each of the gate electrodes extending in a second direction parallel to the upper surface of the substrate; A channel extends through the gate electrode structure in the first direction; A dividing pattern is located on each side of the gate electrode structure on opposite sides in a third direction, the third direction being parallel to the upper surface of the substrate and intersecting the second direction, the dividing pattern extending in the second direction; An insulating pattern structure extends through a portion of the gate electrode structure; A through-hole extends through the insulating pattern structure in the first direction; A first support structure extends through the gate electrode structure in the first direction; and A second support structure extends in the first direction through the portion of the gate electrode structure between the insulating pattern structure and the dividing pattern. The second support structure includes a first extension portion extending in the second direction in a plan view, and includes a second extension portion connected to the first extension portion, the second extension portion extending upward from the first extension portion in the third direction. Peripheral circuit wiring is configured to apply electrical signals to the memory cell structure; and Input / output pads are electrically connected to the peripheral circuit wiring; and A controller, electrically connected to the semiconductor device via the input / output pads, is configured to control the semiconductor device. Wherein, the first support structure is one of a plurality of first support structures arranged in a column of support structures extending in the second direction. The second support structure is one of a plurality of second support structures arranged as a first support structure column and a second support structure column, wherein the first support structure column and the second support structure column extend in the second direction and are spaced apart from each other in the third direction, and The first support structure column of the plurality of second support structures is arranged between the support structure column of the plurality of first support structures and the second support column of the plurality of second support structures.

19. The massive data storage system according to claim 18, wherein, The second extension extends upward from each of the opposite ends of the first extension in the second direction in the third direction.

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