Semiconductor device and electronic system including the same

Abstract

A semiconductor device and an electronic system including the same are provided. The semiconductor device may include: a peripheral circuit structure including circuitry; a substrate located on the peripheral circuit structure; a pair of word line dicing structures extending in a first direction on the substrate; and a memory cell block located between the pair of word line dicing structures and on the substrate. The memory cell block may include: a memory stack structure including gate lines overlapping each other in a vertical direction; an interlayer insulating layer located on the edge portions of each of the gate lines; a dam structure extending through the gate lines and the interlayer insulating layer; an intersecting direction dicing structure extending through the memory stack structure and the interlayer insulating layer in the vertical direction and spaced apart from the dam structure; and a dummy channel structure located between the intersecting direction dicing structure and the dam structure.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0146317, filed on November 4, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to semiconductor devices and electronic systems including the thereof, and more specifically, to semiconductor devices including non-volatile vertical memory devices and electronic systems including the semiconductor devices. Background Technology

[0004] Electronic systems requiring data storage may include semiconductor devices for storing large amounts of data. Therefore, methods to increase the data storage capacity of semiconductor devices are being investigated. For example, to increase the data storage capacity of semiconductor devices, semiconductor devices incorporating vertical memory devices have been proposed, which include memory cells arranged in three dimensions rather than two dimensions. Summary of the Invention

[0005] The present invention provides a semiconductor device in which, even if the number of word line stacks is increased to improve the integration of the semiconductor device including three-dimensionally arranged memory cells and thus the height of the word line stacks is increased, tilting or collapse of the memory stack structure can be reduced or prevented, thereby reducing or preventing process defects and improving reliability in the process of manufacturing the semiconductor device.

[0006] The present invention provides an electronic system including semiconductor devices, wherein even if the number of word line stacks is increased to improve the integration of the semiconductor devices including three-dimensionally arranged memory cells and thus the height of the word line stacks is increased, tilting or collapse of the memory stack structure can be reduced or prevented, thereby reducing or preventing process defects and improving reliability in the process of manufacturing semiconductor devices.

[0007] According to some embodiments of the present invention, a semiconductor device is provided, comprising: a peripheral circuit structure including a plurality of circuits; a substrate located on (e.g., covering) the peripheral circuit structure; a pair of word line dicing structures extending longitudinally in a first horizontal direction on the substrate, the pair of word line dicing structures being spaced apart from each other in a second horizontal direction that may be perpendicular to the first horizontal direction; and a memory cell block located between the pair of word line dicing structures and on the substrate, wherein the memory cell block includes: a memory stack structure including a plurality of gate lines overlapping each other in a vertical direction; interlayer insulation; An interlayer insulating layer is located on the edge portion of each of the plurality of gate lines (e.g., covering the edge portion of each of the plurality of gate lines); a dam structure extending through the memory stack structure (e.g., the plurality of gate lines) and the interlayer insulating layer; an intersecting direction cut structure extending through the memory stack structure and the interlayer insulating layer in the vertical direction and extending longitudinally in a horizontal direction intersecting or intersecting the first horizontal direction, the intersecting direction cut structure being spaced apart from the dam structure in the first horizontal direction; and a plurality of dummy channel structures located between the intersecting direction cut structure and the dam structure.

[0008] According to some embodiments of the present invention, a semiconductor device is provided, comprising: a peripheral circuit structure including a plurality of circuits; a memory stack structure including a plurality of gate lines overlapping the peripheral circuit structure in a vertical direction; an interlayer insulating layer located on an edge portion of each of the plurality of gate lines (e.g., covering the edge portion of each of the plurality of gate lines); a dam structure extending in the vertical direction through the memory stack structure (e.g., the plurality of gate lines) and the interlayer insulating layer and defining a through-path region in the memory stack structure; an intersecting direction cut structure extending in the vertical direction through the memory stack structure and the interlayer insulating layer, the intersecting direction cut structure being spaced apart from the dam structure in a first horizontal direction and extending longitudinally in a second horizontal direction intersecting or intersecting the first horizontal direction; and a plurality of dummy channel structures located between the intersecting direction cut structure and the dam structure.

[0009] According to some embodiments of the present invention, an electronic system is provided, comprising: a main substrate; a semiconductor device located on the main substrate; and a controller electrically connected to the semiconductor device, the controller being located on the main substrate, wherein the semiconductor device includes: a peripheral circuit structure including a plurality of circuits; a memory stack structure including a plurality of gate lines overlapping the peripheral circuit structure in a vertical direction; an interlayer insulating layer located on an edge portion of each of the plurality of gate lines (e.g., covering the edge portion of each of the plurality of gate lines); and a dam structure. The dam structure extends vertically through the plurality of gate lines and the interlayer insulating layer and defines a through-path region in the memory stack structure; an intersecting direction cut structure extends vertically through the memory stack structure and the interlayer insulating layer, the intersecting direction cut structure being spaced apart from the dam structure in a first horizontal direction and extending longitudinally in a second horizontal direction intersecting or intersecting the first horizontal direction; a plurality of dummy channel structures are located between the intersecting direction cut structure and the dam structure; and input / output pads electrically connected to the peripheral circuit structure. Attached Figure Description

[0010] Exemplary embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a block diagram of a semiconductor device according to some embodiments of the present invention;

[0012] Figure 2 This is a schematic perspective view of a semiconductor device according to an embodiment of the present invention.

[0013] Figure 3 This is an equivalent circuit diagram of a memory cell array of a semiconductor device according to some embodiments of the present invention;

[0014] Figure 4 This is a schematic top view of a portion of a semiconductor device according to some embodiments of the present invention;

[0015] Figure 5A This is a top view showing some elements of a memory cell block of a semiconductor device according to some embodiments of the present invention;

[0016] Figure 5B It is along Figure 5A A cross-sectional view taken by line X1-X1';

[0017] Figure 5C It is along Figure 5A A cross-sectional view taken from line Y1-Y1';

[0018] Figure 5D It shows Figure 5A A top view of some of the elements included in the VAX region;

[0019] Figure 5E It shows Figure 5C A cross-sectional view of some components included in the VCX region;

[0020] Figure 6 These are cross-sectional views of semiconductor devices according to some embodiments of the present invention;

[0021] Figure 7 This is a top view of a semiconductor device according to some embodiments of the present invention;

[0022] Figure 8 This is a top view of a semiconductor device according to some embodiments of the present invention;

[0023] Figure 9 These are cross-sectional views of semiconductor devices according to some embodiments of the present invention;

[0024] Figure 10A and Figure 10B These are cross-sectional views of semiconductor devices according to some embodiments of the present invention;

[0025] Figure 11 These are cross-sectional views of semiconductor devices according to some embodiments of the present invention;

[0026] Figure 12A This is a top view of a semiconductor device according to some embodiments of the present invention;

[0027] Figure 12B This is a top view of a semiconductor device according to some embodiments of the present invention;

[0028] Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A and Figure 18B This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention;

[0029] Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A and Figure 18A It is along Figure 5A A cross-sectional view taken by line X1-X1';

[0030] Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B and Figure 18B It is along Figure 5A A cross-sectional view taken from line Y1-Y1';

[0031] Figure 19 This is a schematic view illustrating an electronic system including semiconductor devices according to some embodiments of the present invention;

[0032] Figure 20 This schematically illustrates a perspective view of an electronic system including semiconductor devices according to some embodiments of the present invention; and

[0033] Figure 21 This schematically illustrates a cross-sectional view of a semiconductor package according to some embodiments of the present invention. Detailed Implementation

[0034] In the following, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The same reference numerals refer to the same elements, and repeated descriptions of them may be omitted. As used herein, an element or region that “covers,” “encloses,” or “fills” another element or region may completely or partially cover, enclose, or fill the other element or region.

[0035] Figure 1 This is a block diagram of a semiconductor device 10 according to some embodiments of the present invention.

[0036] Reference Figure 1 The semiconductor device 10 may include a memory cell array 20 and peripheral circuitry 30. The memory cell array 20 may include multiple memory cell blocks BLK1, BLK2, ..., and BLKp. Each of the multiple memory cell blocks BLK1, BLK2, ..., and BLKp may include multiple memory cells. The multiple memory cell blocks BLK1, BLK2, ..., and BLKp can be connected to the peripheral circuitry 30 via bit lines BL, word lines WL, serial select lines SSL, and ground select lines GSL.

[0037] The peripheral circuitry 30 may include a row decoder 32, a page buffer 34, data input / output (I / O) circuitry 36, control logic 38, and a common source line (CSL) driver 39. The peripheral circuitry 30 may also include various circuits, such as voltage generation circuitry for generating the various voltages required for the operation of the semiconductor device 10, error correction circuitry for correcting errors in the data read from the memory cell array 20, and I / O interfaces.

[0038] The cell array 20 can be connected to the row decoder 32 via word lines WL, string select lines SSL, and ground select lines GSL, and can be connected to the page buffer 34 via bit lines BL. In the cell array 20, multiple memory cells included in each of multiple cell blocks BLK1, BLK2, ..., and BLKp can be flash memory cells. The cell array 20 can include a three-dimensional (3D) cell array. The 3D cell array can include multiple NAND strings, and each NAND string can include multiple memory cells vertically stacked and connected to multiple word lines WL.

[0039] The peripheral circuit 30 can receive address ADDR, command CMD and control signal CTRL from the outside of the semiconductor device 10, and can send data DATA to a device outside the semiconductor device 10 and receive data DATA from the device outside the semiconductor device 10.

[0040] The row decoder 32 can select at least one of a plurality of memory cell blocks BLK1, BLK2, ..., and BLKp in response to an external address ADDR, and can select the word line WL, serial select line SSL, and ground select line GSL of the selected memory cell block. The row decoder 32 can transmit the voltage used to perform the memory operation to the word line WL of the selected memory cell block.

[0041] Page buffer 34 can be connected to memory cell array 20 via bit line BL. During programming operations, page buffer 34 can function as a write driver to apply a voltage to bit line BL based on the data DATA stored in memory cell array 20, and during read operations, page buffer 34 can function as a sense amplifier to sense the data DATA stored in memory cell array 20. Page buffer 34 can operate based on control signal PCTL provided from control logic 38.

[0042] Data I / O circuit 36 ​​can be connected to page buffer 34 via multiple data lines DL. During programming operations, data I / O circuit 36 ​​can receive data DATA from the memory controller (not shown) and can provide programming data DATA to page buffer 34 based on the column address C_ADDR provided from control logic 38. During read operations, data I / O circuit 36 ​​can provide read data DATA stored in page buffer 34 to the memory controller based on the column address C_ADDR.

[0043] Data I / O circuitry 36 can transmit addresses or commands input to it to control logic 38 or line decoder 32. Peripheral circuitry 30 may also include electrostatic discharge (ESD) circuitry and / or pull-up / pull-down drivers. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0044] Control logic 38 can receive commands CMD and control signals CTRL from the memory controller. Control logic 38 can provide the row address R_ADDR to the row decoder 32 and the column address C_ADDR to the data I / O circuit 36. Control logic 38 can generate various internal control signals used in the semiconductor device 10 in response to the control signal CTRL. For example, control logic 38 can control the voltage levels of the word line WL and bit line BL during memory operations such as programming or erasing operations.

[0045] The common source line driver 39 can be connected to the memory cell array 20 via the common source line CSL. The common source line driver 39 can apply a common source voltage (e.g., source voltage) or a ground voltage to the common source line CSL based on the control of the signal CTRL_BIAS by the control logic 38.

[0046] Figure 2 This is a schematic perspective view of a semiconductor device 10 according to some embodiments of the present invention.

[0047] Reference Figure 2 The semiconductor device 10 may include a cell array structure CAS and a peripheral circuit structure PCS overlapping in the vertical direction (Z direction). The cell array structure CAS may include the above-mentioned reference... Figure 1 The described memory cell array 20. The peripheral circuitry PCS may include the components described above. Figure 1 The peripheral circuit 30 is described. As used herein, reference to element A overlapping element B in the vertical direction (or similar language) means that at least one vertical line intersecting both elements A and B can be drawn.

[0048] The CAS (Cellular Array) structure can include multiple tiles 24. Each tile 24 can include multiple storage cell blocks BLK1, BLK2, ..., and BLKp. Each storage cell block BLK1, BLK2, ..., and BLKp can include multiple storage cells arranged in three dimensions.

[0049] In an example embodiment, a mat may include two tiles 24, but the inventive concept is not limited thereto. (Refer to above) Figure 1 The described memory cell array 20 may include multiple pads (e.g., four pads), but the inventive concept is not limited thereto.

[0050] Figure 3 This is an equivalent circuit diagram of a memory cell array (MCA) of a semiconductor device according to some embodiments of the present invention. Figure 3 The equivalent circuit diagram of a vertical NAND flash memory with a vertical channel structure is shown in the figure. Figure 1 and Figure 2 The multiple storage cell blocks BLK1, BLK2, ... and BLKp shown can each include those having... Figure 3 The circuit configuration shown is for the memory cell array MCA.

[0051] Reference Figure 3 A memory cell array (MCA) can include multiple memory cell strings (MS). The MCA can include multiple bit lines BL (BL1, BL2, ..., BLm), multiple word lines WL (WL1, WL2, ..., WLn-1, and WLn), at least one string select line SSL, at least one ground select line GSL, and a common source line CSL. Multiple memory cell strings (MS) can be formed between the multiple bit lines BL and the common source line CSL. Figure 3 The example shown illustrates multiple memory cell strings (MS) each including one ground select line (GSL) and two string select lines (SSL), but the inventive concept is not limited thereto. For example, multiple memory cell strings (MS) may each include one string select line (SSL).

[0052] Multiple memory cell strings (MS) may include a string select transistor (SST), a ground select transistor (GST), and multiple memory cell transistors (MC1, MC2, ..., MCn-1 and MCn). The drain region of the string select transistor (SST) may be connected to the bit line (BL), and the source region of the ground select transistor (GST) may be connected to the common source line (CSL). The common source line (CSL) may be a region that is commonly connected to the source regions of the multiple ground select transistors (GST).

[0053] The serial select transistor SST can be connected to the serial select line SSL, and the ground select transistor GST can be connected to the ground select line GSL. Multiple memory cell transistors MC1, MC2, ..., MCn-1 and MCn can all be connected to the word line WL.

[0054] Figure 4 This is a schematic top view of a portion of a semiconductor device 100 according to some embodiments of the present invention.

[0055] Reference Figure 4 The cell array structure CAS of the semiconductor device 100 may include an upper substrate 110 and multiple memory cell blocks BLK1, BLK2, ... and BLKp disposed on the upper substrate 110.

[0056] Peripheral circuit structure PCS (see) Figure 2 The upper substrate 110 can be located below the upper substrate 110. Multiple memory cell blocks BLK1, BLK2, ..., and BLKp can overlap with the peripheral circuit structure PCS in the vertical direction (Z direction), with the upper substrate 110 situated between them. The peripheral circuit structure PCS located below the upper substrate 110 can include the components mentioned above. Figure 1 The peripheral circuit 30 is described.

[0057] The cell array structure CAS may include a memory cell region MEC and a connection region CON configured to be adjacent to each side of the memory cell region MEC in the first horizontal direction (X direction) (e.g., configured at each side of the memory cell region MEC in the first horizontal direction (X direction)). Multiple memory cell blocks BLK1, BLK2, ..., and BLKp may each include a memory stack structure MST extending in the first horizontal direction (X direction) on the memory cell region MEC and the connection region CON. The memory stack structure MST may include multiple gate lines 130 stacked in the memory cell region MEC and the connection region CON of the upper substrate 110, overlapping in the vertical direction (Z direction). In each of the multiple memory stack structures MST, the multiple gate lines 130 may be included in a gate stack GS. In each of the multiple memory stack structures MST, the multiple gate lines 130 may include multiple gate lines 130 that are all located in the memory cell region MEC and the connection region CON. Figure 3 The ground select line GSL, multiple word lines WL, and string select line SSL are shown. In the XY plane, the multiple gate lines 130 can progressively decrease in area as the distance from the upper substrate 110 increases. In some embodiments, the surface area of ​​the multiple gate lines 130 in the XY plane decreases as the distance from the upper substrate 110 increases, such as... Figure 4As shown. The central portion of each of the multiple gate lines 130 overlapping in the vertical direction (Z direction) may be included in the memory cell region MEC, and the edge portion of each of the multiple gate lines 130 may be included in the connection region CON. As used herein, "element A extends in direction X" (or similar language) may refer to element A extending longitudinally in direction X.

[0058] Multiple word line cut structures (WLCs) extending longitudinally in the first horizontal direction (X direction) within the memory cell region (MEC) and the connection region (CON) can be disposed on the upper substrate 110. The multiple word line cut structures (WLCs) can be spaced apart from each other in the second horizontal direction (Y direction). Multiple memory cell blocks BLK1, BLK2, ..., and BLKp can each be disposed between two adjacent word line cut structures (WLCs).

[0059] Figures 5A to 5E These are views of some embodiments of the present invention for a more detailed description of the semiconductor device 100. Figure 5A It is shown in Figure 4 The diagram shows a top view of some elements of storage cell blocks BLK11 and BLK12 in the multiple storage cell blocks BLK1, BLK2, ... and BLKp. Figure 5B It is along Figure 5A The cross-sectional view taken by line X1-X1'. Figure 5C It is along Figure 5A The cross-sectional view taken from line Y1-Y1'. Figure 5D It shows that it includes Figure 5A A top view of some elements in the VAX region. Figure 5E It shows that it includes Figure 5C A cross-sectional view of some components in the VCX region.

[0060] Reference Figures 5A to 5E The semiconductor device 100 may include a peripheral circuit structure PCS and a cell array structure CAS disposed on the peripheral circuit structure PCS and overlapping the peripheral circuit structure PCS in the vertical direction (Z direction).

[0061] The cell array structure (CAS) may include an upper substrate 110, a first conductive plate 114, a second conductive plate 118, an insulating plate 112, and a memory stack structure (MST). In the cell array structure (CAS), the first conductive plate 114, the second conductive plate 118, and the memory stack structure (MST) may be sequentially stacked on the upper substrate 110 within the memory cell region (MEC). In the cell array structure (CAS), the insulating plate 112, the second conductive plate 118, and the memory stack structure (MST) may be sequentially stacked on the upper substrate 110 within the connection region (CON).

[0062] The first conductive plate 114 and the second conductive plate 118 can perform the above-mentioned reference. Figure 3 The function of the common source line (CSL) is described. The first conductive plate 114 and the second conductive plate 118 can be used as source regions to provide current to multiple vertical memory cells included in the cell array structure (CAS).

[0063] In an example embodiment, the upper substrate 110 may include a semiconductor material such as polysilicon. Both the first conductive plate 114 and the second conductive plate 118 may include doped polysilicon, a metal layer, or a combination thereof. The metal layer may include, for example, tungsten (W), but the inventive concept is not limited thereto. The memory stack structure MST may include a gate stack GS. The gate stack GS may include multiple gate lines 130 extending parallel in the horizontal direction and overlapping in the vertical direction (Z direction). Each of the multiple gate lines 130 may include a metal, a metal silicide, a doped semiconductor, or a combination thereof. For example, each of the multiple gate lines 130 may include a metal such as tungsten, nickel, cobalt, or tantalum, a metal silicide such as tungsten silicide, nickel silicide, cobalt silicide, or tantalum silicide, doped polysilicon, or a combination thereof.

[0064] An insulating layer 132 may be disposed between the second conductive plate 118 and the plurality of gate lines 130, and between two adjacent gate lines 130 among the plurality of gate lines 130. The uppermost gate line 130 among the plurality of gate lines 130 may be covered by the insulating layer 132. The insulating layer 132 may include silicon oxide.

[0065] In the memory cell region MEC and the connection region CON, multiple word line cut structures (WLCs) can extend longitudinally in a first horizontal direction (X direction) on the upper substrate 110. The width of each gate line in the multiple gate lines 130 included in the memory cell blocks BLK11 and BLK12 in the second horizontal direction (Y direction) can be defined by the multiple word line cut structures (WLCs).

[0066] Multiple word-line cut structures (WLCs) may all include an insulating structure. In example embodiments, the insulating structure may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material. For example, the insulating structure may include a silicon oxide layer, a silicon nitride layer, a SiON layer, a SiOCN layer, a SiCN layer, or a combination thereof. In some example embodiments, at least a portion of the insulating structure may include an air gap. Hereinafter, the term "air" may refer to a gas in air or a gas used in a manufacturing process (e.g., an inert gas). It will be understood that an "air gap" can be, for example, any void or cavity or a gap defining a vacuum.

[0067] Between two adjacent word line cut structures WLC, multiple gate lines 130, including those in a gate stack GS, can be stacked on a second conductive plate 118 to overlap each other in the vertical direction (Z direction). The multiple gate lines 130 of a gate stack GS may include a ground select line GSL, multiple word lines WL, and a string select line SSL, as shown above. Figure 3 They were all described.

[0068] like Figure 5C As shown, two upper gate lines 130 of the multiple gate lines 130 can be spaced apart from each other in the second horizontal direction (Y direction) using a string select line cut structure (SSLC). The two upper gate lines 130 spaced apart from each other using the SSLC can be as described above. Figure 3 The description refers to the SSL selection line. In Figure 5C The image shows an example of a string select wire-cut structure (SSLC) formed in a gate stack (GS), but the inventive concept is not limited thereto. Figure 5C The illustration shows that, for example, at least two string select wire-cut structures (SSLCs) can be formed in a gate stack (GS). The SSLC can be filled with an insulating layer. In an example embodiment, the SSLC may include an insulating layer comprising, for example, oxides, nitrides, or combinations thereof. In an example embodiment, at least a portion of the SSLC may include an air gap.

[0069] like Figure 5A and Figure 5C As shown, multiple channel structures 180 can pass through multiple gate lines 130, multiple insulating layers 132, a second conductive plate 118, and a first conductive plate 114, and can extend in the vertical direction (Z direction) and be located on the upper substrate 110 in the memory cell region (MEC). The multiple channel structures 180 can be spaced apart from each other by specific intervals in a first horizontal direction (X direction) and a second horizontal direction (Y direction). Each of the multiple channel structures 180 can include a gate dielectric layer 182, a channel region 184, a buried insulating layer 186, and a drain region 188.

[0070] like Figure 5E As shown, the gate dielectric layer 182 may include a tunneling dielectric layer TD, a charge storage layer CS, and a barrier dielectric layer BD sequentially formed on the channel region 184. The relative thicknesses of the tunneling dielectric layer TD, the charge storage layer CS, and the barrier dielectric layer BD are not limited to... Figure 5E The diagram can be modified in different ways.

[0071] The tunneling dielectric layer TD may include, for example, silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, and / or tantalum oxide. The charge storage layer CS may be a region that stores electrons passing through the tunneling dielectric layer TD from the channel region 184, and may include, for example, silicon nitride, boron nitride, boron silicon nitride, and / or polycrystalline silicon doped with impurities. The barrier dielectric layer BD may include a metal oxide with a dielectric constant greater than that of silicon oxide, silicon nitride, or silicon oxynitride. The metal oxide may include, for example, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or combinations thereof.

[0072] like Figure 5E As shown, the first conductive plate 114 can extend through a portion of the gate dielectric layer 182 in the horizontal direction (X and / or Y direction) and can contact the channel region 184. The thickness of the portion of the first conductive plate 114 that perpendicularly overlaps with the gate dielectric layer 182 in the Z direction can be greater than the thickness of the portion of the first conductive plate 114 that perpendicularly overlaps with the second conductive plate 118 in the Z direction. The gate dielectric layer 182 may include a portion covering the sidewalls of the channel region 184 at a height above the horizontal level of the first conductive plate 114 and a portion covering the bottom surface of the channel region 184 at a height below the horizontal level of the first conductive plate 114. The channel region 184 can be spaced apart from the upper substrate 110 by the lowermost portion of the gate dielectric layer 182. The sidewalls of the channel region 184 can contact the first conductive plate 114 and can be electrically connected to the first conductive plate 114.

[0073] like Figure 5C and Figure 5E As shown, the channel region 184 may have a cylindrical shape. The channel region 184 may include, for example, doped polysilicon and / or undoped polysilicon.

[0074] The buried insulation layer 186 can fill the internal space of the trench region 184. The buried insulation layer 186 can include an insulating material. For example, the buried insulation layer 186 can include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. In some embodiments, the buried insulation layer 186 can be omitted. In this case, the trench region 184 can have a non-hollow columnar structure.

[0075] The drain region 188 may include, for example, doped polysilicon. Multiple drain regions 188 are insulated from each other by a first upper insulating layer 187. In the memory cell region (MEC), multiple channel structures 180 and the first upper insulating layer 187 may be covered by a second upper insulating layer 189.

[0076] The string select wire-cut structure SSLC can extend through the first upper insulating layer 187 and the second upper insulating layer 189 in the vertical direction (Z direction). The top surface of the string select wire-cut structure SSLC, the top surface of the word wire-cut structure WLC, and the top surface of the second upper insulating layer 189 can be located at a first horizontal height LV1 away from the upper substrate 110. The string select wire-cut structure SSLC, the word wire-cut structure WLC, and the second upper insulating layer 189 can be covered by a third upper insulating layer 190. The first upper insulating layer 187, the second upper insulating layer 189, and the third upper insulating layer 190 can all comprise, for example, oxides, nitrides, or combinations thereof.

[0077] like Figure 5A and Figure 5C As shown, in the memory cell region (MEC) of the memory stack structure (MST), multiple bit lines BL can be disposed on the third upper insulating layer 190. The multiple bit lines BL can extend parallel to each other in the second horizontal direction (Y direction). Multiple channel structures 180 can be connected to one of the multiple bit lines BL via multiple contact plugs 194 passing through the second upper insulating layer 189 and the third upper insulating layer 190, respectively.

[0078] like Figure 5B As shown, in the connection region CON of the storage stack structure MST, an insulating plate 112 and a second conductive plate 118 can be sequentially stacked on an upper substrate 110. The insulating plate 112 may include an insulating layer with a multilayer structure, comprising a first insulating layer 112A, a second insulating layer 112B, and a third insulating layer 112C sequentially stacked on the upper substrate 110. In an example embodiment, the first insulating layer 112A and the third insulating layer 112C may include silicon oxide, and the second insulating layer 112B may include silicon nitride.

[0079] In the connection region CON, the edge portions of each of the plurality of gate lines 130 and the plurality of insulating layers 132 may be covered by an interlayer insulating layer 138. The interlayer insulating layer 138 may include silicon oxide, but the inventive concept is not limited thereto.

[0080] like Figure 5A and Figure 5BAs shown, in the connection region CON, multiple dummy channel structures D180 can pass through the interlayer insulating layer 138, multiple gate lines 130, multiple insulating layers 132, the second conductive plate 118, and the insulating plate 112, and can extend in the vertical direction (Z direction). The multiple dummy channel structures D180 can be spaced apart from each other by specific intervals in the first horizontal direction (X direction) and the second horizontal direction (Y direction). Similar to the channel structure 180, the multiple dummy channel structures D180 may include a gate dielectric layer 182, a channel region 184, a buried insulating layer 186, and a drain region 188. In the top view, the size of each of the multiple dummy channel structures D180 can be larger than the size of the channel structure 180. The drain region 188 of each of the plurality of dummy channel structures D180 may not be electrically connected to any conductive element of the semiconductor device 100 (e.g., multiple bit lines BL), and the channel region 184 of each of the plurality of dummy channel structures D180 may not be used as a channel. In some embodiments, the second upper insulating layer 189 may contact the entire upper surface of the drain region 188 of each of the plurality of dummy channel structures D180.

[0081] like Figure 5B As shown, in the connection region CON, the interlayer insulation layer 138 can be covered by the first upper insulation layer 187. The drain region 188 of each of the plurality of dummy channel structures D180 can be insulated from the adjacent drain region 188 through the first upper insulation layer 187. In the connection region CON, the plurality of dummy channel structures D180 and the first upper insulation layer 187 can be covered by the second upper insulation layer 189.

[0082] like Figure 5A and Figure 5B As shown, memory cell blocks BLK11 and BLK12 located between two adjacent word line cut structures WLC in the connection region CON can each include a dam structure DM and an intersecting direction cut structure YDC. Both the dam structure DM and the intersecting direction cut structure YDC can pass through the interlayer insulating layer 138, multiple gate lines 130, multiple insulating layers 132, the second conductive plate 118, and the insulating plate 112, can extend in the vertical direction (Z direction), and can be located on the upper substrate 110.

[0083] The dam structure DM may include a first insulating pad 142, a second insulating pad 144, and a main plug 146, sequentially stacked from the inner wall of the dam hole DMH passing through the interlayer insulating layer 138, multiple gate lines 130, multiple insulating layers 132, second conductive plate 118, and insulating plate 112 toward the interior of the dam hole DMH. In an example embodiment, the first insulating pad 142 may include silicon oxide, the second insulating pad 144 may include silicon nitride, and the main plug 146 may include polysilicon. However, the inventive concept is not limited thereto.

[0084] exist Figure 5A The diagram illustrates a dam structure DM positioned between two adjacent word-line cut structures WLC, but the inventive concept is not limited thereto. For example, multiple dam structures DM can be arranged in a row in a second horizontal direction (Y direction) and can be spaced apart from each other between two adjacent word-line cut structures WLC.

[0085] The intersecting direction cut structure YDC may include an insulating structure that fills intersecting direction holes YH passing through interlayer insulating layer 138, multiple gate lines 130, multiple insulating layers 132, second conductive plate 118, and insulating plate 112. The material of the intersecting direction cut structure YDC may differ from the material of the dam structure DM. A more detailed construction of the insulating structure of the intersecting direction cut structure YDC may be the same as the insulating structure of a multiple word line cut structure WLC.

[0086] like Figure 5A As shown, the intersecting direction cut structure YDC can extend linearly and longitudinally in the second horizontal direction (Y direction) between two adjacent word line cut structures WLC. The intersecting direction cut structure YDC can extend in a direction parallel to multiple bit lines BL disposed in the memory cell region MEC. In a memory stack structure MST between two adjacent word line cut structures WLC, the intersecting direction cut structure YDC can be configured to be adjacent to each side of the opposite sides of the dam structure DM in the first horizontal direction (X direction) (e.g., disposed at each side of the opposite sides of the dam structure DM in the first horizontal direction (X direction)). In some embodiments, the intersecting direction cut structure YDC can have a linear shape extending longitudinally in the second horizontal direction (Y direction), such as... Figure 5A As shown.

[0087] like Figure 5A and Figure 5D As shown, the intersecting direction cut structure YDC can include multiple cut lines YDCA and YDCB that are separated from each other. The multiple cut lines YDCA and YDCB can be arranged in a row in the second horizontal direction (Y direction) in a storage stack structure MST, and can be separated from each other in the second horizontal direction (Y direction).

[0088] exist Figure 5A and Figure 5DThe illustration shows an example of an intersecting direction cutting structure YDC comprising two cutting lines YDCA and YDCB spaced apart from each other in a second horizontal direction (Y direction), but the inventive concept is not limited thereto. In an example embodiment, an intersecting direction cutting structure YDC may include a single cutting line extending longitudinally in the second horizontal direction (Y direction). In some example embodiments, an intersecting direction cutting structure YDC may include at least three separate cutting lines extending longitudinally in the second horizontal direction (Y direction) and spaced apart from each other in the second horizontal direction (Y direction).

[0089] exist Figure 5B and Figure 5C The diagram illustrates a structure where the material of the dam structure DM differs from the material of the intersecting direction cutting structure YDC; however, the inventive concept is not limited thereto. According to some embodiments, the material of the dam structure DM may be the same as the material of the intersecting direction cutting structure YDC.

[0090] like Figure 5A As shown, multiple dummy word line cut structures XDC1, XDC2, XDC3, and XDC4 can be disposed in each of the memory cell blocks BLK11 and BLK12. Similar to the multiple word line cut structures WLC, the multiple dummy word line cut structures XDC1, XDC2, XDC3, and XDC4 can all extend longitudinally in a first horizontal direction (X direction). Similar to the dam structure DM, in the connection region CON, the multiple dummy word line cut structures XDC1, XDC2, XDC3, and XDC4 can all pass through the interlayer insulating layer 138, multiple gate lines 130, multiple insulating layers 132, second conductive plate 118, and insulating plate 112, can extend in the vertical direction (Z direction), and can be located on the upper substrate 110. In some embodiments, the material of each of the multiple dummy word line cut structures XDC1, XDC2, XDC3, and XDC4 can be the same as the material of each of the multiple word line cut structures WLC described above.

[0091] Multiple dummy word line cut structures XDC1 can be disposed between the memory cell region MEC and the intersecting direction cut structure YDC. The multiple dummy word line cut structures XDC1 can be spaced apart from each other in the second horizontal direction (Y direction), can be repeatedly arranged in the second horizontal direction (Y direction), can extend parallel to each other in the first horizontal direction (X direction), and can be located between the memory cell region MEC and the intersecting direction cut structure YDC.

[0092] Multiple dummy word line cutting structures XDC2 can be set between the intersecting direction cutting structure YDC and the dam structure DM. These multiple dummy word line cutting structures XDC2 can be spaced apart from each other in the second horizontal direction (Y direction), can be repeatedly arranged in the second horizontal direction (Y direction), can extend parallel to each other in the first horizontal direction (X direction), and can be located between the intersecting direction cutting structure YDC and the dam structure DM.

[0093] Multiple dummy channel structures D180 can be positioned between the intersecting direction cutting structure YDC and the dam structure DM. These multiple dummy channel structures D180 may include two dummy channel structures D180 spaced apart from each other by a dummy line cutting structure XDC2. Figure 5A The diagram shows multiple dummy channel structures D180 disposed only in a portion of the connection region CON, but the inventive concept is not limited thereto. Multiple dummy channel structures D180 selected from the storage stack structure MST within the connection region CON can be arranged in various locations.

[0094] Multiple dummy word line cut structures XDC3 can be disposed between the word line cut structure WLC and the dam structure DM. The multiple dummy word line cut structures XDC3 can extend parallel to a portion of the dam structure DM in a first horizontal direction (X direction). The dummy word line cut structures XDC3 can be positioned for certain portions (e.g., Figure 5A The portion of VAY in the middle is supported and can extend longitudinally along the sidewall of the dam structure DM in the first horizontal direction (X direction). It can be located in the connection area CON, which includes the storage stack structure MST and the interlayer insulation layer 138 covering the top surface of the storage stack structure MST (see Figure 5B The stacked structure of the dam structure DM is located adjacent to the dam structure DM, so that these parts will not collapse or crumble due to the stress caused by the relatively large volume of the interlayer insulation layer 138. The intersecting direction cut structure YDC can be set on the corresponding opposite side of the dam structure DM in the first horizontal direction (X direction) (e.g., set on the corresponding opposite side of the dam structure DM in the first horizontal direction (X direction)). At the same time, the dummy line cut structure XDC3 and the dam structure DM are located between the intersecting direction cut structure YDC. Therefore, the volume of the interlayer insulation layer 138 in the peripheral region of the dam structure DM can be divided into several small parts. Therefore, the undesirable stress caused by the relatively large volume of the interlayer insulation layer 138 can be reduced near the dam structure DM, and undesirable deformation can be reduced or prevented near the dam structure DM, that is, including the storage stacked structure MST and the interlayer insulation layer 138 covering the top surface of the storage stacked structure MST (see Figure 5B The stacked structure collapsed or collapsed due to stress caused by the relatively large volume of interlayer insulation layer 138.

[0095] Multiple dummy word line cutting structures XDC4 can be spaced apart from dummy word line cutting structures XDC1, while the dam structure DM, multiple intersecting direction cutting structures YDC, and multiple dummy word line cutting structures XDC2 and XDC3 are located between them. Similar to multiple dummy word line cutting structures XDC1, multiple dummy word line cutting structures XDC4 can be spaced apart from each other in the second horizontal direction (Y direction), can be repeatedly arranged in the second horizontal direction (Y direction), and can extend parallel to each other in the first horizontal direction (X direction).

[0096] Some of the dummy word line cut structures XDC1, XDC2, XDC3, and XDC4 can be arranged in a row in the first horizontal direction (X direction) and can be spaced apart from each other in the first horizontal direction (X direction).

[0097] like Figure 5B As shown, in the connection region CON, the top surface of the dam structure DM and the top surface of each of the plurality of intersecting direction cut structures YDC can be located at a first horizontal height LV1 away from the upper substrate 110. Although not shown, the top surface of each of the plurality of dummy word line cut structures XDC1, XDC2, XDC3 and XDC4 can be located at a first horizontal height LV1 away from the upper substrate 110.

[0098] In the connection area CON, the dam structure DM, multiple intersecting direction cutting structures YDC, multiple word line cutting structures WLC, multiple dummy word line cutting structures XDC1, XDC2, XDC3 and XDC4, and the second upper insulation layer 189 can be covered by the third upper insulation layer 190.

[0099] like Figure 5B As shown, an insulating plug 120 passing through the upper substrate 110, the insulating plate 112, and the second conductive plate 118 may be disposed in a portion of the connection region CON. The insulating plug 120 may be disposed in a region perpendicularly overlapping the through-path region TA defined by the dam structure DM. The insulating plug 120 may comprise silicon oxide, silicon nitride, or a combination thereof.

[0100] A portion of the through-path region TA defined by the dam structure DM may be filled with insulating islands INS. The insulating islands INS may be spaced apart from multiple gate lines 130, with the dam structure DM located between them. The insulating islands INS may include multiple insulating layer structures, such as insulating layers 132 and sacrificial insulating layers 134, stacked alternately. In the insulating islands INS, insulating layer 132 may include, for example, silicon oxide, and sacrificial insulating layer 134 may include, for example, silicon nitride. In some example embodiments, the insulating islands INS may include a single insulating layer. The upper portion of the through-path region TA defined by the dam structure DM may be filled with a portion of interlayer insulating layer 138, a portion of the first upper insulating layer 187, and a portion of the second upper insulating layer 189.

[0101] Within the through-path region TA defined by the dam structure DM, multiple through-paths THV can pass through the insulating island INS, interlayer insulation layer 138, first upper insulation layer 187, second upper insulation layer 189, and third upper insulation layer 190, and can extend in the vertical direction (Z direction). The top surface of each of the multiple through-paths THV can contact the wiring layer ML formed on the third upper insulation layer 190.

[0102] Multiple through-path THVs can pass through the insulating plug 120 and extend longitudinally in the vertical direction (Z direction) to the peripheral circuit structure PCS. Each through-path THV can include a portion surrounded by the insulating plug 120 and the insulating island INS. The multiple through-path THVs can connect to peripheral circuitry included in the peripheral circuit structure PCS. The multiple through-path THVs can include, for example, tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or combinations thereof.

[0103] like Figure 5B As shown, multiple contact structures CTS, respectively connected to the edge portions of multiple gate lines 130, can be disposed in the connection region CON. Each of the multiple contact structures CTS can extend through the interlayer insulating layer 138, the first upper insulating layer 187, the second upper insulating layer 189, and the third upper insulating layer 190 from the edge portion of a corresponding gate line among the multiple gate lines 130, and can extend longitudinally in the vertical direction (Z direction). The top surface of each of the multiple contact structures CTS can contact the wiring layer ML formed on the third upper insulating layer 190. In the connection region CON, the multiple wiring layers ML formed on the third upper insulating layer 190 can be disposed at the same horizontal height from the upper substrate 110 as the multiple bit lines BL disposed in the memory cell region MEC. The multiple contact structures CTS and the multiple wiring layers ML can all comprise, for example, tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or combinations thereof.

[0104] like Figure 5Band Figure 5C As shown, the peripheral circuit structure PCS may include a lower substrate 52, a plurality of peripheral circuits formed on the lower substrate 52, and a multilayer wiring structure MWS that connects the plurality of peripheral circuits or connects the plurality of peripheral circuits to components in the memory cell region MEC.

[0105] The lower substrate 52 may include, for example, a semiconductor substrate. For example, the lower substrate 52 may include silicon (Si), germanium (Ge), or SiGe. The active region AC may be defined in the lower substrate 52 by an isolation layer 54. Multiple transistors TR of multiple peripheral circuits may be formed on the active region AC. Each of the multiple transistors TR may include a gate PG and multiple ion-implanted regions PSD formed in the active region AC adjacent to (e.g., located at) a corresponding opposite side of the gate PG. Each of the multiple ion-implanted regions PSD may be a source or drain region of a corresponding transistor TR.

[0106] Multiple peripheral circuits included in the peripheral circuit structure PCS may include those referenced above. Figure 1 The peripheral circuit 30 described includes various circuits. In an example embodiment, multiple peripheral circuits included in the peripheral circuit structure PCS may all be included in... Figure 1 The diagram shows a row decoder 32, a page buffer 34, a data I / O circuit 36, control logic 38, and a common source line driver 39.

[0107] The multilayer wiring structure MWS included in the peripheral circuit structure PCS may include multiple peripheral circuit wiring layers ML60, ML61, and ML62 and multiple peripheral circuit contacts MC60, MC61, and MC62. At least some of the multiple peripheral circuit wiring layers ML60, ML61, and ML62 may be electrically connected to transistors TR. The multiple peripheral circuit contacts MC60, MC61, and MC62 may connect some of the multiple transistors TR to some of the multiple peripheral circuit wiring layers ML60, ML61, and ML62.

[0108] Multiple through-paths (THVs) located in the connection area CON of the cell array structure CAS can be connected to at least one of the multiple peripheral circuits via a multi-layer wiring structure (MWS) included in the peripheral circuit structure PCS. The multiple through-paths (THVs) can be connected to one of the multiple peripheral circuit wiring layers ML60, ML61, and ML62. For example, the multiple through-paths (THVs) can all contact the outermost peripheral circuit wiring layer ML62 closest to the cell array structure CAS among the multiple peripheral circuit wiring layers ML60, ML61, and ML62. Figure 5B and Figure 5CIn the diagram, the Multilayer Wiring System (MWS) is shown as comprising three wiring layers in the vertical direction (Z direction), but the inventive concept is not limited to this. Figure 5B and Figure 5C The illustration shows an example. For instance, a multilayer cabling structure (MWS) may include two, four, or more cabling layers.

[0109] The multiple peripheral circuit wiring layers ML60, ML61, and ML62, as well as the multiple peripheral circuit contacts MC60, MC61, and MC62, may all comprise, for example, metals, conductive metal nitrides, metal silicides, or combinations thereof. For instance, the multiple peripheral circuit wiring layers ML60, ML61, and ML62, as well as the multiple peripheral circuit contacts MC60, MC61, and MC62, may all comprise conductive materials such as tungsten, molybdenum, titanium, cobalt, tantalum, nickel, tungsten silicide, titanium silicide, cobalt silicide, tantalum silicide, or nickel silicide.

[0110] Multiple transistors (TRs) and multilayer wiring structures (MWS) included in the peripheral circuit structure (PCS) can be covered by the interlayer insulating layer (70). Multiple through-paths (THVs) can pass through a portion of the interlayer insulating layer (70) and can contact the top surface of the peripheral circuit wiring layer (ML62). The interlayer insulating layer (70) can include, for example, silicon oxide, SiON, or SiOCN.

[0111] Refer to the above Figure 4 and Figures 5A to 5E In the described semiconductor device 100, the number of gate lines 130 stacked in the vertical direction (Z direction) is increased to improve the integration density of the semiconductor device 100 and thus the height of the memory stack structure MST is increased, thereby increasing the interlayer insulating layer 138 covering the memory stack structure MST in the connection region CON of the cell array structure CAS (see Figure 5B In the above case, the intersecting direction cut structure YDC can be set close to the dam structure DM in the connection region CON. Therefore, the volume of the interlayer insulation layer 138 can be divided into several small parts in the peripheral region of the dam structure DM. Therefore, the undesirable stress caused by the relatively large volume of the interlayer insulation layer 138 can be reduced near the dam structure DM. Therefore, undesirable deformation can be reduced or prevented near the dam structure DM, i.e., including the storage stack structure MST and the interlayer insulation layer 138 covering the top surface of the storage stack structure MST (see...). Figure 5B The stacked structure collapsed or collapsed due to stress caused by the relatively large volume of interlayer insulation layer 138.

[0112] Figure 6 This is a cross-sectional view of a semiconductor device 200 according to some embodiments of the present invention, and is related to... Figure 5C An enlarged cross-sectional view of the portion corresponding to the VCX region.

[0113] Reference Figure 6 Semiconductor device 200 may include the same components as those referenced above. Figures 5A to 5E The semiconductor device 100 described herein has substantially the same components. However, the semiconductor device 200 may include a gate dielectric layer 182A instead of a gate dielectric layer 182. The gate dielectric layer 182A may include components similar to those described above. Figure 5B and Figure 5C The elements of the described gate dielectric layer 182 are substantially the same. Gate dielectric layer 182A may include a first barrier dielectric layer BD1 and a second barrier dielectric layer BD2, instead of a barrier dielectric layer BD. The first barrier dielectric layer BD1 may extend parallel to the channel region 184, and the second barrier dielectric layer BD2 may be configured to surround the gate line 130. Both the first barrier dielectric layer BD1 and the second barrier dielectric layer BD2 may include, for example, silicon oxide, silicon nitride, or a metal nitride. For example, the first barrier dielectric layer BD1 may include silicon oxide, and the second barrier dielectric layer BD2 may include a metal oxide with a dielectric constant greater than that of silicon oxide. The metal oxide may include, for example, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or combinations thereof.

[0114] Figure 7 This is a top view of a semiconductor device 300 according to some embodiments of the present invention, and is related to... Figure 5A An enlarged cross-sectional view of the portion corresponding to region VAX.

[0115] Reference Figure 7 Semiconductor device 300 may include the same components as referenced above. Figures 5A to 5E The semiconductor device 100 described herein has substantially the same components. However, the semiconductor device 300 may include an intersecting direction cut structure YDC3. The intersecting direction cut structure YDC3 may include components similar to those described above. Figure 5A and Figure 5B The elements of the described intersecting direction cut structure YDC are substantially the same. The intersecting direction cut structure YDC3 can extend non-linearly and longitudinally in the second horizontal direction (Y direction). In the example embodiment, the intersecting direction cut structure YDC3 can extend non-linearly in the second horizontal direction (Y direction), thereby having a concave shape as viewed from the dam structure DM.

[0116] The intersecting direction cut structure YDC3 may include multiple cut lines YDC3A and YDC3B spaced apart from each other in the second horizontal direction (Y direction). The multiple cut lines YDC3A and YDC3B may be arranged in a row in the second horizontal direction (Y direction). The multiple cut lines YDC3A and YDC3B may pass through the storage stack structure MST and the interlayer insulating layer 138 in the vertical direction (Z direction) (see...). Figure 5B ).

[0117] exist Figure 7 The illustration shows an example of an intersecting direction cutting structure YDC3 comprising two cutting lines YDC3A and YDC3B spaced apart from each other in a second horizontal direction (Y direction), but the inventive concept is not limited thereto. In some example embodiments, the intersecting direction cutting structure YDC3 may include a single cutting line extending non-linearly and longitudinally in the second horizontal direction (Y direction). In some example embodiments, the intersecting direction cutting structure YDC3 may include at least three cutting lines spaced apart from each other in the second horizontal direction (Y direction) and extending non-linearly and longitudinally in the second horizontal direction (Y direction).

[0118] Figure 8 This is a top view of a semiconductor device 400 according to some embodiments of the present invention, and is related to... Figure 5A A magnified top view of the area corresponding to VAX.

[0119] Reference Figure 8 Semiconductor device 400 may include the same components as referenced above. Figures 5A to 5E The semiconductor device 100 has substantially the same components as those in the semiconductor device 400. However, the semiconductor device 400 may include an intersecting direction cut structure YDC4. The intersecting direction cut structure YDC4 may include components similar to those referenced above. Figure 5A and Figure 5B The elements of the intersecting direction cut structure YDC are substantially the same. The intersecting direction cut structure YDC4 can extend non-linearly and longitudinally in the second horizontal direction (Y direction). In the example embodiment, the intersecting direction cut structure YDC4 can extend non-linearly in the second horizontal direction (Y direction), thus having a convex shape as viewed from the dam structure DM.

[0120] The intersecting direction cut structure YDC4 may include multiple cut lines YDC4A and YDC4B spaced apart from each other in the second horizontal direction (Y direction). The multiple cut lines YDC4A and YDC4B may be arranged in a row in the second horizontal direction (Y direction). The multiple cut lines YDC4A and YDC4B may pass through the memory stack structure MST and the interlayer insulating layer 138 in the vertical direction (Z direction) (see...). Figure 5B ).

[0121] exist Figure 8The illustration shows an example of an intersecting direction cutting structure YDC4 comprising two cutting lines YDC4A and YDC4B spaced apart from each other in a second horizontal direction (Y direction), but the inventive concept is not limited thereto. In some example embodiments, the intersecting direction cutting structure YDC4 may include a single cutting line extending non-linearly and longitudinally in the second horizontal direction (Y direction). In some example embodiments, the intersecting direction cutting structure YDC4 may include at least three cutting lines spaced apart from each other in the second horizontal direction (Y direction) and extending non-linearly and longitudinally in the second horizontal direction (Y direction).

[0122] exist Figures 5A to 5E , Figure 7 and Figure 8 The semiconductor devices 100, 300, and 400 shown can each include multiple intersecting direction cut structures YDC, YDC3, and YDC4 extending linearly or nonlinearly and longitudinally in the second horizontal direction (Y direction). The multiple intersecting direction cut structures YDC, YDC3, and YDC4 can be disposed near the dam structure DM, thus the volume of the interlayer insulating layer 138 in the peripheral region of the dam structure DM can be divided into several small portions. Furthermore, the intersecting direction cut structure YDC extending linearly in the second horizontal direction (Y direction), the intersecting direction cut structure YDC3 having a concave shape as viewed from the dam structure DM, or the intersecting direction cut structure YDC4 having a convex shape as viewed from the dam structure DM can be implemented based on the type and magnitude of stress caused by the interlayer insulating layer 138. Therefore, various methods can be used to reduce or prevent problems caused by stress in the interlayer insulating layer 138 near the dam structure DM. Therefore, in the semiconductor devices to be manufactured, despite the various types and magnitudes of stress caused by the relatively large volume of the interlayer insulating layer 138, intersecting direction cut structures YDC, YDC3, and YDC4 with appropriate shapes can be applied. Thus, undesirable deformations, i.e., including the memory stack structure MST near the dam structure DM and the interlayer insulating layer 138 covering the memory stack structure MST (see...), can be effectively reduced or prevented. Figure 5B The stacked structure collapsed or collapsed due to the stress caused by the relatively large volume of the interlayer insulation layer 138.

[0123] Figure 9 This is a cross-sectional view of a semiconductor device 500 according to some embodiments of the present invention. Figure 9 In the diagram, a semiconductor device 500 is shown that is along... Figure 5A The enlarged cross-sectional structure of some elements in the region corresponding to the cross-sectional surface intercepted by line X1-X1'. Figure 9 In, with Figures 5A to 5EThe same reference numerals refer to the same elements, and their detailed descriptions may be omitted.

[0124] Reference Figure 9 Semiconductor device 500 may include the same components as referenced above. Figures 5A to 5E The semiconductor device 100 described herein has substantially the same components. However, the semiconductor device 500 may include an intersecting direction cut structure YDC5. The intersecting direction cut structure YDC5 may include components similar to those described above. Figure 5A and Figure 5B The components of the intersecting direction cut structure YDC described are essentially the same. The material of the intersecting direction cut structure YDC5 can be the same as the material of the dam structure DM. That is, similar to the reference above. Figure 5B and Figure 5C The described dam structure DM, with its intersecting direction cut structure YDC5, may include a first insulating pad 142, a second insulating pad 144, and a main plug 146 sequentially stacked from the inner wall of the intersecting direction hole YH toward the interior of the dam hole DMH. In an example embodiment, the first insulating pad 142 may include, for example, silicon oxide, the second insulating pad 144 may include, for example, silicon nitride, and the main plug 146 may include, for example, polysilicon. However, the inventive concept is not limited thereto.

[0125] Figure 10A and Figure 10B This is a cross-sectional view of a semiconductor device 600 according to some embodiments of the present invention. Figure 10A In the image, a semiconductor device 600 is shown with respect to the elements along the [path / parameter]. Figure 5A The enlarged cross-sectional structure of some elements in the region corresponding to the cross-sectional surface intercepted by line X1-X1'. Figure 10B In the image, a semiconductor device 600 is shown with respect to the elements along the [path / parameter]. Figure 5A The enlarged cross-sectional structure of some elements in the region corresponding to the cross-sectional surface intercepted by line Y1-Y1'. Figure 10A and Figure 10B In, with Figures 5A to 5E The same reference numerals refer to the same elements, and their detailed descriptions may be omitted.

[0126] Reference Figure 10A and Figure 10B Semiconductor device 600 may include the same components as referenced above. Figures 5A to 5E The semiconductor device 100 described herein contains substantially the same components. The semiconductor device 600 may include an intersecting direction cut structure YDC6 and a plurality of word line cut structures WLC6. The intersecting direction cut structure YDC6 and the plurality of word line cut structures WLC6 may include components similar to those described above. Figure 5A and Figure 5BThe intersecting direction cut structure YDC and the word line cut structure WLC described herein have substantially the same components. Both the intersecting direction cut structure YDC6 and the plurality of word line cut structures WLC6 may include an insulating pad 644 and a main plug 646 surrounded by the insulating pad 644. In an example embodiment, the insulating pad 644 may include, for example, a silicon oxide layer, and the main plug 646 may include, for example, a metal layer. For example, the metal layer included in the main plug 646 may include a W layer.

[0127] Figure 11 This is a cross-sectional view of a semiconductor device 700 according to some embodiments of the present invention. Figure 11 In the image, a semiconductor device 700 is shown with respect to the elements along the [path / parallel] path. Figure 5A The enlarged cross-sectional structure of some elements in the region corresponding to the cross-sectional surface intercepted by line Y1-Y1'. Figure 11 In, with Figures 5A to 5E The same reference numerals refer to the same elements, and their detailed descriptions may be omitted.

[0128] Reference Figure 11 Semiconductor device 700 may include the same components as referenced above. Figures 5A to 5E The semiconductor device 100 described has substantially the same components. However, the semiconductor device 700 may include a memory stack structure MST7 instead of the memory stack structure MST of the semiconductor device 100.

[0129] The memory stack structure MST7 may include a lower gate stack GS71 and an upper gate stack GS72. The lower gate stack GS71 includes multiple gate lines 130, and the upper gate stack GS72 includes multiple gate lines 730. In the lower gate stack GS71, an insulating layer 132 may be disposed between two adjacent gate lines 130. In the upper gate stack GS72, an insulating layer 732 may be disposed between two adjacent gate lines 730. An intermediate insulating layer 750 having a thickness greater than that of the insulating layer 132 or the insulating layer 732 may be disposed between the lower gate stack GS71 and the upper gate stack GS72. Both the insulating layer 732 and the intermediate insulating layer 750 may comprise, for example, silicon oxide.

[0130] In an example embodiment, the lower gate stack GS71 may include 48, 64, or 96 gate lines 130 stacked in the vertical direction (Z direction), and the upper gate stack GS72 may include 48, 64, or 96 gate lines 730 stacked in the vertical direction (Z direction). In an example embodiment, the sum of the number of gate lines 130 in the lower gate stack GS71 and the number of gate lines 730 in the lower gate stack GS72 may be at least 128.

[0131] In the memory cell region MEC of the CAS cell array structure, multiple channel structures 780 can pass through multiple gate lines 730, multiple insulating layers 732, intermediate insulating layer 750, multiple gate lines 130, multiple insulating layers 132, second conductive plate 118 and first conductive plate 114, and can extend longitudinally in the vertical direction (Z direction), and can be located on the upper substrate 110.

[0132] The multiple channel structures 780 may include a gate dielectric layer 782, a channel region 784, a buried insulating layer 786, and a drain region 788. The gate dielectric layer 782, channel region 784, buried insulating layer 786, and drain region 788 may be as described above. Figure 5A and Figure 5C The gate dielectric layer 182, channel region 184, buried insulating layer 186, and drain region 188 included in the described channel structure 180 are the same or similar. The gate dielectric layer 782, channel region 784, and buried insulating layer 786 included in the plurality of channel structures 780 may all include bent portions in the region surrounded by the intermediate insulating layer 750. In an example embodiment, in the process of manufacturing the semiconductor device 700, to form the plurality of channel structures 780, a lower channel via through a lower molded structure including a plurality of insulating layers 132 may first be formed. Then, with a sacrificial layer filled into the lower channel via, an upper channel via through an upper molded structure including a plurality of insulating layers 732 and communicating with the lower channel via may be formed, thereby forming a channel via with a two-level structure required for forming the plurality of channel structures 780. Subsequently, the gate dielectric layer 782, channel region 784, and buried insulating layer 786 may be formed in the channel via with the two-level structure. In this configuration, a lower portion of the intermediate insulating layer 750 may include the insulating layer included in the lower molding structure, and a higher portion of the intermediate insulating layer 750 may include the insulating layer included in the lower molding structure. When the gate dielectric layer 782, the channel region 784, and the buried insulating layer 786 are being formed in a channel via having a two-level structure, a bent portion INF may be formed in each of the gate dielectric layer 782, the channel region 784, and the buried insulating layer 786 near the portion where the lower channel via contacts the upper channel via, based on the horizontal width difference between the lower and upper channel vias.

[0133] A more detailed description of the gate dielectric layer 782, channel region 784, buried insulating layer 786, and drain region 788 can be found in the above description. Figures 5A to 5C The gate dielectric layer 182, channel region 184, buried insulating layer 186, and drain region 188 described are substantially the same. Although not shown, they are referenced above. Figure 5A and Figure 5BThe described plurality of dummy channel structures D180 can be disposed in the connection region CON of the semiconductor device 700. The cross-sectional structure of each of the plurality of dummy channel structures D180 can have the same cross-sectional structure as described above. Figure 11 Each of the multiple channel structures 780 described has a similar structure.

[0134] Figure 12A This is a top view of a semiconductor device 800 according to some embodiments of the present invention. Figure 12A In, with Figures 5A to 5E The same reference numerals refer to the same elements, and their detailed descriptions may be omitted. Figure 12A It shows the ability to constitute Figure 4 Some elements of storage cell blocks BLK81 and BLK82 of the multiple storage cell blocks BLK1, BLK2, ... and BLKp shown in the figure.

[0135] Reference Figure 12A The semiconductor device 800 may include the same components as referenced above. Figures 5A to 5E The semiconductor device 100 described uses the same elements. The semiconductor device 800 may include multiple dam structures DM81 and DM82 spaced apart from each other in a first horizontal direction (X direction) between two adjacent word line cut structures WLC in the connection region CON of the cell array structure CAS. An intersecting direction cut structure YDC may be configured to be adjacent to each side of the multiple dam structures DM81 and DM82 in the first horizontal direction (X direction) (e.g., disposed at each side of the multiple dam structures DM81 and DM82 in the first horizontal direction (X direction), while the multiple dam structures DM81 and DM82 are located between the intersecting direction cut structures YDC. A portion of the memory stack structure MST may be disposed in the space between the multiple dam structures DM81 and DM82 separated from each other along the first horizontal direction (X direction). Multiple through-paths THV may be disposed in each of the multiple dam structures DM81 and DM82.

[0136] Multiple virtual channel structures D180 can be set between the intersecting direction cutting structure YDC and multiple dam structures DM81 and DM82. Figure 5A The multiple dummy word line cutting structures XDC2 shown in the figure may not be set between the intersecting direction cutting structure YDC and the multiple dam structures DM81 and DM82.

[0137] exist Figure 12A The above reference is shown in the middle. Figure 5A and Figure 5D The described intersecting direction cutting structure YDC extends linearly and longitudinally in the second horizontal direction (Y direction), but the inventive concept is not limited thereto. Figure 12A The semiconductor device 800 shown can be used between two adjacent word line cut structures (WLCs) like... Figure 7 The intersecting direction cutting structure YDC3 or shown in the figure Figure 8 The intersecting direction cutting structure shown is an intersecting direction cutting structure YDC4, which has a structure that extends non-linearly and longitudinally in the direction intersecting with the word line cutting structure WLC, rather than the intersecting direction cutting structure YDC.

[0138] Figure 12B This is a top view of a semiconductor device 900 according to some embodiments of the present invention. Figure 12B In, with Figures 5A to 5E The same reference numerals refer to the same elements, and their detailed descriptions may be omitted.

[0139] Reference Figure 12B Semiconductor device 900 may include the same components as referenced above. Figures 5A to 5E The semiconductor device 100 described herein has substantially the same components. However, the semiconductor device 900 may include an intersecting direction cut structure YDC9. The intersecting direction cut structure YDC9 may include components similar to those described above. Figure 5A and Figure 5B The components of the intersecting direction cut structure YDC described are essentially the same. The intersecting direction cut structure YDC9 may include a cut line extending longitudinally in a second horizontal direction (Y direction) between two adjacent word line cut structures WLC.

[0140] exist Figure 12B The above reference is shown in the middle. Figure 5A and Figure 5D The described intersecting direction cutting structure YDC9 is a structure that extends linearly and longitudinally in the second horizontal direction (Y direction), but the inventive concept is not limited thereto. Figure 12B The semiconductor device 900 shown can be used between two adjacent word line cut structures (WLCs) like... Figure 7 The intersecting direction cutting structure YDC3 or shown in the figure Figure 8 The intersecting direction cutting structure shown is an intersecting direction cutting structure YDC4, which has a structure that extends non-linearly and longitudinally in the direction intersecting with the word line cutting structure WLC, rather than the intersecting direction cutting structure YDC9.

[0141] Methods for manufacturing semiconductor devices according to some embodiments of the present invention will be described in detail.

[0142] Figures 13A to 18B This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some embodiments. Specifically, Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A and Figure 18A It is along Figure 5A The cross-sectional view taken by line X1-X1', and Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B and Figure 18B It is along Figure 5A The cross-sectional view taken by line Y1-Y1'. (Refer to...) Figures 13A to 18B The description of the manufacturing process is based on the above reference. Figures 5A to 5E The method described for the semiconductor device 100.

[0143] Reference Figure 13A and Figure 13B This can form a peripheral circuit structure PCS including a lower substrate 52, multiple transistors TR, a multilayer wiring structure MWS, and an interlayer insulating layer 70.

[0144] An upper substrate 110 can be formed on the interlayer insulating layer 70 of the peripheral circuit structure PCS, and a cell array structure CAS (see [reference]) can be formed on the peripheral circuit structure PCS. Figure 5B and Figure 5C An insulating plate 112 and a second conductive plate 118, both covering the substrate 110, are sequentially formed in the memory cell region MEC and the connection region CON. The insulating plate 112 may include an insulating layer with a multilayer structure, which may include a first insulating layer 112A, a second insulating layer 112B, and a third insulating layer 112C.

[0145] It can be in the through-path area TA (see) of the connecting area CON. Figure 5B A through hole is formed at the corresponding position, passing through the upper substrate 110, the insulating plate 112, and the second conductive plate 118, and an insulating plug 120 can be formed to fill the through hole.

[0146] Reference Figure 14A and Figure 14B In the memory cell region (MEC) and the connection region (CON), multiple insulating layers 132 and multiple sacrificial insulating layers 134 may be alternately stacked on the second conductive plate 118 and the insulating plug 120. The multiple insulating layers 132 may include, for example, silicon oxide, and the multiple sacrificial insulating layers 134 may include, for example, silicon nitride. The multiple sacrificial insulating layers 134 may each ensure space for forming multiple gate lines 130 in subsequent processes.

[0147] Reference Figure 15A and Figure 15BIn the connection region CON, a portion of each of the plurality of insulating layers 132 and the plurality of sacrificial insulating layers 134 may be removed to form a stepped structure having a width that decreases horizontally as the plurality of insulating layers 132 and the plurality of sacrificial insulating layers 134 move away from the upper substrate 110. Subsequently, an interlayer insulating layer 138 may be formed to cover the edge portions of each of the plurality of insulating layers 132 and the plurality of sacrificial insulating layers 134 forming the stepped structure in the connection region CON. After the interlayer insulating layer 138 is formed, the top surface of the uppermost insulating layer 132 of the plurality of insulating layers 132 in the memory cell region MEC and the top surface of the interlayer insulating layer 138 in the connection region CON may be at the same horizontal height from the upper substrate 110.

[0148] Multiple channel structures 180 and multiple dummy channel structures D180 can be formed. The multiple channel structures 180 pass through multiple insulating layers 132 and multiple sacrificial insulating layers 134 in the memory cell region MEC and extend longitudinally in the vertical direction (Z direction). The multiple dummy channel structures D180 pass through multiple insulating layers 132, multiple sacrificial insulating layers 134 and interlayer insulating layers 138 in the memory cell region MEC and extend longitudinally in the vertical direction (Z direction). In the process of forming multiple channel structures 180 and multiple dummy channel structures D180, a gate dielectric layer 182, a channel region 184 and a buried insulating layer 186 can be formed in the memory cell region MEC and the connection region CON. Then, before forming the drain region 188, the uppermost insulating layer 132 of the multiple insulating layers 132 in the memory cell region MEC and a first upper insulating layer 187 covering the interlayer insulating layer 138 in the connection region CON can be formed. Subsequently, a plurality of drain regions 188 can be formed through the first upper insulating layer 187 and connected to the channel region 184.

[0149] Reference Figure 16A and Figure 16B A second upper insulating layer 189 covering multiple channel structures 180, multiple dummy channel structures D180, and a first upper insulating layer 187 can be formed in the memory cell region MEC and the connection region CON.

[0150] Multiple word line cut holes (WCH), multiple dam holes (DMH), and multiple intersecting direction holes (YH) can be formed in the memory cell region (MEC) and the connection region (CON) through the second upper insulating layer 189, the first upper insulating layer 187, multiple insulating layers 132, multiple sacrificial insulating layers 134, the second conductive plate 118, and the insulating plate 112 to expose the upper substrate 110. While the multiple word line cut holes (WCH), multiple dam holes (DMH), and multiple intersecting direction holes (YH) are being formed, holes for forming... Figure 5AMultiple dummy holes (not shown) of the multiple dummy word wire-cut structures XDC1, XDC2, XDC3, and XDC4 are shown in the figure. As used herein, "simultaneous formation" may refer to formation by the same (one or more) processes at approximately (but not necessarily precisely) the same time.

[0151] A first insulating gasket 142, a second insulating gasket 144, and a main plug 146 can be formed in each of the multiple letter-cut holes WCH, multiple dam holes DMH, and multiple intersecting direction holes YH. At this time, in the connection area CON, for forming... Figure 5A A first insulating gasket 142, a second insulating gasket 144, and a main plug 146 are formed in multiple dummy holes (not shown) of the multiple dummy word wire-cut structures XDC1, XDC2, XDC3, and XDC4 shown in the figure. The first insulating gasket 142, the second insulating gasket 144, and the main plug 146 filling the multiple dam holes DM can form multiple dam structures DM.

[0152] By executing the above reference Figure 16A and Figure 16B In the structure obtained by the described process, multiple intersecting holes YH extending longitudinally in the second horizontal direction (Y direction) can be formed near the dam structure DM in the connecting region CON, and the first insulating gasket 142, the second insulating gasket 144, and the main plug 146 can fill the multiple intersecting holes YH. Therefore, the interlayer insulation layer 138 can be partially divided by the multiple intersecting holes YH in the peripheral region of the dam structure DM, and thus the volume of the interlayer insulation layer 138 can be divided into several small portions. Therefore, undesirable stress caused by the relatively large volume of the interlayer insulation layer 138 can be reduced near the dam structure DM. Therefore, undesirable deformation, i.e., the collapse or toppling of the molded structure including multiple insulating layers 132 and multiple sacrificial insulating layers 134 due to stress caused by the relatively large volume of the interlayer insulation layer 138, can be reduced or prevented near the dam structure DM while performing subsequent processes. Therefore, process defects caused by undesirable deformation of the molded structure can be reduced or prevented. (Refer to...) Figure 17A and Figure 17B Covering the mask pattern (not shown) Figure 16A and Figure 16BIn the resulting structure, with multiple dam structures DM in the connection region CON, by removing the first insulating pad 142, the second insulating pad 144, and the main plug 146 from each of the multiple word line cut holes WCH and multiple intersecting direction holes YH in the memory cell region MEC and the connection region CON, multiple insulating layers 132, multiple sacrificial insulating layers 134, the second conductive plate 118, the insulating plate 112, and the upper substrate 110 can be exposed through the multiple word line cut holes WCH and multiple intersecting direction holes YH. In this case, the structures formed in the connection region CON can also be removed. Figure 5A The first insulating pad 142, the second insulating pad 144, and the main plug 146 are shown in each of the plurality of dummy vias (not shown) of the plurality of dummy word wire-cut structures XDC1, XDC2, XDC3, and XDC4. In the example embodiment, the mask pattern may include a photoresist pattern.

[0153] The insulating plate 112 can be selectively removed only within the memory cell region MEC, which is located within the connection region CON, through the internal space of each of the multiple word line cutting holes WCH and multiple intersecting direction holes YH, and the resulting empty space can be filled by the first conductive plate 114. While the insulating plate 112 is being removed within the memory cell region MEC, the portion of the gate dielectric layer 182 included in the channel structure 180 within the memory cell region MEC adjacent to the insulating plate 112 can be removed along the insulating plate 112. Therefore, the first conductive plate 114 can pass horizontally through a portion of the gate dielectric layer 182 and can contact the channel region 184.

[0154] Alternatively, multiple sacrificial insulating layers 134 can be replaced with multiple gate lines 130 within the internal space of each of the multiple word line cut holes WCH and multiple intersecting direction holes YH in the memory cell region MEC and the connection region CON. In this case, the portion of the multiple sacrificial insulating layers 134 located in the through-path region TA surrounded by the dam structure DM can be protected by the dam structure DM and can be retained (e.g., it can be incompletely removed). The multiple sacrificial insulating layers 134 and multiple insulating layers 132, all retained in the through-path region TA, can form insulating islands INS.

[0155] After forming the first conductive plate 114 and multiple gate lines 130, multiple word line cut structures WLC can be used to fill multiple word line cut holes WCH, and multiple intersecting direction cut structures YDC can be used to fill multiple intersecting direction holes YH.

[0156] By executing the above reference Figure 17A and Figure 17BIn the structure obtained by the described process, multiple intersecting directional holes YH extending longitudinally in the second horizontal direction (Y direction) can be formed near the dam structure DM in the connection region CON, and intersecting directional cut structures YDC can be filled into the multiple intersecting directional holes YH. Therefore, the interlayer insulating layer 138 can be divided by the multiple intersecting directional holes YH in the peripheral region of the dam structure DM, and thus the volume of the interlayer insulating layer 138 can be divided into several small parts, and the structure near the multiple intersecting directional holes YH can be supported by the intersecting directional cut structures YDC. Therefore, the undesirable stress caused by the relatively large volume of the interlayer insulating layer 138 can be reduced near the dam structure DM, and undesirable deformation, i.e., the collapse or collapse of the memory stack structure MST, including multiple insulating layers 132 and multiple gate lines 130, due to the stress caused by the relatively large volume of the interlayer insulating layer 138, can be reduced or prevented near the dam structure DM while performing subsequent processes.

[0157] Reference Figure 18A and Figure 18B , can Figure 17A and Figure 17B A third upper insulating layer 190 is formed on the resulting structure. Multiple contact plugs 194 can be formed in the memory cell region (MEC) passing through the third upper insulating layer 190 and the second upper insulating layer 189 and connecting to multiple channel structures 180. Additionally, multiple contact structures CTS can be formed in the connection region (CON) passing through the third upper insulating layer 190, the second upper insulating layer 189, the first upper insulating layer 187, and the interlayer insulating layer 138 and connecting to the edge portions of multiple gate lines 130. Subsequently, multiple bit lines BL can be formed on the multiple contact plugs 194 in the memory cell region (MEC), and multiple wiring layers ML can be formed on the multiple through-paths THV in the connection region (CON), thereby fabricating the structure described above. Figures 5A to 5E The semiconductor device 100 is described.

[0158] The above has been referenced Figures 13A to 18B Describes manufacturing Figures 5A to 5E The method of semiconductor device 100 shown above is illustrated, but those skilled in the art will understand that it can be performed by means of the method described above within the scope of the inventive concept. Figures 13A to 18B Various modifications and changes were made to the described process to manufacture the above-mentioned reference. Figures 6 to 12B The semiconductor devices described are 200, 300, 400, 500, 600, 700, 800 and 900, as well as semiconductor devices having various structures obtained by various modifications and changes made according to them within the scope of the inventive concept.

[0159] Figure 19This is a schematic diagram illustrating an electronic system including semiconductor devices according to some embodiments of the present invention.

[0160] Reference Figure 19 An electronic system 1000 according to some embodiments of the present invention may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may include a storage device or an electronic device including a storage device, the storage device comprising one or more semiconductor devices 1100. For example, the electronic system 1000 may include a solid-state drive (SSD) device having at least one semiconductor device 1100, a universal serial bus (USB), a computing system, a medical device, or a communication device.

[0161] Semiconductor device 1100 may include a non-volatile memory device. For example, semiconductor device 1100 may include a NAND flash memory device, which includes the aforementioned referenced... Figures 4 to 12B The semiconductor device 1100 describes at least one of the structures selected from 100, 200, 300, 400, 500, 600, 700, 800, and 900. Semiconductor device 1100 may include a first structure 1100F and a second structure 1100S located on the first structure 1100F. In an example embodiment, the first structure 1100F may be arranged next to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and logic circuit 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, multiple word lines WL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and multiple memory cell strings CSTRs located between the bit line BL and the common source line CSL.

[0162] In the second structure 1100S, each of the multiple memory cell strings CSTRs may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and multiple memory cell transistors MCTs located between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may be modified in various ways depending on the embodiment.

[0163] In the example embodiment, upper transistors UT1 and UT2 may each include a string select transistor, and lower transistors LT1 and LT2 may each include a ground select transistor. Multiple lower gate lines LL1 and LL2 may be the gate electrodes of lower transistors LT1 and LT2, respectively. The word line WL may be the gate electrode of the memory cell transistor MCT, and upper gate lines UL1 and UL2 may be the gate electrodes of upper transistors UT1 and UT2, respectively.

[0164] The common source line CSL, multiple gate-on lines LL1 and LL2, multiple word lines WL, and multiple gate-on lines UL1 and UL2 can be electrically connected to the decoder circuit 1110 via multiple first connection wiring lines 1115 extending from the interior of the first structure 1100F to the second structure 1100S. Multiple bit lines BL can be electrically connected to the page buffer 1120 via multiple second connection wiring lines 1125 extending from the interior of the first structure 1100F to the second structure 1100S.

[0165] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one of the plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by the logic circuit 1130.

[0166] Semiconductor device 1100 can communicate with controller 1200 via input / output pads 1101 electrically connected to logic circuit 1130. Input / output pads 1101 can be electrically connected to logic circuit 1130 via input / output connection wiring lines 1135 extending from the interior of first structure 1100F to second structure 1100S.

[0167] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In an example embodiment, the electronic system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100.

[0168] Processor 1210 can control the overall operation of electronic system 1000, including controller 1200. Processor 1210 can operate according to specific firmware and can access semiconductor device 1100 by controlling NAND controller 1220. NAND controller 1220 may include NAND interface 1221 for handling communication with semiconductor device 1100. Through NAND interface 1221, control commands for controlling semiconductor device 1100, data to be written to multiple memory cell transistors (MCTs) of semiconductor device 1100, data to be read from multiple memory cell transistors (MCTs) of semiconductor device 1100, etc., can be transmitted. Host interface 1230 can provide communication functionality between electronic system 1000 and external host. When a control command is received from external host via host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0169] Figure 20 This is a schematic perspective view illustrating an electronic system including semiconductor devices according to some embodiments of the present invention.

[0170] Reference Figure 20 An electronic system 2000 according to an exemplary embodiment of the present invention may include a main substrate 2001, a controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003, and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the controller 2002 via a plurality of wiring patterns 2005 formed on the main substrate 2001.

[0171] The main board 2001 may include a connector 2006, which includes a plurality of pins for coupling to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and the external host. In an example embodiment, the electronic system 2000 may communicate with the external host via one of an interface such as Universal Serial Bus (USB), Peripheral Component Fast Interconnect (PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Memory (UFS). In an example embodiment, the electronic system 2000 may operate via power supplied from the external host via the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0172] The controller 2002 can write data to or read data from the semiconductor package 2003 and can improve the operating speed of the electronic system 2000.

[0173] DRAM 2004 can be a buffer memory used to reduce the speed difference between an external host and the semiconductor package 2003, which serves as data storage space. DRAM 2004 included in electronic system 2000 can also function as a cache memory and can provide space for temporarily storing data during control operations on semiconductor package 2003. When DRAM 2004 is included in electronic system 2000, controller 2002 may also include a NAND controller for controlling DRAM 2004, in addition to a NAND controller for controlling semiconductor package 2003.

[0174] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Both the first semiconductor package 2003a and the second semiconductor package 2003b may be semiconductor packages including a plurality of semiconductor chips 2200. Both the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a plurality of semiconductor chips 2200 located on the package substrate 2100, an adhesive layer 2300 located on the lower surface of each of the plurality of semiconductor chips 2200, a connection structure 2400 electrically connecting the plurality of semiconductor chips 2200 to the package substrate 2100, and a molding layer 2500 disposed on the package substrate 2100 to cover the plurality of semiconductor chips 2200 and the connection structure 2400.

[0175] The package substrate 2100 may include, for example, a printed circuit board having a plurality of package-on-pads 2130. The plurality of semiconductor chips 2200 may each include input / output pads 2210. The input / output pads 2210 may correspond to... Figure 19 The input / output pads 1101. Multiple semiconductor chips 2200 may include multiple gate stacks 3210 and multiple channel structures 3220. Multiple semiconductor chips 2200 may include the above-mentioned reference... Figures 4 to 12B The semiconductor device described is at least one of 100, 200, 300, 400, 500, 600, 700, 800 and 900.

[0176] In an example embodiment, the connection structure 2400 may include bonding leads that electrically connect the input / output pads 2210 to the on-package pads 2130. Therefore, in the first semiconductor package 2003a and the second semiconductor package 2003b, a plurality of semiconductor chips 2200 may be electrically connected to each other via bonding leads and may be electrically connected to the on-package pads 2130 of the package substrate 2100. In an example embodiment, in the first semiconductor package 2003a and the second semiconductor package 2003b, a plurality of semiconductor chips 2200 may be electrically connected to each other via a connection structure including a through-silicon via (TSV) instead of via a bonding lead type connection structure 2400.

[0177] In an example embodiment, the controller 2002 and the plurality of semiconductor chips 2200 may be included in a single package. In an example embodiment, the controller 2002 and the plurality of semiconductor chips 2200 may be mounted on a separate internal substrate different from the main substrate 2001, and may be interconnected with each other via wiring formed on the internal substrate.

[0178] Figure 21 This is a schematic cross-sectional view showing some embodiments of a semiconductor package according to the present invention. Figure 21 A more detailed illustration is shown along... Figure 20 The structure corresponding to the section cut by line II-II'.

[0179] Reference Figure 21 In the semiconductor package 2003, the package substrate 2100 may include, for example, a printed circuit board. The package substrate 2100 may include a package substrate body 2120 and a plurality of package pads 2130 disposed on the upper surface of the package substrate body 2120 (see...). Figure 20 The package includes multiple lower pads 2125 disposed on or exposed on the lower surface of the package substrate body 2120, and multiple internal wiring lines 2135 disposed inside the package substrate body 2120 to electrically connect multiple upper pads 2130 to the multiple lower pads 2125. The multiple upper pads 2130 can be electrically connected to multiple connection structures 2400. The multiple lower pads 2125 can be connected via multiple conductive connection units 2800 to... Figure 20 The diagram shows multiple wiring patterns 2005 located on the main substrate 2001 of the electronic system 2000.

[0180] Multiple semiconductor chips 2200 may each include a semiconductor substrate 3010, a first structure 3100, and a second structure 3200, which are stacked sequentially on the semiconductor substrate 3010 in the order stated above. The first structure 3100 may include a peripheral circuit region, which includes a plurality of peripheral wiring lines 3110. The second structure 3200 may include a common source line 3205, a gate stack 3210 located on the common source line 3205, a channel structure 3220 passing through the gate stack 3210, and a bit line 3240 electrically connected to the channel structure 3220. In an example embodiment, multiple semiconductor chips 2200 may each include the same as described above. Figure 4 and Figures 5A to 5E The components of the semiconductor device 100 described are substantially the same.

[0181] Each of the multiple semiconductor chips 2200 may include a plurality of peripheral wiring lines 3110 electrically connected to the first structure 3100 and extending into the second structure 3200 via wiring lines 3245. The via wiring lines 3245 may be disposed outside the gate stack 3210. In some example embodiments, the semiconductor package 2003 may also include via wiring lines passing through the gate stack 3210. Each of the multiple semiconductor chips 2200 may include input / output pads electrically connected to the plurality of peripheral wiring lines 3110 of the first structure 3100. Figure 20 (2210). Multiple semiconductor chips 2200 may also include contact structures CTS.

[0182] Although the inventive concept has been specifically shown and described with reference to some exemplary embodiments thereof, it will be understood that various changes in form and detail may be made herein without departing from the scope of the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: Peripheral circuit structure; A substrate, the substrate being located on the peripheral circuit structure; A pair of character line cut structures, the pair of character line cut structures extending longitudinally in a first horizontal direction on the substrate, the pair of character line cut structures being spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction; as well as Storage cell blocks, the storage cell blocks being located between the pairs of word line cut structures and on the substrate, The storage unit block includes: A memory stack structure comprising multiple gate lines that overlap each other in a vertical direction; An interlayer insulating layer is located on the edge portion of each of the plurality of gate lines; A dam structure extending through the storage stack structure and the interlayer insulation layer; An intersecting direction cut structure, the intersecting direction cut structure extending through the storage stack structure and the interlayer insulation layer in the vertical direction and extending longitudinally in a horizontal direction intersecting the first horizontal direction, the intersecting direction cut structure being spaced apart from the dam structure in the first horizontal direction; and Multiple ditch structures are located between the intersecting direction cutting structure and the dam structure.

2. The semiconductor device of claim 1, wherein, The intersecting direction cutting structure includes a linear cutting line extending in the second horizontal direction.

3. The semiconductor device of claim 1, wherein, The intersecting direction cutting structure includes nonlinear cutting lines.

4. The semiconductor device according to claim 1, wherein, The intersecting direction cutting structure includes multiple cutting lines aligned along the second horizontal direction and spaced apart from each other in the second horizontal direction.

5. The semiconductor device of claim 1, further comprising a dummy word line cut structure extending in the vertical direction through the memory stack structure and the interlayer insulating layer and extending longitudinally in the first horizontal direction, the dummy word line cut structure being located between the dam structure and the intersecting direction cut structure. wherein, The plurality of dummy channel structures include a first dummy channel structure and a second dummy channel structure spaced apart from each other, and the dummy word line cutting structure is located between the first dummy channel structure and the second dummy channel structure.

6. The semiconductor device of claim 1, further comprising a plurality of dummy word line cut structures extending through the memory stack structure and the interlayer insulating layer in the vertical direction, the plurality of dummy word line cut structures being spaced apart from each other in the second horizontal direction. wherein The plurality of dummy word line-cutting structures are located between the storage cell block and the intersecting direction cutting structures.

7. The semiconductor device of claim 1, further comprising a dummy word line cut structure located between a first word line cut structure and the dam structure in the paired word line cut structures, the dummy word line cut structure extending through the memory stack structure and the interlayer insulating layer in the vertical direction and extending longitudinally along the sidewall of the dam structure in the first horizontal direction.

8. The semiconductor device of claim 1, wherein, Both the intersecting direction cutting structure and the paired character line cutting structure include an insulating structure, and The dam structure includes an insulating layer and a polycrystalline silicon layer.

9. The semiconductor device of claim 1, wherein, The paired character line cutting structures all include an insulating structure, and Both the intersecting direction cutting structure and the dam structure include an insulating layer and a polycrystalline silicon layer.

10. The semiconductor device of claim 1, wherein, Both the intersecting direction cutting structure and the paired character line cutting structure include a first insulating layer and a metal layer, and The dam structure includes a second insulating layer and a polycrystalline silicon layer.

11. The semiconductor device according to claim 1, further comprising: An insulating island is located within the dam structure and spaced apart from the plurality of gate lines, the dam structure being located between the insulating island and the plurality of gate lines; as well as A through-path extends through the insulating island in the vertical direction and is electrically connected to a circuit of the peripheral circuit structure.

12. The semiconductor device according to claim 1, further comprising: Multiple channel structures, the multiple channel structures extending through the multiple gate lines in the vertical direction; as well as Multiple bit lines, which extend longitudinally in the second horizontal direction on the multiple channel structures. The intersecting direction cutting structure extends parallel to the multiple bit lines.

13. A semiconductor device, said semiconductor device comprising: Peripheral circuit structure; A memory stack structure, the memory stack structure including multiple gate lines that overlap with the peripheral circuit structure in the vertical direction; An interlayer insulating layer is located on the edge portion of each of the plurality of gate lines; A dam structure that extends through the storage stack structure and the interlayer insulation layer in the vertical direction and defines a through-path region in the storage stack structure; An intersecting direction cutting structure extends through the storage stack structure and the interlayer insulation layer in the vertical direction, the intersecting direction cutting structure is spaced apart from the dam structure in a first horizontal direction and extends longitudinally in a second horizontal direction that intersects the first horizontal direction; as well as Multiple ditch structures are located between the intersecting direction cutting structure and the dam structure.

14. The semiconductor device of claim 13, wherein, The intersecting direction cutting structure includes multiple linear cutting lines aligned with and spaced apart from each other in a third horizontal direction perpendicular to the first horizontal direction.

15. The semiconductor device according to claim 13, wherein, The intersecting direction cutting structure includes multiple nonlinear cutting lines aligned with and spaced apart from each other in a third horizontal direction perpendicular to the first horizontal direction.

16. The semiconductor device according to claim 13, wherein, The intersecting direction cutting structure and the dam structure are made of the same material.

17. The semiconductor device according to claim 13, wherein, The plurality of dummy channel structures extend in the vertical direction through the storage stack structure and the interlayer insulation layer.

18. The semiconductor device of claim 13, further comprising a through-path extending through the through-path region in the vertical direction, the through-path being electrically connected to a circuit of the peripheral circuit structure.

19. An electronic system, the electronic system comprising: main substrate; A semiconductor device located on the main substrate; as well as A controller electrically connected to the semiconductor device, the controller being located on the main substrate, wherein the semiconductor device comprises: Peripheral circuit structure; A memory stack structure, the memory stack structure including multiple gate lines that overlap with the peripheral circuit structure in the vertical direction; An interlayer insulating layer is located on the edge portion of each of the plurality of gate lines; A dam structure that extends through the plurality of gate lines and the interlayer insulating layer in the vertical direction and defines a through-path region in the memory stack structure; An intersecting direction cutting structure extends through the storage stack structure and the interlayer insulation layer in the vertical direction, the intersecting direction cutting structure is spaced apart from the dam structure in a first horizontal direction and extends longitudinally in a second horizontal direction that intersects the first horizontal direction; Multiple ditch structures are located between the intersecting direction cutting structure and the dam structure; and Input / output pads are electrically connected to the peripheral circuit structure.

20. The electronic system of claim 19, wherein, The main substrate also includes multiple wiring patterns for electrically connecting the semiconductor devices to the controller, and The intersecting direction cutting structure includes multiple cutting lines aligned with and spaced apart from each other in a third horizontal direction perpendicular to the first horizontal direction.

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