Semiconductor device and electronic system including the same

Abstract

A semiconductor device and electronic system, the device comprising a cell structure stacked on a peripheral circuit structure, wherein the cell structure comprises a first interlayer dielectric layer and a first metal pad exposed at the first interlayer dielectric layer and connected to a gate electrode layer and a channel region, the peripheral circuit structure comprises a second interlayer dielectric layer and a second metal pad exposed at the second interlayer dielectric layer and connected to a transistor, the first metal pad comprises a first and a second adjacent sub-pads, the second metal pad comprises a third and a fourth adjacent sub-pads, the first and third sub-pads are coupled, and a width of the first sub-pad is greater than a width of the third sub-pad, the second and fourth sub-pads are coupled, and a width of the fourth sub-pad is greater than a width of the second sub-pad.

Description

[0001] Cross-references to related applications

[0002] Korean Patent Application No. 10-2020-0146263, filed with the Korean Intellectual Property Office on November 4, 2020, entitled "Semiconductor Device and Electronic System Including the Same", is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments relate to semiconductor devices and electronic systems including them. Background Technology

[0004] Semiconductor devices can potentially store large amounts of data in electronic systems that require data storage. Therefore, research has been conducted to increase the data storage capacity of semiconductor devices. For example, as a method to increase the data storage capacity of semiconductor devices, the devices may include three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells. Summary of the Invention

[0005] An embodiment can be implemented by providing a semiconductor device comprising a unit structure stacked on a peripheral circuit structure, wherein the unit structure includes: a plurality of gate electrode layers stacked on a first substrate; a plurality of channel regions vertically extending through the plurality of gate electrode layers; a first interlayer dielectric layer located on the first substrate and covering the plurality of gate electrode layers and the plurality of channel regions; and a plurality of first metal pads exposed at the first interlayer dielectric layer and connected to the plurality of gate electrode layers and the plurality of channel regions, the peripheral circuit structure comprising: at least one transistor on a second substrate; a second interlayer dielectric layer located on the second substrate and covering the at least one transistor; and so on. and a plurality of second metal pads exposed at the second interlayer dielectric layer and connected to the at least one transistor, the plurality of first metal pads including at least one first sub-pad and at least one second sub-pad adjacent to each other, the plurality of second metal pads including at least one third sub-pad and at least one fourth sub-pad adjacent to each other, the at least one first sub-pad and the at least one third sub-pad being coupled to each other, and the width of the at least one first sub-pad being greater than the width of the at least one third sub-pad, the at least one second sub-pad and the at least one fourth sub-pad being coupled to each other, and the width of the at least one fourth sub-pad being greater than the width of the at least one second sub-pad.

[0006] An embodiment can be implemented by providing a semiconductor device comprising: a first substrate; a second substrate; a memory cell region including at least one first pad and at least one second pad on the first substrate; a peripheral circuit region including at least one third pad and at least one fourth pad on the second substrate, the peripheral circuit region being connected to the memory cell region via the at least one first pad, the at least one second pad, the at least one third pad, and the at least one fourth pad; and a memory cell array on the memory cell region, the memory cell array including a plurality of cell strings, a plurality of word lines, a plurality of bit lines, and a ground select line, the plurality of cell strings including a plurality of memory cells, the plurality of word lines connected to the plurality of memory cells, and the plurality of bit lines connected to the plurality of cells. On one side of the string, the ground selection line is connected to the plurality of cell strings; control circuitry on the peripheral circuitry area, the control circuitry including free charge control circuitry controlling each cell string and a plurality of data programming steps for the plurality of memory cells; and a row decoder on the peripheral circuitry area, the row decoder being configured to activate at least one of the plurality of word lines in response to control of the control circuitry, wherein: the at least one first pad is coupled to the at least one third pad, the at least one second pad is coupled to the at least one fourth pad, and when viewed in a plan view, the area of ​​the planar shape of the at least one first pad is greater than the area of ​​the planar shape of the at least one third pad, and the area of ​​the planar shape of the at least one fourth pad is greater than the area of ​​the planar shape of the at least one second pad.

[0007] An embodiment can be implemented by providing an electronic system comprising: a motherboard; a semiconductor device on the motherboard, the semiconductor device including a lower structure and an upper structure stacked on the lower structure; and a controller on the motherboard and electrically connected to the semiconductor device, wherein: the lower structure includes: a first semiconductor substrate; a first circuit pattern on the first semiconductor substrate; a first interlayer dielectric layer on the first semiconductor substrate, the first interlayer dielectric layer covering the first circuit pattern; and at least one first metal pad and at least one second metal pad exposed at the first interlayer dielectric layer and connected to the first circuit pattern, and the upper structure includes A second semiconductor substrate; a second circuit pattern on the second semiconductor substrate; a second interlayer dielectric layer on the second semiconductor substrate, the second interlayer dielectric layer covering the second circuit pattern; and at least one third metal pad and at least one fourth metal pad exposed at the second interlayer dielectric layer, the at least one third metal pad being coupled to the at least one first metal pad, and the at least one fourth metal pad being coupled to the at least one second metal pad, the width of the at least one first metal pad and the width of the at least one fourth metal pad being greater than the width of the at least one third metal pad and the width of the at least one second metal pad, respectively. Attached Figure Description

[0008] Features will be apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0009] Figures 1 to 4 A cross-sectional view of a semiconductor device according to some example embodiments is shown.

[0010] Figure 5 A plan view of a substrate having an integrated semiconductor device according to some example embodiments is shown.

[0011] Figure 6 A perspective view of a semiconductor device according to some example embodiments is shown.

[0012] Figure 7 A circuit diagram of a cell array of semiconductor devices according to some example embodiments is shown.

[0013] Figure 8 and Figure 9 A semiconductor device according to some example embodiments is shown. Figure 5 An enlarged plan view of part A in the diagram.

[0014] Figure 10 A diagram of an electronic system including a semiconductor device according to some example embodiments is shown.

[0015] Figure 11 A perspective view of an electronic system including a semiconductor device according to some example embodiments is shown.

[0016] Figure 12 A cross-sectional view of a semiconductor package according to some example embodiments is shown.

[0017] Figure 13 A plan view of a semiconductor device according to some example embodiments is shown.

[0018] Figure 14 The semiconductor device shown according to some example embodiments is shown along Figure 13 A sectional view taken by line A-A'.

[0019] Figure 15 A cross-sectional view of a semiconductor device according to some example embodiments is shown.

[0020] Figure 16 A cross-sectional view of a semiconductor device according to some example embodiments is shown.

[0021] Figures 17 to 27 Cross-sectional views are shown of various stages in a method of manufacturing a semiconductor device according to some example embodiments. Detailed Implementation

[0022] Figure 1 and Figure 2 A cross-sectional view of a semiconductor device according to some example embodiments is shown.

[0023] Reference Figure 1 The semiconductor device may include a lower structure 10 and an upper structure 30 stacked on the lower structure 10.

[0024] The lower structure 10 may include a first substrate 12, a first circuit layer 14, a first dielectric layer 16, and a first pad 20.

[0025] The first substrate 12 may be a semiconductor substrate, such as a semiconductor wafer. The first substrate 12 may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or an epitaxial layer substrate obtained by performing selective epitaxial growth (SEG). For example, the first substrate 12 may include silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or mixtures thereof. In embodiments, the first substrate 12 may be a dielectric substrate. As used herein, the term "or" is not an exclusive term; for example, "A or B" would include A, B, or A and B.

[0026] A first circuit layer 14 may be located on a first substrate 12. The first circuit layer 14 may include a first circuit pattern on the first substrate 12 and a dielectric layer covering the first circuit pattern. The first circuit pattern may be a memory circuit, a logic circuit, or a combination thereof, any of which includes one or more transistors. In implementations, the first circuit pattern may include passive components, such as resistors or capacitors.

[0027] The first pad 20 may be located on the first circuit layer 14. The first pad 20 may be electrically connected to a first circuit pattern of the first circuit layer 14. The first pad 20 may include metal. In an embodiment, the first pad 20 may include copper (Cu). The first pad 20 may have an damascene structure. In an embodiment, the first pad 20 may include a seed layer or barrier layer covering its side and bottom surfaces. The first pad 20 may have a width that decreases with decreasing distance from the first substrate 12 (e.g., an inwardly tapering shape). In an embodiment, the first pad 20 may have a T-shaped cross-section including a through-hole portion and a pad portion on the through-hole portion, wherein the through-hole portion and the pad portion are integrally connected to a single body.

[0028] The first pad 20 may include a first sub-pad 22 and a second sub-pad 24. The first sub-pad 22 and the second sub-pad 24 may be adjacent to each other (e.g., laterally). Multiple first sub-pads 22 and second sub-pads 24 may be provided. In an implementation, multiple first sub-pads 22 and multiple second sub-pads 24 may alternate in a direction parallel to the top surface of the first substrate 12 (e.g., horizontally). In an implementation, a single second sub-pad 24 may be between adjacent first sub-pads 22, and a single first sub-pad 22 may be between adjacent second sub-pads 24. The width W1 (e.g., maximum width) of each first sub-pad 22 may be greater than the width W2 (e.g., maximum width) of each of the second sub-pads 24 (e.g., in the horizontal direction). The width W1 of the first sub-pad 22 may be approximately 1.2 to 2 times the width W2 of the second sub-pad 24. The distance between the side surface of a first sub-pad 22 and the side surface of a second sub-pad 24 adjacent to the first sub-pad 22 can be from about 0.1 μm to about 10 μm. For example, the pitch P1 of the first sub-pad 22 and the second sub-pad 24 can be from about 0.1 μm to about 10 μm. The widths W1 and W2 of the first sub-pad 22 and the second sub-pad 24, as well as the pitch P1, can be measured at the interface between the first dielectric layer 16 and the second dielectric layer 36, which will be discussed below.

[0029] A first dielectric layer 16 may be on the first circuit layer 14. The first dielectric layer 16 may surround the first pad 20 on the first circuit layer 14. The first dielectric layer 16 may expose the top surface of the first pad 20 (e.g., the surface facing away from the first substrate 12) (e.g., may cover the side of the first pad 20). The first dielectric layer 16 may have a top surface coplanar with the top surface of the first pad 20. The first dielectric layer 16 may include a dielectric material, such as silicon oxide (SiO), silicon nitride (SiN), or silicon carbonitride (SiCN).

[0030] The upper structure 30 may include a second substrate 32, a second circuit layer 34, a second dielectric layer 36, and a second pad 40.

[0031] The second substrate 32 may be a semiconductor substrate, such as a semiconductor wafer. The second substrate 32 may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or an epitaxial layer substrate obtained by performing selective epitaxial growth (SEG). For example, the second substrate 32 may include silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or mixtures thereof. In an embodiment, the second substrate 32 may be a dielectric substrate.

[0032] The second circuit layer 34 may be on the second substrate 32. The second circuit layer 34 may include a second circuit pattern on the second substrate 32 and a dielectric layer covering the second circuit pattern. The second circuit pattern may be a memory circuit, a logic circuit, or a combination thereof, any of which includes one or more transistors. In implementations, the second circuit pattern may include passive components, such as resistors or capacitors.

[0033] The second pad 40 may be on the second circuit layer 34. The second pad 40 may be electrically connected to a second circuit pattern of the second circuit layer 34. The second pad 40 may include metal. In an embodiment, the second pad 40 may include copper (Cu). Each of the second pads 40 may have an damascene structure. In an embodiment, the second pad 40 may include a seed layer or barrier layer covering its side and bottom surfaces. The second pad 40 may have a width that decreases with decreasing distance from the second substrate 32 (e.g., a tapered shape). In an embodiment, the second pad 40 may have a T-shaped cross-section including a through-hole portion and a pad portion on the through-hole portion, the through-hole portion and the pad portion being integrally connected as a single body.

[0034] The second pad 40 may include a third sub-pad 42 and a fourth sub-pad 44. The third sub-pad 42 and the fourth sub-pad 44 may be adjacent to each other. Multiple third sub-pads 42 and multiple fourth sub-pads 44 may each be provided. In an implementation, the multiple third sub-pads 42 and multiple fourth sub-pads 44 may alternate in a horizontal direction parallel to the top surface of the second substrate 32. The third sub-pads 42 and fourth sub-pads 44 may be vertically aligned with the first sub-pad 22 and the second sub-pad 24, respectively. In an implementation, each of the third sub-pads 42 may be located on a single first sub-pad 22, and each of the fourth sub-pads 44 may be located on a single second sub-pad 24. The width W3 of each of the third sub-pads 42 may be smaller than the width W4 of each of the fourth sub-pads 44 (e.g., in the horizontal direction). The width W4 of the fourth sub-pad 44 may be approximately 1.2 to 2 times the width W3 of the third sub-pad 42. The distance between the side surface of a third sub-pad 42 and the side surface of a fourth sub-pad 44 adjacent to the third sub-pad 42 can be from about 0.1 μm to about 10 μm. For example, the pitch P2 of the third sub-pad 42 and the fourth sub-pad 44 can be from about 0.1 μm to about 10 μm. The widths W3 and W4 of the third sub-pad 42 and the fourth sub-pad 44, as well as the pitch P2 (e.g., the maximum horizontal width of the third sub-pad 42 and the fourth sub-pad 44), can be measured at the interface between the first dielectric layer 16 and the second dielectric layer 36.

[0035] A second dielectric layer 36 may be present on the second circuit layer 34. The second dielectric layer 36 may surround the second pad 40 on the second circuit layer 34. The second dielectric layer 36 may expose (e.g., may not cover) the top surface of the second pad 40 (e.g., the surface facing away from the second substrate 32). The second dielectric layer 36 may have a top surface coplanar with the top surface of the second pad 40. The second dielectric layer 36 may include a dielectric material, such as silicon oxide (SiO), silicon nitride (SiN), or silicon carbonitride (SiCN).

[0036] The upper structure 30 may be on the lower structure 10. The upper structure 30 may be connected to the lower structure 10. In an implementation, the first dielectric layer 16 and the second dielectric layer 36 may be bonded to each other. At the interface between the first dielectric layer 16 and the second dielectric layer 36, the first pad 20 of the lower structure 10 may be bonded to the second pad 40 of the upper structure 30. In an implementation, the first pad 20 and the second pad 40 may constitute a hybrid intermetallic bond between them. In this description, the term "hybrid bond" may refer to a bond in which two components of the same kind merge at their interface. In an implementation, the bonded first pad 20 and second pad 40 may have a continuous configuration, for example, it may be an integral monolithic structure in which no visual boundary or obvious interface is identifiable between the first pad 20 and the second pad 40. In an implementation, the first pad 20 and the second pad 40 may be formed of the same material, and there may be no interface between the first pad 20 and their corresponding second pad 40. In implementation, the first pad 20 and the second pad 40 may be provided as a single component. In implementation, the first sub-pad 22 and the third sub-pad 42 may be combined into a single body, and the second sub-pad 24 and the fourth sub-pad 44 may be combined into a single body. The width of the first sub-pad 22 may be greater than the width of the third sub-pad 42. In implementation, the width of the first sub-pad 22 may be approximately 1.2 to 2 times the width of the third sub-pad 42. The area of ​​the planar shape of the first sub-pad 22 (e.g., the shape when viewed in a plan view) may be greater than the area of ​​the planar shape of the third sub-pad 42. The area of ​​the first sub-pad 22 may be greater than the area of ​​the third sub-pad 42, and when viewed in a plan view, the third sub-pad 42 may be located inside the corresponding first sub-pad 22 (e.g., the planar shape of the third sub-pad 42 may be contained within the planar shape of the first sub-pad 22). The width of the second sub-pad 24 may be less than the width of the fourth sub-pad 44. In implementation, the width of the fourth sub-pad 44 can be approximately 1.2 to 2 times the width of the second sub-pad 24. The area of ​​the planar shape of the second sub-pad 24 can be smaller than the area of ​​the planar shape of the fourth sub-pad 44. The area of ​​the second sub-pad 24 can be smaller than the area of ​​the fourth sub-pad 44, and when viewed in a plan view, the second sub-pad 24 can be located inside the corresponding fourth sub-pad 44. (e.g., in the horizontal direction) The distance between the side surfaces of the first sub-pad 22 and the second sub-pad 24 that are adjacent to each other can be substantially the same as the distance between the side surfaces of the third sub-pad 42 and the fourth sub-pad 44 that are adjacent to each other (e.g., in the horizontal direction).

[0037] In implementation, one of the first pad 20 and the second pad 40 can have a larger area. Therefore, even if the upper structure 30 and the lower structure 10 are misaligned due to process errors in semiconductor device manufacturing, the smaller second sub-pad 24 and the third sub-pad 42 can vertically and completely overlap with the larger fourth sub-pad 44 and the first sub-pad 22, resulting in a uniform contact area between the first sub-pad 22 and the third sub-pad 42, and between the second sub-pad 24 and the fourth sub-pad 44. In implementation, the contact resistance between the first pad 20 and the second pad 40 can be constant between the first sub-pad 22 and the third sub-pad 42, and between the second sub-pad 24 and the fourth sub-pad 44. This implementation can improve the electrical characteristics of the semiconductor device.

[0038] If the lower structure has all large pads and the upper structure has all small pads, the lower structure may have narrow spacing and / or short circuits between the pads.

[0039] Conversely, according to the embodiment, larger pads and smaller pads can be alternately arranged on each of the lower structure 10 and the upper structure 30. Therefore, a wide spacing can be provided between the first pads 20 or between the second pads 40, preventing short circuits between the first pads 20 or between the second pads 40. Furthermore, a large spacing margin can be provided between the first pads 20 or between the second pads 40, thus allowing the semiconductor device to be configured with highly integrated pads.

[0040] In implementation, such as Figure 1 As shown, the first sub-pad 22 and the second sub-pad 24 can be arranged alternately, and the third sub-pad 42 and the fourth sub-pad 44 can be arranged alternately.

[0041] Reference Figure 2 The first sub-pad 22 may be on the first region R1 of the first substrate 12. The second sub-pad 24 may be on the second region R2 of the first substrate 12. In an implementation, the first pads 20 may be grouped, each group including at least two first sub-pads 22 or at least two second sub-pads 24, and these groups may be adjacent to each other.

[0042] The third sub-pad 42 may be located on the second substrate 32 at a position corresponding to (e.g., covering or aligning with) the first sub-pad 22, and the fourth sub-pad 44 may be located at a position corresponding to the second sub-pad 24. In an implementation, the third sub-pad 42 may be located on a first region R1. The fourth sub-pad 44 may be located on a second region R2. In an implementation, the second pads 40 may be grouped, each group including at least two third sub-pads 42 or at least two fourth sub-pads 44, and these groups may be adjacent to each other.

[0043] The first dielectric layer 16 and the second dielectric layer 36 may be bonded to each other. At the interface between the first dielectric layer 16 and the second dielectric layer 36, the first pad 20 of the lower structure 10 may be coupled to the second pad 40 of the upper structure 30. In implementation, the first sub-pad 22 and the third sub-pad 42 may be combined into a single body, and the second sub-pad 24 and the fourth sub-pad 44 may be combined into a single body. The width of the first sub-pad 22 may be greater than the width of the third sub-pad 42. The planar area of ​​the first sub-pad 22 may be greater than the planar area of ​​the third sub-pad 42, and when viewed in a plan view, the third sub-pad 42 may be located inside the corresponding first sub-pad 22. The width of the second sub-pad 24 may be less than the width of the fourth sub-pad 44. The planar area of ​​the second sub-pad 24 may be less than the planar area of ​​the fourth sub-pad 44, and when viewed in a plan view, the second sub-pad 24 may be located inside the corresponding fourth sub-pad 44. In practice, on the first region R1, the width of the first pad 20 can be greater than the width of the second pad 40 bonded to it, and on the second region R2, the width of the second pad 40 can be greater than the width of the first pad 20 bonded to it.

[0044] Figure 3 A cross-sectional view of a semiconductor device according to some example embodiments is shown.

[0045] Reference Figure 3 The first pad 20 may further include one or more fifth sub-pads 26 between one of the first sub-pads 22 and an adjacent second sub-pad 24. In this case, the first sub-pad 22 and the second sub-pad 24 may be grouped on the first region R1 and the second region R2, respectively, as shown below. Figure 2 or Figure 3 As shown. In implementation, the first sub-pad 22 and the second sub-pad 24 can be as follows: Figure 1 The arrangement is alternating as shown. The width of the fifth sub-pad 26 may be smaller than the width of the first sub-pad 22 and larger than the width of the second sub-pad 24. The fifth sub-pad 26 may be connected to the first sub-pad 22 or the second sub-pad 24, or it may be a wiring pattern connected to the first circuit layer 14.

[0046] The second pad 40 may further include one or more sixth sub-pads 46 between one of the third sub-pads 42 and an adjacent fourth sub-pad 44. In this case, the third sub-pad 42 and the fourth sub-pad 44 may be grouped on the first region R1 and the second region R2, respectively, as follows. Figure 2 or Figure 3 As shown. In implementation, the third sub-pad 42 and the fourth sub-pad 44 can be as follows: Figure 1The positions are alternated as shown. The sixth sub-pad 46 may be located at a position corresponding to the fifth sub-pad 26. In an implementation, the sixth sub-pad 46 may be located on the corresponding fifth sub-pad 26. The width of the sixth sub-pad 46 may be greater than the width of the third sub-pad 42 and less than the width of the fourth sub-pad 44. The sixth sub-pad 46 may be connected to the third sub-pad 42 or the fourth sub-pad 44, or may be a wiring pattern connected to the second circuit layer 34.

[0047] The first dielectric layer 16 and the second dielectric layer 36 may be bonded to each other. At the interface between the first dielectric layer 16 and the second dielectric layer 36, the first pad 20 of the lower structure 10 may be coupled to the second pad 40 of the upper structure 30. The fifth sub-pad 26 and the sixth sub-pad 46 may be combined into a single body. The fifth sub-pad 26 and the sixth sub-pad 46 may have the same width. In this case, the fifth sub-pad 26 may be vertically aligned with the sixth sub-pad 46. In implementation, the side surface of the fifth sub-pad 26 may contact or align with the side surface of the sixth sub-pad 46 coupled thereto. The fifth sub-pad 26 may have the same planar shape as the sixth sub-pad 46.

[0048] In implementation, such as Figures 1 to 3 As shown, the first sub-pad 22 can be correspondingly coupled to the third sub-pad 42, and the second sub-pad 24 can be correspondingly coupled to the fourth sub-pad 44.

[0049] Figure 4 A cross-sectional view of a semiconductor device according to some example embodiments is shown.

[0050] Reference Figure 4 The semiconductor device can be configured such that at least two third sub-pads 42 are coupled to a single first sub-pad 22, and at least two second sub-pads 24 are coupled to a single fourth sub-pad 44.

[0051] At least two second sub-pads 24 may be located between adjacent first sub-pads 22. The width of the first sub-pad 22 may be greater than the width of the second sub-pad 24.

[0052] At least two third sub-pads 42 may be located between adjacent fourth sub-pads 44. The width of the fourth sub-pad 44 may be greater than the width of the third sub-pad 42.

[0053] A third sub-pad 42 between adjacent fourth sub-pads 44 may be aligned with one of the first sub-pads 22, and a second sub-pad 24 between adjacent first sub-pads 22 may be aligned with one of the fourth sub-pads 44. In an implementation, at least two third sub-pads 42 may be located on a single first sub-pad 22, and at least two second sub-pads 24 may be located on a single fourth sub-pad 44.

[0054] The upper structure 30 may be located on the lower structure 10. The upper structure 30 may be connected to the lower structure 10. At the interface between the first dielectric layer 16 and the second dielectric layer 36, the first pad 20 of the lower structure 10 may be bonded to the second pad 40 of the upper structure 30. In this case, the first pad 20 and the second pad 40 may form a hybrid intermetallic bond between them. One of the first sub-pads 22 may be coupled to at least two third sub-pads 42, and one of the fourth sub-pads 44 may be coupled to at least two second sub-pads 24. The width of the first sub-pad 22 may be greater than the width of the third sub-pad 42. In an implementation, the width of the first sub-pad 22 may be about 2 to 10 times the width of the third sub-pad 42. The area of ​​the planar shape of the first sub-pad 22 may be greater than the area of ​​the planar shape of the third sub-pad 42. When viewed in a plan view, the third sub-pad 42 may be located inside the corresponding first sub-pad 22. The width of the second sub-pad 24 may be less than the width of the fourth sub-pad 44. In implementation, the width of the fourth sub-pad 44 can be approximately 2 to 10 times the width of the second sub-pad 24. The area of ​​the planar shape of the second sub-pad 24 can be smaller than the area of ​​the planar shape of the fourth sub-pad 44. When viewed in a plan view, the second sub-pad 24 can be located inside the corresponding fourth sub-pad 44.

[0055] In implementation, such as Figure 4 As shown, two third sub-pads 42 and two second sub-pads 24 can be coupled to a first sub-pad 22 and a fourth sub-pad 44, respectively. In an implementation, two or more third sub-pads 42 can be coupled to a first sub-pad 22, and two or more second sub-pads 24 can be coupled to a fourth sub-pad 44.

[0056] Figure 5 A plan view of a substrate having an integrated semiconductor device, according to some example embodiments, is shown, showing a second substrate 32 stacked on a first substrate 12.

[0057] Reference Figure 5 The first substrate 12 and the second substrate 32 may be semiconductor substrates, such as semiconductor wafers. The first substrate 12 and the second substrate 32 may be bulk silicon substrates, silicon-on-insulator (SOI) substrates, germanium substrates, germanium-on-insulator (GOI) substrates, silicon-germanium substrates, or epitaxial layer substrates obtained by performing selective epitaxial growth (SEG). For example, the first substrate 12 and the second substrate 32 may include silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or mixtures thereof. The first substrate 12 and the second substrate 32 may have a single-crystal structure.

[0058] The first substrate 12 and the second substrate 32 may be substantially identical or similar to each other. Each of the first substrate 12 and the second substrate 32 may include a chip region CR on which a semiconductor chip is formed and a scribing region SR between the chip regions CR. The chip regions CR may be arranged in two dimensions along a first direction D1 and a second direction D2 that intersect each other. The scribing region SR may surround each of the chip regions CR. In an implementation, the scribing region SR may be located between chip regions CR that are adjacent to each other in the first direction D1 and between chip regions CR that are adjacent to each other in the second direction D2. Each of the first substrate 12 and the second substrate 32 may have a cutout NT at one end in the second direction D2. The first substrate 12 and the second substrate 32 may be stacked on a third direction D3, and their cutout NT may be used to align the first substrate 12 and the second substrate 32 with each other. In an implementation, when viewed in a plan view, the chip regions CR and scribing regions SR of the first substrate 12 may be aligned and overlapped with the chip regions CR and scribing regions SR of the second substrate 32.

[0059] In practice, a semiconductor device comprising memory cells arranged in three dimensions may be formed on each of the chip regions CR of the first substrate 12 and the second substrate 32.

[0060] Figure 6 A perspective view showing a semiconductor device according to some example embodiments is shown.

[0061] Reference Figure 6 The semiconductor device may include a peripheral circuit structure PS and a cell array structure CS, wherein the peripheral circuit structure PS may be stacked on the cell array structure CS. In an implementation, when viewed in a plan view, the cell array structure CS and the peripheral circuit structure PS may overlap each other. The peripheral circuit structure PS integrated on the second substrate 32 may be stacked on the cell array structure CS integrated on the first substrate 12, and in this case, the cell array structure CS and the peripheral circuit structure PS may be in contact with each other.

[0062] The cell array structure CS may have a cell array comprising a plurality of three-dimensionally arranged memory cells. In an implementation, the cell array may be integrated on a first substrate 12. In an implementation, the first substrate 12 and the cell array structure CS may correspond to a reference. Figure 1 The discussed lower structure 10, the unit array structure CS can correspond to Figure 1 The first circuit layer 14.

[0063] The cell array structure CS may include one or more spacers, each of which may include multiple memory blocks BLK1 to BLKn. Each of the memory blocks BLK1 to BLKn may include memory cells arranged in a three-dimensional manner. In an implementation, each of the memory blocks BLK1 to BLKn may include a structure stacked along a third direction D3 on a first substrate 12.

[0064] The peripheral circuit structure PS may include control circuitry for a row decoder, column decoder, page buffer, and control unit array. The second substrate 32 may have integrated peripheral logic circuitry constituting the peripheral circuit structure PS disposed thereon. In an implementation, the second substrate 32 and the peripheral circuit structure PS may correspond to a reference. Figure 1 The upper structure 30 discussed, the peripheral circuit structure PS can correspond to Figure 1 The second circuit layer 34.

[0065] Figure 7 A circuit diagram of a cell array of semiconductor devices according to some example embodiments is shown.

[0066] Reference Figure 7 According to some example embodiments, the three-dimensional semiconductor device may be a three-dimensional NAND flash memory device. The cell array of the three-dimensional NAND flash memory device may include a common-source line CSL, multiple bit lines BL1 to BL3, and multiple cell strings CSTRs between the common-source line CSL and the bit lines BL1 to BL3. The cell strings CSTRs may extend along a third direction D3 perpendicular to the first direction D1 and the second direction D2.

[0067] Bit lines BL1 to BL3 can be arranged in a two-dimensional configuration, and multiple cell strings CSTRs can be connected in parallel with each of the bit lines BL1 to BL3. The cell strings CSTRs can all be connected to a common source line CSL. For example, multiple cell strings CSTRs can be located between multiple bit lines BL1 to BL3 and a common source line CSL. Multiple common source lines CSLs can be arranged in a two-dimensional configuration. In this configuration, the common source lines CSLs can be supplied with the same voltage, or they can be electrically controlled independently of each other.

[0068] Each cell string CSTR may include a ground select transistor GST coupled to the common-source line CSL, a string select transistor SST coupled to one of bit lines BL1 to BL3, and a plurality of memory cell transistors MCTs disposed between the ground select transistor GST and the string select transistor SST. The ground select transistor GST, the string select transistor SST, and the memory cell transistors MCTs may be connected in series. The common-source line CSL may be connected together to the source of the ground select transistor GST.

[0069] The ground select line GSL between the common source line CSL and the bit lines BL1 to BL3, the multiple word lines WL0 to WL3, and the multiple string select lines SSL0 to SSL2 can be used as the gate electrodes of the ground select transistor GST, the memory cell transistor MCT, and the string select transistor SST, respectively. Each of the memory cell transistors MCT can include a data storage element.

[0070] Figure 8 and Figure 9 A semiconductor device according to some example embodiments is shown. Figure 5 An enlarged plan view of part A in the diagram.

[0071] Reference Figure 5 , Figure 8 and Figure 9 This includes the peripheral circuit structure (see...) Figure 6 The chip region CR of the second substrate 32 of the PS can be correspondingly set in a cell array structure (see Figure 6 On the chip region CR of the first substrate 12 of the CS).

[0072] Each chip region CR of the second substrate 32 may have a peripheral circuit structure PS including a row decoder (ROW DEC), a column decoder (COL DEC), a page buffer (PBR), and a control circuit (CTRL). The chip region CR may be surrounded by a scribing region SR, which can be used to individualize the three-dimensional semiconductor device during a sawing process in the fabrication of the three-dimensional semiconductor device.

[0073] Reference Figure 8 On each of the chip regions CR, a spacer MT or a block can form a cell array structure (see...). Figure 6 (CS). In implementation, the spacer MT may be located on the first substrate (see CS). Figure 6 On 12). A pad MT can be used with the external circuit structure (see 12). Figure 6 Part of the PS overlaps. In the implementation, when viewed in a plan view, the row decoder ROW DEC and page buffer PBR may overlap around the pad MT. The column decoder COL DEC and control circuit CTRL may overlap with the pad MT. In the implementation, the peripheral circuit structure (see...) Figure 6 The peripheral circuitry of the PS can be freely or arbitrarily located on the pad MT.

[0074] Reference Figure 9 Each of the chip regions CR can be provided with a unit array structure (see Figure 6 Multiple spacers MT or multiple blocks of a first substrate (CS). The multiple spacers MT can be arranged along a first direction D1 and a second direction D2. In an implementation, the multiple spacers MT can be disposed on a first substrate (see...). Figure 6 12) on.

[0075] Figure 10 A schematic diagram of an electronic system including a semiconductor device is shown according to some example embodiments.

[0076] Reference Figure 10According to some example embodiments, the electronic system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be a storage device including one or more semiconductor devices 1100, or may be an electronic device including a storage device. In implementations, the electronic system 1000 may be a solid-state drive (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device, each of which includes one or more semiconductor devices 1100.

[0077] Semiconductor device 1100 may be a non-volatile memory device, such as a NAND flash memory device. Semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In an implementation, the first structure 1100F may be located on one side of the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and logic circuit 1130. The second structure 1100S may be a memory cell structure, which includes a bit line BL, a common-source line CSL, a word line WL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a cell string CSTR between the bit line BL and the common-source line CSL.

[0078] In the second structure 1100S, each of the cell strings CSTRs may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and memory cell transistors MCTs between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary depending on the embodiment.

[0079] In implementation, upper transistors UT1 and UT2 may include string select transistors, and lower transistors LT1 and LT2 may include ground select transistors. Gate lower lines LL1 and LL2 may be the gate electrodes of lower transistors LT1 and LT2, respectively. Word line WL may be the gate electrode of memory cell transistor MCT, and gate upper lines UL1 and UL2 may be the gate electrodes of upper transistors UT1 and UT2, respectively.

[0080] In implementation, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series. One or both of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used to perform an erase operation in which the gate-induced drain leakage (GIDL) phenomenon is used to erase the data stored in the memory cell transistor MCT.

[0081] The common-source line CSL, the first lower gate line LL1, the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first connection line 1115 extending from the first structure 1100F toward the second structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second connection line 1125 extending from the first structure 1100F toward the second structure 1100S.

[0082] On the first structure 1100F, the decoder circuit 1110 and page buffer 1120 can perform control operations on at least one of the plurality of memory cell transistors (MCTs) to select a memory cell transistor. The logic circuit 1130 can control the decoder circuit 1110 and page buffer 1120. The semiconductor device 1100 can communicate with the controller 1200 via input / output pads 1101 electrically connected to the logic circuit 1130. The input / output pads 1101 can be electrically connected to the logic circuit 1130 via input / output connection lines 1135 extending from the first structure 1100F toward the second structure 1100S.

[0083] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface (I / F) 1230. In an implementation, the electronic system 1000 may include multiple semiconductor devices 1100, in which case the controller 1200 may control the multiple semiconductor devices 1100.

[0084] Processor 1210 can control the overall operation of electronic system 1000, including controller 1200. Processor 1210 can operate based on predetermined firmware and can control NAND controller 1220 to access semiconductor device 1100. NAND controller 1220 may include NAND interface 1221 for processing communication with semiconductor device 1100. NAND interface 1221 can be used to transmit control commands for controlling semiconductor device 1100, data intended to be written to and / or data intended to be read from memory cell transistors (MCTs) of semiconductor device 1100. Host interface 1230 can provide electronic system 1000 with communication with an external host. When a control command is received from an external host through host interface 1230, semiconductor device 1100 can be controlled by processor 1210 in response to the control command.

[0085] Figure 11 A perspective view of an electronic system including a semiconductor device according to some example embodiments is shown.

[0086] Reference Figure 11According to some example embodiments, the electronic system 2000 may include a motherboard 2001, a controller 2002 mounted on the motherboard 2001, one or more semiconductor packages 2003, and dynamic random access memory (DRAM) 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the controller 2002 via wiring patterns 2005 provided in the motherboard 2001.

[0087] The motherboard 2001 may include a connector 2006, which includes multiple pins for connection to an external host. The number and arrangement of the multiple pins on the connector 2006 may vary based on the communication interface between the electronic system 2000 and the external host. In implementations, the electronic system 2000 may communicate with the external host via one or more interfaces, such as Universal Serial Bus (USB), Peripheral Component Interconnect High Speed ​​(PIC-Express), Serial Advanced Technology Attachment (SATA), and / or M-PHY for Universal Flash Memory (UFS). In implementations, the electronic system 2000 may operate using power supplied from the external host via the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) that distributes the power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0088] The controller 2002 can write data to the semiconductor package 2003, read data from the semiconductor package 2003, or increase the operating speed of the electronic system 2000.

[0089] DRAM 2004 can serve as a cache memory, reducing the speed difference between the external host and the semiconductor package 2003, which serves as data storage space. The DRAM 2004 included in the electronic system 2000 can operate as a cache memory and can provide temporary data storage space during the control operation of the semiconductor package 2003. When DRAM 2004 is included in the electronic system 2000, the controller 2002 can include not only a NAND controller for controlling the semiconductor package 2003 but also a DRAM controller for controlling the DRAM 2004.

[0090] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 on the bottom surface of the semiconductor chips 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 to the package substrate 2100, and a molding layer 2500 located on the package substrate 2100 and covering the semiconductor chips 2200 and the connection structure 2400.

[0091] The package substrate 2100 may be an integrated circuit board including pads 2130 on the package. Each of the semiconductor chips 2200 may include one or more input / output pads 2210. The input / output pads 2210 may correspond to... Figure 10 The input / output pads 1101. Each of the semiconductor chips 2200 may include a gate stack structure 3210 and a vertical structure 3220. Each of the semiconductor chips 2200 may include a semiconductor device, which will be discussed below.

[0092] In implementation, the connection structure 2400 may be a bonding wire electrically connecting the input / output pads 2210 to the pads 2130 on the package. Therefore, on each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other by wire bonding and may be electrically connected to the pads 2130 on the package substrate 2100. In implementation, on each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other using silicon through-holes instead of the connection structure 2400 or bonding wires.

[0093] In some implementations, the controller 2002 and the semiconductor chip 2200 may be included in a single package. Alternatively, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate insertion substrate instead of the motherboard 2001, and may be interconnected via wiring formed in the insertion substrate.

[0094] Figure 12 A cross-sectional view of a semiconductor package according to some example embodiments is shown. Figure 12 Described Figure 11 The example of the semiconductor package shown conceptually illustrates the following along... Figure 11 The cross-section of the semiconductor package shown is taken along line I-I'.

[0095] Reference Figure 12 In the semiconductor package 2003A, each of the semiconductor chips 2200b may include a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 located on the first structure 4100 and coupled to the first structure 4100 using wafer bonding technology.

[0096] The first structure 4100 may include a peripheral circuit region, which includes peripheral wiring 4110 and a first bonding structure 4150. The second structure 4200 may include a source structure 4205, a stacked structure 4210 between the source structure 4205 and the first structure 4100, a vertical structure 4220 passing through the stacked structure 4210, a separation structure, and word lines electrically connected to the vertical structure 4220 and the stacked structure 4210 (see See...). Figure 10 The second bonding structure 4250 of the word line WL. In an implementation, the second bonding structure 4250 is electrically connected to the vertical structure 4220 via a bit line 4240 electrically connected to the vertical structure 4220, and also electrically connected to the word line WL via a cell contact plug 4235 electrically connected to the word line WL. The first bonding structure 4150 of the first structure 4100 and the second bonding structure 4250 of the second structure 4200 can be coupled to and in contact with each other. The bonding portion of the first bonding structure 4150 and the second bonding structure 4250 can be formed of copper (Cu).

[0097] Each of the first structure 4100, the second structure 4200, and the semiconductor chip 2200b may further include the source structure discussed below. Each of the semiconductor chip 2200b may further include input / output pads electrically connected to the peripheral wiring 4110 (see...). Figure 11 (of 2210).

[0098] Figure 12 The semiconductor chip 2200b can be connected via its respective bonding wire-like structure (see...). Figure 11 The 2400 chips are electrically connected to each other. In implementation, semiconductor chips (such as...) in a single semiconductor package... Figure 12 The semiconductor chip 2200b can be electrically connected to each other through one or more connection structures including through electrodes.

[0099] Figure 12 The first structure 4100 can correspond to the peripheral circuit structure discussed in the following embodiments. Figure 12 The second structure 4200 can correspond to the cell array structure discussed in the following embodiments.

[0100] Figure 13 A plan view of a semiconductor device according to some example embodiments is shown. Figure 14 The diagram illustrates a semiconductor device according to some example embodiments. Figure 13 A sectional view taken by line A-A'.

[0101] Reference Figure 13 and Figure 14 Semiconductor device 1 may be a memory device. Semiconductor device 1 may have a chip-to-chip structure. The chip-to-chip structure may be manufactured by the following steps: forming an upper chip including a cell array structure CS on a first wafer; forming a lower chip including a peripheral circuit structure PS on a second wafer different from the first wafer; and subsequently connecting the upper chip and the lower chip to each other using a bonding method. In an implementation, the bonding method may include: electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip to a bonding metal formed on the uppermost metal layer of the lower chip. When the bonding metal is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may also be formed of aluminum or tungsten.

[0102] Each of the cell array structure CS and the peripheral circuit structure PS of the semiconductor device 1 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0103] A first substrate 12 may be provided. The first substrate 12 may be formed of a semiconductor material and may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a germanium (Ge) substrate, or a single-crystal epitaxial layer grown on a single-crystal silicon substrate. In an embodiment, the first substrate 12 may be a silicon substrate. In an embodiment, the first substrate 12 may include a semiconductor doped with impurities of a first conductivity type (e.g., p-type) and / or an intrinsic semiconductor without impurities.

[0104] In implementation, the cell array structure CS can be disposed on the first substrate 12, and may include a stacked structure ST, a vertical structure VS, and interconnection structures CPLG, CL, WPLG, and PCL. In implementation, the first substrate 12 and the cell array structure CS can correspond to a reference. Figure 1 The lower structure 10 under discussion, and a portion of the cell array structure CS, can correspond to Figure 1 The first circuit layer 14.

[0105] On the first substrate 12, stacked structures ST may extend longitudinally parallel to each other in a first direction D1 and may be arranged spaced apart from each other in a second direction D2. Each of the stacked structures ST may include an electrode EL and a dielectric layer ILD vertically stacked on the first substrate 12 between the electrodes EL. The dielectric layer ILD of the stacked structure ST may have a thickness that can be varied according to the characteristics of the semiconductor memory device. In an implementation, one or more of the dielectric layer ILDs may be thicker than the other dielectric layer ILDs. The dielectric layer ILD may include silicon oxide (SiO). The electrode EL may include a conductive material, including, for example, a semiconductor layer, a metal silicon layer, a metal layer, a metal nitride layer, or a combination thereof.

[0106] The stacked structure ST can extend along the first direction D1 from the bit line bonding region BLBA toward the word line bonding region WLBL, and can have a stepped structure on the word line bonding region WLBA. The length of the electrode EL of the stacked structure ST in the first direction D1 can decrease as the distance from the first substrate 12 increases. The stacked structure ST can have stepped structures of various shapes on the word line bonding region WLBA.

[0107] In implementation, semiconductor device 1 can be a three-dimensional NAND flash memory device, and the cell string (see...) Figure 7 The CSTR can be integrated on the first substrate 12. In this case, the stacked structure ST can be configured such that the topmost and bottommost electrodes EL can be used as selection transistors (see...). Figure 7 The gate electrode (SST and GST). In implementation, the uppermost electrode EL can be used as a string select transistor to control the electrical connection between the bit line BL and the vertical structure VS (see SST and GST). Figure 7 The gate electrode of the SST, the bottommost electrode EL can be used as a control common source electrode (see SST). Figure 7 The ground selection transistor (see CSL) is the electrical connection between the vertical structure VS and the ground selection transistor (see CSL). Figure 7 The gate electrode of the GST. The other electrodes EL between the uppermost electrode EL and the lowermost electrode EL can be used as control gate electrodes for memory cells and as word lines to connect the control gate electrodes to each other (see GST). Figure 7 (WL0 to WL3).

[0108] On the word line bonding area (BLBA), a vertical structure VS can pass through the stacked structure ST to contact the first substrate 12. The vertical structure VS can be electrically connected to the first substrate 12. When viewed in a plan view, the vertical structure VS can be arranged in a straight line or a zigzag pattern along one direction. Additionally, on the word line bonding area (WLBA) or the external pad bonding area (PA), a pseudo-vertical structure can be configured to have a structure substantially identical to that of the vertical structure VS.

[0109] The vertical structure VS may include semiconductor materials, such as silicon (Si), germanium (Ge), or mixtures thereof. In implementations, the vertical structure VS may include doped semiconductors or undoped intrinsic semiconductors. A vertical structure VS comprising semiconductor materials may be used as a reference. Figure 7 The discussion focuses on the selection of channels for transistors SST and GST, as well as memory cell transistors MCT. The bottom surface of the vertical structure VS can be located between the top and bottom surfaces of the first substrate 12. Each vertical structure VS can have a contact pad bonded to a bit line contact plug BPLG at its upper end.

[0110] Each of the vertical structures VS may include a vertical dielectric pattern VP and a semiconductor pattern SP in contact with the first substrate 12. The semiconductor pattern SP may have a hollow tube (e.g., a hollow cylinder) shape or a macaroni shape. The bottom end of the semiconductor pattern SP may have a closed shape, and the buried dielectric pattern VI may fill the interior of the semiconductor pattern SP. The semiconductor pattern SP may contact the top surface of the first substrate 12. The semiconductor pattern SP may be undoped or doped with impurities of the same conductivity type as the first substrate 12. The semiconductor pattern SP may be polycrystalline or single-crystal.

[0111] A vertical dielectric pattern VP may be located between the stacked structure ST and the vertical structure VS. The vertical dielectric pattern VP may extend in the third direction D3 and surround the sidewalls of the vertical structure VS. In implementation, the vertical dielectric pattern VP may have a macaroni shape or a tubular shape with both the top and bottom open.

[0112] The vertical dielectric pattern VP can be formed from a single thin layer or multiple thin layers. In implementations, the vertical dielectric pattern VP can be part of a data storage layer. In implementations, the vertical dielectric pattern VP can include a tunnel dielectric layer, a charge storage layer, and a barrier dielectric layer, which constitute the data storage layer of a NAND flash memory device. In implementations, the charge storage layer can be a trapping dielectric layer, a floating gate electrode, or a dielectric layer comprising conductive nanodots. In implementations, the charge storage layer can include silicon nitride (SiN), silicon oxynitride (SiON), silicon-rich nitride, nanocrystalline silicon, or a stacked trapping layer. The tunnel dielectric layer can be one of the materials with a band gap larger than that of the charge storage layer, and the barrier dielectric layer can be a high-k dielectric layer, such as alumina (Al2O3) or hafnium oxide (Hf2O). In implementations, the vertical dielectric pattern VP can include a thin layer for a phase-change memory device or for a variable resistance memory device.

[0113] A horizontal dielectric pattern HP may be located between the vertical dielectric pattern VP and the sidewall of the electrode EL. The horizontal dielectric pattern HP may extend from the sidewall of the electrode EL to the top and bottom surfaces of the electrode EL. The horizontal dielectric pattern HP may include a charge storage layer and a barrier dielectric layer, which are portions of the data storage layer of a NAND flash memory device. In an implementation, the horizontal dielectric pattern HP may include a barrier dielectric layer.

[0114] The common source region CSR may be located in a first substrate 12 between adjacent stacked structures ST. The common source region CSR may extend longitudinally in a first direction D1 parallel to the stacked structures ST. The common source region CSR may be formed by doping the first substrate 12 with an impurity having a second conductivity type. The common source region CSR may include, for example, n-type impurities (e.g., arsenic (As) or phosphorus (P)).

[0115] The common source plug (CSP) can be coupled to the common source region (CSR). Sidewall dielectric spacers (SSPs) can be located between the common source plug (CSP) and the stacked structure (ST). In read or programmable modes of a 3D NAND flash memory device, ground voltage can be applied to the common source region (CSR) via the common source plug (CSP).

[0116] The first buried dielectric layer 150 may be located on the first substrate 12, thereby covering the stepped end of the electrode EL. The first interlayer dielectric layer 151 may cover the top surface of the vertical structure VS, and a second interlayer dielectric layer 153 may be disposed thereon, covering the top surface of the common source plug CSP.

[0117] Bit lines BL may be located on the second interlayer dielectric layer 153 and may extend longitudinally in the second direction D2, thereby spanning the stack structure ST. Each bit line BL may be electrically connected to the vertical structure VS via a bit line contact plug BPLG. Bit lines BL may correspond to pads for electrical connection with the peripheral circuit structure PS, which will be discussed below. Bit lines BL may have a first sub-pad BLa and a second sub-pad BLb. The first sub-pad BLa and the second sub-pad BLb may be referenced... Figure 1 The first sub-pad 22 and the second sub-pad 24 discussed are the same or similar. In implementation, the width of the first sub-pad BLa can be greater than the width of the second sub-pad BLb, and the first sub-pad BLa and the second sub-pad BLb can be arranged alternately in a direction parallel to the top surface of the first substrate 12.

[0118] The stepped ends of the stacked structure ST may be provided with connection line structures that electrically connect the cell array structure CS to the peripheral circuit structure PS. The connection line structure may include cell contact plugs CPLG that pass through the first interlayer dielectric layer 151, the second interlayer dielectric layer 153, and the first buried dielectric layer 150 to connect to the corresponding ends of the electrode EL. The connection line structure may also include connection lines CL disposed on the second interlayer dielectric layer 153 to connect to the corresponding cell contact plugs CPLG. In an implementation, the connection line structure may include well contact plugs WPLG coupled to the well pickup region PUR in the first substrate 12, and also includes peripheral connection lines PCL connected to the well contact plugs WPLG.

[0119] The first substrate 12 may include well pickup regions (PURs) therein, which are adjacent to the opposite ends of each of the stacked structures ST. The well pickup regions (PURs) may have the same conductivity type as the first substrate 12, and their impurity concentration is greater than that of the first substrate 12. In an implementation, the well pickup regions (PURs) may include heavily doped p-type impurities (e.g., boron (B)). In an implementation, during an erase operation of a three-dimensional NAND flash memory device, an erase voltage can be applied to the well pickup regions (PURs) via the peripheral interconnect (PCL) and the well contact plug (WPLG).

[0120] The second interlayer dielectric layer 153 may have a third interlayer dielectric layer 155 disposed thereon, surrounding the bit line BL, the connector CL, and the peripheral connector PCL. The third interlayer dielectric layer 155 may expose the top surfaces of the bit line BL, the connector CL, and the peripheral connector PCL. The bit line BL, the connector CL, and the peripheral connector PCL may constitute a cell array wiring layer 160. The bit line BL, the connector CL, and the peripheral connector PCL may be electrically connected to the pads of the cell array structure of the peripheral circuit structure PS, which will be discussed below.

[0121] Thus, the unit array structure CS can be located on the first substrate 12.

[0122] The peripheral circuit structure PS can be located on the cell array structure CS.

[0123] A second substrate 32 may be provided. The second substrate 32 may be a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a single-crystal silicon substrate. In an embodiment, the second substrate 32 may be a silicon substrate having a first conductivity type (e.g., p-type) and may include a well region.

[0124] The peripheral circuit structure PS may include peripheral circuitry integrated across the entire surface of the second substrate 32, and further include a second buried dielectric layer 250 covering the peripheral circuitry. In an implementation, the second substrate 32 and the peripheral circuit structure PS may correspond to a reference. Figure 1The upper structure 30 is discussed, and a portion of the peripheral circuit structure PS can correspond to Figure 1 The second circuit layer 34.

[0125] As described above, the peripheral circuitry may include row and column decoders, page buffers, and control circuitry, and may include NMOS and PMOS transistors, low-voltage and high-voltage transistors, and resistors integrated on one surface of the second substrate 32. In implementation, the peripheral circuitry may include free charge control circuitry controlling multiple data programming steps for multiple memory cells and controlling one or more of the multiple cell strings.

[0126] In implementation, the second substrate 32 may have a device isolation layer 211 therein defining an active region. A peripheral gate electrode 223 may be disposed on the active region of the second substrate 32, and a gate dielectric layer may be located between the peripheral gate electrode 223 and the second substrate 32. Source / drain regions 221 may be disposed on opposite sides of each of the peripheral gate electrodes 223 within the second substrate 32.

[0127] The peripheral circuit wiring layer 230 can be connected to peripheral circuits on the second substrate 32. The peripheral circuit wiring layer 230 may include peripheral circuit lines 233 and peripheral circuit contact plugs 231. The peripheral circuit lines 233 can be electrically connected to peripheral circuits through the peripheral circuit contact plugs 231. In an implementation, the peripheral circuit contact plugs 231 and the peripheral circuit lines 233 can be coupled to NMOS transistors and PMOS transistors.

[0128] The second buried dielectric layer 250 may cover the peripheral gate electrode 223, the peripheral circuit contact plug 231, and the peripheral circuit line 233. The peripheral circuit wiring layer 230 may also include exposure lines 235 exposed on the bottom surface of the second buried dielectric layer 250. Exposure lines 235 may correspond to pads for electrically connecting the peripheral circuit structure PS to the cell array structure CS. Exposure lines 235 may have a third sub-pad 237 and a fourth sub-pad 239. The third sub-pad 237 and the fourth sub-pad 239 may be related to a reference... Figure 1The third sub-pad 42 and the fourth sub-pad 44 discussed are the same or similar. In an implementation, the third sub-pad 237 may have a width smaller than that of the fourth sub-pad 239, and the third sub-pad 237 and the fourth sub-pad 239 may be arranged alternately in a direction parallel to the top surface of the first substrate 12. The third sub-pad 237 may be located at a position corresponding to the position of the first sub-pad BLa, and the fourth sub-pad 239 may be located at a position corresponding to the position of the second sub-pad BLb. In an implementation, the third sub-pad 237 may be located on the first sub-pad BLa, and the fourth sub-pad 239 may be located on the second sub-pad BLb. The first sub-pad BLa may have a width greater than that of the third sub-pad 237, and the second sub-pad BLb may have a width smaller than that of the fourth sub-pad 239. The second buried dielectric layer 250 may include a plurality of stacked dielectric layers. In practice, for example, the second buried dielectric layer 250 may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or a low-k dielectric material.

[0129] In practice, the peripheral circuit line 233 and the peripheral circuit contact plug 231 can be formed of tungsten with relatively high resistance, and the exposure line 235 can be formed of copper with relatively low resistance.

[0130] In implementation, the peripheral circuit lines 233 can reside on a single layer. Alternatively, the peripheral circuit lines 233 can be stacked on different layers. In this case, one or more of the peripheral circuit lines 233 can be formed of aluminum with a resistance less than that of the copper forming the exposure line 235.

[0131] The cell array structure CS and the peripheral circuit structure PS can be in direct contact with each other. In implementation, such as... Figure 14As shown, the cell array wiring layer 160 of the cell array structure CS can contact the peripheral circuit wiring layer 230 of the peripheral circuit structure PS. In an implementation, the third interlayer dielectric layer 155 can contact the second buried dielectric layer 250, and the exposure line 235 can be connected to one or more of the bit line BL, the connection line CL, and the peripheral connection line PCL. In this case, the cell array wiring layer 160 and the peripheral circuit wiring layer 230 can form a hybrid intermetallic bond. The exposure line 235 can have a corresponding continuous configuration with the bit line BL, the connection line CL, and the peripheral connection line PCL, so that no visual boundary is identifiable between the exposure line 235 and each of the corresponding bit line BL, the corresponding connection line CL, and the corresponding peripheral connection line PCL. For example, the first sub-pad BLa and the third sub-pad 237 can be formed of the same material, so there may be no interface between the first sub-pad BLa and their corresponding third sub-pad 237. Therefore, each of the first sub-pads BLa and its corresponding third sub-pad 237 can be formed as a single body. In implementation, the second sub-pad BLb and the fourth sub-pad 239 can be formed of the same material, and there may be no interface between the second sub-pad BLb and their corresponding fourth sub-pad 239. Therefore, each of the second sub-pads BLb and its corresponding fourth sub-pad 239 can be formed as a single entity.

[0132] In practice, on the high-density bit line bonding region BLBA, the larger first sub-pad BLa can be alternately arranged with the smaller second sub-pad BLb. Therefore, a wide spacing can be set between the first sub-pad BLa and the second sub-pad BLb, and short circuits between the first sub-pad BLa and the second sub-pad BLb can be prevented. As a result, the bit line BL can have a high degree of routing freedom.

[0133] In implementation, such as Figure 14 As shown, the first sub-pad BL1 and the second sub-pad BL2 can be arranged alternately, and the third sub-pad 237 and the fourth sub-pad 239 can be arranged alternately. Figure 15 A cross-sectional view showing a semiconductor device according to some example embodiments is shown. For example... Figure 15 As shown, bit lines BL can be grouped, each group including at least two first sub-pads BLa or at least two second sub-pads BLb, and these groups can be adjacent to each other. Third sub-pads 237 can be located at positions corresponding to the first sub-pads BLa, and fourth sub-pads 239 can be located at positions corresponding to the second sub-pads BLb. Exposure lines 235 can be grouped, each group including at least two third sub-pads 237 or at least two fourth sub-pads 239, and these groups can be adjacent to each other.

[0134] The cell array wiring layer 160 and the peripheral circuit wiring layer 230 can form a hybrid intermetallic bonding. Exposure lines 235 can correspondingly have a continuous configuration with bit lines BL, interconnect lines CL, and peripheral interconnect lines PCL, thus preventing visually discernible boundaries between each of the exposure lines 235 and their respective bit lines BL, CL, and PCL. In implementation, the first sub-pad BLa and the third sub-pad 237 can be formed of the same material, and there may be no interface between the first sub-pad BLa and its corresponding third sub-pad 237. Therefore, each of the first sub-pads BLa and its corresponding third sub-pad 237 can form a single entity. In implementation, the second sub-pad BLb and the fourth sub-pad 239 can be formed of the same material, and there may be no interface between the second sub-pad BLb and its corresponding fourth sub-pad 239. Therefore, each of the second sub-pads BLb and its corresponding fourth sub-pad 239 can form a single entity.

[0135] Figure 16 A cross-sectional view of a semiconductor device according to some example embodiments is shown.

[0136] like Figure 16 As shown, bit line BL may include a first sub-pad BLa and a second sub-pad BLb. At least two third sub-pads 237 may be coupled to a single first sub-pad BLa, and at least two second sub-pads BLb may be coupled to a single fourth sub-pad 239.

[0137] At least two second sub-pads BLb may be located between adjacent first sub-pads BLa. The width of the first sub-pad BLa may be greater than the width of the second sub-pad BLb.

[0138] At least two third sub-pads 237 may be located between adjacent fourth sub-pads 239. The width of the fourth sub-pad 239 may be greater than the width of the third sub-pad 237.

[0139] In this configuration, the third sub-pads 237 between adjacent fourth sub-pads 239 can be aligned with one of the first sub-pads BLa, and the second sub-pads BLb between the first sub-pads BLa can be aligned with one of the fourth sub-pads 239. In practice, at least two third sub-pads 237 can be located on a single first sub-pad BLa, and at least two second sub-pads BLb can be located on a single fourth sub-pad 239.

[0140] The cell array wiring layer 160 and the peripheral circuit wiring layer 230 can form a hybrid intermetallic bonding. Exposure lines 235 can correspondingly have a continuous configuration with bit lines BL, interconnect lines CL, and peripheral interconnect lines PCL, so that no visual boundary is discernible between the exposure line 235 and each of the corresponding bit lines BL, interconnect lines CL, and peripheral interconnect lines PCL. In this case, one of the first sub-pads BLa can be coupled to at least two third sub-pads 237, and one of the fourth sub-pads 239 can be coupled to at least two second sub-pads BLb. The width of the first sub-pad BLa can be greater than the width of the third sub-pads 237. In an implementation, the width of each of the first sub-pads BLa can be approximately 2 to 10 times the width of each of the third sub-pads 237. The width of the second sub-pads BLb can be less than the width of the fourth sub-pads 239. In an implementation, the width of each of the fourth sub-pads 239 can be approximately 2 to 10 times the width of each of the second sub-pads BLb.

[0141] Figures 17 to 27 A cross-sectional view is shown of a stage in a method of manufacturing a semiconductor device according to some example embodiments. Figures 17 to 24 The formation of the unit array structure is shown. Figures 25 to 27 The formation of the peripheral circuit structure is shown.

[0142] Reference Figure 13 and Figure 17 For reference Figure 5 The discussed first substrate 12 can be fabricated to include chip regions and scribing regions. In an implementation, the first substrate 12 may be a semiconductor substrate having a first conductivity type (e.g., p-type). The first substrate 12 may be a single-crystal silicon substrate.

[0143] A thin-layer structure may be formed on a first substrate 12. This thin-layer structure may be formed to cover the entire surface of the first substrate 12. The thin-layer structure may include alternating and repeatedly stacked sacrificial layers SL and dielectric layers ILD. The individual sacrificial layers SL of the thin-layer structure may have the same thickness. The sacrificial layers SL and dielectric layers ILD may be formed using thermochemical vapor deposition (CVD), plasma-enhanced CVD, or atomic layer deposition (ALD). The sacrificial layers SL may be formed of a material that can be etched selectively relative to the dielectric layers ILD. For example, the sacrificial layers SL and dielectric layers ILD may have high etch selectivity relative to a chemical solution used for wet etching and low etch selectivity relative to an etching gas used for dry etching. In an embodiment, the sacrificial layers SL and dielectric layers ILD may be formed of dielectric materials, one of which has a different etch selectivity than the other. In an embodiment, the sacrificial layers SL may be formed of silicon nitride (SiN), and the dielectric layers ILD may be formed of silicon oxide (SiO).

[0144] The thin-layer structure can then undergo a patterning process to form a mold structure 110 on the first substrate 12. The mold structure 110 can be formed by performing a trimming process on the thin-layer structure. The trimming process may include forming a mask pattern on the thin-layer structure, etching a portion of the thin-layer structure, reducing the horizontal area of ​​the mask pattern, and alternately and repeatedly performing the etching and reduction steps. The trimming process can give the mold structure 110 a stepped structure at the edge of the first substrate 12.

[0145] A first buried dielectric layer 150 may be formed on a first substrate 12 on which the mold structure 110 is formed. The first buried dielectric layer 150 may be formed by depositing a thick dielectric layer to cover the mold structure 110 and then performing a planarization process on the dielectric layer. The first buried dielectric layer 150 may be formed of a dielectric material that has etch selectivity relative to the sacrificial layer SL.

[0146] Reference Figure 13 and Figure 18 The hard mask layer MP can be formed with openings that expose portions of the mold structure 110. The hard mask layer MP may include: a silicon-containing material, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or polycrystalline silicon; a carbon-containing material, such as an amorphous carbon layer (ACL) or a spin-on hard mask (SOH) layer; a metallic material, such as tungsten; or an organic material. The hard mask layer MP can be formed to cover the entire surface of the first substrate 12.

[0147] An anisotropic etching process can be performed on the portion of the mold structure 110 that exposes the opening of the hard mask layer MP to form a plurality of vertical holes LH on the mold structure 110 that expose the first substrate 12. When viewed in a plan view, the vertical holes LH can be arranged in one direction or in a zigzag pattern. The anisotropic etching process for the mold structure 110 can be a plasma etching process, a reactive ion etching (RIE) process, a radio frequency inductively coupled plasma reactive ion etching (ICP-RIE) process, or an ion beam etching (IBE) process.

[0148] Reference Figure 13 and Figure 19 It can be done in a vertical hole (see Figure 18 A vertical structure VS is formed in the LH. As described above, the vertical structure VS may include a semiconductor material or a conductive material.

[0149] The formation of the vertical structure VS may include: forming semiconductor spacers to expose the first substrate 12 and cover the sidewalls of the vertical via LH; and subsequently forming a semiconductor body connected to the first substrate 12. The vertical structure VS may include silicon (Si), germanium (Ge), or a mixture thereof, and may be an impurity-doped semiconductor or an intrinsic semiconductor without impurities. The vertical structure VS may be connected to the first substrate 12. Furthermore, the vertical structure VS may have conductive pads at its top. The conductive pads may be impurity-doped regions or may be formed of a conductive material.

[0150] In implementation, as referenced Figure 14 The vertical dielectric pattern VP discussed herein can be formed in the vertical via LH before forming the vertical structure VS. The vertical dielectric pattern VP can be formed from a single thin layer or multiple thin layers. The vertical dielectric pattern VP can be part of a data storage layer.

[0151] After forming the vertical structure VS, a conductive layer can replace the sacrificial layer SL of the mold structure 110, so that the stacked structure ST can be formed to include electrodes vertically stacked on the first substrate 12 (see...). Figure 20 (EL). This will refer to Figure 19 and Figure 20 Detailed description.

[0152] Refer again Figure 13 and Figure 19 A first interlayer dielectric layer 151 can be formed on the first embedded dielectric layer 150, thereby covering the top surface of the vertical structure VS. After the formation of the first interlayer dielectric layer 151, the electrode separation region ESR can be formed as a through-mold structure (see...). Figure 18 The first substrate 12 is exposed. The electrode separation region ESR can be formed by anisotropically etching the mold structure 110, and the electrode separation region ESR can expose the sidewalls of the mold structure 110.

[0153] The electrode separation region (ESR) can extend from the word line bonding region (WLBA) along the first direction D1 toward the bit line bonding region (BLBA). The length of at least one electrode separation region (ESR) in the first direction D1 can be less than the length of the other electrode separation regions (ESRs). The electrode separation regions (ESRs) can be formed into a plurality of sub-mold structures spaced apart from each other in the second direction D2.

[0154] The sacrificial layer SL exposed to the electrode separation region ESR can be removed to form the gate region GR. The gate region GR can be formed by isotropically etching the sacrificial layer SL using an etch formulation that has etch selectivity relative to the dielectric layer ILD, the vertical structure VS, and the first substrate 12. The isotropic etching process can completely remove the sacrificial layer SL. In an embodiment, when the sacrificial layer SL comprises silicon nitride (SiN) and the dielectric layer ILD comprises silicon oxide (SiO), an etchant comprising phosphoric acid can be used to perform the isotropic etching process. When the gate region GR is formed, the vertical structure VS prevents the collapse of the dielectric layer ILD defining the gate region GR.

[0155] The gate region GR can be an empty space between vertically adjacent dielectric layers ILD and can partially expose the sidewalls of the vertical structure VS. The gate region GR can also expose the sidewalls of the first buried dielectric layer 150.

[0156] Reference Figure 13 and Figure 20 A horizontal dielectric pattern HP and an electrode EL can be formed in the gate region GR, so that a stacked structure ST can be formed on the first substrate 12.

[0157] In practice, the horizontal dielectric pattern HP and the electrode EL can be formed by the following steps: a mold structure in which the gate region GR is formed (see...). Figure 18 A horizontal dielectric layer, a barrier metal layer (e.g., TiN, TaN, or WN), and a metal layer (e.g., W) are sequentially deposited on the electrode separation region (ESR); and the horizontal dielectric layer and metal layer deposited on the inner wall of the electrode separation region (ESR) are then anisotropically etched. The horizontal dielectric pattern HP may include one or more of silicon oxide (SiO) and high-k dielectric materials used as part of the data storage layer of a NAND flash memory device.

[0158] After forming the electrode EL, a common source region CSR can be formed in the first substrate 12 exposed to the electrode separation region ESR, and the electrode separation region ESR can be filled with a dielectric material. The common source region CSR may include, for example, n-type impurities (e.g., arsenic (As) or phosphorus (P)). A common source plug CSP can be formed in the electrode separation region ESR to contact the common source region CSR.

[0159] refer to Figure 13 and Figure 21A second interlayer dielectric layer 153 can be formed on the first interlayer dielectric layer 151. Thereafter, the second interlayer dielectric layer 153, the first interlayer dielectric layer 151, and the first buried dielectric layer 150 can undergo a patterning process to form contact holes. In implementation, cell contact holes can be formed to expose the corresponding ends of the electrodes EL located on the word line bonding region WLBA. Connection contact holes can be formed on the external pad bonding region PA to expose the first substrate 12. Bit line contact holes can be formed to expose the vertical structure VS on the bit line bonding region BLBA.

[0160] Then, conductive material can be used to fill the contact holes to form bit line contact plugs (BPLG), cell contact plugs (CPLG), and well contact plugs (WPLG), as shown in the reference. Figure 14 The subject of discussion.

[0161] Reference Figure 13 and Figure 22 A third interlayer dielectric layer 155 can be formed on the second interlayer dielectric layer 153. The third interlayer dielectric layer 155 can cover the bit line contact plug (BPLG), cell contact plug (CPLG), and well contact plug (WPLG) on the second interlayer dielectric layer 153. The third interlayer dielectric layer 155 can then undergo a patterning process to form openings. In this implementation, a first opening OP1 and a second opening OP2 can be formed on the bit line bonding region (BLBA). One or more of the first opening OP1 and the second opening OP2 can expose the bit line contact plug (BPLG). A third opening OP3 can be formed to expose the cell contact plug (CPLG) on the word line bonding region (BLBA). A fourth opening OP4 can be formed to expose the well contact plug (WPLG) on the outer pad bonding region (PA). The width of one of the first opening OP1, the second opening OP2, the third opening OP3, and the fourth opening OP4 can be greater than the width of the other openings in the first opening OP1, the second opening OP2, the third opening OP3, and the fourth opening OP4. In practice, the width of the first opening OP1 can be greater than the width of the second opening OP2. In this case, the first opening OP1 and the second opening OP2 can be arranged alternately.

[0162] A first conductive layer 156 may be formed on the third interlayer dielectric layer 155. The first conductive layer 156 may cover the third interlayer dielectric layer 155 and may fill the first opening OP1, the second opening OP2, the third opening OP3, and the fourth opening OP4. The first conductive layer 156 may include copper (Cu).

[0163] Reference Figure 13 and Figure 23The first conductive layer 156 may undergo a planarization process to form bit lines BL, interconnect lines CL, and peripheral interconnect lines PCL. For example, the planarization process may include a chemical mechanical polishing (CMP) process. The planarization process may be performed until the top surface of the third interlayer dielectric layer 155 is exposed. Therefore, bit lines BL may be formed to fill the first opening OP1 and the second opening OP2, interconnect lines CL may be formed to fill the third opening OP3, and peripheral interconnect lines PCL may be formed to fill the fourth opening OP4. Bit lines BL, interconnect lines CL, and peripheral interconnect lines PCL may constitute a cell array wiring layer 160. The top surfaces of bit lines BL, interconnect lines CL, and peripheral interconnect lines PCL may be coplanar with the top surface of the third interlayer dielectric layer 155. Bit lines BL may include a first sub-pad BLa in the first opening OP1 and a second sub-pad BLb in the second opening OP2. The width of the first sub-pad BLa may be greater than the width of the second sub-pad BLb.

[0164] The above process can be used to form a cell array structure CS.

[0165] Reference Figure 13 and Figure 24 A second substrate 32, including chip regions and scribing regions, can be fabricated, as shown in reference. Figure 5 Discussed. In an implementation, the second substrate 32 may be a semiconductor substrate having a first conductivity type (e.g., p-type).

[0166] Peripheral circuitry PTRs may be formed on each of the chip regions of the second substrate 32. For example, the peripheral circuitry PTRs may include high-voltage transistors and low-voltage transistors. The formation of the peripheral circuitry PTRs may include: sequentially forming a peripheral gate dielectric layer and a peripheral gate electrode 223 on the second substrate 32; and subsequently forming source / drain regions 221 by implanting impurities into the second substrate 32 on opposite sides of the peripheral gate electrode 223.

[0167] A peripheral gate spacer can be formed on the sidewall of the peripheral gate electrode 223.

[0168] Reference Figure 13 and Figure 25 The peripheral wiring structure of the peripheral circuit wiring layer 230 can be configured to connect to the peripheral circuit PTR, and its wiring structure may include peripheral circuit contact plugs 231 and peripheral circuit lines 233. In implementation, row decoders and column decoders, page buffers and control circuitry can be formed on each of the chip regions of the second substrate 32.

[0169] After forming the peripheral circuit PTR and peripheral wiring structure, the second buried dielectric layer 250 can be formed to cover the entire surface of the second substrate 32. In this case, the peripheral circuit line 233 can be buried in the second buried dielectric layer 250. The second buried dielectric layer 250 may include a single dielectric layer or multiple stacked dielectric layers including, for example, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or low-k dielectric materials. The second buried dielectric layer 250 can then undergo a patterning process to form openings. In an implementation, the fifth opening OP5 and the sixth opening OP2 can be formed on the bit line bonding region BLBA. The seventh opening OP7 can be formed on the word line bonding region WLBA and the external pad bonding region PA. Each of the fifth opening OP5, the sixth opening OP6, and the seventh opening OP7 can expose the peripheral circuit contact plug 231 or the peripheral circuit line 233. The width of one of the fifth opening OP5, the sixth opening OP6, and the seventh opening OP7 may be greater than the width of the other openings in the same group. In practice, the width of the sixth opening OP6 may be greater than the width of the fifth opening OP5. In this case, the fifth opening OP5 and the sixth opening OP6 may be arranged alternately.

[0170] A second conductive layer 236 may be formed on the second buried dielectric layer 250. The second conductive layer 236 may cover the second buried dielectric layer 250 and may fill the fifth opening OP5, the sixth opening OP6, and the seventh opening OP7. The second conductive layer 236 may include copper (Cu).

[0171] Reference Figure 13 and Figure 26 The second conductive layer 236 may undergo a planarization process to form exposure lines 235. For example, the planarization process may include a chemical mechanical polishing (CMP) process. The planarization process may be performed until the top surface of the second buried dielectric layer 250 is exposed. Therefore, exposure lines 235 may be formed to fill the fifth opening OP5, the sixth opening OP6, and the seventh opening OP7. The top surfaces of the bit line BL and the exposure lines 235 may be coplanar with the top surface of the second buried dielectric layer 250. The exposure lines 235 may include a third sub-pad 237 in the fifth opening OP5 and a fourth sub-pad 239 in the sixth opening OP6. The width of the third sub-pad 237 may be smaller than the width of the fourth sub-pad 239.

[0172] The above process can be used to form the peripheral circuit structure PS.

[0173] If the cell array structure CS is configured with a large area for all pads, and the peripheral circuit structure PS is configured with a small area for all pads, a narrow pitch may be provided between the first opening OP1 and the second opening OP2 on the cell array structure CS. This will provide a small pitch margin to the bit line BL or the first sub-pad BLa and the second sub-pad BLb formed during the polishing process of the first conductive layer 156. Therefore, defects are more likely to occur during the manufacture of semiconductor devices.

[0174] Conversely, according to an embodiment, wide pads can be primarily disposed on one of the cell array structure CS and the peripheral circuit structure PS, and wide and narrow pads can be formed to alternately reside on each of the cell array structure CS and the peripheral circuit structure PS. Therefore, a large pitch margin can be provided to the bit lines BL or the first sub-pads BLa and second sub-pads BLb formed during the polishing process of the first conductive layer 156, and fewer defects can be generated during the manufacture of the semiconductor device.

[0175] Reference Figure 13 and Figure 27 The cell array structure CS and the peripheral circuit structure PS can be bonded to each other. In this implementation, a second substrate 32 may be located on the first substrate 12. The second substrate 32 allows the peripheral circuit structure PS to face the cell array structure CS. In this case, the peripheral circuit wiring layer 230 of the peripheral circuit structure PS can be aligned with the cell array wiring layer 160 of the cell array structure CS. In this implementation, the first sub-pad BLa can be aligned with the third sub-pad 237, and the second sub-pad BLb can be aligned with the fourth sub-pad 239. The exposure line 235 of the peripheral circuit structure PS can be aligned with the connection line CL and the peripheral connection line PCL of the cell array structure CS.

[0176] Figure 5 The notch NT discussed herein can be used to align the first substrate 12 and the second substrate 32 with each other.

[0177] Reference Figure 13 and Figure 14 The peripheral circuit structure PS can contact the cell array structure CS. In implementation, the first sub-pad BLa can be coupled to the third sub-pad 237, and the second sub-pad BLB can be coupled to the fourth sub-pad 239. The exposure line 235 of the peripheral circuit structure PS can be coupled to the connection line CL and the peripheral connection line PCL of the cell array structure CS. The second buried dielectric layer 250 of the peripheral circuit structure PS can be coupled to the third interlayer dielectric layer 155 of the cell array structure CS.

[0178] The peripheral circuit wiring layer 230 of the peripheral circuit structure PS can be coupled to the cell array wiring layer 160 of the cell array structure CS. In implementation, the exposure line 235 of the peripheral circuit structure PS can be coupled to each of the bit line BL, the connection line CL, and the peripheral connection line PCL of the cell array structure CS, such that the exposure line 235 and any one of the bit line BL, the connection line CL, and the peripheral connection line PCL can be formed as a single entity. The exposure line 235 of the peripheral circuit structure PS can be automatically combined with the bit line BL, the connection line CL, and the peripheral connection line PCL of the cell array structure CS. For example, the peripheral circuit wiring layer 230 and the cell array wiring layer 160 can comprise the same material (e.g., copper) and can be bonded to each other by an intermetallic hybrid bonding process (e.g., Cu-Cu hybrid bonding) due to surface activation of the interface between the peripheral circuit wiring layer 230 and the cell array wiring layer 160 that are in contact with each other.

[0179] Subsequently, the first substrate 12 and the second substrate 32 can be cut along the scribing area using a cutting machine or a saw, thereby dividing the semiconductor device formed on the first substrate 12 and the second substrate 32 into multiple semiconductor chips.

[0180] According to some embodiments, the semiconductor device can be configured such that one of the first and second pads has a larger area. Therefore, even when the upper and lower structures are misaligned due to process errors in semiconductor device manufacturing, the smaller sub-pad can vertically and completely overlap with the larger sub-pad, providing a uniform contact area between the sub-pads. In implementation, the contact resistance between the first and second pads can be constant between the sub-pads. In summary, a semiconductor device with improved electrical characteristics can be provided.

[0181] One or more embodiments may provide a semiconductor device with improved electrical characteristics.

[0182] One or more embodiments may provide highly integrated semiconductor devices.

[0183] Example embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some instances, it will be apparent to those skilled in the art at the time of filing this application that features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless expressly indicated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device comprising a unit structure stacked on a peripheral circuit structure, wherein: The unit structure includes: Multiple gate electrode layers are stacked on a first substrate; Multiple channel regions that vertically penetrate the multiple gate electrode layers; A first interlayer dielectric layer, located on the first substrate and covering the plurality of gate electrode layers and the plurality of channel regions; and Multiple first metal pads are exposed at the first interlayer dielectric layer and connected to the multiple gate electrode layers and the multiple channel regions. The peripheral circuit structure includes: At least one transistor is located on a second substrate; A second interlayer dielectric layer, located on the second substrate and covering the at least one transistor; and Multiple second metal pads are exposed at the second interlayer dielectric layer and connected to the at least one transistor. The plurality of first metal pads include at least one first sub-pad and at least one second sub-pad that are adjacent to each other. The plurality of second metal pads include at least one third sub-pad and at least one fourth sub-pad that are adjacent to each other. The at least one first sub-pad and the at least one third sub-pad are coupled to each other, and the width of the at least one first sub-pad is greater than the width of the at least one third sub-pad. The at least one second sub-pad and the at least one fourth sub-pad are coupled to each other, and the width of the at least one fourth sub-pad is greater than the width of the at least one second sub-pad.

2. The semiconductor device according to claim 1, wherein, At the interface between the first interlayer dielectric layer and the second interlayer dielectric layer: The area of ​​the at least one first sub-pad is larger than the area of ​​the at least one third sub-pad, such that, when viewed in a plan view, the at least one third sub-pad is located inside the at least one first sub-pad, and The area of ​​the at least one fourth sub-pad is larger than the area of ​​the at least one second sub-pad, and when viewed in a plan view, the at least one second sub-pad is located inside the at least one fourth sub-pad.

3. The semiconductor device according to claim 1, wherein: The at least one first sub-pad includes a plurality of first sub-pads, the at least one second sub-pad includes a plurality of second sub-pads, the at least one third sub-pad includes a plurality of third sub-pads, and the at least one fourth sub-pad includes a plurality of fourth sub-pads. The plurality of first sub-pads and the plurality of second sub-pads are arranged alternately in a direction parallel to the top surface of the first substrate.

4. The semiconductor device according to claim 1, wherein: The at least one first sub-pad includes a plurality of first sub-pads, the at least one second sub-pad includes a plurality of second sub-pads, the at least one third sub-pad includes a plurality of third sub-pads, and the at least one fourth sub-pad includes a plurality of fourth sub-pads. The plurality of first sub-pads are located on a first region of the first substrate, and The plurality of second sub-pads are located on the second region of the first substrate.

5. The semiconductor device according to claim 1, wherein, The plurality of first metal pads also include a fifth sub-pad between the at least one first sub-pad and the at least one second sub-pad. The plurality of second metal pads also include a sixth sub-pad between the at least one third sub-pad and the at least one fourth sub-pad. The fifth sub-pad is coupled to the sixth sub-pad, and The width of the fifth sub-pad is the same as the width of the sixth sub-pad.

6. The semiconductor device according to claim 5, wherein, The fifth sub-pad and the sixth sub-pad are vertically aligned with each other.

7. The semiconductor device according to claim 1, wherein, At the interface between the first interlayer dielectric layer and the second interlayer dielectric layer: The at least one first sub-pad and the at least one third sub-pad constitute a single body formed of the same material, and The at least one second sub-pad and the at least one fourth sub-pad constitute a single body formed of the same material.

8. The semiconductor device according to claim 1, wherein: The width of the at least one first sub-pad is greater than the width of the at least one second sub-pad, and The width of the at least one third sub-pad is less than the width of the at least one fourth sub-pad.

9. The semiconductor device according to claim 1, wherein, The distance between the side surface of the at least one first sub-pad and the side surface of the at least one second sub-pad adjacent to the at least one first sub-pad is substantially the same as the distance between the side surface of the at least one third sub-pad and the side surface of the at least one fourth sub-pad adjacent to the at least one third sub-pad.

10. The semiconductor device according to claim 1, wherein, The unit structure further includes a memory cell array, the memory cell array comprising: Multiple unit strings, which include multiple memory units; Multiple word lines connect to the multiple memory cells; Multiple bit lines connected to one side of the multiple cell strings; and A ground selection line, which is connected to the plurality of unit strings.

11. A semiconductor device, comprising: First substrate; Second substrate; A memory cell region, comprising at least one first pad and at least one second pad on the first substrate; The peripheral circuit area includes at least one third pad and at least one fourth pad on the second substrate, and the peripheral circuit area is connected to the memory cell area through the at least one first pad, the at least one second pad, the at least one third pad and the at least one fourth pad; A memory cell array is located on the memory cell area. The memory cell array includes multiple cell strings, multiple word lines, multiple bit lines, and a ground select line. The multiple cell strings include multiple memory cells. The multiple word lines are connected to the multiple memory cells. The multiple bit lines are connected to one side of the multiple cell strings. The ground select line is connected to the multiple cell strings. A control circuit, located on the peripheral circuit area, includes a free charge control circuit that controls each cell string and multiple data programming steps for the plurality of memory cells; as well as A line decoder, located on the peripheral circuit area, is configured to activate at least one of the plurality of word lines in response to control by the control circuit. in: The at least one first pad is coupled to the at least one third pad. The at least one second pad is coupled to the at least one fourth pad, and When viewed in a planar view, the area of ​​the planar shape of the at least one first pad is greater than the area of ​​the planar shape of the at least one third pad, and the area of ​​the planar shape of the at least one fourth pad is greater than the area of ​​the planar shape of the at least one second pad.

12. The semiconductor device according to claim 11, wherein: The width of the at least one first pad is greater than the width of the at least one third pad, and The width of the at least one fourth pad is greater than the width of the at least one second pad.

13. The semiconductor device according to claim 11, wherein: The memory cell region further includes a first interlayer dielectric layer on the first substrate, the first interlayer dielectric layer covering the plurality of cell strings, the plurality of word lines, the plurality of bit lines, and the ground select line. The peripheral circuit region further includes a second interlayer dielectric layer on the second substrate, which covers the control circuit. The first interlayer dielectric layer is in contact with the second interlayer dielectric layer, and At the interface between the first interlayer dielectric layer and the second interlayer dielectric layer, the at least one first pad is coupled to the at least one third pad, and the at least one second pad is coupled to the at least one fourth pad.

14. The semiconductor device according to claim 13, wherein, At the interface between the first interlayer dielectric layer and the second interlayer dielectric layer: The area of ​​the at least one first pad is larger than the area of ​​the at least one third pad, such that, when viewed in a plan view, the at least one third pad is located inside the at least one first pad, and The area of ​​the at least one fourth pad is greater than the area of ​​the at least one second pad, such that when viewed in a plan view, the at least one second pad is located inside the at least one fourth pad.

15. The semiconductor device according to claim 13, wherein, At the interface between the first interlayer dielectric layer and the second interlayer dielectric layer: The at least one first pad and the at least one third pad constitute a single body formed of the same material, and The at least one second pad and the at least one fourth pad constitute a single body formed of the same material.

16. The semiconductor device of claim 11, wherein: The at least one first pad includes a plurality of first pads, the at least one second pad includes a plurality of second pads, the at least one third pad includes a plurality of third pads, and the at least one fourth pad includes a plurality of fourth pads. Each of the plurality of first pads is located between adjacent second pads in the plurality of second pads.

17. The semiconductor device according to claim 11, wherein: The memory cell area also includes a fifth pad between the at least one first pad and the at least one second pad. The peripheral circuit area also includes a sixth pad between the at least one third pad and the at least one fourth pad. The fifth pad is coupled to the sixth pad, and the width of the fifth pad is the same as the width of the sixth pad. The width of each of the fifth and sixth pads is less than the width of each of the at least one first and at least one fourth pad, and greater than the width of each of the at least one second and at least one third pad.

18. An electronic system comprising: Motherboard; A semiconductor device located on the motherboard, the semiconductor device comprising a lower structure and an upper structure stacked on the lower structure; as well as The controller, located on the motherboard and electrically connected to the semiconductor device, in: The lower structure includes: First semiconductor substrate, A first circuit pattern is located on the first semiconductor substrate. A first interlayer dielectric layer is located on the first semiconductor substrate, and the first interlayer dielectric layer covers the first circuit pattern. At least one first metal pad and at least one second metal pad of the first circuit pattern are exposed and connected at the first interlayer dielectric layer, and The upper structure includes: Second semiconductor substrate, A second circuit pattern is located on the second semiconductor substrate. A second interlayer dielectric layer, located on the second semiconductor substrate, covers the second circuit pattern. At least one third metal pad and at least one fourth metal pad are exposed at the second interlayer dielectric layer, the at least one third metal pad being coupled to the at least one first metal pad, and the at least one fourth metal pad being coupled to the at least one second metal pad. The width of the at least one first metal pad and the width of the at least one fourth metal pad are respectively greater than the width of the at least one third metal pad and the width of the at least one second metal pad.

19. The electronic system according to claim 18, wherein: The at least one first metal pad includes a plurality of first metal pads, the at least one second metal pad includes a plurality of second metal pads, the at least one third metal pad includes a plurality of third metal pads, and the at least one fourth metal pad includes a plurality of fourth metal pads. The plurality of first metal pads and the plurality of second metal pads are arranged alternately in a direction parallel to the top surface of the first semiconductor substrate.

20. The electronic system according to claim 18, wherein: The at least one first metal pad includes a plurality of first metal pads, the at least one second metal pad includes a plurality of second metal pads, the at least one third metal pad includes a plurality of third metal pads, and the at least one fourth metal pad includes a plurality of fourth metal pads. The plurality of first metal pads are located on a first region of the first semiconductor substrate, and The plurality of second metal pads are located on a second region of the first semiconductor substrate, the second region being spaced apart from the first region.

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