Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The application provides a semiconductor structure manufacturing method and a semiconductor structure. The method comprises the following steps: providing a substrate with a device region and a reference region, the device region comprising a first body structure and a gate line slit, the first body structure comprising alternately stacked sacrificial layers and insulating medium layers along a first direction; the reference region comprising a first blocking part and a second body structure, the second body structure comprising alternately stacked sacrificial parts and second blocking parts along a second direction; replacing the material of the sacrificial layers and the material of the sacrificial parts with conductive material to form a plurality of first conductive layers and a plurality of second conductive layers; removing part of the conductive material so that the exposed surface of the first conductive layer is lower than the surface of the insulating medium layer close to the gate line slit, forming a plurality of first grooves, so that the predetermined surface of the second conductive layer is lower than the predetermined surface of the second blocking part, forming a plurality of second grooves. The method solves the problem that it is difficult to monitor the size of the grooves in the gate line slit of each wafer in the prior art.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more specifically, to a method for fabricating a semiconductor structure, a semiconductor structure, and a 3D NAND device. Background Technology

[0002] In the fabrication of existing 3D NAND devices, the recess in the Gate Line Slit (GLS) refers to the depression structure formed in the gate layer after the sacrificial layer material is replaced with the gate layer material (e.g., W) via GLS, resulting in the removal of a portion of the gate layer material. Currently, a weighing method is commonly used to determine the removal of W. This involves measuring the weight of the device before and after W removal to estimate whether a predetermined amount of W has been removed, and thus whether a recess of the desired size has been obtained. However, monitoring the recess size using a weighing method results in significant errors.

[0003] In existing technologies, relatively accurate groove dimensions can be obtained through TEM (Transmission Electron Microscope), but TEM slicing has a long cycle and can damage the device, and it is impossible to monitor each wafer.

[0004] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0005] The main objective of this application is to provide a method for fabricating a semiconductor structure, a semiconductor structure, and a 3D NAND device to solve the problem in the prior art that it is difficult to monitor the size of the grooves in the gate slits of each wafer.

[0006] According to one aspect of this application, a method for fabricating a semiconductor structure is provided, comprising: providing a substrate having a device region and a reference region, the device region including a first body structure and a gate slit located in the first body structure, the first body structure including a sacrificial layer and an insulating dielectric layer alternately stacked along a first direction; the reference region including a first blocking portion and a second body structure stacked along the first direction, the second body structure including a sacrificial portion and a second blocking portion alternately stacked along a second direction, the first direction being parallel to the thickness direction of the substrate, and the second direction being perpendicular to the thickness direction of the substrate; replacing the material of the sacrificial layer with a conductive material through the gate slit to form a plurality of first conductive layers, and replacing the material of the sacrificial portion with a conductive material to form a plurality of second conductive layers; removing a portion of the conductive material such that, in the second direction, the exposed surface of the first conductive layer is lower than the surface of the insulating dielectric layer near the gate slit, forming a plurality of first grooves, and such that, in the first direction, a predetermined surface of the second conductive layer is lower than a predetermined surface of the second blocking portion, forming a plurality of second grooves, wherein the predetermined surface is a surface away from the substrate.

[0007] Optionally, after removing a portion of the conductive material, the method further includes: obtaining the width of each of the second grooves in the first direction; and determining the consistency of each of the first grooves based on the widths.

[0008] Optionally, the ratio of the width of the second groove in the first direction to the width of the first groove in the second direction is in the range of 1 to 2.5.

[0009] Optionally, a substrate is provided, comprising: forming a first pre-body structure in the device region, the first pre-body structure including the sacrificial layer and the insulating dielectric layer alternately stacked along the first direction; and forming the gate slit extending along the first direction through the first pre-body structure and into the substrate.

[0010] Optionally, the first blocking portion is connected to each of the second blocking portions to provide a substrate, comprising: forming a pre-blocking layer and a patterned mask layer sequentially stacked along the first direction in the reference region; etching the pre-blocking layer using the patterned mask layer as a mask to form the first blocking portion and a plurality of second blocking portions, wherein a third groove is formed between two adjacent second blocking portions; depositing sacrificial material in each of the third grooves to form each sacrificial portion; and removing the patterned mask layer to obtain the reference region.

[0011] Optionally, replacing the material of the sacrificial layer with a conductive material through the gate slit to form a plurality of first conductive layers, and replacing the material of the sacrificial portion with a conductive material to form a plurality of second conductive layers, includes: removing the sacrificial layer through the gate slit to form a plurality of fourth grooves, removing the sacrificial portion to form a plurality of fifth grooves; filling each of the fourth grooves and each of the fifth grooves with a metal material to fill the fourth grooves and the fifth grooves, thereby obtaining the first conductive layer and the second conductive layer.

[0012] Optionally, the material of the insulating dielectric layer is the same as the material of the second blocking portion.

[0013] Optionally, the material of the first conductive layer and the material of the second conductive layer are the same.

[0014] According to another aspect of this application, a semiconductor structure is provided, said semiconductor structure being fabricated using any of the methods described above.

[0015] According to another aspect of this application, a 3D NAND device is also provided, including the aforementioned semiconductor structure.

[0016] According to the technical solution of this application, in the method for fabricating the semiconductor structure, a device region and a reference region are first formed on a substrate. In the device region, the first body structure includes a sacrificial layer and an insulating dielectric layer alternately stacked along a first direction. In the reference region, the second body structure includes a sacrificial portion and a blocking portion alternately stacked along a second direction. The second direction is perpendicular to the first direction and parallel to the surface of the substrate, which is equivalent to rotating a portion of the device region by 90 degrees to obtain the reference region. Then, the material of the sacrificial layer is replaced with a conductive material through the gate slits in the first body structure, and the material of the sacrificial portion is replaced with a conductive material. Finally, a plurality of first grooves are formed in the device region, and a plurality of second grooves are formed in the reference region. The method involves forming a device region on a substrate and rotating a portion of the device region by 90 degrees to obtain the reference region. Then, a replacement process and a removal process are performed on both regions. This ensures that the resulting second grooves are proportionally transformed to the first grooves, meaning the size data of each second groove reflects the changing trend of each first groove. Subsequently, by measuring the data of each second groove in the reference region, the size of each first groove in the device region can be determined. This allows for monitoring the size of the grooves in the gate slits of each wafer, effectively solving the problem in existing technologies where it is difficult to monitor the size of the grooves in the gate slits of each wafer. Attached Figure Description

[0017] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0018] Figure 1 A schematic flowchart illustrating the fabrication method of a semiconductor structure according to an embodiment of this application is shown.

[0019] Figures 2 to 8 The diagram shows a schematic representation of the semiconductor structure fabricated according to the present application after different process steps.

[0020] The above figures include the following reference numerals:

[0021] 100, Substrate; 101, Sacrificial layer; 102, Insulating dielectric layer; 103, First conductive layer; 104, Gate slit; 105, First groove; 200, First blocking portion; 201, Sacrificial portion; 202, Second blocking portion; 203, Second conductive layer; 204, Second groove; 205, Third groove. Detailed Implementation

[0022] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0023] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0024] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0025] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0026] As described in the background section, it is difficult to monitor the size of the grooves in the gate slits of each wafer in the prior art. In order to solve the above problem, this application proposes a method for fabricating a semiconductor structure, a semiconductor structure, and a 3D NAND device.

[0027] According to a typical embodiment of this application, a method for fabricating a semiconductor structure is provided.

[0028] Figure 1 A schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application is shown. Figure 1 As shown, the above method includes:

[0029] Step S101: Provide a substrate 100, which has a device region and a reference region, such as... Figure 2 As shown, the device region includes a first body structure and a gate slit 104 located within the first body structure. The first body structure includes a sacrificial layer 101 and an insulating dielectric layer 102 alternately stacked along a first direction, namely... Figure 2 The positive and negative Y directions in the equation; such as Figure 6 As shown, the reference area includes a first blocking portion 200 stacked along the first direction and a second body structure. The second body structure includes sacrificial portions 201 and second blocking portions 202 alternately stacked along a second direction. The first direction is parallel to the thickness direction of the substrate 100, and the second direction is perpendicular to the thickness direction of the substrate 100. The second direction is... Figure 6 The positive and negative X directions in the equation;

[0030] In step S102, the material of the sacrificial layer 101 is replaced with a conductive material through the gate slit 104 to form a plurality of first conductive layers 103, and the material of the sacrificial portion 201 is replaced with a conductive material to form a plurality of second conductive layers 203, resulting in the following: Figure 3 and Figure 7 The structure shown;

[0031] Step S103: Remove a portion of the conductive material, such that in the second direction, the exposed surface of the first conductive layer 103 is lower than the surface of the insulating dielectric layer 102 near the gate wire slit, forming a plurality of first grooves 105; and in the first direction, such that a predetermined surface of the second conductive layer 203 is lower than a predetermined surface of the second blocking portion 202, forming a plurality of second grooves 204, wherein the predetermined surface is the surface away from the substrate 100, resulting in... Figure 4 and Figure 8 The structure shown.

[0032] In the above-described semiconductor structure fabrication method, a device region and a reference region are first formed on a substrate. In the device region, the first body structure includes a sacrificial layer and an insulating dielectric layer alternately stacked along a first direction. In the reference region, the second body structure includes a sacrificial portion and a blocking portion alternately stacked along a second direction. The second direction is perpendicular to the first direction and parallel to the surface of the substrate, which is equivalent to rotating a portion of the device region by 90 degrees to obtain the reference region. Then, the material of the sacrificial layer is replaced with a conductive material through the gate slits in the first body structure, and the material of the sacrificial portion is replaced with a conductive material. Finally, a plurality of first grooves are formed in the device region, and a plurality of second grooves are formed in the reference region. The above method forms a device region on a substrate and rotates a portion of the device region by 90 degrees to obtain the reference region. Then, a replacement process and a removal process are performed on the two regions. This ensures that the resulting second grooves are proportionally transformed to the first grooves. That is, the size data of each second groove can reflect the changing trend of each first groove. Subsequently, by measuring the data of each second groove in the reference region, the size of each first groove in the device region can be determined. This allows for monitoring the size of the grooves in the GLS of each wafer, effectively solving the problem in the prior art that it is difficult to monitor the size of the grooves in the gate slits of each wafer.

[0033] In the reference area of ​​this application, the opening direction of each of the second grooves is upward away from the substrate, which further ensures that the measurement of the size data of each of the second grooves is easier, thereby further ensuring the monitoring of the size of each first groove in the GLS of each wafer.

[0034] Specifically, in order to further ensure that each second groove is proportionally transformed to each first groove, the material of the sacrificial layer is replaced with a conductive material through the aforementioned grid slit to form a plurality of first conductive layers, and the material of the sacrificial portion is replaced with a conductive material to form a plurality of second conductive layers, including: while replacing the material of the sacrificial layer with a conductive material through the aforementioned grid slit to form a plurality of first conductive layers, the material of the sacrificial portion is replaced with a conductive material to form a plurality of second conductive layers.

[0035] In practical applications, in order to simplify the process and further ensure that the second grooves obtained thereafter can better reflect the changing trends of the first grooves, the material of the sacrificial layer is the same as the material of the sacrificial part, the material of the insulating dielectric layer is the same as the material of the second blocking part, and the material of the first conductive layer is the same as the material of the second conductive layer.

[0036] In practical applications, the materials for the sacrificial layer, the insulating dielectric layer, the first conductive layer, the sacrificial portion, the second blocking portion, and the second conductive layer can all be conventional materials found in the prior art. In one specific embodiment, the materials for the sacrificial layer and the sacrificial portion both include silicon nitride, the materials for the insulating dielectric layer and the second blocking portion both include silicon oxide, and the materials for the first conductive layer and the second conductive layer both include tungsten. In a more specific embodiment, the insulating dielectric layer and the second blocking portion are both silicon oxide layers, the sacrificial layer and the sacrificial portion are both silicon nitride layers, and the first conductive layer and the second conductive layer are both tungsten layers.

[0037] The number of stacked layers of the first body structure and the number of stacked layers of the second body structure are the same, and the number of layers can be determined according to specific needs.

[0038] According to a specific embodiment of this application, after removing a portion of the conductive material, the method further includes: obtaining the width of each of the second grooves in the first direction; and determining the consistency of each of the first grooves based on the widths. This application converts the variation of the width data of each of the first grooves in the second direction into the variation of the width data of each of the second grooves in the first direction, and determines the consistency of each of the first grooves based on the consistency of the second grooves. This further ensures the monitoring of the dimensions of each first groove, facilitating subsequent determination of whether to adjust process parameters based on the consistency of each of the first grooves. It further solves the problem in the prior art where sampling and slicing tests are used to determine groove consistency in GLS, which has a delay and cannot monitor each wafer. This application achieves real-time monitoring of each wafer, thereby further ensuring better performance of the obtained semiconductor structure.

[0039] In practical applications, multiple wafers are processed simultaneously to obtain a batch of wafers. Based on the size of the second groove on each wafer, the uniformity of the multiple wafers in a batch can be determined, facilitating the control of processing uniformity within the same batch. Simultaneously, multiple reference areas can be set on a single wafer, such as in the center and edge regions. By comparing the second groove size in the center region with that in the edge region, the processing uniformity of different areas of the wafer can be obtained, thus facilitating the control of processing uniformity at different locations on each wafer.

[0040] To further ensure that the obtained second groove reflects the changing trend of the first groove, in a specific embodiment, such as... Figure 4 as well as Figure 8 As shown, the ratio of the width d2 of the second groove in the first direction to the width d1 of the first groove in the second direction ranges from 1 to 2.5. This ensures that the positions of each sacrificial portion in the reference area are completely filled with conductive material during the replacement process, and that each second conductive layer in the reference area is etched into a groove during the etching process. This further guarantees that the final obtained second grooves map the consistency of each first groove in the device area.

[0041] The method for forming the aforementioned device region can be any feasible method in the prior art. Those skilled in the art can flexibly select any feasible process in the prior art to form the aforementioned device region of this application according to the actual situation. To further ensure that the process for forming the aforementioned device region is relatively simple, according to another specific embodiment of this application, a substrate is provided, comprising: forming a first preparatory body structure in the aforementioned device region, the first preparatory body structure including the aforementioned sacrificial layer and the aforementioned insulating dielectric layer alternately stacked along the aforementioned first direction; forming the aforementioned gate slit that penetrates the aforementioned preparatory body structure along the aforementioned first direction and extends to the aforementioned substrate; and forming the aforementioned reference region on the aforementioned substrate.

[0042] In practical applications, the aforementioned device region also includes multiple channel vias located within the first body structure. Specifically, the process for forming the channel vias includes: forming multiple pre-exposed channel vias in the first pre-exposed body structure; forming an epitaxial layer at the bottom of the pre-exposed channel vias; and sequentially depositing a charge blocking layer, an electron trapping layer, a tunneling layer, a channel layer, and a filling material on the sidewalls of the pre-exposed channel vias to form the channel vias. The charge blocking layer, the electron trapping layer, the tunneling layer, and the channel layer can be an ONOP stacked structure.

[0043] In one specific embodiment, forming the gate line slit exposing the substrate in the first pre-body structure includes: etching the pre-body structure using a dry etching process to form the gate line slit. During the etching process to form the gate line slit, the sacrificial layer and the insulating dielectric layer have an almost 1:1 dry etching selectivity ratio.

[0044] The first body structure described above in this application can be formed by a single stacking and a single etching, or by multiple stackings and multiple etchings.

[0045] In another specific embodiment of this application, such as Figure 5 and Figure 6As shown, the first blocking portion is connected to each of the second blocking portions, meaning that each of the second blocking portions and the first blocking portion are integrally formed. A substrate is provided, comprising: forming a pre-blocking layer and a patterned mask layer sequentially stacked along the first direction in the reference region; etching the pre-blocking layer using the patterned mask layer as a mask to form the first blocking portion and a plurality of the second blocking portions, with a third groove 205 formed between adjacent two second blocking portions; depositing sacrificial material in each of the third grooves 205 to form each sacrificial portion 201; removing the patterned mask layer to obtain the reference region; and forming the device region on the substrate. This ensures that the reference region can be formed relatively easily.

[0046] The aforementioned preparatory barrier layer can include any feasible material in the prior art. To simplify the process and further ensure that the subsequently obtained second grooves can better reflect the changing trends of the first grooves, the material of the preparatory barrier layer is the same as the material of the insulating dielectric layer. Specifically, the aforementioned preparatory barrier layer can be a silicon oxide layer.

[0047] The method for forming the patterned mask layer of this application can employ any feasible method in the prior art. Those skilled in the art can determine a suitable method to form the patterned mask layer of this application based on the actual situation. In another specific embodiment of this application, to form the patterned mask layer more simply and quickly, the step of forming a preliminary reference area on the substrate includes: sequentially covering a mask material layer and a photoresist layer on the preliminary barrier layer; patterning the photoresist layer using a photolithography process; etching the mask material layer using the patterned photoresist layer as a mask to obtain the patterned mask layer; and removing the photoresist layer.

[0048] In another embodiment of this application, a mask material layer is sequentially covered on the preparatory barrier layer, comprising: providing a hard mask layer on the exposed surface of the preparatory barrier layer; providing an anti-reflection layer on the exposed surface of the hard mask layer, wherein the hard mask layer and the anti-reflection layer form the mask material layer.

[0049] Of course, the above-mentioned mask material layer of this application is not limited to the above-mentioned formation method, but can also be formed by other methods. Those skilled in the art can select appropriate materials and processes according to the actual situation to form the above-mentioned mask material layer of this application.

[0050] In order to form a more stable mask material layer and ensure better photolithography and etching effects, in a specific embodiment of this application, the material of the hard mask layer includes Kodiak and the anti-reflection layer includes SiON.

[0051] There are many methods for forming the photoresist layer described above in this application. Those skilled in the art can choose an appropriate method to form the photoresist layer described above in this application based on the actual situation.

[0052] It should be noted that each step in the above-described substrate formation embodiments can be implemented using feasible methods in the prior art. The substrate in the above-described substrate can be selected according to the actual needs of the device, and may include a silicon substrate, a germanium substrate, a silicon-germanium composite, an SOI (Silicon on Insulator) substrate, or a GOI (Germanium on Insulator) substrate. In other embodiments, the substrate may also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, and may also be a stacked structure, such as Si / SiGe, or other epitaxial structures, such as SGOI (Sand-Germanium on Silicon). Of course, it may also be other substrates feasible in the prior art.

[0053] These structural layers can be formed by one or more of molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), metal-organic vapor phase epitaxy (MOVPE), hydride vapor phase epitaxy (HVPE) and / or other known crystal growth processes.

[0054] According to another specific embodiment of this application, the material of the sacrificial layer is replaced with a conductive material through the gate slit to form a plurality of first conductive layers, and the material of the sacrificial portion is replaced with a conductive material to form a plurality of second conductive layers, including: removing the sacrificial layer through the gate slit to form a plurality of fourth grooves, and removing the sacrificial portion to form a plurality of fifth grooves; filling each of the fourth grooves and each of the fifth grooves with a metal material to fill the fourth grooves and the fifth grooves, thereby obtaining the first conductive layers and the second conductive layers.

[0055] It should be noted that the fifth groove mentioned above is the same as the third groove mentioned above.

[0056] Removing all of the aforementioned sacrificial layers and sacrificial portions includes: wet etching the replaced substrate with an acidic solution to remove all of the aforementioned sacrificial layers and sacrificial portions. The acidic solution can be any feasible etching solution in the prior art; in one specific embodiment of this application, the acidic solution includes phosphoric acid. The aforementioned sacrificial layer and the aforementioned insulating dielectric layer have a high wet etching selectivity ratio, for example, 30:1 or even higher.

[0057] According to another typical embodiment of this application, a semiconductor structure is provided, which is obtained by any of the methods described above.

[0058] The aforementioned semiconductor structure is fabricated using any of the above-described fabrication methods. These methods involve forming a device region on a substrate, rotating a portion of the device region by 90 degrees to obtain a reference region, and then performing a replacement and etching process on both regions. This ensures that each second groove is proportionally transformed to each first groove, meaning the size data of each second groove reflects the changing trend of each first groove. Subsequently, by measuring the data of each second groove in the reference region, the size of each first groove in the device region can be determined. This allows for monitoring the size of the grooves in the GLS of each wafer, effectively solving the problem in the prior art of difficulty in monitoring the size of the grooves in the gate slits of each wafer, thus ensuring good performance of the obtained semiconductor structure.

[0059] According to another typical embodiment of this application, a 3D NAND device is also provided, including the semiconductor structure described above.

[0060] The aforementioned 3D NAND device includes the aforementioned semiconductor structure, which is fabricated using any of the aforementioned fabrication methods. These methods involve forming a device region on a substrate, rotating a portion of the device region by 90 degrees to obtain a reference region, and then performing replacement and etching processes on both regions. This ensures that each second groove is proportionally transformed to each first groove, meaning the size data of each second groove reflects the changing trend of each first groove. Subsequently, by measuring the data of each second groove in the reference region, the size of each first groove in the device region can be determined. This allows for monitoring the size of the grooves in the GLS of each wafer, effectively solving the problem in the prior art where it is difficult to monitor the size of the grooves in the gate slits of each wafer. This ensures better performance of the aforementioned semiconductor structure, thereby guaranteeing better performance of the aforementioned 3D NAND device.

[0061] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0062] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0063] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0064] 1) In the semiconductor structure fabrication method described above in this application, a device region and a reference region are first formed on a substrate. In the device region, the first body structure includes a sacrificial layer and an insulating dielectric layer alternately stacked along a first direction. In the reference region, the second body structure includes a sacrificial portion and a blocking portion alternately stacked along a second direction. The second direction is perpendicular to the first direction and parallel to the surface of the substrate, which is equivalent to rotating a portion of the device region by 90 degrees to obtain the reference region. Then, the material of the sacrificial layer is replaced with a conductive material through the gate slit in the first body structure, and the material of the sacrificial portion is replaced with a conductive material. Finally, a plurality of first grooves are formed in the device region, and a plurality of second grooves are formed in the reference region. The above method forms a device region on a substrate and rotates a portion of the device region by 90 degrees to obtain the reference region. Then, a replacement process and a removal process are performed on the two regions. This ensures that the resulting second grooves are proportionally transformed to the first grooves. That is, the size data of each second groove can reflect the changing trend of each first groove. Subsequently, by measuring the data of each second groove in the reference region, the size of each first groove in the device region can be determined. This allows for monitoring the size of the grooves in the GLS of each wafer, effectively solving the problem in the prior art that it is difficult to monitor the size of the grooves in the gate slits of each wafer.

[0065] 2) The semiconductor structure described above in this application is fabricated using any of the above-described fabrication methods. The above methods involve forming a device region on a substrate, rotating a portion of the device region by 90 degrees to obtain the reference region, and then performing a replacement process and an etching process on the two regions. This ensures that each second groove is proportionally transformed to each first groove, meaning that the size data of each second groove can reflect the changing trend of each first groove. Subsequently, by measuring the data of each second groove in the reference region, the size of each first groove in the device region can be determined. This allows for monitoring the size of the grooves in the GLS of each wafer, effectively solving the problem in the prior art that it is difficult to monitor the size of the grooves in the gate slits of each wafer, and ensuring that the semiconductor structure obtained has good performance.

[0066] 3) The 3D NAND device described in this application includes the aforementioned semiconductor structure, which is fabricated using any of the aforementioned fabrication methods. These methods involve forming a device region on a substrate, rotating a portion of the device region by 90 degrees to obtain a reference region, and then performing a replacement process and an etching process on the two regions. This ensures that each second groove is proportionally transformed to each first groove, meaning the size data of each second groove reflects the changing trend of each first groove. Subsequently, by measuring the data of each second groove in the reference region, the size of each first groove in the device region can be determined. This allows monitoring of the groove size in the GLS of each wafer, effectively solving the problem in the prior art where it is difficult to monitor the groove size in the gate slits of each wafer, ensuring better performance of the aforementioned semiconductor structure, and thus ensuring better performance of the aforementioned 3D NAND device.

[0067] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method of fabricating a semiconductor structure, the method comprising: include: A substrate is provided having a device region and a reference region. The device region includes a first body structure and a gate slit located in the first body structure. The first body structure includes a sacrificial layer and an insulating dielectric layer alternately stacked along a first direction. The reference region includes a first blocking portion and a second body structure stacked along the first direction. The second body structure includes a sacrificial portion and a second blocking portion alternately stacked along a second direction. The first direction is parallel to the thickness direction of the substrate, and the second direction is perpendicular to the thickness direction of the substrate. The material of the sacrificial layer is replaced with a conductive material through the gate wire slits to form multiple first conductive layers, and the material of the sacrificial portion is replaced with a conductive material to form multiple second conductive layers; A portion of the conductive material is removed such that, in the second direction, the exposed surface of the first conductive layer is lower than the surface of the insulating dielectric layer near the gate slit, forming a plurality of first grooves; and, in the first direction, a predetermined surface of the second conductive layer is lower than a predetermined surface of the second blocking portion, forming a plurality of second grooves, wherein the predetermined surface is the surface away from the substrate. The first blocking portion is connected to each of the second blocking portions respectively, providing a substrate, including: A pre-blocking layer and a patterned mask layer are formed in the reference area, which are stacked sequentially along the first direction; The patterned mask layer is used as a mask to etch the pre-blocking layer to form the first blocking portion and a plurality of second blocking portions, and a third groove is formed between two adjacent second blocking portions; Sacrificial material is deposited in each of the third grooves to form each of the sacrificial portions; Remove the patterned mask layer to obtain the reference area.

2. The method of claim 1, wherein, After removing a portion of the conductive material, the method further includes: Obtain the width of each of the second grooves in the first direction; The consistency of each of the first grooves is determined based on the width of each groove.

3. The method of claim 1, wherein, The ratio of the width of the second groove in the first direction to the width of the first groove in the second direction is in the range of 1 to 2.

5.

4. The method of claim 1, wherein, Provide a substrate, including: A first pre-body structure is formed in the device region, the first pre-body structure including the sacrificial layer and the insulating dielectric layer alternately stacked along the first direction; The gate slit is formed to penetrate the first pre-body structure along the first direction and extend to the substrate.

5. The method of claim 1, wherein, The material of the sacrificial layer is replaced with a conductive material through the gate slits to form multiple first conductive layers, and the material of the sacrificial portion is replaced with a conductive material to form multiple second conductive layers, including: The sacrificial layer is removed through the grid slits to form a plurality of fourth grooves, and the sacrificial portion is removed to form a plurality of fifth grooves; Metal material is filled into each of the fourth and fifth grooves to fill them completely, thereby obtaining the first conductive layer and the second conductive layer.

6. The method according to any one of claims 1 to 5, characterized in that, The material of the insulating dielectric layer is the same as the material of the second blocking portion.

7. The method according to any one of claims 1 to 5, characterized in that, The material of the first conductive layer is the same as the material of the second conductive layer.

8. A semiconductor structure, characterized in that, The semiconductor structure is fabricated using the method described in any one of claims 1 to 5.

9. A 3D NAND device, characterized in that, include: The semiconductor structure according to claim 8.

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