Semiconductor device and data storage system including the same

Abstract

A semiconductor device includes a pattern structure, a stack structure including gate layers stacked in a first region on the pattern structure and extending into a second region, a memory vertical structure penetrating the stack structure in the first region, a gate contact plug electrically connected to the gate layers in the second region, and a first peripheral contact plug spaced apart from the gate layers, the gate layers include a first gate layer, the gate contact plug includes a first gate contact plug electrically connected to the first gate layer, side surfaces of the first gate contact plug and the first peripheral contact plug have different numbers of upper bends, and the number of the upper bends of the side surfaces of the first gate contact plug is greater than the number of the upper bends of the side surfaces of the first peripheral contact plug.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0143002, filed on October 30, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The exemplary embodiments disclosed herein relate to semiconductor devices and data storage systems including such semiconductor devices. Background Technology

[0004] Semiconductor devices are needed to store large amounts of data in electronic systems requiring data storage. Therefore, methods to improve the data storage capacity of semiconductor devices have been investigated. For example, as one method for improving the data storage capacity of semiconductor devices, a semiconductor device comprising three-dimensionally arranged memory cells (instead of two-dimensionally arranged memory cells) has been proposed. Summary of the Invention

[0005] The exemplary embodiments disclosed herein provide semiconductor devices that can improve integration density and reliability.

[0006] The exemplary embodiments of this disclosure provide a data storage system including semiconductor devices.

[0007] According to an exemplary embodiment of this disclosure, a semiconductor device includes: a patterned structure; a stacked structure including a plurality of gate layers, the plurality of gate layers being stacked vertically and spaced apart from each other in a first region on the patterned structure, and extending into a second region on the patterned structure; a memory vertical structure penetrating the stacked structure in the first region; a plurality of gate contact plugs electrically connected to the plurality of gate layers in the second region; and a first peripheral contact plug spaced apart from the plurality of gate layers, wherein the plurality of gate layers includes a first gate layer, and wherein the plurality of gate contact plugs includes a first gate contact plug that contacts and is electrically connected to the first gate layer. Each of the plurality of gate contact plugs and the first peripheral contact plug includes a conductive gap filling pattern and a conductive liner covering the side and bottom surfaces of the conductive gap filling pattern, wherein at a height higher than the height of the highest gate layer among the plurality of gate layers, the side surfaces of the first gate contact plug and the side surfaces of the first peripheral contact plug have different numbers of upper bends, and wherein at a height higher than the height of the highest gate layer, the number of upper bends on the first side of the side surface of the first gate contact plug in a first direction is greater than the number of upper bends on the first side of the side surface of the first peripheral contact plug in the first direction.

[0008] According to an exemplary embodiment of this disclosure, a semiconductor device includes: a patterned structure; a stacked structure including a plurality of gate layers stacked vertically and spaced apart from each other in a first region on the patterned structure, and extending into a second region on the patterned structure; a memory vertical structure penetrating the stacked structure in the first region; and a plurality of gate contact plugs electrically connected to the plurality of gate layers in the second region, wherein the stacked structure includes: a lower stacked structure including a lower gate layer; and an upper stacked structure including an upper gate layer on the lower stacked structure, wherein each of the plurality of gate contact plugs includes a conductive gap filling pattern and a conductive liner covering a side surface and a bottom surface of the conductive gap filling pattern, wherein the plurality of gate contact plugs includes a first gate contact plug electrically connected to a first upper gate layer in the upper gate layer and a second gate contact plug electrically connected to a first lower gate layer in the lower gate layer, and wherein at a height higher than the height of the highest gate layer among the plurality of gate layers, a first side of the side surface of each of the first gate contact plug and the second gate contact plug in a first direction includes a plurality of upper bends disposed at different heights.

[0009] According to an example embodiment of this disclosure, a data storage system includes: a main substrate; a semiconductor device on the main substrate; and a controller electrically connected to the semiconductor device on the main substrate, wherein the semiconductor device includes: a patterned structure; a stacked structure including a plurality of gate layers stacked vertically and spaced apart from each other in a first region on the patterned structure, and extending into a second region on the patterned structure; a memory vertical structure penetrating the stacked structure in the first region; and a plurality of gate contact plugs electrically connected to the plurality of gate layers in the second region, wherein the stacked structure includes: a lower stacked structure including a lower gate layer; and The upper stacked structure includes an upper gate layer on the lower stacked structure, wherein each of the plurality of gate contact plugs includes a conductive gap filling pattern and a conductive liner covering the side surface and bottom surface of the conductive gap filling pattern, wherein the plurality of gate contact plugs includes a first gate contact plug electrically connected to a first upper gate layer in the upper gate layer and a second gate contact plug electrically connected to a first lower gate layer in the lower gate layer, and wherein at a height higher than the height of the highest gate layer in the plurality of gate layers, a first side of the side surface of each of the first gate contact plug and the second gate contact plug in a first direction includes a plurality of upper bends. Attached Figure Description

[0010] The above and other aspects, features and advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which the same reference numerals denote the same elements throughout the drawings. In the drawings:

[0011] Figure 1A , Figure 1B , Figure 2A and Figure 2B This is a plan view illustrating a semiconductor device according to an exemplary embodiment of the present disclosure;

[0012] Figure 3A , Figure 3B and Figure 3C This is a cross-sectional view showing a semiconductor device according to an exemplary embodiment of the present disclosure;

[0013] Figure 4 This is an enlarged cross-sectional view showing a portion of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0014] Figures 5A to 5C This is an enlarged cross-sectional view showing a modified example of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0015] Figure 6 This is an enlarged cross-sectional view showing a portion of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0016] Figures 7A to 7C This is an enlarged cross-sectional view showing a portion of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0017] Figures 8A to 8C This is an enlarged cross-sectional view showing a modified example of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0018] Figure 9 This is an enlarged cross-sectional view showing a portion of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0019] Figure 10A and Figure 10B This is an enlarged cross-sectional view showing a portion of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0020] Figures 11A to 11C This is an enlarged cross-sectional view showing a modified example of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0021] Figure 12 This is an enlarged cross-sectional view showing a modified example of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0022] Figure 13 This is an enlarged cross-sectional view showing a portion of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0023] Figure 14A This is an enlarged cross-sectional view showing a modified example of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0024] Figure 14B This is an enlarged cross-sectional view showing a modified example of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0025] Figure 15 This is an enlarged cross-sectional view showing a portion of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0026] Figure 16 This is a cross-sectional view illustrating a modified example of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0027] Figure 17 This is a cross-sectional view illustrating a modified example of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0028] Figure 18 This is a cross-sectional view illustrating another modified example of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0029] Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A , Figure 22B , Figure 23 , Figure 24A , Figure 24B , Figure 25A , Figure 25B , Figure 26A and Figure 26B This is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure;

[0030] Figure 27 This is a diagram illustrating a data storage system including semiconductor devices according to an exemplary embodiment of the present disclosure;

[0031] Figure 28 This is a perspective view illustrating a data storage system including semiconductor devices according to an exemplary embodiment of the present disclosure; and

[0032] Figure 29 This is a cross-sectional view illustrating a data storage system including semiconductor devices according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0033] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0034] Reference Figures 1A to 3C A semiconductor device according to an example embodiment is described. Figures 1A to 3C middle, Figure 1A This is a plan view illustrating a semiconductor device according to an example embodiment. Figure 1B It is shown Figure 1A A partial plan view of the components. Figure 2A and 2B This is a plan view illustrating a semiconductor device according to an example embodiment. Figure 3A It is along Figure 1A A cross-sectional view taken from line I-I' in the diagram. Figure 3B It is along Figure 1A The cross-sectional view taken from line II-II' in the diagram, and Figure 3C It is along Figure 2A The cross-sectional view taken from line III-III' in the diagram.

[0035] refer to Figures 1A to 3C In an example embodiment, semiconductor device 1 may include: a patterned structure 24; a stacked structure ST' including a plurality of gate layers 115g, the plurality of gate layers 115g being stacked in the vertical direction Z and spaced apart from each other in a first region MCA on the patterned structure 24, and extending into a second region SA on the patterned structure 24; a memory vertical structure 81 penetrating the stacked structure ST' in the first region MCA; a plurality of gate contact plugs 136 electrically connected to the plurality of gate layers 115g in the second region SA; and a first peripheral contact plug 139 spaced apart from the plurality of gate layers 115g.

[0036] The stacked structure ST' may further include an insulating horizontal layer 115i disposed in the third region TA and at a height substantially the same as the height of the gate layer 115g. The insulating horizontal layer 115i may include a lower insulating horizontal layer 40a and an upper insulating horizontal layer 64a. As used herein, when referring to orientation, layout, location, shape, size, quantity, or other measure, terms such as “same,” “equal,” “planar,” or “coplanar” do not necessarily mean exactly the same orientation, layout, location, shape, size, quantity, or other measure, but are intended to include, for example, substantially the same orientation, layout, location, shape, size, quantity, or other measure within acceptable variations that may occur due to manufacturing processes. Unless the context or other statement otherwise indicates, the term “substantially” may be used herein to emphasize that meaning. For example, terms described as “substantially same,” “substantially equal,” or “substantially planar” may be exactly the same, completely equal, or completely planar, or may be the same, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes.

[0037] In the example, the first region MCA can be referred to as a memory cell region or a memory cell array region in which memory cells can be formed, and the second region SA can be referred to as a stepped region in which the gate layer 115g is formed in a stepped manner, or a contact region in which a gate contact plug electrically connected to the gate layer 115g is formed. The second region SA may be adjacent to the first region MCA in the first direction X. The third region TA may be adjacent to the first region MCA in the second direction Y. The second direction Y may be perpendicular to the first direction X. The third region TA may be referred to as a through region or a through insulating region.

[0038] Semiconductor device 1 may also include the following structure 3.

[0039] The lower structure 3 may include: a semiconductor substrate 5; an isolation region 7s defining a peripheral active region 7a on the semiconductor substrate 5; peripheral circuits 11 and 13 formed on the semiconductor substrate 5; peripheral pads 15 electrically connected to the peripheral circuits 11 and 13; and a lower insulating layer 21 covering the peripheral pads 15. The peripheral circuits 11 and 13 may include: a circuit device 11 such as a transistor, including a peripheral gate 11g and a peripheral source / drain 11sd; and circuit wiring 13 electrically connected to the circuit device 11. The peripheral pads 15 may be electrically connected to the circuit wiring 13.

[0040] The peripheral pads 15 may include first peripheral pads to fourth peripheral pads 15a, 15b, 15c, and 15d. In an example, each peripheral pad 15 may include a conductive material, such as a metallic material, such as tungsten. The lower structure 3 may also include a capping layer 17 formed on each peripheral pad 15, and an etch stop layer 19 formed on the capping layer 17. In an example, the capping layer 17 may be formed of a silicon layer, and the etch stop layer 19 may be formed of an insulating material such as silicon oxide.

[0041] The patterned structure 24 can be disposed on the lower structure 3 and can include a first opening 24a and a second opening 24b. For example, at least a portion of the patterned structure 24 can be formed of doped silicon (e.g., polysilicon with N-type conductivity). In the patterned structure 24, the region formed of polysilicon with N-type conductivity can be a common source region.

[0042] In the example, pattern structure 24 can be formed as a single layer, such as a silicon layer.

[0043] In another example, pattern structure 24 may include multiple stacked pattern layers. For example, pattern structure 24 may include a lower pattern layer, an intermediate pattern layer on the lower pattern layer, and an upper pattern layer on the intermediate pattern layer. At least one of the lower pattern layer, the intermediate pattern layer, and the upper pattern layer may be a silicon layer. For example, the lower pattern layer and the upper pattern layer may be silicon layers, and at least a portion of the intermediate pattern layer may include a silicon layer.

[0044] In another example, pattern structure 24 may include a metal layer and a silicon layer on the metal layer.

[0045] In the example, pattern structure 24 may include a patterned via 24p extending downward from the lower surface of pattern structure 24 and electrically connected to a fourth peripheral pad 15d. The patterned via 24p may be formed of a conductive material layer. For example, the patterned via 24p may be formed of a silicon layer. The side surfaces of the patterned via 24p may be sloped. For example, the width of the patterned via 24p may decrease as the patterned via 24p extends in the downward direction.

[0046] The patterned via 24p can be electrically connected to the impurity region 11i of the semiconductor substrate 5 via circuit wiring 13 electrically connected to the fourth peripheral pad 15d. In this example, the impurity region 11i of the semiconductor substrate 5 can be a ground region. In another example, the impurity region 11i of the semiconductor substrate 5 can be the source / drain of a device included in the peripheral circuits 11 and 13.

[0047] The semiconductor device 1 may further include a first intermediate insulating layer 33a filling the first opening 24a, a second intermediate insulating layer 33b filling the second opening 24b, and an outer intermediate insulating layer 33c formed on the outside of the pattern structure 24.

[0048] The stacked structure ST' may include a lower stacked structure LS' and an upper stacked structure US' on the lower stacked structure LS'. The lower stacked structure LS' may include a lower gate layer 115L of gate layer 115g, and the upper stacked structure US' may include an upper gate layer 115U of gate layer 115g.

[0049] The lower stacked structure LS' may further include a lower interlayer insulating layer 38 alternately and repeatedly disposed with the lower gate layer 115L. In the lower stacked structure LS', the lowest layer may be the lowest lower interlayer insulating layer 38L, and the highest layer may be the highest lower interlayer insulating layer 38U. The upper stacked structure US' may further include an upper interlayer insulating layer 62 alternately and repeatedly disposed with the upper gate layer 115U. In the upper stacked structure US', the lowest layer may be the lowest upper interlayer insulating layer 62L, and the highest layer may be the highest upper interlayer insulating layer 62U.

[0050] Semiconductor device 1 may further include a first capping insulating layer 47, a second capping insulating layer 75, a third capping insulating layer 78, a fourth capping insulating layer 103, and a fifth capping insulating layer 121. The first capping insulating layer 47 may cover the portion of the patterned structure 24 that does not overlap with the stacked structure ST', and the stepped region of the lower stacked structure LS' that covers the outer intermediate insulating layer 33c but does not overlap with the upper stacked structure US'. The first capping insulating layer 47 may have an upper surface coplanar with the upper surface of the lower stacked structure LS'. The second capping insulating layer 75 may cover the first capping insulating layer 47, may have an upper surface coplanar with the upper surface of the upper stacked structure US', and may cover the stepped region of the upper stacked structure US'. The lower surface of the second capping insulating layer 75 may contact the upper surface of the first capping insulating layer 47. It will be understood that when referring to an element being "connected" or "coupled" to another element or "on" another element, the element may be directly connected or coupled to the other element or directly on the other element, or there may be intermediate elements present. Conversely, when it is mentioned that an element is "directly connected" or "directly coupled" to another element or "in contact" with another element, there is no intermediate element at the point of contact.

[0051] In the stepped region of the lower stacked structure LS', the lower gate layer 115L can be arranged in a stepped shape, and in the stepped region of the upper stacked structure US', the upper gate layer 115U can be arranged in a stepped shape.

[0052] In the example embodiment, the shape of the steps is not limited to the shape shown in the figures, and can be changed.

[0053] The third to fifth capping insulation layers 78, 103, and 124 can be sequentially stacked on the stacked structure ST' and the second capping insulation layer 75. For example, the third capping insulation layer can be on and in contact with the second capping insulation layer 75, the fourth capping insulation layer 103 can be on and in contact with the third capping insulation layer 78, and the fifth capping insulation layer 124 can be on and in contact with the fourth capping insulation layer 103.

[0054] In the example, the first to fifth capping insulation layers 47, 75, 78, 103 and 124 can be formed of silicon oxide.

[0055] In the example, the memory vertical structure 81 can penetrate the third cover insulation layer 78 and the stacked structure ST', can extend into the patterned structure 24, and can contact the patterned structure 24.

[0056] In an example embodiment, a "bend" can be defined as the portion between a lower side surface disposed below the bend and an upper side surface disposed above the bend, wherein the lower side surface has a predetermined inclination relative to the bend, and the upper side surface has a predetermined inclination relative to the bend. For example, the bend of the side surface can be a portion extending from the lower end of the lower side surface and the upper end of the upper side surface when the lower end of the lower side surface and the upper end of the upper side surface are not aligned in the vertical direction. Alternatively, the bend of the side surface can be a portion extending from a lower side surface and an upper side surface with different inclinations when the inclinations of the lower side surface and the upper side surface are different. The "bend" can be referred to as an inflection point.

[0057] The side surface of the vertical memory structure 81 may include at least two curved portions 81b_L and 81b_U. For example, a first side of the side surface of the vertical memory structure 81, disposed in one direction, may include a lower curved portion 81b_L and an upper curved portion 81b_U. The upper curved portion 81b_U may be disposed at a height higher than the height of the lower curved portion 81b_L. For example, on the side surface of the vertical memory structure 81, the lower curved portion 81b_L may be disposed between the lowest upper gate layer of the upper gate layer 115U and the highest lower gate layer of the lower gate layer 115L, and the upper curved portion 81b_U may be disposed at a height higher than the height of the highest upper gate layer of the upper gate layer 115U.

[0058] Multiple gate contact plugs 136 can penetrate the fifth capping insulating layer 121, the fourth capping insulating layer 103, and the third capping insulating layer 78, extend downwards, and contact the first peripheral pad 15a. Therefore, the multiple gate contact plugs 136 can be electrically connected to peripheral circuits 11 and 13 through the first peripheral pad 15a. The multiple gate contact plugs 136 can also penetrate the stacked structure ST' in the second region SA.

[0059] The plurality of gate contact plugs 136 may include a first gate contact plug 136_1 and a second gate contact plug 136_2. The first gate contact plug 136_1 may be electrically connected to the upper gate layer 115U, and the second gate contact plug 136_2 may be electrically connected to the lower gate layer 115L.

[0060] Each of the plurality of gate contact plugs 136 may include a lower bend 136b_L on its side surface and a plurality of upper bends 136b_U at a height higher than the height of the lower bend 136b_L. For example, on a first side of the side surface of each of the plurality of gate contact plugs 136 disposed in one direction, the lower bend 136b_L may be disposed between the lowest upper gate layer of the upper gate layer 115U and the highest lower gate layer of the lower gate layer 115L, and the plurality of upper bends 136b_U may be disposed at a height higher than the height of the highest upper gate layer of the upper gate layer 115U.

[0061] In the example, on a first side of one of the side surfaces of the gate contact plugs 136, which is arranged in one direction, the number of multiple upper bends 136b_U can be two.

[0062] In the following description, for the sake of simplicity, a first gate contact plug 136_1 and an upper gate layer 115U electrically connected to each other, and a second gate contact plug 136_2 and a lower gate layer 115L electrically connected to each other will be described.

[0063] Each of the first gate contact plug 136_1 and the second gate contact plug 136_2 may include a lower plug portion 136L and an upper plug portion 136U on the lower plug portion 136L.

[0064] The first gate contact plug 136_1 may further include a gate contact portion 136E, which extends horizontally from the upper plug portion 136U and contacts the conductive material portion of the upper gate layer 115U. The second gate contact plug 136_2 may further include a gate contact portion 136E, which extends horizontally from the lower plug portion 136L and contacts the conductive material portion of the lower gate layer 115L.

[0065] In the first region MCA, the upper gate layer 115U may have a first thickness, and the portion of the upper gate layer 115U that contacts the gate contact portion 136E of the first gate contact plug 136_1 may have a second thickness greater than the first thickness. In the first region MCA, the lower gate layer 115L may have a first thickness, and the portion of the lower gate layer 115L that contacts the gate contact portion 136E of the second gate contact plug 136_2 may have a second thickness. Thickness can refer to the thickness or height measured in the vertical direction Z.

[0066] In the example, the gate contact 136E may have a second thickness.

[0067] In another example, the gate contact 136E may have a third thickness greater than the second thickness.

[0068] Semiconductor device 1 may also include a second peripheral contact plug 142 (in Figure 3C (Middle). The second peripheral contact plug 142 can penetrate the fifth capping insulating layer 121, the fourth capping insulating layer 103, and the third capping insulating layer 78, can extend downward, can sequentially penetrate the insulating horizontal layer 115i and the second intermediate insulating layer 33b, and can contact the third peripheral pad 15c. The first peripheral contact plug 139 can penetrate the fifth capping insulating layer 121, the fourth capping insulating layer 103, the third capping insulating layer 78, the second capping insulating layer 75, the first capping insulating layer 47, the outer intermediate insulating layer 33c, and the lower insulating layer 21, can extend downward, and can contact the second peripheral pad 15b. The first peripheral contact plug 139 can penetrate the outer intermediate insulating layer 33c and can be spaced apart from the pattern structure 24 and the gate layer 115g.

[0069] In the example, the first peripheral contact plug 139 and the second peripheral contact plug 142 may have substantially the same cross-sectional structure. For example, the side surface of each of the first peripheral contact plug 139 and the second peripheral contact plug 142 may include at least two bends 138b_L and 138b_U. For example, a first side of the side surface of each of the first peripheral contact plug 139 and the second peripheral contact plug 142, arranged in any direction, may include a lower bend 138b_L and an upper bend 138b_U. The upper bend 138b_U may be located at a height higher than the lower bend 138b_L.

[0070] Semiconductor device 1 may also include source contact plug 145 (in Figure 3A (in the middle). The source contact plug 145 can penetrate the fifth cover insulating layer 121, the fourth cover insulating layer 103, the third cover insulating layer 78, the second cover insulating layer 75 and the first cover insulating layer 47, can extend downward, can be spaced apart from the gate layer 115g, and can contact the pattern structure 24.

[0071] The side surface of the source contact plug 145 may include at least two bends 145b_L and 145b_U. For example, a first side of the side surface of the source contact plug 145, disposed in one direction, may include a lower bend 145b_L and an upper bend 145b_U. The upper bend 145b_U may be disposed at a height higher than that of the lower bend 145b_L.

[0072] Semiconductor device 1 may also include a supporting vertical structure 91 (in Figure 3B(in the middle), which penetrates the stacked structure ST' in the second region SA. The side surface supporting the vertical structure 91 may include at least two bends 91b_L and 91b_U. For example, a first side of the side surface supporting the vertical structure 91, arranged in one direction, may include a lower bend 91b_L and an upper bend 91b_U.

[0073] In the example, the memory vertical structure 81, gate contact plug 136, first peripheral contact plug 139, second peripheral contact plug 142, source contact plug 145, and the lower curved portions 81b_L, 136b_L, 138b_L, 145b_L, and 91b_L on the side surface supporting the vertical structure 91 can be set at substantially the same height.

[0074] In the example, at the height between the lower gate layer 115L and the upper gate layer 115U, which are adjacent to each other in the vertical direction Z among the plurality of gate layers 115g, the memory vertical structure 81, the gate contact plug 136, the first peripheral contact plug 139, the second peripheral contact plug 142, the source contact plug 145, and the side surface supporting the vertical structure 91 may each include at least one lower bend 81b_L, 136b_L, 138b_L, 145b_L, and 91b_L.

[0075] In the example, the gate contact plug 136, the first peripheral contact plug 139, the second peripheral contact plug 142, and the source contact plug 145 may have upper surfaces disposed at substantially the same height.

[0076] In the example, the upper surfaces of the memory vertical structure 81 and the supporting vertical structure 91 can be positioned at a height lower than the height of the upper surfaces of the gate contact plug 136, the first peripheral contact plug 139, the second peripheral contact plug 142 and the source contact plug 145.

[0077] In the example, at a height higher than the height of the highest gate layer in gate layer 115, the memory vertical structure 81, the first peripheral contact plug 139, the second peripheral contact plug 142, the source contact plug 145, and the side surface supporting the vertical structure 91, which are arranged in one direction, may include the same number of upward bends.

[0078] In the example, at a height higher than the height of the highest gate layer in gate layer 115, the memory vertical structure 81, the first peripheral contact plug 139, the second peripheral contact plug 142, the source contact plug 145, and the upper curved portions 81b_U, 138b_U, 145b_U, and 91b_U of the side surface supporting the vertical structure 91 can be disposed at substantially the same height.

[0079] In the example, at a height higher than the height of the highest gate layer in gate layer 115, the first side of the side surface of one of the gate contact plugs 136 (e.g., the first gate contact plug 136_1) may include an upward bend of n, and the first side of the side surface of each of the memory vertical structure 81, the first peripheral contact plug 139, the second peripheral contact plug 142, the source contact plug 145, and the supporting vertical structure 91 in the first direction may include an upward bend of m, where n and m are natural numbers, and n may be greater than m.

[0080] In the example, n can be 2, and m can be 1.

[0081] The semiconductor device 1 may also include a separation structure 118. The separation structure 118 may penetrate the stacked structure ST' on the patterned structure 24. In one example, the separation structure 118 may be formed of an insulating material, such as silicon oxide. In another example, each separation structure 118 may include a conductive pattern and insulating spacers covering the side surfaces of the conductive pattern.

[0082] The upper surface of the separation structure 118 can be positioned at a height higher than the upper surface of the memory vertical structure 81, and at a height lower than the upper surfaces of the gate contact plug 136, the first peripheral contact plug 139, the second peripheral contact plug 142, and the source contact plug 145. For example, the upper surface of the separation structure 118 can be coplanar with the upper surface of the fourth capping insulating layer 103, the upper surfaces of the gate contact plug 136, the first peripheral contact plug 139, the second peripheral contact plug 142, and the source contact plug 145 can be coplanar with the upper surface of the fifth capping insulating layer 121, and the upper surfaces of the memory vertical structure 81 and the supporting vertical structure 91 can be coplanar with the upper surface of the third capping insulating layer 78.

[0083] The semiconductor device 1 may also include an upper insulating layer 148 on the fifth capping insulating layer 121.

[0084] The semiconductor device 1 may further include: a first bit connection plug 152b1 extending downward through the upper insulating layer 148 and electrically connected to the memory vertical structure 81; a second bit connection plug 152b2 extending through the upper insulating layer 148 and electrically connected to a second peripheral contact plug 142; a peripheral connection plug 152p extending through the upper insulating layer 148 and electrically connected to a first peripheral contact plug 139; and a source connection plug 152s extending through the upper insulating layer 148 and electrically connected to a source contact plug 145. The upper surfaces of the first bit connection plug 152b1, the second bit connection plug 152b2, the peripheral connection plug 152p, and the source connection plug 152s may be coplanar with the upper surface of the upper insulating layer 148.

[0085] In this example, the entire upper surface of the gate contact plug 136 may be covered by the upper insulating layer 148. For example, the upper insulating layer 148 may contact the upper surface of the gate contact plug 136.

[0086] Semiconductor device 1 may further include: bit line 155b, electrically connected to a first bit line connection plug 152b1 and a second bit line connection plug 152b2 on the upper insulating layer 148; peripheral wiring 155p, electrically connected to peripheral connection plug 152p; and source wiring 155s, electrically connected to source connection plug 152s.

[0087] Reference Figure 4 Examples describing the stacked structure ST', patterned structure 24, memory vertical structure 81, and first bit line connection plug 152b1. Figure 4 It is shown Figure 3A An enlarged cross-sectional view of part 'A' in the diagram.

[0088] In the example, refer to Figure 4 In the stacked structure ST', each gate layer 115g may include a first layer 115a and a second layer 115b. The first layer 115a may cover the upper and lower surfaces of the second layer 115b and may extend to the region between the memory vertical structure 81 and the second layer 115b.

[0089] In the example, the first layer 115a may include a dielectric material, and the second layer 115b may include a conductive material. For example, the first layer 115a may include a high-k dielectric such as AlO, and the second layer 115b may include a conductive material such as TiN, WN, Ti, or W.

[0090] In another example, the first layer 115a may include a first conductive material (e.g., TiN or W), and the second layer 115b may include a second conductive material (e.g., Ti or W) that is different from the first conductive material.

[0091] In another example, each of the first layer 115a and the second layer 115b may be formed of doped polycrystalline silicon, metal semiconductor compounds (e.g., TiSi, TaSi, CoSi, NiSi or WSi), metal nitrides (e.g., TiN, TaN or WN) or metals (e.g., Ti or W).

[0092] In the example, at least a portion of the intermediate gate layer disposed between the lower gate layer and the upper gate layer in the gate layer 115g can be a word line.

[0093] The vertical memory structure 81 may include: a gap-filling insulating layer 87; a channel material layer 85 covering the outer and bottom surfaces of the gap-filling insulating layer 87; a data storage structure 83 covering the outer and bottom surfaces of the channel material layer 85; and a pad material layer 89 on the gap-filling insulating layer 87. The pad material layer 89 may contact the upper surface of the gap-filling insulating layer 87.

[0094] The data storage structure 83 may include: a first dielectric layer 83c, covering the outer and bottom surfaces of the channel material layer 85; a data storage material layer 83b, covering the outer and bottom surfaces of the first dielectric layer 83c; and a second dielectric layer 83a, covering the outer and bottom surfaces of the data storage material layer 83b. The second dielectric layer 83a may contact the channel material layer 85, and the data storage material layer 83b may be spaced apart from the channel material layer 85.

[0095] For example, the gap-filling insulating layer 87 may include silicon oxide, such as ALD silicon oxide formed by an ALD (atomic layer deposition) process or silicon oxide in which voids are formed.

[0096] The first dielectric layer 83c may comprise silicon oxide or silicon oxide doped with impurities. The second dielectric layer 83a may comprise at least one of silicon oxide and a high-k dielectric. The data storage material layer 83b may comprise a material capable of trapping charge, such as silicon nitride.

[0097] The data storage material layer 83b of the data storage structure 83 of the vertical memory structure 81 may include a region in a semiconductor device (e.g., a flash memory device) that can store data. The channel material layer 85 may include polysilicon. The pad material layer 89 may include at least one of doped polysilicon, metal nitride (e.g., TiN, etc.), metal (e.g., W, etc.), and metal semiconductor compound (e.g., TiSi, etc.).

[0098] The vertical structure 81 of the memory may include a lower vertical portion 81L, a first upper vertical portion 81U1 on the lower vertical portion 81L, and a second upper vertical portion 81U2 on the first upper vertical portion 81U1.

[0099] In the memory vertical structure 81, the lower vertical portion 81L can penetrate the lower stacked structure LS', extend into the patterned structure 24, and contact the patterned structure 24. The first upper vertical portion 81U1 can penetrate the upper stacked structure US', and the second upper vertical portion 81U2 can penetrate the third cover insulating layer 78.

[0100] In the example, the width of the upper region of the lower vertical portion 81L may differ from the width of the lower region of the first upper vertical portion 81U1. For example, the width of the upper region of the lower vertical portion 81L may be greater than the width of the lower region of the first upper vertical portion 81U1. In some embodiments, each of the lower vertical portion 81L and the first upper vertical portion 81U1 may have a tapered shape that narrows in the downward direction.

[0101] In the example, the width of the upper region of the first upper vertical portion 81U1 may be different from the width of the lower region of the second upper vertical portion 81U2. For example, the width of the upper region of the first upper vertical portion 81U1 may be smaller than the width of the lower region of the second upper vertical portion 81U2.

[0102] In the example, on the first side of the side surface of the vertical structure 81 of the memory, which is arranged in one direction, the upper end of the lower side surface 81s_L of the lower vertical part 81L may not be aligned with the lower end of the first upper side surface 81s_U1 of the first upper vertical part 81U1 in the vertical direction Z, and the upper end of the first upper side surface 81s_U1 of the first upper vertical part 81U1 may not be aligned with the lower end of the second upper side surface 81s_U2 of the second upper vertical part 81U2 in the vertical direction Z. Therefore, the first side of the side surface of the vertical structure 81 of the memory, which is disposed in one direction, may include: a lower curved portion 81b_L extending from the upper end of the lower side surface 81s_L of the lower vertical portion 81L (which may be misaligned) and the lower end of the first upper side surface 81s_U1 of the first upper vertical portion 81U1; and an upper curved portion 81b_U extending from the upper end of the first upper side surface 81s_U1 of the first upper vertical portion 81U1 (which may be misaligned) and the lower end of the second upper side surface 81s_U2 of the second upper vertical portion 81U2. In some embodiments, the lower curved portion 81b_L may have a surface extending in a direction different from the direction in which the upper end of the lower side surface 81s_L of the lower vertical portion 81L and the lower end of the first upper side surface 81s_U1 of the first upper vertical portion 81U1 extend. For example, the lower curved portion 81b_L may have a surface coplanar with the upper surface of the highest lower interlayer insulating layer 38U. In some embodiments, the upper curved portion 81b_U may extend in a direction different from the direction in which the upper end of the first upper surface 81s_U1 of the first upper vertical portion 81U1 and the lower end of the second upper surface 81s_U2 of the second upper vertical portion 81U2 extend.

[0103] The first line connection plug 152b1 can contact and be electrically connected to the pad material layer 89 of the memory vertical structure 81. In the example, the first line connection plug 152b1 may include: a gap-filling conductive layer 150b; and a conductive liner 150a covering the side and bottom surfaces of the gap-filling conductive layer 150b.

[0104] The pattern structure 24 may include: a lower pattern layer 26; a first intermediate pattern layer 28a on and in contact with the lower pattern layer 26; and an upper pattern layer 30 on and in contact with the first intermediate pattern layer 28a. The lower pattern layer 26, the first intermediate pattern layer 28a, and the upper pattern layer 30 may include polysilicon. The first intermediate pattern layer 28a may penetrate the data storage structure 83 of the memory vertical structure 81 and may contact the channel material layer 85. In some embodiments, the thickness of the portion of the first intermediate pattern layer 28a that contacts the channel material layer 85 in the vertical direction Z may be greater than the thickness of the portion of the first intermediate pattern layer 28a disposed between the lower pattern layer 26 and the upper pattern layer 30.

[0105] In the following description, reference will be made to Figure 5A describe Figure 4 A modified example of the vertical memory structure 81 described in the document. Figure 5A It is shown that... Figure 4 An enlarged view of the region 'Aa1' corresponding to the region represented by 'Aa', used for illustration. Figure 4 Modification examples of the first upper vertical portion 81U1 and the second upper vertical portion 81U2 of the memory vertical structure 81 described herein.

[0106] In the modified example, refer to Figure 5A In the vertical structure 81 of the memory, the vertical central axis of the first upper vertical portion 81U1a and the vertical central axis of the second upper vertical portion 81U2 may not be aligned. The vertical central axis of the first upper vertical portion 81U1a may be in the vertical direction Z, passing through the center between the side surfaces 81s_U1a and 81s_U1b of the first upper vertical portion 81U1a, and the vertical central axis of the second upper vertical portion 81U1b may be in the vertical direction Z, passing through the center between the side surfaces 81s_U2a and 81s_U2b of the second upper vertical portion 81U2a.

[0107] The side surfaces 81s_U1a and 81s_U1b of the first upper vertical portion 81U1a and the side surfaces 81s_U2a and 81s_U2b of the second upper vertical portion 81U2a may be misaligned in the vertical direction Z, and curved portions 81b_Ua and 81b_Ub may be formed to connect the side surfaces 81s_U1a and 81s_U1b of the first upper vertical portion 81U1a to the side surfaces 81s_U2a and 81s_U2b of the second upper vertical portion 81U2a.

[0108] In the vertical structure 81 of the memory, the curved portion 81b_Ua provided in the +X direction may not overlap with the first upper vertical portion 81U1a but may overlap with the second upper vertical portion 81U1b. The curved portion 81b_Ub provided in the -X direction may overlap with the first upper vertical portion 81U1a but may not overlap with the second upper vertical portion 81U1b.

[0109] In the following description, reference will be made to Figure 5B describe Figure 4 Example of modification of the vertical memory structure 81 in the image. Figure 5B It is shown that... Figure 4 An enlarged view of region 'Ab1' corresponding to region 'Ab' in the diagram, used for illustration. Figure 4 A modified example of the lower vertical portion 81L and the first upper vertical portion 81U1 of the memory vertical structure 81 described herein.

[0110] In the modified example, refer to Figure 5B In the vertical structure 81 of the memory, the vertical central axis of the first upper vertical portion 81U1a and the vertical central axis of the lower vertical portion 81La may not be aligned. The vertical central axis of the first upper vertical portion 81U1a may be in the vertical direction Z, and may pass through the center between the two side surfaces of the first upper vertical portion 81U1a. Similarly, the vertical central axis of the lower vertical portion 81La may be in the vertical direction Z, and may pass through the center between the two side surfaces of the lower vertical portion 81La.

[0111] The two side surfaces of the first upper vertical portion 81U1a and the two side surfaces of the lower vertical portion 81La may be misaligned in the vertical direction Z, and may form a curved portion 81b_La and a curved portion 81b_Lb that connect the two side surfaces of the first upper vertical portion 81U1a and the two side surfaces of the lower vertical portion 81La.

[0112] In the following description, reference will be made to Figure 5C describe Figure 4 Example of modifications to the memory vertical structure 81 and pattern structure 24. Figure 5C It is shown that... Figure 4 An enlarged view of region 'Ac1' corresponding to region 'Ac' in the diagram, used for illustration. Figure 4 Example of modification of the lower vertical part 81L of the vertical structure 81 of the memory and Figure 4 Example of modification of pattern structure 24 in the image.

[0113] In the modified example, refer to Figure 5CThe lower vertical portion 81L' of the memory vertical structure 81 may include: an epitaxial channel layer 82, including a portion disposed in the pattern structure 24, the portion being disposed at a height higher than the height of the upper surface of at least the lowest lower gate layer in the lower gate layer 115L, and the epitaxial channel layer 82 having an upper surface disposed at a height lower than the height of the lower surface of the second lowest lower gate layer; a gap-filling insulating layer 87' disposed on the epitaxial channel layer 82; a channel material layer 85' inserted between the gap-filling insulating layer 87' and the epitaxial channel layer 82 and covering the side surface of the gap-filling insulating layer 87'; and a data storage structure 83' covering the outer surface of the channel material layer 85'. The data storage structure 83' may include a first dielectric layer 83c, a second dielectric layer 83a, and a data storage material layer 83b between the first dielectric layer 83c and the second dielectric layer 83a.

[0114] The lower vertical portion 81L' of the memory vertical structure 81 may include a dielectric layer 114 at least between the lowest lower gate layer 115L and the epitaxial channel layer 82. The dielectric layer 114 may contact the epitaxial channel layer 82.

[0115] In the following description, reference will be made to Figure 6 , Figure 7A , Figure 7B and Figure 7C An example is described for the first peripheral contact plug 139 and the second peripheral contact plug 142. Figure 6 It is shown Figure 3C area 'B1' and Figure 3A A magnified view of region 'B2' in the image. Figure 7A It is shown Figure 6 A magnified view of region 'Ba' in the image. Figure 7B It is shown Figure 6 A magnified view of region 'Bb' in the image. Figure 7C It is shown Figure 6 A magnified view of region 'Bc' in the image.

[0116] refer to Figure 6 , Figure 7A , Figure 7B and Figure 7C For reference Figure 3A and Figure 3C As described in the above example embodiments, the first peripheral contact plug 139 and the second peripheral contact plug 142 may have substantially the same cross-sectional structure. The first peripheral contact plug 139 and the second peripheral contact plug 142 may form a contact plug 138.

[0117] Figure 7A , Figure 7B and Figure 7CA single contact plug 138 is shown, but contact plug 138 can be replaced by a first peripheral contact plug 139 and a second peripheral contact plug 142.

[0118] Each of the first peripheral contact plug 139 and the second peripheral contact plug 142 may include a lower plug portion 138L, a first upper plug portion 138U1 on the lower plug portion 138L, and a second upper plug portion 138U2 on the first upper plug portion 138U1.

[0119] In the example, the width of the upper region of the lower plug portion 138L may be different from the width of the lower region of the first upper plug portion 138U1. For example, the width of the upper region of the lower plug portion 138L may be greater than the width of the lower region of the first upper plug portion 138U1.

[0120] In the example, the width of the upper region of the first upper plug portion 138U1 may be different from the width of the lower region of the second upper plug portion 138U2. For example, the width of the upper region of the first upper plug portion 138U1 may be smaller than the width of the lower region of the second upper plug portion 138U2.

[0121] In the example, on the first side of the side surface of each of the first peripheral contact plug 139 and the second peripheral contact plug 142, which is arranged in one direction, the upper end of the lower side surface 138s_L of the lower plug portion 138L may not be aligned with the lower end of the first upper side surface 138s_U1 of the first upper plug portion 138U1 in the vertical direction Z, and the upper end of the upper side surface 138s_U1 of the first upper plug portion 138U1 may not be aligned with the lower end of the second upper side surface 138s_U2 of the second upper plug portion 138U2 in the vertical direction Z. Therefore, the first side of the side surface of each of the first peripheral contact plug 139 and the second peripheral contact plug 142, which is arranged in one direction, may include: a lower curved portion 138b_L extending from the upper end of the lower side surface 138s_L of the lower plug portion 138L, which may be misaligned with each other, and the lower end of the first upper side surface 138s_U1 of the first upper plug portion 138U1; and an upper curved portion 138b_U extending from the upper end of the first upper side surface 138s_U1 of the first upper vertical portion 138U1, which may be misaligned with each other, and the lower end of the second upper side surface 138s_U2 of the second upper vertical portion 138U2.

[0122] In the example, the second bit connection plug 152b2 and the peripheral connection plug 152p may include the same material as the first bit connection plug 152b1, such as the gap-filling conductive layer 150b and the conductive liner 150a covering the side and bottom surfaces of the gap-filling conductive layer 150b.

[0123] In the example, each of the first peripheral contact plug 139 and the second peripheral contact plug 142 may include: a contact gap filling conductive pattern 138b; and a contact conductive liner 138a covering the side and bottom surfaces of the contact gap filling conductive pattern 138b. The contact gap filling conductive pattern 138b may include a metallic material (e.g., W, etc.), and the contact conductive liner 138a may include a metal nitride (e.g., TiN, TaN, or WN).

[0124] Each of the first peripheral contact plug 139 and the second peripheral contact plug 142 can sequentially penetrate the etch stop layer 19 and the capping layer 17 and can contact the peripheral pad 15.

[0125] In the following description, reference will be made to Figure 8A describe Figure 7A A modified example of the contact plug 138. Figure 8 shows a modification of the contact plug 138. Figure 7A An enlarged view of region 'Ba1' corresponding to region 'Ba' in the diagram, used for illustration. Figure 7A A modified example of the first upper plug portion 138U1 and the second upper plug portion 138U2 of the contact plug 138.

[0126] In the modified example, refer to Figure 8A The width of the upper region of the first upper plug portion 138U1 may be greater than the width of the lower region of the second upper plug portion 138U2a. Therefore, the first side of the side surface of the contact plug 138, which is provided in one direction, may include an upper curved portion 138b_Ua, extending from the upper end of the first upper side surface 138s_U1 of the first upper plug portion 138U1, which may be misaligned with each other, and the lower end of the second upper side surface 138s_U2a of the second upper plug portion 138U2a.

[0127] In the following description, reference will be made to Figure 8B describe Figure 7A Another example of a modification to contact plug 138. Figure 8B It is shown that... Figure 7A An enlarged view of region 'Ba2' corresponding to region 'Ba' in the diagram, used for illustration. Figure 7A A modified example of the first upper plug portion 138U1 and the second upper plug portion 138U2 of the contact plug 138.

[0128] In the modified example, refer to Figure 8BIn the contact plug 138, the vertical central axis of the first upper plug portion 138U1 and the vertical central axis of the second upper plug portion 138U2b may not be aligned. The vertical central axis of the first upper plug portion 138U1 may pass through the center between the side surfaces 138s_U1a and 138s_U1b of the first upper plug portion 138U1 in the vertical direction Z, and the vertical central axis of the second upper plug portion 138U2b may pass through the center between the side surfaces 138s_U2aa and 138s_U2ab of the second upper plug portion 138U2b in the vertical direction Z.

[0129] The side surfaces 138s_U1a and 138s_U1b of the first upper plug portion 138U1 and the side surfaces 138s_U2aa and 138s_U2ab of the second upper plug portion 138U2b may be misaligned in the vertical direction Z, such that the side surface of the contact plug 138 may include a curved portion 138b_Uaa in the +X direction and a curved portion 138b_Uab in the -X direction.

[0130] In the following description, reference will be made to Figure 8C describe Figure 7B Another example of a modification to contact plug 138. Figure 8C It is shown that... Figure 7B An enlarged view of region Bb1′ corresponding to region 'Bb' in the diagram, used for illustration. Figure 7B A modified example of the first upper plug portion 138U1 and lower plug portion 138L of the contact plug 138.

[0131] In the modified example, refer to Figure 8C In the contact plug 138, the vertical central axis of the first upper plug portion 138U1 and the vertical central axis of the lower plug portion 138L may not be aligned. The vertical central axis of the first upper plug portion 138U1 may pass through the center between the side surfaces 138s_U1aa and 138s_U1ba of the first upper plug portion 138U1 in the vertical direction Z, and the vertical central axis of the lower plug portion 138L may pass through the center between the side surfaces 138s_La and 138s_Lb of the lower plug portion 138L in the vertical direction Z.

[0132] The side surfaces 138s_U1aa and 138s_U1ba of the first upper plug portion 138U1 and the side surfaces 138s_La and 138s_Lb of the lower plug portion 138L can be misaligned in the vertical direction Z, such that the side surfaces of the contact plug 138 can include a curved portion 138b_La in the +X direction and a curved portion 138b_Lb in the -X direction.

[0133] In the following description, reference will be made to Figure 9 , Figure 10A and Figure 10B Describe the stacked structure ST' and the gate contact plug 136. Figure 9 This is an enlarged view showing part 'C'. Figure 10A It is shown Figure 9 An enlarged view of part 'Ca' in the image. Figure 10B It is shown Figure 10A A magnified view of part 'Cd' in the image.

[0134] refer to Figure 9 , Figure 10A and Figure 10B ,like Figure 3A As shown, each of the plurality of gate contact plugs 136 may include a lower plug portion 136L and an upper plug portion 136U on the lower plug portion 136L. The upper plug portion 136U may include a first upper plug portion 136U1, a second upper plug portion 136U2 on the first upper plug portion 136U1, and a third upper plug portion 136U3 on the second upper plug portion 136U2.

[0135] Each of the plurality of gate contact plugs 136 may include the same material as the first peripheral contact plug 139 and the second peripheral contact plug 142. For example, each of the plurality of gate contact plugs 136 may include: a contact gap filling conductive layer 138b; and a contact conductive liner 138a covering the side and bottom surfaces of the contact gap filling conductive layer 138b.

[0136] The upper end of the first upper plug portion 136U1 can be set at a height that is basically the same as the height of the upper surface of the second cover insulation layer 75. The second upper plug portion 136U2 can penetrate the second cover insulation layer 78 and the third cover insulation layer 103, and the third upper plug portion 136U3 can penetrate the fourth cover insulation layer 121.

[0137] like Figure 3A As shown, the side surface of the upper plug portion 136U may include a plurality of upper curved portions 136b_U.

[0138] In the example, the width of the upper region of the first upper plug portion 136U1 may be different from the width of the lower region of the second upper plug portion 136U2, and the width of the upper region of the second upper plug portion 136U2 may be different from the width of the lower region of the third upper plug portion 136U3. For example, the width of the upper region of the first upper plug portion 136U1 may be smaller than the width of the lower region of the second upper plug portion 136U2, and the width of the upper region of the second upper plug portion 136U2 may be larger than the width of the lower region of the third upper plug portion 136U3.

[0139] In the example, on a first side of the side surface of each gate contact plug 136 arranged in one direction, the upper end of the first upper side surface 136s_U1 of the first upper plug portion 136U1 may not be aligned with the lower end of the second upper side surface 136s_U2 of the second upper plug portion 136U2 in the vertical direction Z, and the upper end of the second upper side surface 136s_U2 of the second upper plug portion 136U2 may not be aligned with the lower end of the third upper side surface 136s_U3 of the third upper plug portion 136U3 in the vertical direction Z. Therefore, on a first side of the side surface of each gate contact plug 136 arranged in one direction, the upper end of the first upper surface 136s_U1 of the first upper plug portion 136U1 may include a first upper curved portion 136b_U1 extending from the lower end of the second upper surface 136s_U2 of the second upper plug portion 136U2, which may be misaligned with each other, and the upper end of the second upper surface 136s_U2 of the second upper plug portion 136U2 may include a second upper curved portion 136b_U2 extending from the lower end of the third upper surface 136s_U3 of the third upper plug portion 136U3, which may be misaligned with each other.

[0140] The second upper curved portion 136b_U2 can be set at a height higher than that of the first upper curved portion 136b_U1.

[0141] In the example, at a height higher than the height of the highest gate layer in gate layer 115, the first upper bend 136b_U1 of the side surface of each gate contact plug 136 can be disposed at a height substantially the same as the height of the upper bends 81b_U, 139b_U, 142b_U, 145b_U, and 91b_U of the side surfaces supporting the memory vertical structure 81, the first peripheral contact plug 139, the second peripheral contact plug 142, the source contact plug 145, and the supporting vertical structure 91. In the example embodiment, the horizontal surface of the first upper bend 136b_U1 can be coplanar with the lower surface of the third capping insulating layer 78, and the horizontal surface of the second upper bend 136b_U2 can be coplanar with the upper surface of the fourth capping insulating layer 103.

[0142] In the example, Figure 9 The cross-sectional shape of a gate contact plug 136 in part 'Cb' can be similar to... Figure 7B The cross-sectional shape of the contact plug 138 in the middle or Figure 8C The cross-sectional shape of the contact plug 138 is basically the same.

[0143] In the example, Figure 9 The cross-sectional shape of the gate contact plug 136 of part 'Cc' can be similar to... Figure 7C The cross-sectional shape of the contact plug 138 is basically the same.

[0144] Gate layer 115g may include Figure 4 The first layer 115a and the second layer 115b are shown. (Compared to...) Figure 3A Similarly, each of the plurality of gate contact plugs 136 may include a conductive material portion of the gate layer 115g, and the gate contact portion 136E is electrically connected to and contacts the second layer 115b.

[0145] One of the gate contacts 136E, such as the gate contact 136E1 of the first gate contact plug 1361, may further include a protrusion 136p that extends to cover the upper and lower surfaces of the second layer 115b of the upper gate layer 115U.

[0146] Each gate contact plug 136 may include a gate contact portion 136E, and when the gate layer 115g is disposed below a gate contact portion 136E, a buffer insulating pattern 109a may be disposed between the gate layer 115g disposed in the lower part of the gate contact portion 136E and each gate contact plug 136 to electrically insulate the gate layer 115g disposed in the lower part of the gate contact portion 136E from each gate contact plug 136.

[0147] In the following description, reference will be made to Figure 11A describe Figure 10A A modified example of the gate contact plug 136 described herein. Figure 11 shows a modification of the gate contact plug 136. Figure 7A An enlarged view of region 'Ca1' corresponding to region 'Ca' in the diagram, used for illustration. Figure 10A Modification examples of the second upper plug portion 136U2 and the third upper plug portion 136U3 of the gate contact plug 136.

[0148] In the modified example, refer to Figure 11AIn the gate contact plug 136, the vertical central axis of the second upper plug portion 136U2 and the vertical central axis of the third upper plug portion 136U3 may not be aligned. The vertical central axis of the second upper plug portion 136U2 may pass through the center between the side surfaces 136s_U2a and 136s_U2b of the second upper plug portion 136U2 in the vertical direction Z, and the vertical central axis of the third upper plug portion 136U3 may pass through the center between the side surfaces 136s_U3aa and 136s_U3ab of the third upper plug portion 136U3 in the vertical direction Z. The side surfaces 136s_U2a and 136s_U2b of the second upper plug portion 136U2 and the side surfaces 136s_U3aa and 136s_U3ab of the third upper plug portion 136U3 may not be aligned in the vertical direction Z. Therefore, the side surface of the gate contact plug 136 may include a bent portion 136b_U2a disposed in the +X direction and a bent portion 136b_U2b disposed in the -X direction.

[0149] In the following description, reference will be made to Figure 11B describe Figure 10A A modified example of the gate contact plug 136 described herein. Figure 11A It is shown that... Figure 10A An enlarged view of region 'Ca2' corresponding to region 'Ca' in the diagram, used for illustration. Figure 10A Modification examples of the second upper plug portion 136U2 and the third upper plug portion 136U3 of the gate contact plug 136.

[0150] In the modified example, refer to Figure 11B In the gate contact plug 136, the vertical center axis of the second upper plug portion 136U2 and the vertical center axis of the third upper plug portion 136U3 may not be aligned. Figure 11A Same as in China.

[0151] The vertical central axis of the first upper plug portion 136U1 and the vertical central axis of the second upper plug portion 136U2 may not be aligned. The vertical central axis of the first upper plug portion 136U1 may be in the vertical direction Z, passing through the center between the side surfaces 136s_U1a and 136s_U1b of the first upper plug portion 136U1, and the vertical central axis of the second upper plug portion 136U2 may be in the vertical direction Z, passing through the center between the side surfaces 136s_U2aa and 136s_U2ab of the second upper plug portion 136U2.

[0152] Because the side surfaces 136s_U1a and 136s_U1b of the first upper plug portion 136U1 and the side surfaces 136s_U2aa and 136s_U2ab of the second upper plug portion 136U2 can be misaligned in the vertical direction Z, the side surface of the gate contact plug 136 can include a bent portion 136b_U1a in the +X direction and a bent portion 136b_U1b in the -X direction.

[0153] In the following description, reference will be made to Figure 11C describe Figure 10A A modified example of the gate contact plug 136 described herein. Figure 11C It is shown that... Figure 7A An enlarged view of the region 'Ca' corresponding to region 'Ca3', used for illustration. Figure 10A Modification examples of the second upper plug portion 136U2 and the third upper plug portion 136U3 of the gate contact plug 136.

[0154] In the modified example, refer to Figure 11C The width of the upper region of the first upper plug portion 136U1 may be greater than the width of the lower region of the second upper plug portion 136U2, and the width of the upper region of the second upper plug portion 136U2 may be greater than the width of the lower region of the third upper plug portion 136U3. Therefore, the first side of the side surface of the gate contact plug 136, which is disposed in one direction, may include: a first upper curved portion 136b_U1c, extending from the upper end of the side surface of the first upper plug portion 136U1 and the lower end of the side surface of the second upper plug portion 136U2, which may be misaligned; and a second upper curved portion 136b_U2c, extending from the upper end of the side surface of the second upper plug portion 136U2 and the lower end of the side surface of the third upper plug portion 136U3, which may be misaligned.

[0155] The vertical central axis of the second upper plug portion 136U2 and the vertical central axis of the third upper plug portion 136U3 may not be aligned. The vertical central axis of the second upper plug portion 136U2 may be in the vertical direction Z, passing through the center between the side surfaces 136s_U2a and 136s_U2b of the second upper plug portion 136U2, and the vertical central axis of the third upper plug portion 136U3 may be in the vertical direction Z, passing through the center between the side surfaces 136s_U3aa and 136s_U3ab of the third upper plug portion 136U3. The side surfaces 136s_U2a and 136s_U2b of the second upper plug portion 136U2 and the side surfaces 136s_U3aa and 136s_U3ab of the third upper plug portion 136U3 may not be aligned in the vertical direction Z. Therefore, the side surface of the gate contact plug 136 may include a bent portion 136b_U2a disposed in the +X direction and a bent portion 136b_U2b disposed in the -X direction.

[0156] In the following description, reference will be made to Figure 12 Description Reference Figure 10B A modified example of the described gate contact plug 136. Figure 12 It is shown that... Figure 10B An enlarged view of region 'Cd1' corresponding to region 'Cd' in the diagram, used for illustration. Figure 10B Example of modification of gate contact plug 136.

[0157] In the modified example, refer to Figure 12 One of the gate contact plugs, such as the first gate contact plug 136_1, may include the gate contact portion 136E as described above. The first gate contact plug 136_1 may further include an extension 136p extending from the lower portion of the gate contact portion 136E along the direction of the buffer insulating pattern 109a. Therefore, one of the gate contact plugs, such as the first gate contact plug 136_1, may have a curved side surface below the gate contact portion 136E. For example, the width of the first gate contact plug 136_1 may be increased at the same height as the buffer insulating pattern 109a disposed below the gate contact portion 136E.

[0158] In the following description, reference will be made to Figure 13 Describe the source contact plug 145. Figure 13 It is shown Figure 3A A magnified view of part 'D' in the image.

[0159] refer to Figure 13 The source contact plug 145 may include a lower plug portion 145L, a first upper plug portion 145U1 on the lower plug portion 145L, and a second upper plug portion 145U2 on the first upper plug portion 145U1.

[0160] exist Figure 13 In the middle, the cross-sectional shape of the source contact plug 145 in part 'Da' can be similar to... Figure 6 and Figure 7A The cross-sectional shape of the contact plug 138, represented by 'Ba', Figure 8A The cross-sectional shape of the contact plug 138, represented by 'Ba1', or Figure 8B The cross-sectional shape of the contact plug 138 represented by 'Ba2' is basically the same.

[0161] exist Figure 13 In the middle, the cross-sectional shape of the source contact plug 145 in part 'Db' can be similar to... Figure 6 and Figure 7B The cross-sectional shape of the contact plug 138, represented by 'Bb', or Figure 8C The contact plugs 138 represented by 'Bb1' have basically the same cross-sectional shape.

[0162] In the example, the lower surface 145b1 of the source contact plug 145 can be set at a height lower than the height of the upper surface of the pattern structure 24, and at a height higher than the height of the upper surface of the patterned via 24p.

[0163] In the following description, reference will be made to Figure 14A describe Figure 13 Example of modification of source contact plug 145 in the example. Figure 14A It is shown Figure 3A A magnified view of part 'D' in the image.

[0164] refer to Figure 14A The lower surface 145b2 of the source contact plug 145 can be positioned at a height lower than the height of the upper surface of the patterned via 24p, and can also be positioned at a height higher than the height of the lower surface of the patterned via 24p. The upper surface of the patterned via 24p can be at the same height as the upper surface of the lower insulating layer 21.

[0165] In the following description, reference will be made to Figure 14B describe Figure 13 Example of modification of source contact plug 145 in the example. Figure 14B It is shown Figure 3A A magnified view of part 'D' in the image.

[0166] refer to Figure 14B The lower surface 14563 of the source contact plug 145 can penetrate the patterned via 24p and can contact the fourth peripheral pad 15d.

[0167] In the following description, reference will be made to Figure 15 Describe the pattern structure 24 and the supporting vertical structure 91. Figure 15 It is shown Figure 3B Enlarged view of the supporting vertical structure 91 in the image.

[0168] refer to Figure 15 The vertical support structure 91 may include and Figure 4 The material layers 83, 85, 87, and 89 of the memory vertical structure 81 described herein are substantially the same. At a height higher than the pattern structure 24, the supporting vertical structure 91 can have the same material layers as... Figure 4 The shape and structure of the memory vertical structure 81 described herein are substantially the same. For example, the supporting vertical structure 91 may include a lower vertical portion 91L, a first upper vertical portion 91U1 on the lower vertical portion 91L, and a second upper vertical portion 91U2 on the first upper vertical portion 91U1. For example, with Figure 3B Similarly, the first side of the side surface of the supporting vertical structure 91, which is arranged in one direction, may include: a lower curved portion 91b_L, between the side surface of the lower vertical portion 91L and the side surface of the first upper vertical portion 91U1; and an upper curved portion 91b_U, between the side surface of the first upper vertical portion 91U1 and the side surface of the second upper vertical portion 91U2.

[0169] The pattern structure 24 may include a lower pattern layer 26, a second intermediate pattern layer 28b on the lower pattern layer 26, and an upper pattern layer 30 on the first intermediate pattern layer 28b. The lower pattern layer 26 and the upper pattern layer 30 may include polysilicon. The second intermediate pattern layer 28b may include polysilicon and / or an insulating material.

[0170] In the following description, reference will be made to Figure 16 Describe a modified example of supporting the vertical structure 91. Figure 16 It is shown Figure 3B A cross-sectional view of a modified example of the supporting vertical structure 91 in the diagram.

[0171] refer to Figure 16 The supporting vertical structure 91' can have a higher degree of support than the above ( Figure 3B and Figure 15 The upper surface of the supporting vertical structure 91 is positioned at a height higher than that of the upper surface of the memory vertical structure 81. For example, the upper surface of the supporting vertical structure 91 can be positioned at a height higher than that of the upper surface of the memory vertical structure 81, and at a height lower than that of the upper surfaces of the contact plug 138 and the separation structure 118.

[0172] The supporting vertical structure 91' may include a material different from that of the memory vertical structure 81. For example, the supporting vertical structure 91' may not include the same materials included in the data storage material layer 83b and the channel material layer 85 of the memory vertical structure 81. The supporting vertical structure 91' may be formed of silicon oxide.

[0173] In the following description, reference will be made to Figure 17 Describe an example of a modification to a semiconductor device. Figure 17 This is a cross-sectional view illustrating a modified example of a semiconductor device according to an example embodiment.

[0174] refer to Figure 17 The semiconductor device 200a according to the example embodiment may include a first chip structure CH1 and a second chip structure CH2 bonded to the first chip structure CH1.

[0175] In the example, the second chip structure CH2 may include: a patterned structure 24 with openings as described above; a first intermediate insulating layer 33a and an outer intermediate insulating layer 33c; a memory vertical structure 81; a stacked structure ST'; a gate contact plug 136; a first peripheral contact plug 139 and a source contact plug 145; a bit line 155b; a source wiring 155s; and a peripheral wiring 155p.

[0176] The second chip structure CH2 may also include an insulating layer 221, a first intermediate insulating layer 33a, and an outer intermediate insulating layer 33c disposed below the pattern structure 24.

[0177] The second chip structure CH2 may also include a gate connection plug 152g disposed on the gate contact plug 136, and a gate wiring 155g disposed on the gate connection plug 152g.

[0178] The second chip structure CH2 may include: first bonding patterns 215a, 215c, 215s, and 215b; and a first bonding insulating layer 214 surrounding the side surfaces of the first bonding patterns 215a, 215c, 215s, and 215b. The first bonding patterns 215a, 215c, 215s, and 215b may be electrically connected to bit line 155b, gate wiring 155g, source wiring 155s, and peripheral wiring 155p. The first bonding patterns 215a, 215c, 215s, and 215b may include a metallic material such as copper.

[0179] The second chip structure CH2 may also include: an input pad 206 disposed below the insulating layer 221; and an input / output connection pattern 203 that electrically connects the input pad 206 to the first peripheral contact plug 139.

[0180] In the example, the first chip structure CH1 may include the same elements as those in the lower structure 3 in the above example embodiment. For example, the first chip structure CH1 may include: a semiconductor substrate 305; peripheral circuits 311 and 313 disposed below the semiconductor substrate 305 and including circuit device 311 and peripheral wiring 313 electrically connected to the circuit device 311; second bonding patterns 315a, 315c, 315s and 315b electrically connected to the peripheral wiring 313 and bonded to the first bonding patterns 215a, 215c, 215s and 215b; and a second bonding insulating layer 314 bonded to the first bonding insulating layer 214.

[0181] In the following description, reference will be made to Figure 18 Describe an example of a modification to a semiconductor device. Figure 18 It is shown Figure 17 A cross-sectional view of a modified example of a semiconductor device. The following description will describe... Figure 17 Modification of semiconductor device 200a in the text.

[0182] refer to Figure 18 The semiconductor device 200b according to the example embodiment may include a first chip structure CH1' and a second chip structure CH2' bonded to the first chip structure CH1'.

[0183] The first chip structure CH1' may further include: a protective insulating layer 360 on a semiconductor substrate 305; input / output pads 380 on the protective insulating layer 360; and an input / output through electrode 370 electrically connected to the input / output pads 380, penetrating the protective insulating layer 360 and the semiconductor substrate 305, and electrically connected to the circuit wiring 313.

[0184] In the example, Figure 18 In the second chip structure CH2', it is not necessary to provide Figure 17 The input / output pads 206, input / output connection patterns 203, and first peripheral contact plugs 139 are included.

[0185] In another example, the second chip structure CH2' can have the same characteristics as... Figure 17 It has the same structure as in the text.

[0186] In the following description, reference will be made to Figures 19A to 26B An example describing a method for forming a semiconductor device according to an example embodiment. Figures 19A to 26B middle, Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23 , Figure 24A , Figure 25A and Figure 26A It is along Figure 1A The cross-sectional view taken from line I-I' in the diagram. Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 24B , Figure 25B and Figure 26B It is along Figure 2A The cross-sectional view taken from lines II-II' and III-III' in the diagram.

[0187] refer to Figure 19A and Figure 19B The lower structure 3 can be formed. The lower structure 3 may include: a semiconductor substrate 5; an isolation region 7s defining a peripheral active region 7a on the semiconductor substrate 5; peripheral circuits 11 and 13 formed on the semiconductor substrate 5; peripheral pads 15 electrically connected to the peripheral circuits 11 and 13; and a lower insulating layer 21 covering the peripheral circuits 11 and the peripheral pads 15 on the semiconductor substrate 5. The peripheral circuits 11 and 13 may include: a circuit device 11 such as a transistor, including a peripheral gate 11g and a peripheral source / drain 11sd; and circuit wiring 13 electrically connected to the circuit device 11. The peripheral pads 15 may be electrically connected to the circuit wiring 13.

[0188] The peripheral pads 15 may include first peripheral pads to fourth peripheral pads 15a, 15b, 15c, and 15d. In the example, each peripheral pad 15 may include a conductive material, such as a metallic material like tungsten.

[0189] The lower structure 3 may further include: a capping layer 17 formed on each peripheral pad 15; and an etch stop layer 19 formed on the capping layer 17. In the example, the capping layer 17 may be formed of a silicon layer, and the etch stop layer 19 may be formed of an insulating material such as silicon oxide or silicon nitride.

[0190] A pattern structure 24 with a first opening 24a and a second opening 24b can be formed on the lower structure 3.

[0191] In the example, pattern structure 24 can be formed as a single layer, such as a silicon layer.

[0192] In another example, pattern structure 24 may include a plurality of patterned layers stacked in sequence. For example, pattern structure 24 may include a lower patterned layer, an intermediate patterned layer on the lower patterned layer, and an upper patterned layer on the intermediate patterned layer. At least one of the lower patterned layer, the intermediate patterned layer, and the upper patterned layer may be a silicon layer. For example, the lower patterned layer and the upper patterned layer may be silicon layers, and the intermediate patterned layer may be, for example, a material layer different from the silicon layer, such as a silicon oxide layer and / or a silicon nitride layer.

[0193] In another example, pattern structure 24 may include a metal layer and a silicon layer on the metal layer.

[0194] In the example, pattern structure 24 may include a patterned via 24P extending downward from the lower surface of pattern structure 24 and electrically connected to a fourth peripheral pad 15d. The patterned via 24P may be formed as a silicon layer.

[0195] A first opening 24a and a second opening 24b can be formed to fill the pattern structure 24, and an intermediate insulating layer can be formed on the outer side of the pattern structure 24. The intermediate insulating layer can be formed of silicon oxide. The intermediate insulating layer includes a first intermediate insulating layer 33a filling the first opening 24a, a second intermediate insulating layer 33b filling the second opening 24b, and an outer intermediate insulating layer 33c formed on the outer side of the pattern structure 24.

[0196] The initial stacked structure LS can be formed on the patterned structure 24.

[0197] The initial lower stack structure LS can be formed as follows: forming an alternately and repeatedly stacked lower interlayer insulating layer 38 and a lower horizontal layer 40; forming a lower pad of the lower horizontal layer 40 arranged in a stepped shape by patterning the lower interlayer insulating layer 38 and the lower horizontal layer 40; and forming a lower pad layer 42 on the lower pad of the lower horizontal layer 40.

[0198] A first capping insulating layer 47 can be formed having an upper surface coplanar with the upper surface of the initial lower stack structure LS. The first capping insulating layer 47 can be formed of, for example, silicon oxide. The first capping insulating layer 47 can cover the lower pad layer 42 arranged in a stepped shape.

[0199] A lower sacrificial pattern can be formed that penetrates the structure including the initial lower stacked structure LS and the first capping insulating layer 47. Forming the lower sacrificial pattern may include: forming a lower via penetrating the structure including the initial lower stacked structure LS and the first capping insulating layer 47 by performing a first semiconductor process including a photolithography process and an etching process, wherein the photolithography process and the etching process are each performed once; and filling the lower via with a sacrificial material.

[0200] The lower sacrificial pattern may include a lower sacrificial memory vertical portion 50, a lower sacrificial gate contact portion 52a, a lower sacrificial source contact portion 54a, a first lower sacrificial peripheral contact portion 56a, a second lower sacrificial contact portion 58a, and a lower sacrificial support vertical portion 60.

[0201] The lower sacrificial memory vertical portion 50, the lower sacrificial source contact portion 54a, and the lower sacrificial support vertical portion 60 can contact the pattern structure 24. For example, the lower surfaces of the lower sacrificial memory vertical portion 50, the lower sacrificial source contact portion 54a, and the lower sacrificial support vertical portion 60 can be below the upper surface of the pattern structure 24.

[0202] The lower sacrificial gate contact 52a can penetrate the first intermediate insulating layer 33a that fills the first opening 24a and can contact the capping layer 17 that contacts the first peripheral pad 15a. The first lower sacrificial peripheral contact 56a can penetrate the outer intermediate insulating layer 33c and can contact the capping layer 17 on the second peripheral pad 15b. The second lower sacrificial peripheral contact 58a can penetrate the second intermediate insulating layer 33b and can contact the capping layer 17 on the third peripheral pad 15c.

[0203] refer to Figure 20A and Figure 20B A preliminary upper stack structure US can be formed on the preliminary lower stack structure LS and the first capping insulating layer 47.

[0204] The initial upper stack structure US can be formed as follows: an upper interlayer insulating layer 62 and an upper horizontal layer 64 are formed in an alternating and repeated manner; an upper pad of the upper horizontal layer 64 is formed in a stepped shape by patterning the upper interlayer insulating layer 62 and the lower horizontal layer 64; and an upper pad layer 66 is formed on the upper pad of the upper horizontal layer 64.

[0205] The initial lower stack structure LS and the initial upper stack structure US can form the initial stack structure ST. The lower interlayer insulating layer 38 and the upper interlayer insulating layer 62 can form an interlayer insulating layer. The lower horizontal layer 40 and the upper horizontal layer 64 can form an initial horizontal layer. In this example, the interlayer insulating layer can be formed of silicon oxide, the lower horizontal layer 40 and the upper horizontal layer 64 can be formed of a first silicon nitride, and the lower pad layer 42 and the upper pad layer 66 can be formed of a second silicon nitride.

[0206] The upper pad layer 66 can be arranged in a stepped shape. Therefore, the lower pad layer 42 and the upper pad layer 66 can be arranged in a stepped shape. The lower pad layer 42 and the upper pad layer 66 can overlap with the first intermediate insulating layer 33a of the first opening 24a of the filling pattern structure 24 in the vertical direction Z.

[0207] A second capping insulating layer 75 can be formed having an upper surface coplanar with the upper surface of the initial stacked structure ST. The second capping insulating layer 75 can be formed of silicon oxide. The second capping insulating layer 75 can cover the first capping insulating layer 47 and the upper pad layer 66 arranged in a stepped shape.

[0208] An upper sacrificial pattern can be formed that penetrates the structure including the initial upper stack structure US and the second capping insulating layer 75. Forming the upper sacrificial pattern may include: forming a first upper via penetrating the structure including the initial upper stack structure US and the second capping insulating layer 45 by performing a second semiconductor process including a photolithography process and an etching process, wherein the photolithography process and the etching process are each performed once; and filling the first upper via with a sacrificial material.

[0209] The upper sacrificial pattern may include the upper sacrificial memory vertical section ( Figure 20A The upper sacrificial gate contact 52b, the upper sacrificial source contact 54b, the first upper sacrificial peripheral contact 56b, the second upper sacrificial contact 58b, and the upper sacrificial support vertical portion (81U1) Figure 20B Part of 91U1).

[0210] The vertical part of the upper sacrificial memory can be ( Figure 19A and 19B The lower sacrificial memory vertical portion 50 is formed on the lower sacrificial source contact portion 54a, and the upper sacrificial source contact portion 54b can be formed on the lower sacrificial source contact portion 54a. The upper sacrificial support vertical portion can be formed on the lower sacrificial source contact portion 54a. Figure 19B The lower sacrificial support vertical portion 60 is formed thereon, and the upper sacrificial gate contact portion 52b may be formed on the lower sacrificial gate contact portion 52a. The first upper sacrificial peripheral contact portion 56b may be formed on the first lower sacrificial peripheral contact portion 56a, and the second upper sacrificial contact portion 58b may be formed on the second lower sacrificial peripheral contact portion 58a.

[0211] The third capping insulation layer 78 can be formed on the initial stacked structure ST and the second capping insulation layer 75.

[0212] A third semiconductor process, including photolithography and etching, can be performed to form a vertical portion of the upper sacrificial memory that penetrates the third capping insulating layer 78 and exposes it. Figure 20A Part 81U1) and the upper sacrificial support vertical part ( Figure 20B The second upper hole (91U1) in the middle is subjected to one photolithography process and one etching process. Then, the vertical portion of the upper sacrificial memory ( Figure 20A Part 81U1), vertical section of lower sacrificial memory ( Figure 20A and Figure 20B Part 81L), Upper sacrificial support vertical part ( Figure 20B Part 91U1) and the lower sacrificial support vertical part ( Figure 20B Part 91L) is used to form the memory vertical hole 81H and the support vertical hole 91H.

[0213] In the example, a vertical structure can be formed that simultaneously fills both the memory vertical hole 81H and the supporting vertical hole 91H. For example, a memory vertical structure 81 can be formed in the memory vertical hole 81H, and a supporting vertical structure 91 can be formed in the supporting vertical hole 91H.

[0214] In the example, forming the memory vertical structure 81 and the supporting vertical structure 91 may include: forming a dielectric structure on the side surface of each of the vertical holes 81H and 91H; forming a channel layer covering the dielectric structure in the vertical holes 81H and 91H; forming a core region on the channel layer that partially fills each of the vertical holes 81H and 91H; and forming a pad pattern on the core region that fills the upper region of the vertical holes 81H and 91H.

[0215] refer to Figure 21A and Figure 21B A fourth sealing insulation layer 103 can be formed on the third sealing insulation layer 78.

[0216] A third upper aperture penetrating the third capping insulating layer 78 and the fourth capping insulating layer 103 can be formed by performing a fourth semiconductor process including photolithography and etching, wherein the photolithography process and the etching process are each performed once. The third upper aperture can expose the upper sacrificial gate contact 52b.

[0217] Then, a gate contact hole 106 including a third upper hole can be formed by sequentially etching the upper sacrificial gate contact portion 52b and the lower sacrificial gate contact portion 52a.

[0218] refer to Figure 22A and Figure 22B An extended via extending from the gate contact hole 106 can be formed by partially etching the initial horizontal layer (e.g., lower horizontal layer 40 and upper horizontal layer 64) exposed through the gate contact hole 106, as well as the lower pad layer 42 and upper pad layer 66.

[0219] The portion of the initial horizontal layer that contacts the lower pad layer 42 and the upper pad layer 66, as well as the portion of the lower pad layer 42 and the upper pad layer 66, can be defined as the pad portion.

[0220] The thickness of each pad can be greater than the thickness of each of the initial horizontal layers. Therefore, in the via, due to the etch load effect, the pads can be etched earlier than the initial horizontal layers. In another example, when the lower pad layer 42 and the upper pad layer 66 are formed of materials that are etched earlier than the material of the initial horizontal layers, the pads can be etched earlier than the initial horizontal layers.

[0221] In an expansion hole, the expansion hole formed by etching the pad portion can be defined as a pad expansion hole 106e. The pad expansion hole 106e can be arranged in a stepped shape.

[0222] A buffer insulating layer 109 can be formed on the structure forming the gate contact hole 106 and the expansion hole.

[0223] The buffer insulating layer 109 can cover the sidewall of the gate contact hole 106, may not fill the pad expansion hole 106e in the expansion hole, and can conformally cover the inner wall of the pad expansion hole 106e. It can fill other expansion holes and can cover the upper part of the fourth capping insulating layer. The buffer insulating layer 109 that fills the expansion holes other than the pad expansion hole 106e can be defined as a buffer insulating pattern 109a.

[0224] In the example, the buffer insulating layer 109 can be formed of silicon oxide.

[0225] In another example, the buffer insulating layer 109 may be formed of a high-k dielectric (e.g., AlO, HfO, etc.).

[0226] refer to Figure 23 A sacrificial gate contact plug 110 that fills the gate contact hole 106 and the pad expansion hole 106e can be formed on the buffer insulating layer 109.

[0227] refer to Figure 24A and Figure 24B This can form a separation trench 112. It can penetrate the upper fourth capping insulation layer 103 on the patterned structure 24 to form a structure. The lower horizontal layer 40 and upper horizontal layer 64 of the initial stacked structure ST can be exposed through the separation trench 112.

[0228] An empty space can be formed by etching the lower horizontal layer 40 and upper horizontal layer 64 exposed via the separation trench 112, and etching the lower pad layer 42 and upper pad layer 66, and a gate layer 115g can be formed in this empty space. The gate layer formed in the space where the lower horizontal layer 40 and lower pad layer 42 are removed can be referred to as the lower gate layer 115L, and the gate layer formed in the space where the upper horizontal layer 64 and upper pad layer 66 are removed can be referred to as the upper gate layer 115U.

[0229] In the example, the lower horizontal layer 40 and the upper horizontal layer 64 can be retained and can be formed as a lower insulating horizontal layer 40a and an upper insulating horizontal layer 64a. The lower insulating horizontal layer 40a and the upper insulating horizontal layer 64a can form an insulating horizontal layer 115i.

[0230] Therefore, the initial lower stacked structure LS can be formed as a lower stacked structure LS' including a lower gate layer 115L. The initial upper stacked structure US can be formed as an upper stacked structure US' including an upper gate layer 115U. Therefore, the initial stacked structure ST can be formed as a stacked structure ST'.

[0231] A separation structure 118 can be formed to fill the separation trench 112. In one example, the separation structure 118 can be formed of an insulating material, such as silicon oxide. In another example, each separation structure 118 may include: an insulating spacer covering the side surface of the separation trench 112; and a conductive pattern filling other portions of the separation trench 112.

[0232] refer to Figure 25A and Figure 25B A fifth sealing insulation layer 121 can be formed on the fourth sealing insulation layer 103.

[0233] A fourth upper via penetrating the fifth capping insulating layer 121 can be formed by performing a fifth semiconductor process, including photolithography and etching, wherein the photolithography and etching processes are each performed once. The fourth upper via exposes the sacrificial gate contact plug 110, the upper sacrificial source contact 54b, the first upper sacrificial peripheral contact 56b, and the second upper sacrificial contact 58b. Then, by removing the sacrificial gate contact plug 110, the upper sacrificial source contact 54b, the first upper sacrificial peripheral contact 56b, and the second upper sacrificial contact 58b, etching the lower sacrificial source contact 54a, the first lower sacrificial peripheral contact 56a, and the second lower sacrificial contact 58a, and etching the capping layer 17, the fourth upper via exposes the peripheral pad 15. Therefore, a gate contact hole 124 exposing the first peripheral pad 15a, a first peripheral contact hole 128 exposing the second peripheral pad 15b, a second peripheral contact hole 130 exposing the third peripheral pad 15c, and a source contact hole 126 exposing the pattern structure 24 can be formed.

[0234] The buffer insulating pattern 109a can be partially etched until the conductive material portion of the gate layer 115g is exposed in the gate expansion hole 106E.

[0235] The buffer insulating pattern 109a formed in the gate expansion hole 106E can be removed, while the buffer insulating pattern 109a formed below the gate expansion hole 106E can be retained.

[0236] refer to Figure 26A and Figure 26B It can simultaneously form gate contact plugs 136, first peripheral contact plugs 139, second peripheral contact plugs 142 and source contact plugs 145 that can fill gate contact hole 124, first peripheral contact hole 128, second peripheral contact hole 130 and source contact hole 126.

[0237] In the above example embodiment, the gate contact hole 124 can be formed by four photolithography processes, namely, Figure 19A and 19B The first semiconductor process shown includes performing one photolithography and etching process. Figure 20A and Figure 20B The second semiconductor process shown includes performing one photolithography and etching process. Figure 21A and Figure 21B The diagram shows a fourth semiconductor process that includes performing one photolithography and etching process, and Figure 25A and Figure 25B The fifth semiconductor process shown includes performing one photolithography and one etching process.

[0238] In the above example embodiment, the first peripheral contact hole 128, the second peripheral contact hole 130, and the source contact hole 126 can be formed by three photolithography processes, namely the first semiconductor process, the second semiconductor process, and the fifth semiconductor process.

[0239] The side surface contours of the gate contact hole 124, the first peripheral contact hole 128, the second peripheral contact hole 130, and the source contact hole 126 can be determined by photolithography processes performed at different stages in one direction. Therefore, the gate contact hole 124 can have three bends formed by four photolithography processes performed on the side surface at different stages in one direction, and the first peripheral contact hole 128, the second peripheral contact hole 130, and the source contact hole 126 can have two bends formed by three photolithography processes performed on the side surface at different stages in one direction. The side surface contours of the gate contact hole 124, the first peripheral contact hole 128, the second peripheral contact hole 130, and the source contact hole 126 can be substantially the same as the side surface contours of the gate contact plug 136, the first peripheral contact plug 139, the second peripheral contact plug 142, and the source contact plug 145.

[0240] As described above, by simultaneously forming gate contact plugs 136, 139, 142, and 145 that respectively fill the gate contact holes 124, 128, 130, and 124 formed by photolithography and etching processes, the gate contact plugs 136, 139, 142, and 145 can be stably and reliably formed. Therefore, the reliability of the semiconductor device can be improved.

[0241] Figure 27 This is a diagram illustrating a data storage system including semiconductor devices according to an example embodiment.

[0242] refer to Figure 27According to an embodiment, the data storage system 1000 includes a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 can be implemented as a storage device including the semiconductor device 1100 or an electronic device including a storage device. For example, the data storage system 1000 can be implemented using a solid-state drive (SSD) device including the semiconductor device 1100, a universal serial bus (USB), a computing system, a medical device, or a communication device.

[0243] In an example embodiment, the data storage system 1000 can be implemented as an electronic system for storing data.

[0244] Refer to Figure 1 to Figure 18 The semiconductor devices described in the above example embodiments or those derived from the reference Figures 19A to 26B The semiconductor device 1100 is manufactured by the method for manufacturing a semiconductor device described in the above example embodiments. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F.

[0245] The first structure 1100F can be implemented as a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. For example, the first structure 1100F may include the peripheral circuit described in the above example embodiment. Figure 3A Peripheral circuit 11 or Figure 17 and Figure 18 (External circuit 311 in the middle).

[0246] The second structure 1100S can be configured as a memory cell structure, which includes a bit line BL, a common source line CSL, a word line WL, a first upper gate line UL1 and a second upper gate line UL2, a first lower gate line LL1 and a second lower gate line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0247] The pattern structure 24 described in the above example embodiments may include a silicon layer with N-type conductivity, and the silicon layer with N-type conductivity may be configured as a common source line CSL.

[0248] In the second structure 1100S, each of the memory cell strings CSTRs may include: lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCTs disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary in the example embodiment.

[0249] In the example embodiment, the upper transistors UT1 and UT2 may include string select transistors, and the lower transistors LT1 and LT2 may include ground select transistors. The lower gate lines LL1 and LL2 may be the gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be the gate electrode of the memory cell transistor MCT, and the upper gate lines UL1 and UL2 may be the gate electrodes of the upper transistors UT1 and UT2, respectively.

[0250] The gate layer 115g described in the above example embodiment can form the lower gate lines LL1 and LL2, the word line W1, and the upper gate lines UL1 and UL2.

[0251] In an example embodiment, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series with each other. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series with each other. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used for an erase operation that uses the gate-induced leakage current (GIDL) phenomenon to erase data stored in the memory cell transistor MCT.

[0252] The common source line CSL, the first lower gate line LL1 and the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first connection wiring 1115 extending from the first structure 1100F to the second structure 1100S.

[0253] Bit line BL can be electrically connected to page buffer 1120 via a second connection wiring 1125 extending from the first structure 1100F to the second structure 1100S. Bit line BL can be bit line 155b as described in the example embodiment above.

[0254] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one selected memory cell transistor (MCT) among a plurality of memory cell transistors. The decoder circuit 1110 and the page buffer circuit 1120 can be controlled by the logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via input / output pads 1101 electrically connected to the logic circuit 1130. The input / output pads 1101 can be electrically connected to the logic circuit 1130 via input / output connection lines 1135 extending from the first structure 1100F to the second structure 1100S.

[0255] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In an example embodiment, the data storage system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100.

[0256] Processor 1210 can control the overall operation of data storage system 1000, including controller 1200. Processor 1210 can operate according to predetermined firmware and can access semiconductor device 1100 by controlling NAND controller 1220. NAND controller 1220 may include NAND interface 1221 for handling communication with semiconductor device 1100. Control commands for controlling semiconductor device 1100, data to be written to memory cell transistors (MCTs) of semiconductor device 1100, and data read from memory cell transistors (MCTs) of semiconductor device 1100 can be transmitted through NAND interface 1221. Host interface 1230 provides communication functionality between data storage system 1000 and external host. When a control command is received from an external host through host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0257] Figure 28 This is a perspective view illustrating a data storage system including semiconductor devices according to an example embodiment.

[0258] refer to Figure 28 The data storage system 2000 in the example embodiment may include a main substrate 2001, a controller 2002 mounted on the main substrate 2001, and one or more semiconductor packages 2003 and DRAMs 2004. The semiconductor packages 2003 and DRAMs 2004 may be connected to the controller 2002 via wiring patterns 2005 formed on the main substrate 2001.

[0259] The main substrate 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. In an example embodiment, the data storage system 2000 may communicate with the external host via one of the following interfaces: for example, Universal Serial Bus (USB), Peripheral Component Interconnect High Speed ​​(PCI-Express), Serial Advanced Technology Attachment (SATA), or M-Phy for Universal Flash Memory (UFS). In an example embodiment, the data storage system 2000 may operate via power supplied from the external host via the connector 2006. The data storage system 2000 may also include a power management integrated circuit (PMIC) for distributing power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0260] The controller 2002 can write data to or read data from the semiconductor package 2003, and can improve the operating speed of the data storage system 2000.

[0261] DRAM 2004 can be configured as a buffer memory to reduce the speed difference between semiconductor package 2003, data storage space, and external host. In control operations targeting semiconductor package 2003, DRAM 2004 included in data storage system 2000 can also operate as a high-speed buffer memory and provide space for temporary data storage. When data storage system 2000 includes DRAM 2004, in addition to the NAND controller for controlling semiconductor package 2003, controller 2002 may also include a DRAM controller for controlling DRAM 2004.

[0262] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be implemented as a semiconductor package including a plurality of semiconductor chips 2200. Each semiconductor chip 2200 may include, as shown in Figures 1 to 2003. Figure 18 The semiconductor devices described in the above example embodiments or those derived from the reference Figures 19A to 26B The semiconductor device is manufactured by the method for manufacturing semiconductor devices described in the above example embodiments.

[0263] Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include: a package substrate 2100; a semiconductor chip 2200 on the package substrate 2100; an adhesive layer 2300 disposed on the lower surface of the semiconductor chip 2200; a connection structure 2400 electrically connecting the semiconductor chip 2200 to the package substrate 2100; and a molding layer 2500 covering the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0264] The package substrate 2100 can be implemented as a printed circuit board including on-package pads 2130. Each semiconductor chip 2200 may include input / output pads 2210.

[0265] In an example embodiment, the connection structure 2400 may be configured to electrically connect the input / output pads 2210 to bonding wires on the package pads 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via bonding wires and may be electrically connected to the package pads 2130 of the package substrate 2100. In an example embodiment, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a connection structure including through-silicon vias (TSVs) instead of the bonding wire method connection structure 2400.

[0266] In an example embodiment, the controller 2002 and the semiconductor chip 2200 may be included in a single package. For example, the controller 2002 and the semiconductor chip 2200 may be mounted on an interposer substrate different from the main substrate 2001, and the controller 2002 may be connected to the semiconductor chip 2200 via wiring formed on the interposer substrate.

[0267] Figure 29 This is a cross-sectional view illustrating a data storage system including semiconductor devices according to an example embodiment. Figure 29 Show Figure 28 Example embodiments of semiconductor packaging 2003 are shown. Figure 28 The area intercepted along line V-V' in the semiconductor package 2003.

[0268] refer to Figure 29In semiconductor packaging 2003, packaging substrate 2100 can be configured as a printed circuit board. Packaging substrate 2100 may include: a packaging substrate body portion 2120; a packaging upper pad 2130 disposed on the upper surface of the packaging substrate body portion 2120; a lower pad 2125 disposed on or exposed through the lower surface of the packaging substrate body portion 2120; and internal wiring 2135 in the packaging substrate body portion 2120 electrically connecting the packaging upper pad 2130 to the lower pad 2125. The packaging upper pad 2130 can be electrically connected to a connection structure 2400. The lower pad 2125 can be connected to a wiring pattern 2005 of the main substrate 2001 of the data storage system 2000 via a conductive connection portion 2800.

[0269] Each semiconductor chip 2200 may include: a semiconductor substrate 3010; and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include: a peripheral circuit region including peripheral wiring 3110. The second structure 3200 may include: a common source line 3205; a gate stack structure 3210 on the common source line 3205; a memory channel structure 3220 and a separation structure 3230 penetrating the gate stack structure 3210; a bit line 3240 electrically connected to the memory channel structure 3220; and a gate connection line electrically connected to the word line WL of the gate stack structure 3210. The first structure 3100 may include Figure 27 The first structure 1000F and the second structure 3200 may include Figure 27 The first structure in it is 1000S.

[0270] Each semiconductor chip 2200 may include a peripheral wiring 3110 electrically connected to the first structure 3100 and a through wiring 3245 extending into the second structure 3200. The through wiring 3245 may penetrate the gate stack structure 3210 and may also be disposed on the outside of the gate stack structure 3210.

[0271] Each semiconductor chip 2200 may further include: input / output connection wiring electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200; and input pad 2210 electrically connected to the input / output connection wiring.

[0272] exist Figure 29 In the figure, an enlarged portion of the semiconductor device 1, indicated by reference numeral 1, is provided for representing Figure 29 The semiconductor chip 2200 in the middle can be modified to include and Figure 3A The same cross-sectional structure as in Figure 1. Therefore, each semiconductor chip 2200 may include the same cross-sectional structure as in Figure 1. Figure 18 The semiconductor device 1 described in the above example embodiments or derived from the reference Figures 19A to 26B The semiconductor device 1 is manufactured by the method for manufacturing semiconductor devices described in the above example embodiments.

[0273] According to the above example embodiments, various types of contact holes are formed by performing several photolithography and etching processes, and various types of contact plugs filling each of the various types of contact holes are formed simultaneously, enabling the stable and reliable formation of various types of contact plugs. Therefore, the reliability of the semiconductor device can be improved. Furthermore, because gate layers can be formed and stacked in the vertical direction, the integration density of the semiconductor device can be increased.

[0274] Therefore, it is possible to provide semiconductor devices and data storage systems that can improve integration density and reliability.

[0275] Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and alterations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: Pattern structure; A stacked structure includes multiple gate layers that are stacked vertically and spaced apart from each other in a first region of the patterned structure and extend into a second region of the patterned structure; The memory has a vertical structure that penetrates the stacked structure in the first region; Multiple gate contact plugs are electrically connected to the multiple gate layers in the second region; as well as The first peripheral contact plug is spaced apart from the plurality of gate layers. The plurality of gate layers includes a first gate layer. The plurality of gate contact plugs includes a first gate contact plug that is in contact with and electrically connected to the first gate layer. Each of the plurality of gate contact plugs and the first peripheral contact plug includes a conductive gap filling pattern and a conductive liner covering the side and bottom surfaces of the conductive gap filling pattern. Wherein, at a height higher than the height of the highest gate layer among the plurality of gate layers, the side surface of the first gate contact plug and the side surface of the first peripheral contact plug have different numbers of upward bends, and Wherein, at a height higher than the height of the highest gate layer, the number of upper bends on the first side of the side surface of the first gate contact plug in the first direction is greater than the number of upper bends on the side surface of the first peripheral contact plug in the first direction.

2. The semiconductor device according to claim 1, in, At a height higher than the height of the highest gate layer, the side surface of the first gate contact plug has two upward bends on the first side in the first direction, and Wherein, at a height higher than the height of the highest gate layer, the first side of the side surface of the first peripheral contact plug in the first direction has a single upward bend.

3. The semiconductor device according to claim 1, in, The first peripheral contact plug includes a lower peripheral plug portion and an upper peripheral plug portion on the lower peripheral plug portion. Each of the plurality of gate contact plugs includes a lower gate plug portion and an upper gate plug portion on the lower gate plug portion. The side surface of the first peripheral contact plug further includes a downwardly curved portion between the side surface of the lower peripheral plug portion and the side surface of the upper peripheral plug portion. The side surface of the first gate contact plug further includes a lower curved portion between the side surface of the lower gate plug portion and the side surface of the upper gate plug portion.

4. The semiconductor device according to claim 3, in, The upper gate plug portion of the first gate contact plug includes a first upper gate plug portion, a second upper gate plug portion, and a third upper gate plug portion arranged sequentially in the vertical direction, and Wherein, at a height higher than the height of the highest gate layer among the plurality of gate layers, the upper bend of the side surface of the first gate contact plug on the first side in the first direction includes a first upper bend between the side surface of the first upper gate plug portion and the side surface of the second upper gate plug portion, and a second upper bend between the side surface of the second upper gate plug portion and the side surface of the third upper gate plug portion.

5. The semiconductor device according to claim 4, in, The upper peripheral plug portion of the first peripheral contact plug includes a first upper peripheral plug portion and a second upper peripheral plug portion arranged sequentially in the vertical direction, and Wherein, at a height higher than the height of the highest gate layer among the plurality of gate layers, the upper bend of the first side of the side surface of the first peripheral contact plug includes a single upper bend between the side surface of the first upper peripheral plug portion and the side surface of the second upper peripheral plug portion.

6. The semiconductor device according to claim 5, in, The first peripheral contact plug has an upper surface that is coplanar with the upper surfaces of the plurality of gate contact plugs, and The upper curved portion of the side surface of the first peripheral contact plug is located at a height that is substantially the same as the height of the first upper curved portion of the side surface of the first gate contact plug.

7. The semiconductor device according to claim 5, further comprising: The lower structure includes peripheral circuitry and peripheral pads electrically connected to the peripheral circuitry. The pattern structure is disposed on the lower structure. The pattern structure includes multiple openings. The peripheral pads include a first peripheral pad and a second peripheral pad. The plurality of gate contact plugs extend downward from the portion penetrating the stacked structure, through the plurality of openings, and contact the first peripheral pad. The first peripheral contact plug contacts the second peripheral pad.

8. The semiconductor device according to claim 7, further comprising: The capping layer on the outer pads, The capping layer includes a silicon layer. The plurality of gate contact plugs are spaced apart from the pattern structure. The plurality of gate contact plugs penetrate the capping layer on the first peripheral pad and contact the first peripheral pad. The first peripheral contact plug penetrates the capping layer on the second peripheral pad and contacts the second peripheral pad.

9. The semiconductor device according to claim 7, further comprising: Second peripheral contact plug; The first line contact plug on the vertical structure of the memory; The second position line contact plug on the second peripheral contact plug; as well as The bit line is electrically connected to the first bit line contact plug and the second bit line contact plug.

10. The semiconductor device according to claim 9, in, The stacked structure further includes an insulating horizontal layer disposed at the same height as the plurality of gate layers, and The second peripheral contact plug penetrates the insulating horizontal layer.

11. The semiconductor device according to claim 1, in, The vertical structure of the memory includes a data storage structure and a channel material layer. Wherein, at a height higher than the height of the highest gate layer among the plurality of gate layers, the side surface of the vertical structure of the memory has at least one upwardly curved portion, and Wherein, at the height between the lower gate layer and the upper gate layer that are adjacent to each other along the vertical direction in the plurality of gate layers, each of the side surfaces of the memory vertical structure, the plurality of gate contact plugs and the first peripheral contact plug has at least one downward bend.

12. The semiconductor device according to claim 11, further comprising: Supporting a vertical structure, penetrating the stacked structure in the second region. Wherein, at a height higher than the height of the highest gate layer among the plurality of gate layers, the side surface supporting the vertical structure has at least one upwardly curved portion, and Wherein, at the height between the lower gate layer and the upper gate layer that are adjacent to each other in the vertical direction among the plurality of gate layers, the supporting vertical structure has at least one downward bend.

13. The semiconductor device according to claim 11, further comprising: The source contact plug is spaced apart from the plurality of gate layers and contacts the patterned structure. The source contact plug includes the conductive gap filling pattern and the conductive liner included in the plurality of gate contact plugs and the first peripheral contact plug. Wherein, at a height higher than the height of the highest gate layer among the plurality of gate layers, the side surface of the source contact plug has the same number of upper bends as the side surface of the first peripheral contact plug.

14. A semiconductor device, comprising: Pattern structure; A stacked structure includes multiple gate layers that are stacked vertically and spaced apart from each other in a first region of the patterned structure and extend into a second region of the patterned structure; The memory has a vertical structure that penetrates the stacked structure in the first region; Multiple gate contact plugs are electrically connected to the multiple gate layers in the second region. The stacked structure includes: a lower stacked structure including a lower gate layer; and an upper stacked structure including an upper gate layer on the lower stacked structure. Each of the plurality of gate contact plugs includes a conductive gap filling pattern and a conductive liner covering the side and bottom surfaces of the conductive gap filling pattern. The plurality of gate contact plugs includes a first gate contact plug electrically connected to a first upper gate layer in the upper gate layer, and a second gate contact plug electrically connected to a first lower gate layer in the lower gate layer. Wherein, at a height higher than the height of the highest gate layer among the plurality of gate layers, the first side of the side surface of each of the first gate contact plug and the second gate contact plug, positioned in the first direction, includes a plurality of upper bends disposed at different heights.

15. The semiconductor device according to claim 14, in, The first gate contact plug contacts the first upper gate layer, extends downward and penetrates the gate layer disposed at a height lower than the height of the first upper gate layer, and Wherein, at the height between the lower gate layer and the upper gate layer that are adjacent to each other in the vertical direction among the plurality of gate layers, the side surface of the first gate contact plug has a downwardly curved portion.

16. The semiconductor device according to claim 15, in, The first gate contact plug further includes a gate contact portion extending in the horizontal direction and contacting the first upper gate layer, and The thickness of the gate contact portion is greater than the thickness of each gate layer in the first region.

17. The semiconductor device of claim 16, further comprising: A buffer insulating pattern is disposed below the gate contact portion. The buffer insulation pattern is disposed on the side surface of the first gate contact plug disposed below the gate contact portion, and is disposed at the same height as the gate layer disposed below the gate contact portion.

18. The semiconductor device of claim 15, further comprising: The peripheral contact plugs are spaced apart from the plurality of gate layers. Wherein, at the height between the lower gate layer and the upper gate layer that are adjacent to each other along the vertical direction among the plurality of gate layers, the side surface of the peripheral contact plug includes a downwardly curved portion. Wherein, at a height higher than the height of the highest gate layer, the first side of the side surface of the peripheral contact plug located in the first direction includes an upper curved portion, and Wherein, the number of the plurality of upper bends on the side surface of each of the first gate contact plug and the second gate contact plug, which are located on the first side in the first direction, is greater than the number of upper bends on the side surface of the peripheral contact plug, which are located on the first side in the first direction.

19. A data storage system, comprising: main base plate; Semiconductor devices on the main substrate; as well as The controller is electrically connected to the semiconductor device on the main substrate. The semiconductor device includes: Pattern structure, A stacked structure includes multiple gate layers that are stacked vertically and spaced apart from each other in a first region of the patterned structure, and extend into a second region of the patterned structure. The memory has a vertical structure that penetrates the stacked structure in the first region, and Multiple gate contact plugs are electrically connected to the multiple gate layers in the second region. The stacked structure includes: a lower stacked structure including a lower gate layer; and an upper stacked structure including an upper gate layer on the lower stacked structure. Each of the plurality of gate contact plugs includes a conductive gap filling pattern and a conductive liner covering the side and bottom surfaces of the conductive gap filling pattern. The plurality of gate contact plugs includes a first gate contact plug electrically connected to a first upper gate layer in the upper gate layer, and a second gate contact plug electrically connected to a first lower gate layer in the lower gate layer. Wherein, at a height higher than the height of the highest gate layer among the plurality of gate layers, the first side of the side surface of each of the first gate contact plug and the second gate contact plug, positioned in a first direction, includes a plurality of upwardly curved portions.

20. The semiconductor device of claim 19, further comprising: The peripheral contact plugs are spaced apart from the plurality of gate layers. The first gate contact plug contacts the first upper gate layer, extends downward, and penetrates the gate layer disposed at a height lower than that of the first upper gate layer. Wherein, at the height between the lower gate layer and the upper gate layer that are adjacent to each other in the vertical direction among the plurality of gate layers, the side surface of the first gate contact plug has a downwardly curved portion. Wherein, at the height between the lower gate layer and the upper gate layer that are adjacent to each other along the vertical direction among the plurality of gate layers, the side surface of the peripheral contact plug includes a downwardly curved portion. Wherein, at a height higher than the height of the highest gate layer, the first side of the side surface of the peripheral contact plug in the first direction includes an upper curved portion, and Wherein, the number of the plurality of upper bends on the side surface of each of the first gate contact plug and the second gate contact plug, which are located on the first side in the first direction, is greater than the number of upper bends on the side surface of the peripheral contact plug, which are located on the first side in the first direction.

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