image sensor

Abstract

An image sensor includes a first substrate including a focus pixel region and a pixel region around the focus pixel region, each of the focus pixel region and the pixel region including at least one photoelectric conversion region; a color filter provided on the first surface of the first substrate and on the focus pixel region and the pixel region, respectively; and a microlens provided on the color filter, respectively. The microlens includes an autofocus lens on the focus pixel region, a first microlens adjacent to the autofocus lens, and a standard microlens spaced apart from the autofocus lens.

Description

Technical Field

[0001] This disclosure relates to image sensors, and more particularly, to microlenses of image sensors. Background Technology

[0002] An image sensor is a device that converts optical images into electrical signals. Image sensors are divided into two types: charge-coupled device (CCD) and complementary metal-oxide-semiconductor (CMOS). CMOS image sensors are abbreviated as CIS. A CIS consists of multiple pixels arranged in a two-dimensional pattern. Each pixel area includes a photodiode used to convert incident light into an electrical signal. Summary of the Invention

[0003] One or more exemplary embodiments of this disclosure provide an image sensor capable of outputting images with improved image quality.

[0004] According to an aspect of an example embodiment, an image sensor may include: a first substrate including a focused pixel region and a pixel region surrounding the focused pixel region, each of the focused pixel region and the pixel region including at least one photoelectric conversion region; a color filter provided on the focused pixel region and the pixel region, respectively, and provided on a first surface of the first substrate; and microlenses provided on the color filter, respectively. The microlenses may include an autofocusing lens on the focused pixel region, a first microlens adjacent to the autofocusing lens, and a standard microlens spaced apart from the autofocusing lens. The autofocusing lens may have a first height, the first microlens may have a second height, and the standard microlens may have a third height, the difference between the second height and the third height being less than the difference between the first height and the third height.

[0005] According to an aspect of an example embodiment, an image sensor may include: a substrate including a focused pixel region and a pixel region surrounding the focused pixel region, each of the focused pixel region and the pixel region including at least one photoelectric conversion region; a color filter provided on the focused pixel region and the pixel region, respectively; and microlenses provided on the color filter, respectively. The microlenses may include an autofocusing lens on the focused pixel region, a first microlens adjacent to a first edge of the autofocusing lens, a second microlens adjacent to a second edge of the autofocusing lens, and a standard microlens spaced apart from the autofocusing lens. The autofocusing lens may have a first height, the first microlens may have a second height, the second microlens may have a third height, and the standard microlens may have a fourth height, wherein the second height may be greater than the fourth height and less than the first height, and the third height may be less than the fourth height.

[0006] According to an aspect of an example embodiment, an image sensor may include a circuit chip and an image sensor chip stacked on the circuit chip. The image sensor chip may include: a first substrate having a first surface and a second surface opposite to each other, and including photoelectric conversion regions provided therein; an isolation pattern provided in the first substrate and between the photoelectric conversion regions; an insulating layer covering the first surface; color filters on the insulating layer; a fence pattern between the color filters; microlenses provided on the color filters respectively; a device isolation pattern provided adjacent to the second surface to define an active region; a gate pattern on the second surface; and a first interconnect layer on the second surface. The circuit chip may include a second substrate on which integrated circuits are provided and a second interconnect layer on the second substrate. The first interconnect layer and the second interconnect layer may be provided facing each other and electrically connected to each other. The microlenses may include an autofocusing lens on a focusing pixel region, a first microlens adjacent to the autofocusing lens, and a standard microlens spaced apart from the autofocusing lens. The autofocusing lens may have a first height, the first microlens may have a second height, and the standard microlens may have a third height, the difference between the second height and the third height being less than the difference between the first height and the third height. Attached Figure Description

[0007] The above and / or other aspects will become more apparent from the description of certain exemplary embodiments with reference to the accompanying drawings, in which:

[0008] Figure 1 This is a circuit diagram illustrating the pixels of an image sensor according to an example embodiment;

[0009] Figure 2 This is a plan view illustrating an image sensor according to an example embodiment;

[0010] Figure 3 It is along Figure 2 A cross-sectional view taken from line I-I';

[0011] Figure 4 It is along Figure 2 The line I-I' is cut to show a cross-sectional view of an image sensor according to an example embodiment;

[0012] Figure 5 This illustrates a portion of a microlens according to an example embodiment (e.g., Figure 2 A partial plan view of M);

[0013] Figure 6A It is along Figure 5 A cross-sectional view taken from line I-I';

[0014] Figure 6B It is along Figure 5A cross-sectional view taken from line II-II';

[0015] Figure 7 It is along Figure 5 The line I-I' is cut off to show a cross-sectional view of the microlens according to an example embodiment;

[0016] Figure 8 This illustrates a portion of a microlens according to an example embodiment (e.g., Figure 2 A partial plan view of M);

[0017] Figure 9 This illustrates a portion of a microlens according to an example embodiment (e.g., Figure 2 A partial plan view of M);

[0018] Figure 10 It is along Figure 9 A cross-sectional view taken from line I-I';

[0019] Figure 11 It is shown Figure 5 A planar view of the microlens;

[0020] Figure 12A It is along Figure 11 A cross-sectional view taken from line I-I'; and

[0021] Figure 12B It is along Figure 11 The cross-sectional view taken from line II-II'. Detailed Implementation

[0022] In the following description, exemplary embodiments will be illustrated with reference to the accompanying drawings. Throughout the specification, the same components will be indicated by the same reference numerals.

[0023] As used herein, “about” and “substantially” will be understood by one of ordinary skill in the art and will vary to some extent depending on the context in which they are used. If the use of a term is unclear to one of ordinary skill in the art given the context in which it is used, then “about” and “substantially” will mean within ±10% of the particular term. As used herein, each numerical range will be understood as a shorthand disclosure of each discrete point within that range (thus, for example, a range of 1 to 10 is a description of all possible subranges within that range, such as subranges of 3 to 5, etc.).

[0024] Figure 1 This is a circuit diagram illustrating the pixels of an image sensor according to an example embodiment.

[0025] Reference Figure 1 Each pixel of an image sensor may include a photoelectric conversion area (PD) and a transfer transistor (T). xSource follower transistor S x Reset transistor R x and select transistor A x Transfer transistor T x Source follower transistor S x Reset transistor R x and select transistor A x These can include a transfer gate (TG), a source follower gate (SG), a reset gate (RG), and a select gate (AG).

[0026] The photoelectric conversion region PD can be a photodiode that includes both n-type and p-type impurity regions. The floating diffusion region FD can be used as a transfer transistor T. x The drain electrode. The floating diffusion region FD can be used as the reset transistor R. x The source electrode. The floating diffusion region FD can be electrically connected to the source follower transistor S. x The source follower gate SG. Source follower transistor S x It can be connected to select transistor A x .

[0027] In the following text, reference will be made to Figure 1 Describe the operation of the image sensor. In a light-blocked state (or when no light is incident on the image sensor), the reset transistor R... x and source follower transistor S x The drain electrode is supplied with a power supply voltage V. DD and reset transistor R x When the transistor is turned on, charge can be released from the floating diffusion region FD. Next, the reset transistor R... x The circuit can be turned off. Then, if external light is incident from the outside, electron-hole pairs can be generated in the photoelectric conversion region PD. Holes can move to and accumulate in the p-type impurity region of the photoelectric conversion region PD, and electrons can move to and accumulate in the n-type impurity region of the photoelectric conversion region PD. In this state, if the transfer transistor T... x When conduction occurs, charges such as electrons and holes can transfer to and accumulate in the floating diffusion region FD. The change in the amount of accumulated charge can cause changes in the source follower transistor S. x The change in the gate bias voltage, and thus the source follower transistor S x The change in the source potential. In this case, if transistor A is selected... x When the circuit is turned on, the charge can be read out as a signal Vout through the column lines.

[0028] The interconnect can be electrically connected to at least one of the transfer gate TG, source follower gate SG, reset gate RG, and select gate AG. The interconnect can be configured to transfer the supply voltage V. DD Applied to reset transistor R x Drain or source follower transistor S x The drain electrode. Interconnects may include connections to the select transistor A. x The column lines. Interconnects may include references Figure 3 The first conductive structure 830 is described.

[0029] although Figure 1 The pixel is shown as having a single photoelectric conversion region PD and four transistors (i.e., T). x R x A x and S x However, the implementation is not limited to this. For example, multiple pixels can be provided, and the reset transistor R... x Source follower transistor S x Or select transistor A x It can be shared by adjacent pixels. Therefore, the integration density of the image sensor can be increased.

[0030] Figure 2 This is a plan view illustrating an image sensor according to an example embodiment. Figure 3 It is along Figure 2 The cross-sectional view taken from line I-I'.

[0031] Reference Figure 2 and Figure 3 The image sensor may include a sensor chip 10. The sensor chip 10 may include a first substrate 100, a first interconnect layer 800, an insulating layer 400, a protective layer 470, a color filter CF, a fence pattern 300, and a microlens layer 500 including a raised lens portion 510 (see reference). Figure 6A ).

[0032] When viewed in a plan view, the first substrate 100 may include a pixel array region (APS), an optical black region (OBR), and a pad region (PDR). The pixel array region (APS) may be located in the central region of the first substrate 100. The pixel array region (APS) may include multiple pixel regions (PX). (See reference...) Figure 1 The described pixels can be provided in each pixel region PX of the first substrate 100. For example, constituting Figure 1 The elements of a pixel can be provided on each pixel region PX. The pixel region PX can be formed to generate and output a photoelectric signal from incident light.

[0033] Pixel regions PX can be arranged two-dimensionally to form multiple rows and multiple columns. The multiple rows can be parallel to a first direction D1. The multiple columns can be parallel to a second direction D2. In this specification, the first direction D1 can be parallel to a first surface 100a of the first substrate 100. The second direction D2 can be parallel to the first surface 100a of the first substrate 100, but may not be parallel to the first direction D1. For example, the second direction D2 can be substantially perpendicular to the first direction D1. A third direction D3 can be perpendicular to both the first direction D1 and the second direction D2. For example, the third direction D3 can be substantially perpendicular to the first surface 100a of the first substrate 100.

[0034] A pad region PDR can be provided in the edge region of the first substrate 100 to surround the pixel array region APS. Pads PAD can be provided on the pad region PDR. The pads PAD can be used to output electrical signals generated in the pixel region PX to the outside. Alternatively, the pads PAD can be used to transmit external electrical signals or voltages to the pixel region PX. Because the pad region PDR is located in the edge region of the first substrate 100, the pads PAD can be easily connected to the outside. The optical black region OBR will be described below. In the following text, the pixel array region APS of the image sensor chip 10 will be described in more detail.

[0035] The first substrate 100 may have a first surface 100a and a second surface 100b opposite to each other. The first surface 100a of the first substrate 100 may be a front surface, and the second surface 100b may be a rear surface. Light can be incident on the first substrate 100 through the first surface 100a. The first substrate 100 may be a semiconductor substrate or a silicon-on-insulator (SOI) substrate. The semiconductor substrate may include, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The first substrate 100 may also include a Group 3 element. The Group 3 element may be an impurity of a first conductivity type. In other words, the first substrate 100 may have a first conductivity type (e.g., p-type). As an example, the impurity of the first conductivity type may include aluminum (Al), boron (B), indium (In), and / or gallium (Ga).

[0036] The first substrate 100 may include a plurality of photoelectric conversion regions PD provided therein. The photoelectric conversion regions PD may be located between a first surface 100a and a second surface 100b of the first substrate 100. The photoelectric conversion regions PD may be respectively provided in pixel regions PX of the first substrate 100. The photoelectric conversion regions PD may be... Figure 1 The photoelectric conversion region (PD) is the same.

[0037] The photoelectric conversion region PD may also include a Group 5 element. The Group 5 element can be an impurity of a second conductivity type. In other words, the photoelectric conversion region PD can be an impurity region of a second conductivity type. The second conductivity type (e.g., n-type) can be different from the first conductivity type. Impurities of the second conductivity type can include phosphorus, arsenic, bismuth, and / or antimony. The photoelectric conversion region PD may be adjacent to the first surface 100a of the first substrate 100. The photoelectric conversion region PD may extend from the first surface 100a toward the second surface 100b.

[0038] An isolation pattern 200 may be provided in the first substrate 100 to define a pixel region PX. For example, the isolation pattern 200 may be provided between adjacent pixel regions in the pixel region PX. The isolation pattern 200 may be a pixel isolation pattern. The isolation pattern 200 may be provided in a first trench 201. The first trench 201 may be recessed from the second surface 100b of the first substrate 100 toward the first surface 100a.

[0039] The isolation pattern 200 may be a deep trench isolation layer. In one example embodiment, the isolation pattern 200 may penetrate the first substrate 100. In another example embodiment, the isolation pattern 200 may not penetrate the first substrate 100 and may be spaced apart from the first surface 100a of the first substrate 100. The width of the isolation pattern 200 adjacent to the second surface 100b may be greater than the width of the isolation pattern 200 adjacent to the first surface 100a.

[0040] The isolation pattern 200 may include a first isolation pattern 210 and a second isolation pattern 220. The first isolation pattern 210 may be provided on the inner surface of the first trench 201. The first isolation pattern 210 may be formed of at least one of, for example, a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and / or silicon nitride) and a high-k dielectric material (e.g., hafnium oxide and / or aluminum oxide), or may include at least one of, for example, a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and / or silicon nitride) and a high-k dielectric material (e.g., hafnium oxide and / or aluminum oxide). As another example, the first isolation pattern 210 may include multiple layers, wherein at least two layers are formed of or include materials that are different from each other. The first isolation pattern 210 may have a lower refractive index than the first substrate 100. Therefore, crosstalk between pixel regions PX of the first substrate 100 can be prevented or suppressed.

[0041] A second isolation pattern 220 may be provided within a first isolation pattern 210. The first isolation pattern 210 may be interposed between the second isolation pattern 220 and the first substrate 100. The second isolation pattern 220 may be spaced apart from the first substrate 100 by the first isolation pattern 210. Therefore, during operation of the image sensor, the second isolation pattern 220 may be electrically isolated from the first substrate 100. The second isolation pattern 220 may be formed of at least one of conductive materials (e.g., doped polysilicon), or may include at least one of conductive materials (e.g., doped polysilicon). The second isolation pattern 220 may contain impurities of a first or second conductivity type.

[0042] Color filters CF can be disposed on the first surface 100a of the first substrate 100 and respectively on the pixel region PX. For example, color filters CF can be provided at positions corresponding to the photoelectric conversion region PD. Each color filter CF can be one of a red filter, a blue filter, and a green filter. Color filters CF can be arranged to form a color filter array. For example, color filters CF can be arranged in a two-dimensional Bayer pattern.

[0043] The fence pattern 300 can be disposed on the isolation pattern 200. For example, the fence pattern 300 can overlap the isolation pattern 200 perpendicularly. The fence pattern 300 can be inserted between two adjacent color filters CF to separate the color filters CF from each other. For example, the color filters CF can be physically and optically separated from each other by the fence pattern 300.

[0044] The fence pattern 300 may have a planar shape corresponding to the isolation pattern 200. For example, the fence pattern 300 may have a grid shape. When viewed in a planar view, the fence pattern 300 may be provided to surround each pixel region PX. The fence pattern 300 may surround each color filter CF. The fence pattern 300 may include a first portion and a second portion. The first portion may extend parallel to a first direction D1 and may be spaced apart from each other in a second direction D2. The second portion may extend parallel to the second direction D2 and may be spaced apart from each other in the first direction D1. The second portion may intersect with the first portion.

[0045] The fence pattern 300 may include a first fence pattern 310 and a second fence pattern 320. The first fence pattern 310 may be disposed between the insulating layer 400 and the second fence pattern 320. The first fence pattern 310 may be formed of at least one of conductive materials (e.g., metals and / or metal nitrides), or may include at least one of conductive materials (e.g., metals and / or metal nitrides). For example, the first fence pattern 310 may be formed of titanium and / or titanium nitrides, or may include titanium and / or titanium nitrides.

[0046] The second fence pattern 320 may be disposed on the first fence pattern 310. The second fence pattern 320 may be formed of a material different from the first fence pattern 310, or may include a material different from the first fence pattern 310. The second fence pattern 320 may be formed of an organic material or may include an organic material. The second fence pattern 320 may include a low-refractive-index material and may have insulating properties.

[0047] An insulating layer 400 may be interposed between the first substrate 100 and the color filter CF, and between the isolation pattern 200 and the fence pattern 300. The insulating layer 400 may cover the first surface 100a of the first substrate 100 and the top surface of the isolation pattern 200. The insulating layer 400 may be a back-side insulating layer. The insulating layer 400 may include a bottom anti-reflective coating (hereinafter, BARC) layer. The insulating layer 400 may include multiple layers configured to have different functions from each other.

[0048] In one embodiment, the insulating layer 400 may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer sequentially stacked on a first surface 100a of the first substrate 100. The first insulating layer may cover the first surface 100a of the first substrate 100. The first and second insulating layers may be fixed charge layers. Each fixed charge layer may be formed of a metal oxide layer or a metal fluoride layer. In one embodiment, the metal oxide layer may have an oxygen content lower than its stoichiometric oxygen content, and the metal fluoride layer may have a fluorine content lower than its stoichiometric fluorine content.

[0049] For example, the first insulating layer may be formed of, or comprise a metal oxide or metal fluoride, wherein the metal oxide or metal fluoride contains at least one metallic element from hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y), and the lanthanides. The second insulating layer may be formed of, or comprise at least one of the metal oxides or metal fluorides containing at least one metallic element listed above for the first insulating layer. However, the material used for the second insulating layer may differ from the material used for the first insulating layer. As an example, the first insulating layer may be formed of or comprise aluminum oxide, and the second insulating layer may be formed of or comprise hafnium oxide.

[0050] Each of the first and second insulating layers can have a negative fixed charge and can be configured to cause hole accumulation. Due to the first and second insulating layers, dark current and white spot problems that may occur in the first substrate 100 can be effectively suppressed. The thickness of the second insulating layer can be greater than the thickness of the first insulating layer.

[0051] A third insulating layer may be disposed on the second insulating layer. The third insulating layer may be formed of or comprise a first silicon-containing material. The first silicon-containing material may include, for example, tetraethyl orthosilicate (TEOS) or silicon oxide. The third insulating layer may have good gap-filling properties. The third insulating layer may be formed by, for example, a plasma-enhanced chemical vapor deposition (PE-CVD) process, but this disclosure is not limited to this example. The thickness of the third insulating layer may be greater than the thickness of the first insulating layer and may be greater than the thickness of the second insulating layer.

[0052] A fourth insulating layer may be disposed on the third insulating layer. The fourth insulating layer may be formed of a material different from, or comprise a material different from, the third insulating layer. The fourth insulating layer may include a second silicon-containing material different from the first silicon-containing material. As an example, the fourth insulating layer may be formed of or comprise a silicon nitride. The thickness of the fourth insulating layer may be greater than the thickness of the third insulating layer.

[0053] A fifth insulating layer may be disposed between the fourth insulating layer and the first fence pattern 310, and between the fourth insulating layer and the color filter CF. The fifth insulating layer may be in physical contact with the bottom surface of the first fence pattern 310. The fifth insulating layer may be an adhesive layer or a cover layer. The fifth insulating layer may be formed of at least one of a high-k dielectric material and a metal oxide material, or may include at least one of a high-k dielectric material and a metal oxide material. The fifth insulating layer may be formed of the same material as the second insulating layer, or may include the same material as the second insulating layer. For example, the fifth insulating layer may be formed of or include hafnium oxide. The thickness of the fifth insulating layer may be greater than the thickness of the first insulating layer and the thickness of the second insulating layer, and may be less than the thickness of the third insulating layer and the thickness of the fourth insulating layer.

[0054] The number of layers constituting the insulating layer 400 can be varied, and therefore may differ from the embodiments described above. For example, at least one of the first to fifth insulating layers may be omitted.

[0055] The protective layer 470 may cover the insulating layer 400 and the fence pattern 300. The protective layer 470 may be formed of, or include, at least one high-k dielectric material, and may have insulating properties. For example, the protective layer 470 may be formed of, or include, aluminum oxide or hafnium oxide. In one embodiment, the protective layer 470 may be formed of, or include, aluminum oxide, but this disclosure is not limited to this example. The protective layer 470 may protect the photoelectric conversion region PD of the first substrate 100 from harmful external environmental factors (e.g., moisture).

[0056] Color filters CF can be provided on the protective layer 470. Color filters CF can be spaced apart from each other by the fence pattern 300. Color filters CF may not cover the top surface of the fence pattern 300.

[0057] In one embodiment, refer to Figure 3 Each color filter CF can have an upwardly convex top surface. For example, the level of the central portion of the top surface of the color filter CF can be higher than the level of the edge portion of the top surface. However, the cross-sectional shape of the color filter CF is not limited to this.

[0058] The microlens layer 500 can be provided on the first surface 100a of the first substrate 100. For example, the microlens layer 500 can be provided on the color filter CF and the fence pattern 300. The protective layer 470 can be interposed between the second fence pattern 320 and the microlens layer 500.

[0059] The microlens layer 500 may include a plurality of protruding lens portions 510. The lens portions 510 may be provided at positions corresponding to the photoelectric conversion region PD of the first substrate 100. For example, the lens portions 510 may be provided on and correspond to the color filter CF. When viewed in a plan view, the lens portions 510 may be arranged in a first direction D1 and a second direction D2 to form a two-dimensional array. Each lens portion 510 may protrude in a direction away from the first surface 100a of the first substrate 100. Each lens portion 510 may have a hemispherical cross-section. The lens portions 510 may focus incident light.

[0060] The microlens layer 500 may be transparent, thus allowing incident light to pass through it. The microlens layer 500 may be formed of, or comprise an organic material (e.g., a polymer). For example, the microlens layer 500 may be formed of, or comprise at least one of a photoresist material and a thermosetting resin.

[0061] A lens coating layer 530 may be provided on the microlens layer 500. The lens coating layer 530 may be transparent. The lens coating layer 530 may conformally cover the top surface of the microlens layer 500. The lens coating layer 530 may protect the microlens layer 500.

[0062] The first substrate 100 may include an impurity region 111 provided adjacent to the second surface 100b. The impurity region 111 may be disposed in each pixel region PX. The impurity region 111 may have a bottom surface (the surface facing away from the second surface 100b) perpendicularly spaced from the photoelectric conversion region PD. The impurity region 111 may be doped to have a second conductivity type (e.g., n-type). The impurity region 111 may be an active region. Here, the active region may be a region for transistor operation and may include a reference... Figure 1 The described floating diffusion region FD and / or the source / drain region of the transistor. Impurity region 111 can be used in transistors that may include references. Figure 1 The described transfer transistor T x Source follower transistor S x Reset transistor R x and / or select transistor A x .

[0063] Device isolation pattern 240 may be provided adjacent to a second surface 100b of the first substrate 100. Device isolation pattern 240 may define an active region. Specifically, in each pixel region PX, device isolation pattern 240 may define an impurity region 111. Impurity regions 111 may be separated from each other by device isolation pattern 240. Device isolation pattern 240 may be provided in a second trench recessed from the second surface 100b of the first substrate 100. Device isolation pattern 240 may be a shallow trench isolation (STI) layer. The height of device isolation pattern 240 may be less than the height of isolation pattern 200. A portion of device isolation pattern 240 may be connected to a side surface of first isolation pattern 210. Device isolation pattern 240 may be formed of, for example, at least one of silicon oxide, silicon nitride, and silicon oxide nitride, or may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxide nitride.

[0064] Gate pattern 700 (reference) Figure 4 The gate pattern 700 can be provided on the second surface 100b of the first substrate 100. The gate pattern 700 can be used as a prior reference. Figure 1 The described transfer transistor T x Source follower transistor S x Reset transistor R x and / or select transistor A x The gate electrode. For example, gate pattern 700 may include a transfer gate TG, a source follower gate SG, a reset gate RG, and / or a select gate AG. Although Figure 3An example of a gate pattern 700 disposed on each pixel region PX is shown, but the implementation is not limited to this example. For example, multiple gate patterns 700 may be disposed on each pixel region PX. For simplicity, the following description will refer to an example of providing a gate pattern 700.

[0065] The gate pattern 700 may have a buried gate structure. For example, the gate pattern 700 may include a first portion 710 and a second portion 720. The first portion 710 of the gate pattern 700 may be disposed on a second surface 100b of the first substrate 100. The second portion 720 of the gate pattern 700 may be buried in the first substrate 100. The second portion 720 of the gate pattern 700 may be connected to the first portion 710. Unlike that shown in the figures, the gate pattern 700 may have a planar gate structure. In this case, the gate pattern 700 may not include the second portion 720. The gate pattern 700 may be formed of at least one of a metallic material, a metal silicide material, polysilicon, and combinations thereof, or may include at least one of a metallic material, a metal silicide material, polysilicon, and combinations thereof. Here, the polysilicon may include doped polysilicon.

[0066] A gate insulating pattern 740 may be interposed between the gate pattern 700 and the first substrate 100. The gate insulating pattern 740 may be formed of at least one of, for example, a silicon-based insulating material (e.g., silicon oxide, silicon nitride, and / or silicon nitride) and a high-k dielectric material (e.g., hafnium oxide and / or aluminum oxide), or may include at least one of, for example, a silicon-based insulating material (e.g., silicon oxide, silicon nitride, and / or silicon nitride) and a high-k dielectric material (e.g., hafnium oxide and / or aluminum oxide).

[0067] A first interconnect layer 800 may be disposed on a second surface 100b of a first substrate 100. The first interconnect layer 800 may include a first interlayer insulating layer 810, a second interlayer insulating layer 820, and a first conductive structure 830. The first interlayer insulating layer 810 may cover the second surface 100b of the first substrate 100 and the gate pattern 700. The second interlayer insulating layer 820 may be stacked on top of the first interlayer insulating layer 810. The first interlayer insulating layer 810 and the second interlayer insulating layer 820 may be formed of at least one silicon-based insulating material (e.g., silicon oxide, silicon nitride, and / or silicon nitride), or may include at least one silicon-based insulating material (e.g., silicon oxide, silicon nitride, and / or silicon nitride).

[0068] A first conductive structure 830 may be provided in interlayer insulating layers 810 and 820. The first conductive structure 830 may include a contact plug portion, a wire portion, and a through portion. The contact plug portion may be provided in the first interlayer insulating layer 810 and / or the second interlayer insulating layer 820 and may be electrically connected to one of the impurity region 111 and the gate pattern 700. The wire portion of the first conductive structure 830 may be interposed between two adjacent interlayer insulating layers 810 and 820. The wire portion may be connected to the contact plug portion. The through portion of the first conductive structure 830 may be provided to penetrate at least one of the second interlayer insulating layers 820 and may be connected to the wire portion. The first conductive structure 830 may be used to transmit photoelectric signals output from the photoelectric conversion region PD.

[0069] The circuit chip 20 of the image sensor and the optical black region (OBR) and pad region (PDR) of the first substrate 100 will be described in more detail below. (Return to Reference) Figure 2 and Figure 3 An optical black region (OBR) of the first substrate 100 can be interposed between the pixel array region (APS) and the pad region (PDR). The OBR may include a first reference pixel region (RPX1) and a second reference pixel region (RPX2). The first reference pixel region (RPX1) may be disposed between the second reference pixel region (RPX2) and the pixel array region (APS). In the OBR, a photoelectric conversion region (PD) may be provided in the first reference pixel region (RPX1). The photoelectric conversion region (PD) of the first reference pixel region (RPX1) may have the same planar area and volume as the photoelectric conversion region (PD) of the pixel region (PX). The photoelectric conversion region (PD) may not be provided in the second reference pixel region (RPX2). An impurity region 111, a gate pattern 700, and a device isolation pattern 240 may be disposed in each of the first reference pixel region (RPX1) and the second reference pixel region (RPX2).

[0070] An insulating layer 400 extends from the pixel array region APS through the optical black region OBR to the pad region PDR. A light-shielding layer 950 can be provided on the optical black region OBR. The light-shielding layer 950 can be disposed on the top surface of the insulating layer 400. Due to the light-shielding layer 950, light can be prevented from incident on the photoelectric conversion region PD of the optical black region OBR. Pixels in the first reference pixel region RPX1 and the second reference pixel region RPX2 of the optical black region OBR can be configured to output noise signals instead of photoelectric signals. The noise signals can be generated by electrons, which are generated by heat or dark current. The light-shielding layer 950 may not be provided in the pixel array region APS, so light can be incident on the photoelectric conversion region PD in the pixel array region APS. Noise signals can be removed from the photoelectric signals output from the pixel regions PX. The light-shielding layer 950 can be formed of at least one of a metallic material (e.g., tungsten, copper, aluminum, or alloys thereof), or include at least one of a metallic material (e.g., tungsten, copper, aluminum, or alloys thereof).

[0071] In the optically black region (OBR) of the first substrate 100, a first conductive pattern 911 may be disposed between the insulating layer 400 and the light-shielding layer 950. The first conductive pattern 911 may serve as a barrier layer or an adhesive layer. The first conductive pattern 911 may be formed of at least one of a metallic material and a metal nitride, or may include at least one of a metallic material and a metal nitride. For example, the first conductive pattern 911 may be formed of at least one of a metallic material (e.g., copper, tungsten, aluminum, titanium, tantalum, or alloys thereof), or may include at least one of a metallic material (e.g., copper, tungsten, aluminum, titanium, tantalum, or alloys thereof). The first conductive pattern 911 may not extend into the region on the pixel array region (APS) of the first substrate 100.

[0072] In the optical black region (OBR) of the first substrate 100, a contact plug 960 may be provided on the first surface 100a of the first substrate 100. The contact plug 960 may be disposed on the outermost isolation pattern in the isolation pattern 200 within the optical black region (OBR). A contact trench penetrating the insulating layer 400 may be defined on the first surface 100a of the first substrate 100, and the contact plug 960 may be provided within the contact trench.

[0073] The contact plug 960 may be formed of a material different from, or comprise a material different from, the light-shielding layer 950. For example, the contact plug 960 may be formed of, or comprise at least one of a metallic material (e.g., aluminum). A first conductive pattern 911 may extend into the regions between the contact plug 960 and the insulating layer 400, and between the contact plug 960 and the isolation pattern 200. The contact plug 960 may be electrically connected to the second isolation pattern 220 via the first conductive pattern 911. A negative bias voltage may be applied to the second isolation pattern 220 via the contact plug 960.

[0074] A protective insulating layer 471 may be provided on the optically black region OBR. The protective insulating layer 471 may be disposed on the top surface of the light-shielding layer 950 and the top surface of the contact plug 960. The protective insulating layer 471 may comprise the same material as the protective layer 470 and may be attached to the protective layer 470. The protective insulating layer 471 and the protective layer 470 may be provided as a single object. Alternatively, the protective insulating layer 471 may be formed by a different process than that used for the protective layer 470 and may be spaced apart from the protective layer 470. The protective insulating layer 471 may be formed of at least one of high-k dielectric materials (e.g., aluminum oxide and / or hafnium oxide), or may include at least one of high-k dielectric materials (e.g., aluminum oxide and / or hafnium oxide).

[0075] A filter layer 550 may also be disposed on the first surface 100a in the optical black region (OBR). The filter layer 550 may cover the top surface of the protective insulating layer 471. The filter layer 550 may block light not filtered by the color filter CF. For example, the filter layer 550 may be configured to block infrared light. The filter layer 550 may include a blue filter, but the implementation is not limited to this example.

[0076] An organic layer 501 may be provided on the top surface of the filter layer 550. The organic layer 501 may be transparent. The top surface of the organic layer 501 may be substantially flat. The organic layer 501 may be formed of, for example, a polymer, or may include, for example, a polymer. The organic layer 501 may have insulating properties. In one embodiment, unlike that shown in the figures, the organic layer 501 may be attached to the microlens layer 500. The organic layer 501 may be formed of, or may include, the same material as the microlens layer 500.

[0077] Coating layer 531 may be provided on organic layer 501. Coating layer 531 may conformally cover the top surface of organic layer 501. Coating layer 531 may include an insulating material and may be transparent. Coating layer 531 may be formed of the same material as lens coating layer 530, or may include the same material as lens coating layer 530.

[0078] The image sensor may also include a circuit chip 20. The circuit chip 20 may be stacked on the sensor chip 10. The circuit chip 20 may include a second interconnect layer 1800 and a second substrate 1000. The second interconnect layer 1800 may be interposed between the first interconnect layer 1800 and the second substrate 1000. An integrated circuit 1700 may be disposed on the top surface of the second substrate 1000 or within the second substrate 1000. The integrated circuit 1700 may include logic circuits, memory circuits, or a combination thereof. The integrated circuit 1700 may include, for example, transistors.

[0079] The second interconnect layer 1800 may include a third interlayer insulating layer 1820 and a second conductive structure 1830. The second conductive structure 1830 may be provided between or within the third interlayer insulating layer 1820. The second conductive structure 1830 may be electrically connected to the integrated circuit 1700. The second interconnect layer 1800 may also include a via pattern, which in one embodiment may be connected to the second conductive structure 1830 within the third interlayer insulating layer 1820.

[0080] A pad (PAD) may be provided on a pad region (PDR) of the first substrate 100. The pad (PAD) may be adjacent to a first surface 100a of the first substrate 100. The pad (PAD) may be buried within the first substrate 100. For example, a pad trench 990 may be defined on the first surface 100a of the pad region (PDR) of the first substrate 100, and the pad (PAD) may be provided within the pad trench 990. The pad (PAD) may be formed of at least one of a metallic material (e.g., aluminum, copper, tungsten, titanium, tantalum, or alloys thereof), or may include at least one of a metallic material (e.g., aluminum, copper, tungsten, titanium, tantalum, or alloys thereof). In the process of mounting an image sensor, bonding wires may be formed on the pad (PAD) and may be connected to the pad (PAD). The pad (PAD) may be electrically connected to an external device via the bonding wires.

[0081] A first through-hole 901 may be defined in a region adjacent to a first side of the pad PAD. The first through-hole 901 may be provided between the pad PAD and the contact plug 960. The first through-hole 901 may penetrate the insulating layer 400, the first substrate 100, and the first interconnect layer 800. In one embodiment, the first through-hole 901 may also penetrate at least a portion of the second interconnect layer 1800. The first through-hole 901 may have a first bottom surface and a second bottom surface. The first bottom surface of the first through-hole 901 may be formed to expose a first conductive structure 830. The second bottom surface of the first through-hole 901 may be disposed at a lower level than the first bottom surface. The second bottom surface of the first through-hole 901 may be formed to expose a second conductive structure 1830.

[0082] The first conductive pattern 911 can extend from the optical black region (OBR) to the area on the pad region (PDR). The first conductive pattern 911 can cover the inner surface of the first through-hole 901. The first conductive pattern 911 in the first through-hole 901 can contact the top surface of the first conductive structure 830. Therefore, the first conductive structure 830 can be electrically connected to the second isolation pattern 220 through the first conductive pattern 911.

[0083] The first conductive pattern 911 in the first through-hole 901 can also be connected to the top surface of the second conductive structure 1830. The second conductive structure 1830 can be electrically connected to the first conductive structure 830 and the second isolation pattern 220 through the first conductive pattern 911.

[0084] A first gap-filling pattern 921 may be provided in the first through-hole 901 to fill the first through-hole 901. The first gap-filling pattern 921 may be formed of or include at least one of low-refractive materials and may have insulating properties. The first gap-filling pattern 921 may be formed of or include the same material as the first fence pattern 310. The top surface of the first gap-filling pattern 921 may have a recessed portion. For example, the central portion of the top surface of the first gap-filling pattern 921 may be lower than its edge portions.

[0085] The first overlay pattern 931 may be disposed on the top surface of the first gap-filling pattern 921 to fill the recessed portion. The first overlay pattern 931 may have a substantially flat top surface. The first overlay pattern 931 may be formed of at least one of an insulating polymer (e.g., a photoresist material), or may include at least one of an insulating polymer (e.g., a photoresist material).

[0086] The second through-hole 902 can be defined in a region adjacent to the second side of the pad PAD. The second through-hole 902 can be provided to penetrate the insulating layer 400, the first substrate 100, and the first interconnect layer 800. In one embodiment, the second through-hole 902 can penetrate a portion of the second interconnect layer 1800 and can expose the second conductive structure 1830.

[0087] A second conductive pattern 912 may be provided on the pad area PDR. The second conductive pattern 912 may be provided in the second through-hole 902 to conformally cover the side and bottom surfaces of the second through-hole 902. The second conductive pattern 912 may be electrically connected to the second conductive structure 1830.

[0088] The second conductive pattern 912 can be inserted between the pad PAD and the pad trench 990 to cover the bottom and side surfaces of the pad PAD. During operation of the image sensor, the integrated circuit 1700 of the circuit chip 20 can send and receive electrical signals through the second conductive structure 1830, the second conductive pattern 912, and the pad PAD.

[0089] A second gap-filling pattern 922 may be provided in the second through-hole 902 to fill the second through-hole 902. The second gap-filling pattern 922 may be formed of or include at least one of low-refractive materials and may have insulating properties. For example, the second gap-filling pattern 922 may be formed of or include the same material as the first fence pattern 310. The top surface of the second gap-filling pattern 922 may have a recessed portion.

[0090] The second overlay pattern 932 may be disposed on the top surface of the second gap-filling pattern 922 to fill the recessed portion. The second overlay pattern 932 may have a substantially flat top surface. The second overlay pattern 932 may be formed of at least one of an insulating polymer (e.g., a photoresist material), or may include at least one of an insulating polymer (e.g., a photoresist material).

[0091] A protective insulating layer 471 can extend from the optical black region (OBR) to the area on the pad region (PDR). The protective insulating layer 471 can be provided on the top surface of the insulating layer 400 and can extend into the first through-hole 901 and the second through-hole 902. In the first through-hole 901, the protective insulating layer 471 can be interposed between the first conductive pattern 911 and the first gap fill pattern 921. In the second through-hole 902, the protective insulating layer 471 can be interposed between the second conductive pattern 912 and the second gap fill pattern 922. The protective insulating layer 471 can be provided to expose the pad (PAD).

[0092] Figure 4 It is along Figure 2 Line I-I' is cut to show a cross-sectional view of an image sensor according to an example embodiment. For brevity, previous references... Figures 1 to 3 The described elements may be identified by the same reference numerals without repeating their overlapping descriptions.

[0093] Reference Figure 2 and Figure 4The image sensor may include a sensor chip 10 and a circuit chip 20. The sensor chip 10 may include a first connection pad 850. The first connection pad 850 may be exposed on the bottom surface of the sensor chip 10. The first connection pad 850 may be disposed in the lowermost second interlayer insulating layer of a second interlayer insulating layer 820. The first connection pad 850 may be electrically connected to a first conductive structure 830. The first connection pad 850 may be formed of at least one of conductive materials (e.g., metals), or may include at least one of conductive materials (e.g., metals). For example, the first connection pad 850 may be formed of or include copper. Alternatively, the first connection pad 850 may be formed of at least one of aluminum, tungsten, titanium, and alloys thereof, or may include at least one of aluminum, tungsten, titanium, and alloys thereof.

[0094] The circuit chip 20 may include a second connection pad 1850. The second connection pad 1850 may be exposed on the top surface of the circuit chip 20. The second connection pad 1850 may be disposed in the uppermost third interlayer insulating layer of the third interlayer insulating layer 1820. The second connection pad 1850 may be electrically connected to the integrated circuit 1700. The second connection pad 1850 may be formed of or include at least one of conductive materials (e.g., metals). For example, the second connection pad 1850 may be formed of or include copper. Alternatively, the second connection pad 1850 may be formed of or include at least one of aluminum, tungsten, titanium, and alloys thereof.

[0095] The circuit chip 20 can be directly bonded to the sensor chip 10. For example, the first connection pad 850 and the second connection pad 1850 can be aligned perpendicularly to each other and can be in contact with each other. Therefore, the second connection pad 1850 can be directly bonded to the first connection pad 850. As a result, the integrated circuit 1700 of the circuit chip 20 can be electrically connected to the transistors or pads of the sensor chip 10 through the first connection pad 850 and the second connection pad 1850.

[0096] In one example embodiment, the second interlayer insulating layer 820 can be directly bonded to the third interlayer insulating layer 1820. In this case, chemical bonds can be formed between the second interlayer insulating layer 820 and the third interlayer insulating layer 1820.

[0097] The first through-hole 901 may include a first through-hole portion 91, a second through-hole portion 92, and a third through-hole portion 93. The first through-hole portion 91 may penetrate the insulating layer 400, the first substrate 100, and the first interconnect layer 800, and may have a first bottom surface. The second through-hole portion 92 may penetrate the insulating layer 400, the first substrate 100, and the first interconnect layer 800, and may extend into the upper portion of the second interconnect layer 1800. The second through-hole portion 92 may have a second bottom surface formed to expose the top surface of the second conductive structure 1830. The side surfaces of the second through-hole portion 92 may be spaced apart from the side surfaces of the first through-hole portion 91. The third through-hole portion 93 may be provided between the upper portions of the first through-hole portion 91 and the upper portions of the second through-hole portion 92, and may be connected to the upper portions of the first and second through-hole portions 91 and 92. A first conductive pattern 911, a protective insulating layer 471, and a first gap-filling pattern 921 may be provided within the first through-hole 901. The first conductive pattern 911 can cover the inner surfaces of the first through hole portion 91, the second through hole portion 92, and the third through hole portion 93.

[0098] Figure 5 This illustrates a portion of a microlens according to an example embodiment (e.g., Figure 2 A plan view of part M). Figure 6A It is along Figure 5 The cross-sectional view taken from line I-I'. Figure 6B It is along Figure 5 The cross-sectional view taken from line II-II'. For simplicity, refer to the previous... Figures 1 to 3 The described elements may be identified by the same reference numerals without repeating their overlapping descriptions.

[0099] Reference Figure 5 , Figure 6A and Figure 6B The image sensor may include a first substrate 100. The image sensor may also include an insulating layer 400, a color filter CF, a fencing pattern 300, and a microlens layer 500 provided on a first surface 100a of the first substrate 100. To reduce complexity in the figures, the elements below the first substrate 100 are... Figure 6A , Figure 6B , Figures 7 to 11 , Figure 12A and Figure 12B The characters are omitted, and they can be configured to have the same meaning as the reference. Figure 3 and Figure 4 The components in the described embodiments have substantially the same features and are included. Figure 6A , Figure 6B , Figures 7 to 11 , Figure 12A and Figure 12BIn any of the implementation methods. Furthermore, refer to Figure 3 and Figure 4 The described protective layer 470 can be applied to Figure 6A , Figure 6B , Figures 7 to 11 , Figure 12A and Figure 12B Any of the implementation methods.

[0100] The pixel array region APS of the first substrate 100 may include a focused pixel region RP and a pixel region PX. When viewed in a plan view, the pixel region PX can be arranged in two dimensions around the focused pixel region RP.

[0101] In one example implementation, the focused pixel region RP may include a pair of photoelectric conversion regions PD and an isolation pattern 200 therebetween. The focused pixel region RP may have a substantially the same area as the sum of a pair of adjacent pixel regions PX.

[0102] The focusing pixel region RP can correct the focus of the image emitted from the pixel region PX, but may not output an image of the object. Specifically, the photoelectric conversion regions PD in the focusing pixel region RP can be spaced apart from each other, so the light incident on the photoelectric conversion regions PD in the focusing pixel region RP can have different phases. The focus of the acquired image can be corrected based on the phase difference between the images obtained from the photoelectric conversion regions PD.

[0103] More specifically, the focus of the image output from pixel region PX can be corrected by comparing the photoelectric signal output from the focusing pixel region RP with the photoelectric signal output from pixel region PX. Therefore, the image sensor can obtain 3D depth information about the object.

[0104] In one embodiment, although not shown, the focused pixel region RP can be configured to include three or more photoelectric conversion regions PD. In other words, the number of photoelectric conversion regions PD disposed in the focused pixel region RP can be varied.

[0105] As an example, the color filter CF on the focused pixel region RP may include a white filter or a transparent filter. As another example, similar to the color filter CF on the pixel region PX, the color filter CF on the focused pixel region RP may include a red filter, a green filter, or a blue filter.

[0106] Microlenses can be individually disposed on the color filter CF. Each microlens may include a microlens layer 500 and a lens coating layer 530. An autofocusing lens AFL may be provided on the focusing pixel region RP.

[0107] Return to reference Figure 5The microlenses of the first lens group GR1 can be arranged in two dimensions around the autofocus lens AFL. In one example embodiment, the first lens group GR1 may include 10 microlenses directly surrounding the autofocus lens AFL.

[0108] An autofocusing lens AFL may include a first edge ED1 and a second edge ED2 shorter than the first edge ED1. The second edge ED2 may be parallel to a second direction D2. The autofocusing lens AFL may also include a third edge ED3 opposite to the first edge ED1 and a fourth edge ED4 opposite to the second edge ED2.

[0109] For example, the first lens group GR1 may include a first microlens ML1 adjacent to the first edge ED1, a second microlens ML2 adjacent to the second edge ED2, a third microlens ML3 adjacent to the third edge ED3, and a fourth microlens ML4 adjacent to the fourth edge ED4. The first lens group GR1 may also include a fifth microlens ML5 between the first microlens ML1 and the second microlens ML2.

[0110] When viewed in a planar diagram, the first microlens ML1, the second microlens ML2, and the fifth microlens ML5 in between can have different areas. For example, the area of ​​the fifth microlens ML5 can be larger than the area of ​​the second microlens ML2, and the area of ​​the first microlens ML1 can be larger than the area of ​​the fifth microlens ML5.

[0111] The microlenses (e.g., standard microlenses (SMLs)) of the second lens group GR2 can be arranged two-dimensionally around the first lens group GR1. In one example embodiment, the second lens group GR2 may include 18 standard microlenses SMLs directly surrounding the first lens group GR1. The standard microlenses SMLs may be microlenses disposed on the pixel region PX and having standard dimensions.

[0112] The area of ​​the standard microlens SML may differ from the area of ​​each of the first microlens ML1, the second microlens ML2, and the fifth microlens ML5 described above. In one embodiment, the area of ​​the standard microlens SML may be defined as a reference area of ​​the microlens. For example, the area of ​​the first microlens ML1 may be larger than the area of ​​the standard microlens SML (i.e., the reference area). The areas of each of the second microlens ML2 and the fifth microlens ML5 may be smaller than the area of ​​the standard microlens SML (i.e., the reference area).

[0113] Return to reference Figure 6A and Figure 6BA microlens may have a valley TR defined between the microlens and another adjacent microlens. Furthermore, a microlens may have a peak CR defined at the highest level of its top surface. The horizontal difference between the valley TR and the peak CR of a microlens can be defined as the height of the microlens.

[0114] According to one example implementation, the microlens can have different heights. If the height of the microlens is increased, the amount of light received by the microlens can be increased; if the height of the microlens is decreased, the amount of light received by the microlens can be decreased.

[0115] The height of a microlens can be proportional to its planar area. For example, if the area of ​​the first microlens is larger than the area of ​​the second microlens, the height of the first microlens can be greater than the height of the second microlens.

[0116] In detail, the autofocusing lens AFL can have a first height HE1. Because the autofocusing lens AFL is in Figure 5 The microlens has the largest area, so the first height HE1 can have a relatively large value.

[0117] Each standard microlens SML in the second lens group GR2 may have a third height HE3. The third height HE3 may be defined as a reference height for the microlens. The first height HE1 may be greater than the third height HE3. Specifically, the ratio of the first height HE1 to the third height HE3 may be in the range of about 1.5 to about 5. In one embodiment, the ratio of the first height HE1 to the third height HE3 may be in the range of about 1.5 to about 3.

[0118] The first microlens ML1 of the first lens group GR1 may have a second height HE2. The second height HE2 may be greater than a third height HE3 and less than a first height HE1. For example, the ratio of the second height HE2 to the third height HE3 may be in the range of about 1.1 to about 1.4. By increasing the area of ​​the first microlens ML1, the second height HE2 of the first microlens ML1 can be increased. By adjusting the second height HE2 of the first microlens ML1 to a relatively large value, the light reception of the first microlens ML1 can be increased.

[0119] The difference between the second height HE2 of the first microlens ML1 and the third height HE3, which is defined as the reference height (i.e., HE2-HE3) can be less than the difference between the first height HE1 of the autofocusing lens AFL and the third height HE3, which is defined as the reference height (i.e., HE1-HE3).

[0120] The second microlens ML2 of the first lens group GR1 may have a fourth height HE4. The fourth height HE4 may be smaller than the third height HE3. For example, the ratio of the fourth height HE4 to the third height HE3 may be in the range of about 0.5 to about 0.9. By reducing the area of ​​the second microlens ML2, the fourth height HE4 of the second microlens ML2 can be reduced. By adjusting the fourth height HE4 of the second microlens ML2 to a relatively small value, the amount of light received can be reduced.

[0121] The difference between the fourth height HE4 of the second microlens ML2 and the third height HE3 (defined as the reference height) (i.e., HE3-HE4) can be less than the difference between the first height HE1 of the autofocusing lens AFL and the third height HE3 (defined as the reference height) (i.e., HE1-HE3). The difference between the fourth height HE4 of the second microlens ML2 and the third height HE3 (defined as the reference height) (i.e., HE3-HE4) can be substantially equal to the difference between the second height HE2 of the first microlens ML1 and the third height HE3 (defined as the reference height) (i.e., HE2-HE3).

[0122] Compared to a standard microlens (SML), an autofocusing lens (AFL) can have a larger size (e.g., a larger height). Because the height of the autofocusing lens (AFL) is greater than the height of each of the adjacent microlenses (i.e., the first lens group GR1), the amount of light received in the adjacent first lens group GR1 can be varied by the autofocusing lens (AFL). For example, one of the microlenses constituting the first lens group GR1 may have a reduced amount of light received compared to the standard microlens (SML), while another microlens constituting the first lens group GR1 may have an increased amount of light received compared to the standard microlens (SML). In other words, the amount of light received by each of the microlenses constituting the first lens group GR1 can differ from the amount of light received by the standard microlens (SML).

[0123] According to one example embodiment, by adjusting the height of the microlens in the first lens group GR1, the difference in light reception between the corresponding microlens and the standard microlens SML can be reduced. For example, for the first microlens ML1, which has a small light reception, its light reception can be adjusted to be the same as that of the standard microlens SML by increasing its height. For the second microlens ML2, which has a large light reception, its light reception can be adjusted to be the same as that of the standard microlens SML by decreasing its height.

[0124] As a result, according to an example implementation, by adjusting the physical height of the microlens, the difference in light intensity between the optical signal in the pixel region PX adjacent to the focused pixel region RP and the optical signal in another pixel region PX spaced apart from the focused pixel region RP can be compensated.

[0125] Figure 7 It is along Figure 5 Line I-I' is cut to show a cross-sectional view of a microlens according to an example embodiment. For brevity, previous references... Figure 5 , Figure 6A and Figure 6B The described elements may be identified by the same reference numerals without repeating their overlapping descriptions.

[0126] Reference Figure 5 and Figure 7 The third microlens ML3 of the first lens group GR1 may have a fifth height HE5. The fifth height HE5 may be greater than the second height HE2 and less than the first height HE1. For example, the ratio of the fifth height HE5 to the third height HE3 may be in the range of about 1.3 to about 1.5. In other words, the first microlens ML1 and the third microlens ML3, provided adjacent to the opposing first edges ED1 and third edges ED3 of the autofocus lens AFL, may have different heights than each other.

[0127] The difference between the second height HE2 of the first microlens ML1 and the third height HE3, which is defined as the reference height (i.e., HE2-HE3) can be less than the difference between the fifth height HE5 of the third microlens ML3 and the third height HE3, which is defined as the reference height (i.e., HE5-HE3).

[0128] Figure 8 This illustrates a portion of a microlens according to an example embodiment (e.g., Figure 2 A plan view of part M). For the sake of brevity, refer to the previous section. Figure 5 , Figure 6A and Figure 6B The described elements may be identified by the same reference numerals without repeating their overlapping descriptions.

[0129] Reference Figure 8 A first autofocusing lens AFL1 and a second autofocusing lens AFL2 can be provided. The first autofocusing lens AFL1 and the second autofocusing lens AFL2 can be adjacent to each other in the second direction D2. The microlenses of the first lens group GR1 can be arranged in two dimensions around the first autofocusing lens AFL1 and the second autofocusing lens AFL2.

[0130] For example, the first lens group GR1 may include a first microlens ML1 and a second microlens ML2 adjacent to the first autofocusing lens AFL1. The first lens group GR1 may also include a fifth microlens ML5 between the first microlens ML1 and the second microlens ML2. The first lens group GR1 may include a sixth microlens ML6 and a seventh microlens ML7 adjacent to the second autofocusing lens AFL2. The first lens group GR1 may also include an eighth microlens ML8 between the sixth microlens ML6 and the seventh microlens ML7.

[0131] The first microlens ML1 can have essentially the same area and height as the sixth microlens ML6. The second microlens ML2 can have essentially the same area and height as the seventh microlens ML7. The fifth microlens ML5 can have essentially the same area and height as the eighth microlens ML8.

[0132] The microlenses (i.e., standard microlenses SML) of the second lens group GR2 can be configured in two dimensions to surround the first lens group GR1.

[0133] Figure 9 This illustrates a portion of a microlens according to an example embodiment (e.g., Figure 2 A plan view of part M). Figure 10 It is along Figure 9 The cross-sectional view taken by line I-I'. For simplicity, refer to the previous... Figure 5 , Figure 6A and Figure 6B The described elements may be identified by the same reference numerals without repeating their overlapping descriptions.

[0134] Reference Figure 9 and Figure 10 An autofocusing lens (AFL) and microlenses surrounding a first lens group (GR1) of the AFL can be provided. Furthermore, microlenses in a second lens group (GR2) can be provided surrounding the first lens group (GR1). In one example embodiment, the second lens group (GR2) may include non-standard microlenses (IML). A third lens group (GR3) including standard microlenses (SML) can be provided surrounding the second lens group (GR2).

[0135] Non-standard microlenses (IMLs) can have a reference area and height different from those of standard microlenses (SMLs). For example, a non-standard microlens IML can have an area larger than the reference area and a height larger than the reference height. Figure 10 As shown, a non-standard microlens (IML) can have a sixth height HE6. The sixth height HE6 can be greater than the third height HE3, which is defined as the standard height, and can be less than the second height HE2. The ratio of the sixth height HE6 to the third height HE3 can range from about 1.1 to about 1.3.

[0136] The autofocusing lens AFL can cause changes in the amount of light received not only in the first lens group GR1, which is directly adjacent to the autofocusing lens AFL, but also in the amount of light received in the second lens group GR2. Here, the term "directly adjacent" can mean that the microlens in the first lens group GR1 is adjacent to the autofocusing lens AFL without any intervening microlens (e.g., ML5 in the first lens group GR1). According to an example embodiment, because the second lens group GR2 provides a non-standard microlens IML instead of a standard microlens SML, the change in light received can be compensated for.

[0137] For example, the change in light reception in the first microlens ML1, which constitutes the first lens group GR1, can be greater than the change in light reception in the non-standard microlens IML, which constitutes the second lens group GR2. This is because the distance between the autofocusing lens AFL and the first lens group GR1 is smaller than the distance between the autofocusing lens AFL and the second lens group GR2.

[0138] The difference between the height of the first microlens ML1 and the reference height (i.e., HE2-HE3) can be selected to have a larger value than the difference between the height of the non-standard microlens IML and the reference height (i.e., HE6-HE3). Therefore, variations in light reception can be appropriately compensated depending on the distance from the autofocusing lens AFL.

[0139] In summary, such as Figure 10 As shown, the height of the microlens can be adjusted in such a way that the difference between the height of the microlens and the reference height decreases as the distance from the autofocusing lens AFL in the fourth direction D4 increases.

[0140] Figure 11 It is shown Figure 5 A planar view of the microlens. Figure 12A It is along Figure 11 The cross-sectional view taken from line I-I'. Figure 12B It is along Figure 11 The cross-sectional view taken from line II-II'. For simplicity, refer to the previous... Figure 5 , Figure 6A and Figure 6B The described elements may be identified by the same reference numerals without repeating their overlapping descriptions.

[0141] Reference Figure 11 , Figure 12A and Figure 12B The height of a microlens can be defined as the horizontal difference between the lowest valley TRt and the peak CR. The lowest valley TRt of a microlens can be located at the corner where two adjacent edges of the microlens meet.

[0142] In detail, the lowest point TRt of the autofocus lens AFL can be located at, for example, the corner VER where the first edge ED1 and the second edge ED2 or the third edge ED3 and the fourth edge ED4 meet. Figure 12A The lowest valley TRt shown can be lower than Figure 6A The valley TR is shown. The first height HE1 of the autofocusing lens AFL can be the horizontal difference between the lowest valley TRt and the peak CR in the autofocusing lens AFL.

[0143] The first microlens ML1 may have a lowest valley TRt at one of its corners. The second height HE2 of the first microlens ML1 may be the horizontal difference between the lowest valley TRt and the peak CR in the first microlens ML1. The second microlens ML2 may have a lowest valley TRt at one of its corners. The fourth height HE4 of the second microlens ML2 may be the horizontal difference between the lowest valley TRt and the peak CR in the second microlens ML2. The standard microlens SML may have a lowest valley TRt at one of its corners. The third height HE3 of the standard microlens SML may be the horizontal difference between the lowest valley TRt and the peak CR in the standard microlens SML.

[0144] According to an exemplary embodiment of this disclosure, the height of a microlens near an autofocusing lens can be adjusted. The presence of an autofocusing lens can affect the amount of light received by the microlens, but adjusting the height of the microlens allows for the desired amount of light received by the microlens. In other words, by adjusting the height of the microlens near the autofocusing lens, the variation in the amount of light received by the microlens caused by the autofocusing lens can be compensated for. Therefore, the image quality of the image sensor can be improved.

[0145] While exemplary embodiments of this disclosure have been specifically shown and described, those skilled in the art will understand that variations in form and detail may be made therein without departing from the spirit and scope of the appended claims.

[0146] This application claims priority to Korean Patent Application No. 10-2020-0146667, filed on November 5, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. An image sensor, comprising: A first substrate includes a focused pixel region and a pixel region surrounding the focused pixel region, each of the focused pixel region and the pixel region including at least one photoelectric conversion region; Color filters are provided on the focused pixel region and the pixel region, respectively, and on the first surface of the first substrate; as well as Microlenses are provided on the color filter, The microlens includes: An autofocusing lens on the focused pixel area; The first microlens adjacent to the autofocusing lens; and Standard microlenses spaced apart from the autofocus lens, The autofocusing lens has a first height, the first microlens has a second height, and the standard microlens has a third height. The difference between the second height and the third height is less than the difference between the first height and the third height.

2. The image sensor according to claim 1, wherein the second height is greater than the third height, and the second height is less than the first height.

3. The image sensor of claim 2, wherein the ratio of the second height to the third height is in the range of 1.1 to 1.

4.

4. The image sensor according to claim 1, wherein the first height is greater than the third height, and The second height is smaller than the third height.

5. The image sensor of claim 4, wherein the ratio of the second height to the third height is in the range of 0.5 to 0.

9.

6. The image sensor of claim 1, wherein the microlens further comprises a non-standard microlens between the first microlens and the standard microlens. The non-standard microlens described therein has a fourth height, and The difference between the fourth height and the third height is less than the difference between the second height and the third height.

7. The image sensor according to claim 1, wherein the area of ​​the autofocus lens is larger than the area of ​​the first microlens and larger than the area of ​​the standard microlens, and The area of ​​the first microlens is different from the area of ​​the standard microlens.

8. The image sensor according to claim 1, further comprising: An isolation pattern is provided in the first substrate to define the focused pixel region and the pixel region; A transistor is provided on a second surface of the first substrate, the second surface being opposite to the first surface; The first interconnect layer on the second surface; Second substrate; as well as The second interconnect layer on the second substrate The first interconnect layer and the second interconnect layer are stacked vertically and electrically connected to each other.

9. The image sensor according to claim 8, further comprising: A through-hole penetrates the first substrate and exposes the first interconnect layer and the second interconnect layer; as well as A conductive pattern is provided in the through hole.

10. The image sensor of claim 8, wherein the first interconnect layer includes a first connection pad. The second interconnect layer includes a second connection pad, and The first connection pad and the second connection pad are aligned perpendicularly to each other and in contact with each other.

11. An image sensor, comprising: The substrate includes a focused pixel region and a pixel region surrounding the focused pixel region, each of the focused pixel region and the pixel region including at least one photoelectric conversion region; Color filters are provided on the focused pixel region and the pixel region, respectively; as well as Microlenses are provided on the color filter, The microlens includes: An autofocusing lens on the focused pixel area; A first microlens adjacent to the first edge of the autofocusing lens; A second microlens adjacent to the second edge of the autofocusing lens; and Standard microlenses spaced apart from the autofocus lens, The autofocusing lens has a first height, the first microlens has a second height, the second microlens has a third height, and the standard microlens has a fourth height. Wherein the second height is greater than the fourth height and less than the first height, and The third height is less than the fourth height.

12. The image sensor of claim 11, wherein the ratio of the second height to the fourth height is in the range of 1.1 to 1.

4.

13. The image sensor of claim 11, wherein the ratio of the third height to the fourth height is in the range of 0.5 to 0.

9.

14. The image sensor according to claim 11, wherein the area of ​​the autofocus lens is larger than the area of ​​the first microlens. The area of ​​the first microlens is larger than the area of ​​the standard microlens, and The area of ​​the second microlens is smaller than the area of ​​the standard microlens.

15. The image sensor of claim 11, wherein the microlens further comprises a third microlens adjacent to the third edge of the autofocus lens, the third edge being opposite to the first edge. The third microlens has a fifth height, and The fifth height is greater than the second height and less than the first height.

16. An image sensor, comprising: Circuit chip; as well as Image sensor chips stacked on the circuit chip, The image sensor chip mentioned above includes: A first substrate has a first surface and a second surface, the second surface being opposite to the first surface, and the first substrate includes a photoelectric conversion region provided therein; An isolation pattern is provided in the first substrate and between the photoelectric conversion regions; An insulating layer covering the first surface of the first substrate; Color filter, on the insulating layer; Fence pattern, between the color filters; Microlenses are provided on the color filter; Device isolation patterns are provided adjacent to the second surface to define the active region; Gate pattern, on the second surface; and A first interconnect layer is located on the second surface. The circuit chip mentioned above includes: The second substrate includes an integrated circuit; and The second interconnect layer is located on the second substrate. The first interconnect layer and the second interconnect layer are provided to face each other and be electrically connected to each other. The microlens includes: Autofocus lens; A first microlens, adjacent to the autofocusing lens; and Standard microlenses, spaced apart from the autofocusing lens. The autofocusing lens has a first height, the first microlens has a second height, and the standard microlens has a third height. The difference between the second height and the third height is less than the difference between the first height and the third height.

17. The image sensor of claim 16, wherein the second height is greater than the third height and less than the first height.

18. The image sensor of claim 17, wherein the ratio of the second height to the third height is in the range of 1.1 to 1.

4.

19. The image sensor of claim 16, wherein the first height is greater than the third height, and The second height is smaller than the third height.

20. The image sensor of claim 19, wherein the ratio of the second height to the third height is in the range of 0.5 to 0.9.

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