Display device

Abstract

Display device. According to one aspect of the disclosure, a display device includes a stretchable lower substrate and a plurality of first substrates disposed on the lower substrate and including first pixels and second pixels. The display device also includes a plurality of second substrates configured to connect first substrates adjacent to each other among the plurality of first substrates. The display device further includes a plurality of connection lines disposed on the plurality of second substrates and configured to connect the first pixels and the second pixels. The plurality of connection lines includes a plurality of first connection lines extending in a first direction, a plurality of second connection lines extending in a second direction, and a plurality of third connection lines extending in a third direction. Accordingly, the display device can improve resolution and can be uniformly stretched in all directions.

Description

Technical Field

[0001] This disclosure relates to a display device, and more specifically, to a display device in which connecting lines can be arranged in various ways. Background Technology

[0002] Display devices used in computers, TVs, mobile phones, etc., include self-emissive organic light-emitting displays (OLEDs) and liquid crystal displays (LCDs) that require a separate light source.

[0003] As display devices are increasingly used in various fields such as computer monitors, TVs, and personal mobile devices, display devices with large effective area and reduced size and weight have been researched.

[0004] In addition, recently, display devices in which display elements, wiring, etc. are formed on a flexible substrate made of flexible plastic and can be stretched in a specific direction and manufactured into various shapes have attracted much attention as the next generation of display devices. Summary of the Invention

[0005] The purpose of this disclosure is to provide a display device capable of reducing stress concentrated in the outer regions of a rigid substrate.

[0006] Another objective of this disclosure is to provide a display device that can guarantee a greater number of connection lines.

[0007] Another object of this disclosure is to provide a display device that can increase the number of pixels formed on a single rigid substrate.

[0008] The purpose of this disclosure is not limited to the above-mentioned purposes, and other purposes not mentioned above will be clearly understood by those skilled in the art through the following description.

[0009] According to one aspect of this disclosure, a display device includes a stretchable lower substrate and a plurality of first substrates disposed on the lower substrate and including first pixels and second pixels. The display device also includes a plurality of second substrates configured to connect adjacent first substrates among the plurality of first substrates. The display device further includes a plurality of connecting lines disposed on the plurality of second substrates and configured to connect the first pixels and second pixels. The plurality of connecting lines includes a plurality of first connecting lines extending in a first direction, a plurality of second connecting lines extending in a second direction, and a plurality of third connecting lines extending in a third direction. Therefore, the display device can improve resolution and can be stretched uniformly in all directions.

[0010] According to another aspect of this disclosure, the display device includes a flexible substrate and a plurality of rigid substrates disposed on the flexible substrate. The display device also includes a plurality of pixels formed on each of the plurality of rigid substrates, and a plurality of connecting lines disposed between the plurality of rigid substrates and connected to the plurality of pixels. The plurality of connecting lines may extend in at least three directions.

[0011] Further details of the exemplary embodiments are included in the detailed description and accompanying drawings.

[0012] According to this disclosure, the components will not be damaged when the display device is repeatedly stretched. Therefore, the stretching reliability can be improved.

[0013] According to this disclosure, a greater number of connecting lines can be ensured, and a greater number of connecting lines can be arranged in multiple ways. Therefore, uniform stretching in all directions can be achieved.

[0014] According to this disclosure, the number of pixels formed in a single rigid substrate can be increased. Therefore, the resolution of the display device can be improved.

[0015] The effects of this disclosure are not limited to the examples above, and this specification includes many more effects. Attached Figure Description

[0016] The above and other aspects, features and other advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is an exploded perspective view of a display device according to an exemplary embodiment of the present disclosure; Figure 2 This is an enlarged plan view of the display area of ​​a display device according to an exemplary embodiment of the present disclosure; Figure 3 It is along Figure 2 A schematic cross-sectional view taken from line III-III′; Figure 4 This is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure; Figure 5 This is an enlarged plan view of the display area of ​​a display device according to another exemplary embodiment of the present disclosure; Figure 6A and Figure 6B This is an enlarged plan view of the first substrate of a display device according to another exemplary embodiment of the present disclosure; Figure 7 This is a cross-sectional view of a sub-pixel of a display device according to another exemplary embodiment of the present disclosure; and Figure 8 This is an enlarged plan view of the display area of ​​a display device according to yet another exemplary embodiment of the present disclosure. Detailed Implementation

[0017] <Display Device>

[0018] The display device can display images even when bent or stretched and can be called a stretchable display device. The display device can be more flexible than a typical conventional display device and can be stretched. Therefore, the user can bend or stretch the display device, and the shape of the display device can be freely changed in response to the user's manipulation. For example, when the user pulls the edge of the display device, the display device can be stretched in the direction of the pull. When the user places the display device on an uneven outer surface, the display device can bend along the shape of the outer surface of the wall. Moreover, when the force applied by the user is removed, the display device can return to its original shape.

[0019] Figure 1 This is an exploded perspective view of a display device according to an exemplary embodiment of the present disclosure. (Refer to...) Figure 1 The display device 100 includes a lower substrate 111, an upper substrate 112, a plurality of first substrates 121, a plurality of second substrates 122, a plurality of third substrates 123, and a printed circuit board 130. Furthermore, the display device 100 includes a plurality of pixels PX, a gating driver GD, and a data driver DD.

[0020] The lower substrate 111 is a substrate used to support and protect the various components of the display device 100. In addition, the upper substrate 112 is a substrate used to cover and protect the various components of the display device 100.

[0021] The lower substrate 111 and the upper substrate 112 are each a flexible substrate and are made of a bendable or stretchable insulating material. For example, each of the lower substrate 111 and the upper substrate 112 may be made of silicone rubber such as polydimethylsiloxane (PDMS) and elastomers such as polyurethane (PU) or polytetrafluoroethylene (PTFE). Therefore, each of the lower substrate 111 and the upper substrate 112 may have flexible properties. Furthermore, the lower substrate 111 and the upper substrate 112 may be made of the same material, but are not limited to this, and the material may be modified in various ways.

[0022] Each of the lower substrate 111 and the upper substrate 112 is a tough substrate and can reversibly expand and contract. Therefore, the lower substrate 111 can also be referred to as a lower tough substrate or a first tough substrate, and the upper substrate 112 can also be referred to as an upper tough substrate or a second tough substrate. Furthermore, the lower substrate 111 and the upper substrate 112 can have an elastic modulus in the range of several MPa to several hundred MPa. In addition, the lower substrate 111 and the upper substrate 112 can have a ductile fracture rate of 100% or higher. Here, the ductile fracture rate refers to the distance extended when a stretched object breaks or fractures. The lower substrate can have a thickness from 10 μm to 1 mm, but is not limited to this.

[0023] The lower substrate 111 may have a display area AA and a non-display area NA surrounding the display area AA.

[0024] The display area AA is the area on the display device 100 where an image is displayed. Multiple pixels PX are disposed within the display area AA. Furthermore, each pixel PX may include a display element and various driving elements for driving the display element. These various driving elements may refer to at least one thin-film transistor (TFT) and a capacitor, but are not limited thereto. Additionally, each of the multiple pixels PX may be connected to various lines. For example, each of the multiple pixels PX may be connected to various lines such as a gate line, a data line, a high-potential power line, a low-potential power line, and a reference voltage line.

[0025] The non-display area NA is the area where no image is displayed. The non-display area NA can be an area adjacent to and surrounding the display area AA, but is not limited to this. The non-display area NA is the area in the lower substrate 111 other than the display area AA and can be deformed and separated in various shapes. In the non-display area NA, driving elements for driving the multiple pixels PX disposed in the display area AA are provided. A gating driver GD can be provided in the non-display area NA. Furthermore, multiple pads connected to the gating driver GD and the data driver DD can be provided in the non-display area NA. Each pad can be connected to each pixel among the multiple pixels PX disposed in the display area AA.

[0026] On the lower substrate 111, a plurality of first substrates 121, a plurality of second substrates 122 and a plurality of third substrates 123 are disposed.

[0027] Multiple first substrates 121 are disposed in the display area AA of the lower substrate 111, and multiple pixels PX are disposed on the multiple first substrates 121. In addition, multiple third substrates 123 are disposed in the non-display area NA of the lower substrate 111, and a gate driver GD and multiple pads are formed on the multiple third substrates 123.

[0028] like Figure 1As shown, the gate driver GD can be mounted on one of the multiple third substrates 123 located on the X-axis side of the display area AA. When manufacturing various components on the first substrate 121, the gate driver GD can be formed on the third substrate 123 using a gate-in-panel (GIP) configuration. Therefore, various circuit components (such as various transistors, capacitors, wiring, etc.) constituting the gate driver GD can be disposed on the multiple third substrates 123. However, this disclosure is not limited to this. The gate driver GD can be mounted using a chip-on-film (COF) configuration. Furthermore, the multiple third substrates 123 can be disposed in a non-display area NA located on the other side of the display area AA in the X-axis direction. The gate driver GD can also be mounted on the multiple third substrates 123 located on the other side of the display area AA in the X-axis direction.

[0029] Reference Figure 1 The plurality of third substrates 123 may be larger in size than the plurality of first substrates 121. Specifically, each of the plurality of third substrates 123 may be larger in size than each of the plurality of first substrates 121. As described above, a gate driver GD may be disposed on each of the plurality of third substrates 123. For example, a stage of the gate driver GD may be disposed on each of the plurality of third substrates 123. Therefore, the area of ​​the various circuit components constituting a stage of the gate driver GD is relatively larger than the area of ​​the pixel PX disposed on the first substrate 121. Therefore, each of the plurality of third substrates 123 may be larger in size than each of the plurality of first substrates 121.

[0030] Figure 1 An example is shown where multiple third substrates 123 are disposed on one side of the Y-axis direction and one side of the X-axis direction in the non-display area NA. However, this disclosure is not limited thereto. The multiple third substrates 123 can be disposed in any part of the non-display area NA. Moreover, Figure 1 An example is shown where each of the plurality of first substrates 121 and the plurality of third substrates 123 has a quadrilateral shape. However, this disclosure is not limited thereto. Each of the plurality of first substrates 121 and the plurality of third substrates 123 may have various shapes.

[0031] Each of the plurality of second substrates 122 connects adjacent first substrates 121, adjacent third substrates 123, or adjacent first substrates 121 and third substrates 123. Therefore, each of the plurality of second substrates 122 can also be referred to as a connecting substrate. The plurality of second substrates 122 are disposed between the plurality of first substrates 121, between the plurality of third substrates 123, or between the plurality of first substrates 121 and the plurality of third substrates 123.

[0032] Reference Figure 1The plurality of second substrates 122 have curved shapes. For example, the plurality of second substrates 122 can have a sinusoidal shape. However, the shape of the plurality of second substrates 122 is not limited to this. The plurality of second substrates 122 can have various shapes. For example, the plurality of second substrates 122 can extend in a Z-shape, or a plurality of rhomboid substrates can extend by connecting to each other at their vertices. Furthermore, Figure 1 The number and shape of the plurality of second substrates 122 shown are provided as an example. The number and shape of the plurality of second substrates 122 can vary depending on the design.

[0033] Furthermore, the plurality of first substrates 121, the plurality of second substrates 122, and the plurality of third substrates 123 are rigid substrates. The plurality of first substrates 121, the plurality of second substrates 122, and the plurality of third substrates 123 are more rigid than the lower substrate 111. The plurality of first substrates 121, the plurality of second substrates 122, and the plurality of third substrates 123 may have a higher elastic modulus than the lower substrate 111. Elastic modulus is a parameter representing the rate of deformation of a substrate caused by stress applied to it, and when the elastic modulus is relatively high, the hardness can be relatively high. Therefore, the first substrates 121, the second substrates 122, and the third substrates 123 may also be referred to as first rigid substrates, second rigid substrates, and third rigid substrates, respectively. The elastic modulus of the plurality of first substrates 121, the plurality of second substrates 122, and the plurality of third substrates 123 may be 1000 times or more the elastic modulus of the lower substrate 111, but is not limited thereto.

[0034] The plurality of first substrates 121, second substrates 122, and third substrates 123, which serve as rigid substrates, can be made of a plastic material that has less flexibility than the lower substrate 111. For example, the plurality of first substrates 121, second substrates 122, and third substrates 123 can be made of polyimide (PI), polyacrylate, polyacetate, etc. Here, the plurality of first substrates 121 and the plurality of third substrates 123 can be made of the same material, but are not limited thereto. The plurality of first substrates 121 and the plurality of third substrates 123 can also be made of different materials from each other.

[0035] In some exemplary embodiments, the lower substrate 111 may be defined as including a plurality of first lower patterns and second lower patterns. The plurality of first lower patterns may be disposed in the region of the lower substrate 111 overlapping with the plurality of first substrates 121 and the plurality of third substrates 123. Furthermore, the second lower patterns may be disposed in regions other than those of the plurality of first substrates 121 and the plurality of third substrates 123. Alternatively, the second lower patterns may be disposed throughout the entire area of ​​the display device 100.

[0036] In this case, the first lower pattern can have a higher elastic modulus than the second lower pattern. For example, the plurality of first lower patterns can be made of the same material as the plurality of first substrates 121 and the plurality of third substrates 123. Moreover, the second lower pattern can be made of a material with a lower elastic modulus than the plurality of first substrates 121 and the plurality of third substrates 123.

[0037] The first pattern can be made of polyimide (PI), polyacrylate, polyacetate, etc. The second pattern can be made of silicone rubber such as polydimethylsiloxane (PDMS) and elastomers such as polyurethane (PU) or polytetrafluoroethylene (PTFE).

[0038] A gate driver GD is a component that provides gate voltages to multiple pixels PX disposed in a display area AA. The gate driver GD includes multiple stages formed on multiple third substrates 123, and the stages of the gate driver GD can be electrically connected to each other. Therefore, a gate voltage output from one stage can be transferred to another stage. Furthermore, each stage can sequentially provide gate voltages to the multiple pixels PX connected to that stage.

[0039] A power supply can be connected to a gate driver GD and can provide a gate drive voltage and a gate clock voltage to the gate driver GD. Furthermore, the power supply can be connected to multiple pixels PX and can provide a pixel drive voltage to each of the multiple pixels PX. Additionally, the power supply can be formed on multiple third substrates 123. The power supply can be formed adjacent to the gate driver GD on an outer substrate 121. Furthermore, the power supplies formed on the multiple third substrates 123 can be electrically connected to each other. The multiple power supplies formed on the multiple third substrates 123 can be connected via gate power connection lines and pixel power connection lines. Therefore, each of the multiple power supplies can provide a gate drive voltage, a gate clock voltage, and a pixel drive voltage.

[0040] The printed circuit board 130 is configured to transmit signals and voltages from a controller to the display element for driving the display element. Therefore, the printed circuit board 130 can also be referred to as a driving substrate. A controller, such as an IC chip or circuit, can be mounted on the printed circuit board 130. Furthermore, a memory, processor, etc., can also be mounted on the printed circuit board 130. Moreover, the printed circuit board 130 disposed in the display device 100 may include a stretchable area and a non-stretchable area to ensure stretchability. Furthermore, IC chips, circuits, memory, processors, etc., can be mounted on the non-stretchable area. Furthermore, wiring electrically connected to the IC chips, circuits, memory, and processor can be provided in the stretchable area. Furthermore, the printed circuit board 130 can be bonded to multiple pads of multiple third substrates 123 disposed in the non-display area NA.

[0041] The data driver DD is a component that provides data voltage to multiple pixels PX disposed in the display area AA. The data driver DD can be configured as an IC chip and is therefore also referred to as a data integrated circuit (D-IC). Furthermore, the data driver DD can be disposed in a non-stretchable area of ​​the printed circuit board 130. The data driver DD can be mounted on the printed circuit board 130 as a chip-on-board (COB). Moreover, the data driver DD provides data voltage to each of the multiple pixels PX disposed in the display area AA via multiple pads disposed on multiple third substrates 123. However, Figure 1 An example of mounting a data drive DD using the COB method is given. However, this disclosure is not limited to this. The data drive DD can also be mounted using the COF method, COG method, payload encapsulation (TCP) method, etc.

[0042] and, Figure 1 An example is shown where a third substrate 123 is disposed in a non-display area NA above the display area AA, corresponding to the first substrate 121 disposed in a row in the display area AA. Furthermore, Figure 1 An example is shown where the data driver DD is disposed on the third substrate 123. However, this disclosure is not limited thereto. The third substrate 123 and the data driver DD may be configured to correspond to the first substrate 121 disposed on multiple rows.

[0043] In the following text, reference will be made to Figure 2 and Figure 3 The display area AA of the display device 100 according to an exemplary embodiment of the present disclosure will be described in more detail.

[0044] <Planar and Cross-sectional Structure of the Display Area>

[0045] Figure 2 This is an enlarged plan view of the display area of ​​a display device according to an exemplary embodiment of the present disclosure. Figure 3 It is along Figure 2 A schematic cross-sectional view taken from line III-III′. For ease of description, reference will also be made below. Figure 1 .

[0046] Reference Figure 1 and Figure 2 A plurality of first substrates 121 are disposed on a lower substrate 111 in the display area AA. The plurality of first substrates 121 are configured to be spaced apart from each other on the lower substrate 111. For example, the plurality of first substrates 121 may be disposed on the lower substrate 111 in a matrix configuration, such as... Figure 1 As shown, but not limited to.

[0047] Reference Figure 2 and Figure 3A pixel PX comprising multiple sub-pixels SPX is disposed on the first substrate 121. Furthermore, each sub-pixel SPX may include an LED 170 as a display element, and a driving transistor 160 and a switching transistor 150 for driving the LED 170. However, the display element in each sub-pixel SPX is not limited to LEDs and may be an organic light-emitting diode. Additionally, the multiple sub-pixels SPX may include red sub-pixels, green sub-pixels, and blue sub-pixels, but are not limited to these. The multiple sub-pixels SPX may include pixels of various colors as needed.

[0048] Multiple sub-pixels SPX can be connected to multiple connection lines 180. Multiple sub-pixels SPX can be electrically connected to a first connection line 181 extending in the X-axis direction. Furthermore, multiple sub-pixels SPX can be electrically connected to a second connection line 182 extending in the Y-axis direction.

[0049] In the following text, reference will be made to Figure 3 Describe the cross-sectional structure of the display area in detail.

[0050] Reference Figure 3 Multiple inorganic insulating layers are disposed on multiple first substrates 121. For example, the multiple inorganic insulating layers may include a buffer layer 141, a gate insulating layer 142, a first interlayer insulating layer 143, a second interlayer insulating layer 144, and a passivation layer 145. However, this disclosure is not limited thereto. Various inorganic insulating layers may also be disposed on the multiple first substrates 121. One or more of the buffer layer 141, gate insulating layer 142, first interlayer insulating layer 143, second interlayer insulating layer 144, and passivation layer 145 may be omitted.

[0051] Specifically, a buffer layer 141 is disposed on a plurality of first substrates 121. The buffer layer 141 is formed on the plurality of first substrates 121 to protect the various components of the display device 100 from the infiltration of moisture (H2O) and oxygen (O2) from the lower substrate 111 and the exterior of the plurality of first substrates 121. The buffer layer 141 may be made of an insulating material. For example, the buffer layer 141 may be formed as a single inorganic layer or multiple inorganic layers such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON). However, depending on the structure or characteristics of the display device 100, the buffer layer 141 may be omitted.

[0052] In this case, the buffer layer 141 may be formed only in the region where the buffer layer 141 overlaps with the plurality of first substrates 121 and the plurality of third substrates 123. As described above, the buffer layer 141 may be made of an inorganic material. Therefore, the buffer layer 141 may be easily damaged, such as easily breaking, when the display device 100 is stretched. Therefore, the buffer layer 141 may not be formed in the region between the plurality of first substrates 121 and the plurality of third substrates 123. The buffer layer 141 may be patterned to the shape of the plurality of first substrates 121 and the plurality of third substrates 123 and formed only on the upper part of the plurality of first substrates 121 and the plurality of third substrates 123. Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, the buffer layer 141 is formed only in the region where the buffer layer 141 overlaps with the plurality of first substrates 121 and the plurality of third substrates 123, which are rigid substrates. Therefore, even when the display device 100 is deformed (e.g., bent or stretched), damage to the buffer layer 141 can be suppressed.

[0053] Reference Figure 3 A switching transistor 150, including a gate 151, an active layer 152, a source 153, and a drain 154, is formed on a buffer layer 141. Furthermore, a driving transistor 160, including a gate 161, an active layer 162, a source 163, and a drain 164, is formed on the buffer layer 141.

[0054] First, refer to Figure 3 The active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160 are disposed on the buffer layer 141. For example, each of the active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160 can be made of oxide semiconductor. Each of the active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160 can be made of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), organic semiconductor, etc.

[0055] A gate insulating layer 142 is disposed on the active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160. The gate insulating layer 142 is configured to electrically insulate the gate 151 of the switching transistor 150 from the active layer 152 of the switching transistor 150 and to electrically insulate the gate 161 of the driving transistor 160 from the active layer 162 of the driving transistor 160. Furthermore, the gate insulating layer 142 may be made of an insulating material. For example, the gate insulating layer 142 may be formed as a single inorganic layer or multiple inorganic layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

[0056] The gate 151 of the switching transistor 150 and the gate 161 of the driving transistor 160 are disposed on the gate insulating layer 142. The gate 151 of the switching transistor 150 and the gate 161 of the driving transistor 160 are spaced apart from each other on the gate insulating layer 142. Furthermore, the gate 151 of the switching transistor 150 overlaps with the active layer 152 of the switching transistor 150, and the gate 161 of the driving transistor 160 overlaps with the active layer 162 of the driving transistor 160.

[0057] Each of the gate 151 of the switching transistor 150 and the gate 161 of the driving transistor 160 may be made of any of the following metallic materials: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, each of the gate 151 of the switching transistor 150 and the gate 161 of the driving transistor 160 may be made of an alloy of two or more of them, or of multiple layers thereof, but is not limited thereto.

[0058] A first interlayer insulating layer 143 is disposed on the gate 151 of the switching transistor 150 and the gate 161 of the driving transistor 160. The first interlayer insulating layer 143 insulates the gate 161 of the driving transistor 160 from the intermediate metal layer IM. The first interlayer insulating layer 143 may also be made of an inorganic material, like the buffer layer 141. For example, the first interlayer insulating layer 143 may be formed as a single inorganic layer or multiple inorganic layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

[0059] An intermediate metal layer IM is disposed on the first interlayer insulating layer 143. Furthermore, the intermediate metal layer IM overlaps with the gate 161 of the driving transistor 160. Therefore, a storage capacitor is formed in the region where the intermediate metal layer IM overlaps with the gate 161 of the driving transistor 160. Specifically, the gate 161 of the driving transistor 160, the first interlayer insulating layer 143, and the intermediate metal layer IM form a storage capacitor. However, the location of the intermediate metal layer IM is not limited to this. The intermediate metal layer IM can overlap with another electrode in various ways to form a storage capacitor.

[0060] The intermediate metal layer IM can be made of any of the following metallic materials: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, the intermediate metal layer IM can be made of an alloy of two or more of these materials, or of multiple layers thereof, but is not limited thereto.

[0061] The second interlayer insulating layer 144 is disposed on the intermediate metal layer IM. The second interlayer insulating layer 144 insulates the gate 151 of the switching transistor 150 from the source 153 and drain 154 of the switching transistor 150. Furthermore, the second interlayer insulating layer 144 insulates the intermediate metal layer IM from the source 163 and drain 164 of the driving transistor 160. The second interlayer insulating layer 144 may also be made of an inorganic material, like the buffer layer 141. For example, the first interlayer insulating layer 143 may be formed as a single inorganic layer or multiple inorganic layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

[0062] The source 153 and drain 154 of the switching transistor 150 are disposed on the second interlayer insulating layer 144. Furthermore, the source and drain 164 of the driving transistor 160 are disposed on the second interlayer insulating layer 144. The source 153 and drain 154 of the switching transistor 150 are configured to be spaced apart from each other on the same layer. Additionally, although... Figure 3 The source of driving transistor 160 is not shown, but the source and drain of driving transistor 160 are also configured to be spaced apart from each other on the same layer. In switching transistor 150, the source 153 and drain 154 can be electrically connected to active layer 152 to contact active layer 152. Similarly, in driving transistor 160, the source and drain 164 can be electrically connected to active layer 162 to contact active layer 162. Furthermore, the drain 154 of switching transistor 150 can be electrically connected to the gate 161 of driving transistor 160 to contact the gate 161 of driving transistor 160.

[0063] Source 153 and drain 154 and 164 can be made of any of the following metallic materials: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, source 153 and drain 154 and 164 can be made of an alloy of two or more of them, or of multiple layers thereof, but are not limited thereto.

[0064] Furthermore, in this disclosure, the driving transistor 160 has been described as having a coplanar structure, but various types of transistors having interleaved structures, etc., may also be used.

[0065] In addition, although Figure 3Although not shown, gating pads and data pads may be disposed on the second interlayer insulating layer 144. The gating pads are used to transmit gate voltages to multiple sub-pixels (SPXs). The gate voltage can be transmitted from the gating pads to the gate 151 of the switching transistor 150 via gating lines formed on the first substrate 121. The data pads are used to transmit data voltages to the multiple sub-pixels (SPXs). The data voltage can be transmitted from the data pads to the source 153 of the switching transistor 150 via data lines formed on the first substrate 121. The gating pads and data pads may be made of the same material as the source 153 and the drains 154 and 164, but are not limited thereto.

[0066] Reference Figure 3 A passivation layer 145 is formed on the switching transistor 150 and the driving transistor 160. The passivation layer 145 covers the switching transistor 150 and the driving transistor 160 to protect them from the infiltration of moisture, oxygen, etc. The passivation layer 145 can be made of inorganic material and formed as a single layer or multiple layers, but is not limited thereto.

[0067] Furthermore, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 can be patterned and formed only in the regions where they overlap with the plurality of first substrates 121. The gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 can also be made of inorganic materials, like the buffer layer 141. Therefore, when the display device 100 is stretched, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 may be easily damaged, such as easily cracked. Therefore, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 may not be formed in the regions between the plurality of first substrates 121. The gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144 and the passivation layer 145 can be patterned into the shape of a plurality of first substrates 121 and formed only on the upper part of the plurality of first substrates 121.

[0068] A planarization layer 146 is formed on the passivation layer 145. The planarization layer 146 is used to planarize the upper portion of the switching transistor 150 and the driving transistor 160. The planarization layer 146 can be formed as a single layer or multiple layers and can be made of organic materials. Therefore, the planarization layer 146 can also be referred to as an organic insulating layer. For example, the planarization layer 146 can be made of acrylic-based organic materials, but is not limited thereto.

[0069] Reference Figure 3A planarization layer 146 is disposed on a plurality of first substrates 121 to cover the upper and side surfaces of a buffer layer 141, a gate insulating layer 142, a first interlayer insulating layer 143, a second interlayer insulating layer 144, and a passivation layer 145. Therefore, the planarization layer 146, together with the plurality of first substrates 121, surrounds the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145. Specifically, the planarization layer 146 may be configured to cover the upper and side surfaces of the passivation layer 145, the side surfaces of the first interlayer insulating layer 143, the second interlayer insulating layer 144, the side surfaces of the gate insulating layer 142, the side surfaces of the buffer layer 141, and a portion of the upper surfaces of the plurality of first substrates 121. Therefore, the planarization layer 146 can compensate for the steps between the side surfaces of the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145. Moreover, the planarization layer 146 can enhance the adhesion strength between the planarization layer 146 and the connection lines 180 disposed on the side surface of the planarization layer 146.

[0070] Reference Figure 3 The tilt angle of the side surface of the planarization layer 146 can be smaller than that of the side surfaces of the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145. For example, the side surface of the planarization layer 146 can have a smaller tilt angle than the side surfaces of the passivation layer 145, the first interlayer insulating layer 143, the second interlayer insulating layer 144, the gate insulating layer 142, and the buffer layer 141. Therefore, the connecting line 180 in contact with the side surface of the planarization layer 146 is configured to have a small tilt angle. Therefore, when the display device 100 is stretched, the stress generated in the connecting line 180 can be reduced. Moreover, breakage in the connecting line 180 or peeling of the connecting line 180 from the side surface of the planarization layer 146 can be suppressed.

[0071] Reference Figure 2 and Figure 3 The connection line 180 refers to a line that electrically connects to pads disposed on a plurality of first substrates 121. The connection line 180 is disposed on a plurality of second substrates 122. Furthermore, a portion of the connection line 180 may also be formed on the plurality of first substrates 121 to electrically connect to pads disposed on the plurality of first substrates 121. The pads disposed on the first substrates 121 refer to a plurality of contact pads 170, as well as gate pads and data pads.

[0072] The connecting line 180 includes a first connecting line 181 and a second connecting line 182. The first connecting line 181 and the second connecting line 182 are disposed between a plurality of first substrates 121. Specifically, the first connecting line 181 refers to the line in the connecting line 180 that extends in the X-axis direction between the plurality of first substrates 121. The second connecting line 182 refers to the line in the connecting line 180 that extends in the Y-axis direction between the plurality of first substrates 121.

[0073] The connecting line 180 may be made of a metallic material such as copper (Cu), aluminum (Al), titanium (Ti), or molybdenum (Mo). Alternatively, the connecting line 180 may have a laminated structure of metallic materials such as copper / molybdenum-titanium (Cu / MoTi), titanium / aluminum / titanium (Ti / Al / Ti), etc., but is not limited thereto.

[0074] In a typical display device, various wirings, such as multiple gate lines and multiple data lines, extend in straight lines and are arranged between multiple sub-pixels. Furthermore, multiple sub-pixels are connected to a single signal line. Therefore, in a typical display device, various wirings, such as gate lines, data lines, high-potential power lines, and reference voltage lines, extend continuously from one side of the organic light-emitting display device to the other on the substrate.

[0075] In contrast, in the display device 100 according to an exemplary embodiment of the present disclosure, various wirings formed in straight lines and considered to be used in general organic light-emitting display devices, such as gate lines, data lines, high-potential power lines, and reference voltage lines, are provided only on a plurality of first substrates 121 and a plurality of third substrates 123. In the display device 100 according to an exemplary embodiment of the present disclosure, wirings formed in straight lines are provided only on a plurality of first substrates 121 and a plurality of third substrates 123.

[0076] In the display device 100 according to an exemplary embodiment of the present disclosure, pads on two adjacent first substrates 121 or two adjacent third substrates 123 can be connected by a connecting line 180 to connect discontinuous wiring on the first substrate 121 or third substrate 123. The connecting line 180 electrically connects the pads on two adjacent first substrates 121, two adjacent third substrates 123, and adjacent first substrates 121 and third substrates 123. Therefore, the display device 100 according to an exemplary embodiment of the present disclosure may include multiple connecting lines 180 to electrically connect various wirings such as gate lines, data lines, high-potential power lines, and reference voltage lines between multiple first substrates 121, between multiple third substrates 123, and between multiple first substrates 121 and multiple third substrates 123. For example, gate lines may be provided on multiple first substrates 121 arranged adjacent to each other in the X-axis direction. Moreover, gate pads may be provided at both ends of the gate line. In this configuration, multiple gate pads on a plurality of first substrates 121 arranged adjacent to each other in the X-axis direction can be connected to each other via a first connecting line 181 serving as a gate line. Therefore, the gate lines provided on the plurality of first substrates 121 and the first connecting line 181 provided on the third substrate 123 can be used as a single gate line. Furthermore, wiring such as light-emitting signal lines, low-potential power lines, and high-potential power lines extending in the X-axis direction, which can be included in all the various wirings in the display device 100, can also be electrically connected via the first connecting line 181 as described above.

[0077] Reference Figure 2 and Figure 3 The first connection line 181 can connect to pads on two first substrates 121 arranged side-by-side among a plurality of first substrates 121 arranged adjacent to each other in the X-axis direction. Each first connection line 181 can be used as a gate line, a light-emitting signal line, a high-potential power line, or a low-potential power line, but is not limited thereto. For example, the first connection line 181 can be used as a gate line and electrically connected to gate pads on two first substrates 121 arranged side-by-side in the X-axis direction. Therefore, as described above, the gate pads on a plurality of first substrates 121 arranged in the X-axis direction can be connected by the first connection line 181 used as a gate line. A single gate voltage can be transmitted to the gate pad.

[0078] Furthermore, the second connection line 182 can connect to pads on two first substrates 121 arranged side-by-side among a plurality of first substrates 121 arranged adjacent to each other in the Y-axis direction. Each second connection line 182 can be used as a data line, a high-potential power line, a low-potential power line, or a reference voltage line, but is not limited thereto. For example, the second connection line 182 can be used as a data line and electrically connect to data lines on two first substrates 121 arranged side-by-side in the Y-axis direction. Therefore, as described above, the internal lines on the plurality of first substrates 121 arranged in the Y-axis direction can be connected by multiple second connection lines 182 used as data lines. A single data voltage can be transmitted to the data line.

[0079] Reference Figure 1 The connecting line 180 may also include a third connecting line, which connects pads on a plurality of first substrates 121 and a plurality of third substrates 123, or connects pads on two third substrates 123 arranged side by side among pads on a plurality of third substrates 123 arranged adjacent to each other in the Y-axis direction.

[0080] like Figure 3 As shown, each first connection line 181 can contact the upper surface and side surface of the planarization layer 146 disposed on the first substrate 121 and can extend to the upper surface of the second substrate 122. Similarly, each second connection line 182 can contact the upper surface and side surface of the planarization layer 146 disposed on the first substrate 121 and can extend to the upper surface of the second substrate 122.

[0081] Reference Figure 3 A dam 147 is formed on the connecting pad PD, the connecting line 180, and the planarization layer 146. The dam 147 is a component that distinguishes adjacent sub-pixels SPX. The dam 147 is configured to cover at least a portion of the pad PD, the connecting line 180, and the planarization layer 146. The dam 147 can be made of an insulating material. Furthermore, the dam 147 can contain a black material. Because the dam 147 contains a black material, it is used to hide lines visible through the display area AA. The dam 147 can be made of, for example, a transparent carbon-based mixture. Specifically, the dam 147 can contain carbon black, but is not limited thereto. The dam 147 can also be made of a transparent insulating material.

[0082] Reference Figure 3 LED 170 is disposed on the connection pad PD and the first connection line 181. LED 170 includes an n-type layer 171, an active layer 172, a p-type layer 173, an n-electrode 174, and a p-electrode 175. The LED 170 of the display device 100 according to an exemplary embodiment of the present disclosure has a flip-chip structure, wherein the n-electrode 174 and the p-electrode 175 are formed on one of its surfaces.

[0083] The n-type layer 171 can be formed by implanting n-type impurities into gallium nitride (GaN) with excellent crystallinity. The n-type layer 171 can be disposed on a separate base substrate made of a light-emitting material.

[0084] An active layer 172 is disposed on the n-type layer 171. The active layer 172 is a light-emitting layer that emits light in the LED 170 and can be made of a nitride semiconductor (e.g., indium gallium nitride (InGaN)). A p-type layer 173 is disposed on the active layer 172. The p-type layer 173 can be formed by implanting p-type impurities into gallium nitride (GaN).

[0085] As described above, the LED 170 according to an exemplary embodiment of this disclosure is formed by sequentially stacking an n-type layer 171, an active layer 172, and a p-type layer 173, and then etching predetermined (or selected) regions of these layers to form an n-electrode 174 and a p-electrode 175. In this case, the predetermined (or selected) region is the space that separates the n-electrode 174 and the p-electrode 175 from each other and is etched to expose a portion of the n-type layer 171. In other words, the surface on top of the LED 170 where the n-electrode 174 and the p-electrode 175 are disposed may not be flat and may be a horizontal plane with different heights.

[0086] The n-electrode 174 is disposed on the etched area, i.e., on the n-type layer 171 exposed by etching. The n-electrode 174 can be made of a conductive material. Meanwhile, the p-electrode 175 is disposed on the unetched area, i.e., on the p-type layer 173. The p-electrode 175 can also be made of a conductive material. For example, the p-electrode 175 can be made of the same material as the n-electrode 174.

[0087] An adhesive layer AD is disposed on the upper surface of the connecting pad PD and the first connecting line 181 and between the connecting pad PD and the first connecting line 181. Therefore, the LED 170 can be bonded to the connecting pad PD and the first connecting line 181. In this case, the n-electrode 174 can be disposed on the first connecting line 181 and the p-electrode 175 can be disposed on the connecting pad PD.

[0088] The adhesive layer AD can be a conductive adhesive layer formed by dispersing conductive balls in an insulating base component. Therefore, when heat or pressure is applied to the adhesive layer AD, the conductive balls are electrically connected to have conductive properties in the portions of the adhesive layer AD where heat or pressure is applied. Furthermore, areas of the adhesive layer AD where no pressure is applied can have insulating properties. For example, the n-electrode 174 is electrically connected to the first connection line 181 via the adhesive layer AD, and the p-electrode 175 is electrically connected to the connection pad PD via the adhesive layer AD. After applying the adhesive layer AD to the upper surfaces of the first connection line 181 and the connection pad PD by means of an inkjet printing method, the LED 170 can be transferred onto the adhesive layer AD. Then, the LED 170 can be pressed and heated, thereby electrically connecting the connection pad PD to the p-electrode 175 and the first connection line 181 to the n-electrode 174. However, the portion of the adhesive layer AD except for the portion between the n-electrode 174 and the first connection line 181 and the portion between the p-electrode 175 and the connection pad PD has insulating properties. Meanwhile, the adhesive layer AD can be individually applied to each of the connecting pads PD and the first connecting line 181.

[0089] Furthermore, the connection pad PD is electrically connected to the drain 164 of the driving transistor 160 and receives the driving voltage for driving the LED 170 from the driving transistor 160. Additionally, a low-potential driving voltage 170 for driving the LED is applied to the first connection line 181. Therefore, when the display device 100 is turned on, different voltage levels applied to each of the connection pad PD and the first connection line 181 are transmitted to the n-electrode 174 and the p-electrode 175. Consequently, the LED 170 emits light.

[0090] Reference Figure 3 The upper substrate 112 is disposed on the embankment 147, the LED 170 and the lower substrate 111.

[0091] The upper substrate 112 is used to support various components disposed below the upper substrate 112. Specifically, the upper substrate 112 can be formed by coating and hardening the material forming the upper substrate 112 on the lower substrate 111 and the first substrate 121. Therefore, the upper substrate 112 can be configured to contact the lower substrate 111, the first substrate 121, the second substrate 122 and the connecting line 180.

[0092] The upper substrate 112 can be made of the same material as the lower substrate 111. For example, the upper substrate 112 can be made of silicone rubber such as polydimethylsiloxane (PDMS) and elastomers such as polyurethane (PU) or polytetrafluoroethylene (PTFE). Therefore, the upper substrate 112 can be flexible. However, the material of the upper substrate 112 is not limited to this.

[0093] At the same time, despite Figure 3 Although not shown, a polarizing layer may also be provided on the upper substrate 112. The polarizing layer polarizes light incident from outside the display device 100 and reduces the reflection of external light. In addition, other optical films may be provided on the upper substrate 112 instead of a polarizing layer.

[0094] <Circuit Structure of Display Area>

[0095] Figure 4 This is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure.

[0096] Hereinafter, for ease of description, the structure and operation of a pixel circuit in which the sub-pixel SPX of a display device according to an exemplary embodiment of the present disclosure is a 2T (transistor) 1C (capacitor) pixel circuit will be described. However, the present disclosure is not limited thereto.

[0097] Reference Figure 3 and Figure 4 In a display device according to an exemplary embodiment of the present disclosure, each sub-pixel SPX may include a switching transistor 150, a driving transistor 160, a storage capacitor C, and an LED 170.

[0098] In response to the strobe signal SCAN provided via the first connection line 181, the switching transistor 150 applies the data signal DATA provided via the second connection line 182 to the driving transistor 160 and the storage capacitor C.

[0099] Furthermore, the gate 151 of the switching transistor 150 is electrically connected to the first connection line 181. Also, the source 153 of the switching transistor 150 is connected to the second connection line 182. Additionally, the drain 154 of the switching transistor 150 is connected to the gate 161 of the driving transistor 160.

[0100] The driving transistor 160 can be operated in response to the data voltage DATA stored in the storage capacitor C, causing a driving current to flow based on the high-potential power supply VDD and the data voltage DATA provided through the first connection line 181.

[0101] Furthermore, the gate 161 of the driving transistor 160 is electrically connected to the drain 154 of the switching transistor 150. Additionally, the source of the driving transistor 160 is connected to the first connection line 181. Moreover, the drain 164 of the driving transistor 160 is connected to the LED 170.

[0102] LED 170 can operate to emit light according to the drive current generated by drive transistor 160. Moreover, as described above, the n electrode 174 of LED 170 can be connected to the first connection line 181, and thus a low potential power supply VSS can be applied. Furthermore, the p electrode 175 of LED 170 can be connected to the drain 164 of drive transistor 160, and thus a drive voltage corresponding to the drive current can be applied.

[0103] As an example, each sub-pixel SPX of the display device according to an exemplary embodiment of this disclosure is configured to have a 2T1C structure including a switching transistor 150, a driving transistor 160, a storage capacitor C, and an LED 170. However, when a compensation circuit is added, each sub-pixel SPX can be configured in various ways such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, or 7T2C.

[0104] As described above, a display device according to an exemplary embodiment of this disclosure may include a plurality of sub-pixels on a first substrate, which is a rigid substrate. Each of the plurality of sub-pixels SPX may include a switching transistor, a driving transistor, a storage capacitor, and an LED.

[0105] Therefore, the display device according to the exemplary embodiments of this disclosure can be stretched due to the lower substrate. Furthermore, each first substrate includes a pixel circuit with a 2T1C structure. Therefore, light can be emitted according to the data voltage at each gating timing.

[0106] In the following, a display device 200 according to another exemplary embodiment of the present disclosure will be described in detail. The display device 200 according to another exemplary embodiment of the present disclosure differs from the display device 100 according to an exemplary embodiment of the present disclosure only in the placement relationship between the plurality of first substrates and the plurality of connecting lines. Therefore, detailed descriptions of components identical to those in the display device according to an exemplary embodiment of the present disclosure will be omitted, and the aforementioned differences will be described in detail.

[0107] <Another exemplary embodiment of this disclosure>

[0108] Figure 5 This is an enlarged plan view of the display area of ​​a display device according to another exemplary embodiment of the present disclosure. Figure 6A and Figure 6B This is an enlarged plan view of the first substrate of a display device according to another exemplary embodiment of the present disclosure. Figure 7 This is a cross-sectional view of a sub-pixel of a display device according to another exemplary embodiment of the present disclosure.

[0109] like Figure 5As shown, in a display device 200 according to another exemplary embodiment of the present disclosure, a plurality of first substrates 221 may have a hexagonal shape or a polygonal shape or a circular shape with more than six sides. A plurality of connecting lines 280 may include a first connecting line 281 extending in a first direction X, a second connecting line 282 extending in a second direction D1, and a third connecting line 283 extending in a third direction D2.

[0110] The first direction X can be defined as the X-axis direction, and each of the second direction D1 and the third direction D2 can be defined as a direction diagonally opposite to the X-axis direction. For example, the first direction X can have a zero angle relative to the X-axis direction. The angle and the second direction D1 can have 60 degrees relative to the X-axis direction. The angle. Furthermore, the third-direction D2 can have a 120° angle relative to the X-axis direction. The angle.

[0111] As described above, the angle between the first direction X and the second direction D1 is the same as the angle between the second direction D1 and the third direction D2. Therefore, the elongation rate of the multiple connecting lines extending in the first direction X, the second direction D1, and the third direction D2 can be consistent in all directions.

[0112] like Figure 6A and Figure 6B Each first substrate 221 may have a hexagonal shape or a polygonal shape or a circular shape with more than six sides.

[0113] For example, such as Figure 6A As shown, each first substrate 221 may have a circular shape. Moreover, a plurality of first connecting lines 281, a plurality of second connecting lines 282, and a plurality of third connecting lines 283 may be connected to the outer circumferential surface of the first substrate 221.

[0114] like Figure 6B As shown, each first substrate 221 may have an octagonal shape, which is another example of a hexagonal shape or a polygonal shape with more than six sides. Moreover, a plurality of first connecting lines 281, a plurality of second connecting lines 282 and a plurality of third connecting lines 283 may be connected to the outer circumferential surface of the first substrate 221.

[0115] Meanwhile, multiple first connecting lines 281 and multiple second connecting lines 282 can be arranged on the same layer. Furthermore, multiple third connecting lines 283 can be arranged on a different layer than the multiple first connecting lines 281 and multiple second connecting lines 282. The multiple third connecting lines 283 can be arranged on a layer above the multiple first connecting lines 281 and multiple second connecting lines 282.

[0116] like Figure 7As shown, the upper insulating layer UI is configured to cover at least a portion of the connection pad PD, the first connection line 281, the second connection line 282, and the planarization layer 146. Similar to the planarization layer 146, the upper insulating layer UI can be formed as an organic insulating layer. More specifically, the upper insulating layer UI can be made of an acrylic-based organic material, but is not limited thereto.

[0117] Furthermore, the third connecting line 283 can be disposed on the upper insulating layer UI. Also, the embankment 147 can be configured to cover the third connecting line 283. Figure 7 The third connection line 183 shown is illustrated as being positioned independently in the cross-sectional view, but is not limited thereto. The third connection line 283 can be connected to the assembly of the switching transistor 150 and the driving transistor 160.

[0118] Furthermore, a first pixel PX1 comprising a plurality of first sub-pixels SPX1 and a second pixel PX2 comprising a plurality of second sub-pixels SPX2 may be provided on the first substrate 221.

[0119] Furthermore, multiple first connection lines 281 are connected to the first pixel PX1 and the second pixel PX2. Only multiple second connection lines 282 can be connected to the first pixel PX1, and only multiple third connection lines 283 can be connected to the second pixel PX2. Multiple first connection lines 281 and multiple second connection lines 282 can be connected to the first pixel PX1, and multiple first connection lines 281 and multiple third connection lines 283 can be connected to the second pixel PX2.

[0120] However, this disclosure is not limited thereto. All of the plurality of first connecting lines 281, the plurality of second connecting lines 282, and the plurality of third connecting lines 283 can be connected to each of the plurality of first pixels PX1 and the plurality of second pixels PX2.

[0121] The plurality of first connection lines 281 may include gating lines, high-potential power lines, and low-potential power lines. Furthermore, each of the plurality of second connection lines 282 and the plurality of third connection lines 283 may be a data line. However, this disclosure is not limited thereto. Depending on the structure of sub-pixels SPX1 and SPX2, the plurality of first connection lines 281 may be used as light-emitting lines. Moreover, depending on the structure of sub-pixels SPX1 and SPX2, each of the plurality of second connection lines 282 and the plurality of third connection lines 283 may be used as a reference voltage line, a sensing line, etc.

[0122] Traditional display devices use a first substrate with a quadrilateral shape. As a result, stress is concentrated at the edges of the quadrilateral first substrate, which leads to damage to the lower stretched substrate when the display device is repeatedly stretched.

[0123] However, in the display device 200 according to another exemplary embodiment of the present disclosure, the plurality of first substrates 221 may have a hexagonal shape or a polygonal shape with more than six sides or a circular shape. Therefore, stress concentrated in the outer region of each first substrate 221 can be reduced. Therefore, even when the display device 200 according to another exemplary embodiment of the present disclosure is repeatedly stretched, components such as the lower stretching substrate will not be damaged. Therefore, the tensile reliability of the display device 200 according to another exemplary embodiment of the present disclosure can be improved.

[0124] Furthermore, in conventional display devices, multiple connecting lines, including the first connecting line and the second connecting line, are arranged vertically, and the number and placement of the connecting lines are limited.

[0125] However, in a display device 200 according to another exemplary embodiment of the present disclosure, the plurality of connecting lines includes a first connecting line 281, a second connecting line 282, and a third connecting line 283 arranged diagonally. Therefore, the display device 200 according to another exemplary embodiment of the present disclosure can include a greater number of connecting lines. Therefore, sub-pixels can be compensated by using additional connecting lines. Furthermore, in the display device 200 according to another exemplary embodiment of the present disclosure, the connecting lines can be arranged in various ways. Therefore, the display device 200 according to another exemplary embodiment of the present disclosure can be stretched uniformly in all directions.

[0126] Furthermore, in a display device 200 according to another exemplary embodiment of this disclosure, a first pixel and a second pixel are disposed on each first substrate 221. Therefore, the number of pixels formed in a single rigid substrate can be increased. Thus, the display device 200 can improve resolution and also increase brightness.

[0127] <Another exemplary embodiment of this disclosure>

[0128] Hereinafter, a display device 300 according to yet another exemplary embodiment of the present disclosure will be described in detail. The display device according to yet another exemplary embodiment of the present disclosure differs from the display device 200 according to another exemplary embodiment of the present disclosure only in the placement of the plurality of connecting lines. Therefore, detailed descriptions of components identical to those in the display device according to another exemplary embodiment of the present disclosure will be omitted, and the aforementioned differences will be described in detail.

[0129] Figure 8 This is an enlarged plan view of the display area of ​​a display device according to yet another exemplary embodiment of the present disclosure.

[0130] like Figure 8As shown, the plurality of first connecting lines 381 may include a first main connecting line 381a and a first sub-connecting line 381b. Furthermore, the plurality of second connecting lines 382 may include a second main connecting line 382a and a second sub-connecting line 382b. Additionally, the plurality of third connecting lines 383 may include a third main connecting line 383a and a third sub-connecting line 383b.

[0131] Each first main connecting line 381a may have a larger cross-sectional area than each first sub-connecting line 381b. Furthermore, each second main connecting line 382a may have a larger cross-sectional area than each second sub-connecting line 382b. Additionally, each third main connecting line 383a may have a larger cross-sectional area than each third sub-connecting line 383b.

[0132] For example, such as Figure 8 As shown, each first main connecting line 381a can have a greater thickness than each first sub-connecting line 381b. Furthermore, each second main connecting line 382a can have a greater thickness than each second sub-connecting line 382b. Additionally, each third main connecting line 383a can have a greater thickness than each third sub-connecting line 383b.

[0133] Therefore, each first main connection line 381a can have a lower line resistance than each first sub-connection line 381b. Furthermore, each second main connection line 382a can have a lower line resistance than each second sub-connection line 382b. Additionally, each third main connection line 383a can have a lower line resistance than each third sub-connection line 383b.

[0134] Therefore, each of the first main connection line 381a, the second main connection line 382a, and the third main connection line 383a can be applied with a high-potential power supply or a low-potential power supply with a relatively high voltage level. Furthermore, each of the first sub-connection line 381b, the second sub-connection line 382b, and the third sub-connection line 383b can be applied with a gate voltage, a data voltage, a reference voltage, and a sensing voltage with a relatively low voltage level.

[0135] As described above, the display device 300 according to yet another exemplary embodiment of the present disclosure may include main connection lines 381a, 382a and 383a with relatively high resistance and sub connection lines 381b, 382b and 383b with relatively low resistance.

[0136] Therefore, in the display device 300 according to yet another exemplary embodiment of this disclosure, main connection lines 381a, 382a, and 383a and sub-connection lines 381b, 382b, and 383b are appropriately provided for voltage levels. Thus, various voltage levels can be provided to multiple pixels.

[0137] Therefore, in a display device 300 according to yet another exemplary embodiment of the present disclosure, pixel circuits can be configured in various forms.

[0138] Embodiments of the present invention can also be described as follows: According to one aspect of this disclosure, a display device includes: a stretchable lower substrate and a plurality of first substrates disposed on the lower substrate and including first pixels and second pixels. The display device further includes a plurality of second substrates configured to connect adjacent first substrates among the plurality of first substrates. The display device further includes a plurality of connecting lines disposed on the plurality of second substrates and configured to connect the first pixels and the second pixels. The plurality of connecting lines includes a plurality of first connecting lines extending in a first direction, a plurality of second connecting lines extending in a second direction, and a plurality of third connecting lines extending in a third direction. Therefore, the resolution of the display device can be improved and it can be stretched uniformly in all directions.

[0139] Each of the plurality of first substrates may have a hexagonal shape or a polygonal shape with more than six sides.

[0140] Each of the plurality of first substrates may have a circular shape.

[0141] The angle between the first direction and the second direction can be 60 degrees. And the angle between the second direction and the third direction can be 60 degrees. And the angle between the third direction and the first direction can be 60. .

[0142] Each of the first pixel and the second pixel may include multiple sub-pixels, and each of the multiple sub-pixels includes a switching transistor, a driving transistor, a storage capacitor, and a light-emitting diode.

[0143] The drain of the switching transistor can be connected to the gate of the driving transistor.

[0144] The storage capacitor may include a gate of a driving transistor, a first interlayer insulating layer disposed on the gate of the driving transistor, and an intermediate metal layer disposed on the first interlayer insulating layer.

[0145] Multiple first connection lines and multiple second connection lines can be set on the same layer, and multiple third connection lines can be set on different layers from multiple first connection lines and multiple second connection lines.

[0146] Multiple first connection lines may include first main connection lines and first sub-connection lines.

[0147] Multiple second connection lines may include second main connection lines and second sub-connection lines.

[0148] Multiple third connection lines may include third main connection lines and third sub-connection lines.

[0149] The line resistance of the first main connection line can be lower than the line resistance of the first sub-connection line.

[0150] The line resistance of the second main connection line can be lower than that of the second sub-connection line.

[0151] The line resistance of the third main connection line can be lower than that of the third sub-connection line.

[0152] At least one of the first main connection line, the second main connection line, and the third main connection line can be supplied with a high-potential power supply or a low-potential power supply.

[0153] At least one of the first sub-connection line, the second sub-connection line, and the third sub-connection line may be subject to a gate voltage or a data voltage.

[0154] According to another aspect of this disclosure, the display device includes a flexible substrate and a plurality of rigid substrates disposed on the flexible substrate. The display device also includes a plurality of pixels formed on each of the plurality of rigid substrates, and a plurality of connecting lines disposed between the plurality of rigid substrates and connected to the plurality of pixels. The plurality of connecting lines may extend in at least three directions.

[0155] Each of the multiple rigid substrates may have a polygonal shape, the number of edges of which is greater than the number of extension directions of the multiple connecting lines.

[0156] When the angles between multiple connecting lines can all be the same.

[0157] Any one of the multiple connection lines can be set on a different layer than another of the multiple connection lines.

[0158] Any one of the multiple connecting lines can have a different line resistance than another of the multiple connecting lines.

[0159] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are exemplary in all respects and are not limiting of the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within the scope equivalent to those claims should be understood to fall within the protection scope of the present invention.

[0160] Cross-reference to related applications

[0161] This application claims priority to Korean Patent Application No. 10-2020-0144678, filed with the Korean Intellectual Property Office on November 2, 2020, the disclosure of which is incorporated herein by reference.

Claims

1. A display device, the display device comprising: Stretchable lower substrate; A plurality of first substrates are disposed on the stretchable lower substrate and include a first pixel and a second pixel; A plurality of second substrates, the plurality of second substrates being configured to connect adjacent first substrates among the plurality of first substrates; as well as Multiple connecting lines are disposed on the multiple second substrates and configured to connect the first pixel and the second pixel. The plurality of connecting lines include a plurality of first connecting lines extending in a first direction, a plurality of second connecting lines extending in a second direction, and a plurality of third connecting lines extending upward in a third direction. The plurality of first connecting lines include a first main connecting line and a first sub-connecting line; the plurality of second connecting lines include a second main connecting line and a second sub-connecting line; and the plurality of third connecting lines include a third main connecting line and a third sub-connecting line. Each of the first main connecting lines has a larger cross-sectional area than each of the first sub-connecting lines, each of the second main connecting lines has a larger cross-sectional area than each of the second sub-connecting lines, and each of the third main connecting lines has a larger cross-sectional area than each of the third sub-connecting lines. The voltage applied to the main connection line is higher than the voltage applied to the sub-connection line corresponding to the main connection line.

2. The display device according to claim 1, in, Each of the plurality of first substrates has a hexagonal shape or a polygonal shape with more than six sides.

3. The display device according to claim 1, in, Each of the plurality of first substrates has a circular shape.

4. The display device according to claim 1, in, The angle between the first direction and the second direction is 60 degrees. ,and The angle between the second direction and the third direction is 60 degrees. ,and The angle between the third direction and the first direction is 60 degrees. .

5. The display device according to claim 1, in, Each of the first pixel and the second pixel includes multiple sub-pixels, and Each of the plurality of sub-pixels includes a switching transistor, a driving transistor, a storage capacitor, and a light-emitting diode.

6. The display device according to claim 5, in, The drain of the switching transistor is connected to the gate of the driving transistor.

7. The display device according to claim 5, in, The storage capacitor includes: The gate of the driving transistor; A first interlayer insulating layer is disposed on the gate of the driving transistor; and An intermediate metal layer is disposed on the first interlayer insulating layer.

8. The display device according to claim 1, in, The plurality of first connecting lines and the plurality of second connecting lines are disposed on the same layer, and The plurality of third connection lines are disposed on a different layer than the plurality of first connection lines and the plurality of second connection lines.

9. The display device according to claim 1, wherein, The line resistance of the first main connection line is lower than the line resistance of the first sub-connection line. The line resistance of the second main connection line is lower than the line resistance of the second sub-connection line, and The line resistance of the third main connection line is lower than the line resistance of the third sub-connection line.

10. The display device according to claim 9, in, At least one of the first main connection line, the second main connection line, and the third main connection line is supplied with a high-potential power supply or a low-potential power supply, and At least one of the first sub-connection line, the second sub-connection line, and the third sub-connection line is subjected to a gate voltage or a data voltage.

11. The display device according to claim 1, wherein, The lower substrate has a display area and a non-display area adjacent to the display area, and the plurality of first substrates are disposed in the display area of ​​the lower substrate.

12. The display device according to claim 11, further comprising a plurality of third substrates disposed in the non-display area of ​​the lower substrate, and having a gate driver and a plurality of pads formed on the plurality of third substrates.

13. A display device comprising: Tough substrate; A plurality of rigid substrates, wherein the plurality of rigid substrates are disposed on the flexible substrate; Multiple pixels, said multiple pixels being formed on each of said multiple rigid substrates; as well as Multiple connecting lines are disposed between the multiple rigid substrates and connected to the multiple pixels. The multiple connecting lines extend in at least three directions. The plurality of connecting lines extending in any one of the at least three directions include main connecting lines and sub-connecting lines. Wherein, each of the main connecting lines extending in any of the at least three directions has a larger cross-sectional area than each of the sub-connecting lines extending in any of the three directions, and The voltage applied to the main connection line is higher than the voltage applied to the sub-connection line corresponding to the main connection line.

14. The display device according to claim 13, in, Each of the plurality of rigid substrates has a polygonal shape, the number of edges of which is greater than the number of extension directions of the plurality of connecting lines.

15. The display device according to claim 13, in, The angles between all the connecting lines are the same.

16. The display device according to claim 13, in, Any one of the multiple connecting lines is placed on a different layer than the other of the multiple connecting lines.

17. The display device according to claim 13, in, Any one of the plurality of connecting lines has a different line resistance than the other of the plurality of connecting lines.

18. The display device according to claim 13, wherein, The tough substrate has a toughness fracture rate of 100% or higher, which refers to the distance the stretched object extends when it breaks or fractures.

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