Display device

Abstract

Display apparatus. An organic light emitting display apparatus is disclosed herein. The organic light emitting display apparatus includes at least one thin film transistor and a light emitting device on a substrate, the light emitting device is spaced apart from a substrate hole, and at least one isolation structure is disposed between the substrate hole and the light emitting device. Each thin film transistor includes a source and a drain, each light emitting device includes a first electrode, a light emitting layer, and a second electrode, the organic light emitting display apparatus includes a connection electrode connecting one of the source and the drain of the thin film transistor to the first electrode of the light emitting device, and a planarization layer is disposed between the thin film transistor and the light emitting device. The isolation structure includes at least one undercut structure, and a depth of each undercut structure is greater than a thickness of the light emitting layer.

Description

Technical Field

[0001] This disclosure relates to a display device including a substrate hole passing through a device substrate. Background Technology

[0002] Typically, electronic devices such as monitors, televisions (TVs), laptops, and digital cameras include display devices that display images. For example, a display device may include multiple light-emitting devices. Each of these multiple light-emitting devices can emit light of a specific color. For example, each light-emitting device may include a light-emitting layer disposed between its first and second electrodes.

[0003] Peripheral devices such as cameras, speakers, and sensors can be embedded in the display device. For example, the display device may include substrate holes passing through a device substrate supporting the light-emitting devices. The substrate holes may be disposed between the light-emitting devices. The peripheral devices can be inserted into the substrate holes.

[0004] However, in display devices, external moisture can seep into the device through the substrate holes. This moisture can then travel through the light-emitting layer towards the light-emitting devices adjacent to the substrate holes. Therefore, in display devices, the light-emitting devices adjacent to the substrate holes may be damaged by the external moisture that seeps in through them. Summary of the Invention

[0005] In order to overcome the above-mentioned problems in the related technologies, this disclosure can provide a display device for preventing the light-emitting device from being damaged by external moisture that seeps in through the substrate holes.

[0006] This disclosure provides a display device that simplifies the process of preventing external moisture from penetrating.

[0007] To achieve these and other advantages and for the purposes of this disclosure, as embodied and broadly described herein, the display device includes a substrate hole through the substrate.

[0008] In embodiments of this disclosure, a display device may include at least one thin-film transistor and a light-emitting device located on a substrate, the light-emitting device being spaced apart from a substrate aperture, and at least one isolation structure being disposed between the substrate aperture and the light-emitting device.

[0009] Each thin-film transistor may include a source and a drain, each light-emitting device may include a first electrode, a light-emitting layer and a second electrode, the display device may include a connection electrode that connects one of the source and drain of the thin-film transistor to the first electrode of the light-emitting device, and a planarization layer may be disposed between the thin-film transistor and the light-emitting device.

[0010] At least one isolation structure may include at least one undercut structure, and the depth of each undercut structure may be greater than the thickness of the light-emitting layer.

[0011] The undercut structure of the isolation structure may include a first structure made of the same material as the planarization layer and a second structure made of the same material as the connecting electrode. Multiple undercut structures may be disposed on the insulating layer.

[0012] The light-emitting layer can be disposed on the second structure of the isolation structure, and the light-emitting layer can be further disposed in an island shape on the insulating layer between multiple isolation structures.

[0013] The island-shaped light-emitting layer has two ends and a central portion arranged on the same horizontal line.

[0014] The island-shaped light-emitting layer has a central portion and two ends, and the two ends can be farther away from the substrate than the central portion of the light-emitting layer.

[0015] At least one thin-film transistor may include a first thin-film transistor and a second thin-film transistor, wherein the semiconductor pattern of the first thin-film transistor may include low-temperature polycrystalline silicon (LTPS) and the semiconductor pattern of the second thin-film transistor may include oxide semiconductor.

[0016] In another embodiment of this disclosure, the substrate may include a substrate hole region and a pixel region. The substrate hole region may include a substrate hole and a hole peripheral region. The pixel region may include a thin film transistor and a light-emitting device. The substrate hole may be disposed between the light-emitting devices. At least one isolation structure may be disposed between the substrate hole and the light-emitting device. The encapsulation portion may be disposed on the pixel region and the isolation structure.

[0017] The light-emitting device may include a first electrode, a light-emitting layer, and a second electrode.

[0018] The encapsulation section may include a first inorganic encapsulation layer, a second organic encapsulation layer, and a third inorganic encapsulation layer.

[0019] The display device may further include a connection electrode that connects one of the source and drain of the thin-film transistor to a first electrode of the light-emitting device, and may further include a planarization layer disposed between the thin-film transistor and the light-emitting device.

[0020] The periphery region of the hole may include an isolation region, and multiple isolation structures may be disposed in the isolation region. The gate insulating layer, interlayer insulating layer and isolation layer of the pixel region may not extend.

[0021] The first inorganic encapsulation layer can cover the side surfaces of each of the gate insulating layer, interlayer insulating layer, and isolation layer exposed between the pixel region and the isolation region in a contact manner. Attached Figure Description

[0022] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings: Figure 1 This is a schematic illustration of a display device according to an embodiment of the present invention; Figure 2 This is an enlarged view of the periphery of a substrate hole in a display device according to an embodiment of the present invention; Figure 3 This is a diagram illustrating a cross-section of a pixel in a display device according to an embodiment of the present disclosure; Figure 4 This is a cross-sectional view illustrating the peripheral region of a substrate hole in a display device according to an embodiment of the present disclosure; Figure 5 yes Figure 4 A magnified view of region 700A; Figure 6 This is a diagram illustrating a display device according to another embodiment of the present invention; Figure 7 yes Figure 6 A magnified view of region 800A; Figure 8 This is a diagram illustrating a display device according to another embodiment of the present invention; Figure 9 This is a diagram illustrating a display device according to another embodiment of the present invention; Figure 10 This is a diagram illustrating a display device according to another embodiment of the present invention; and Figure 11 This is a diagram illustrating a display device according to another embodiment of the present disclosure. Detailed Implementation

[0023] In the following description, the present disclosure will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are illustrated. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make the present disclosure thorough and complete and to fully convey the concept of the present disclosure to those skilled in the art.

[0024] Furthermore, similar reference numerals always refer to similar elements, and for convenience, the length or thickness of a layer or region may be exaggerated in the drawings. Additionally, the description of a first element as being "on" a second element can include cases where the first element is disposed on top of the second element in direct contact, and cases where a third element is disposed between the first and second elements.

[0025] It should be understood that although terms including common numbers such as first or second are used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Moreover, for the convenience of those skilled in the art, the first element and the second element may be referred to freely without departing from the spirit and scope of this disclosure.

[0026] Technical terminology is used only to explain specific exemplary embodiments and is not intended to limit this disclosure. Unless otherwise stated, singular terms may include plural forms. The terms described in the specification should be understood as follows. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include plural forms. The terms “first” and “second” are used to distinguish one element from another, and these elements should not be limited by these terms. It will be further understood that the terms “comprising,” “including,” “having,” “possessing,” “comprise,” and / or “contains,” when used herein, indicate the presence of the mentioned features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0027] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments pertain. It will be further understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0028] Figure 1 This is a schematic illustration of a display device according to an embodiment of the present disclosure. Figure 2 This is an enlarged view of the periphery of a substrate hole in a display device according to an embodiment of the present disclosure. Figure 3 This is a cross-sectional view illustrating a pixel in a display device according to an embodiment of the present disclosure. Figure 4 This is a cross-sectional view illustrating the peripheral region of a substrate hole in a display device according to an embodiment of the present disclosure. Figure 5 yes Figure 4 A magnified view of region 700A.

[0029] Reference Figures 1 to 5 The display device DP according to embodiments of the present disclosure may include a substrate 100.

[0030] The substrate 100 may include multiple pixel regions PA defined by multiple gate lines GL and multiple data lines DL. A light-emitting device 500 may be disposed in each pixel region PA. Each light-emitting device 500 may emit light of a specific color. For example, each light-emitting device 500 may include a first electrode 510, a light-emitting layer 520, and a second electrode 530 sequentially stacked.

[0031] The first electrode 510 may include a conductive material. The first electrode 510 may include a metal with relatively high reflectivity. The first electrode 510 may have a multilayer structure. For example, the first electrode 510 may have the following structure: a reflective electrode including a metal such as aluminum (Al) or silver (Ag) is disposed between transparent electrodes including a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0032] The light-emitting layer 520 can emit light with a brightness corresponding to the voltage difference between the first electrode 510 and the second electrode 520. For example, the light-emitting layer 520 may include a light-emitting material layer (EML) 522 containing a light-emitting material. The light-emitting material may include organic materials, inorganic materials, or mixed materials. For example, the display device DP according to embodiments of the present disclosure may be an organic light-emitting display device including a light-emitting layer 520 containing an organic material.

[0033] The light-emitting layer 520 may have a multilayer structure to improve luminous efficiency. For example, the light-emitting layer 520 may further include at least one first organic layer 521 disposed between the first electrode 510 and the light-emitting material layer 522, and at least one second organic layer 523 disposed between the light-emitting material layer 522 and the second electrode 530. The first organic layer 521 may include at least one of a hole injection layer (HIL) and a hole transport layer (HTL). Moreover, the second organic layer 523 may include at least one of an electron transport layer (ETL) and an electron injection layer (EIL). However, this disclosure is not limited thereto. For example, the first organic layer 521 may include at least one of an electron transport layer (ETL) and an electron injection layer (EIL), and the second organic layer 523 may include at least one of a hole injection layer (HIL) and a hole transport layer (HTL).

[0034] The second electrode 530 may include a conductive material. The second electrode 530 may include a material different from that of the first electrode 510. For example, the second electrode 530 may be a transparent electrode comprising a transparent conductive material such as ITO or IZO. Therefore, in the display device DP according to an embodiment of this disclosure, light emitted from the light-emitting layer 520 of each pixel region PA can be transmitted to the outside through the second electrode 530.

[0035] An encapsulation portion 170 can be formed to cover the light-emitting device 500 to prevent moisture from penetrating into the light-emitting device 500. For example, the encapsulation portion 170 for preventing moisture penetration can be provided on the second electrode 530 of the light-emitting device 500.

[0036] The encapsulation portion 170 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the encapsulation portion 170 may include a first encapsulation layer 171 containing inorganic materials, a second encapsulation layer 172 containing organic materials, and a third encapsulation layer 173 containing inorganic materials. The first encapsulation layer 171 of the encapsulation portion 170 may be disposed on the second electrode 213. Moreover, the second encapsulation layer 172 may be disposed on the first encapsulation layer 171. Moreover, the third encapsulation layer 173 may be disposed on the second encapsulation upper layer 172. The first encapsulation layer 171 and the third encapsulation layer 173 of the encapsulation portion 170 may include inorganic materials such as silicon nitride (SiNx) or silicon oxide (SiOx). The second encapsulation layer 172 of the encapsulation portion 170 may include organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0037] A driving current can be provided to each light-emitting device 500, corresponding to a gating signal applied to it via a corresponding gating line GL and a data signal applied to it via a corresponding data line DL. For example, a driving circuit electrically connected to the corresponding light-emitting device 500 can be provided in each pixel region PA. The driving circuit can control the operation of the corresponding light-emitting device 500 based on the gating signal and the data signal. For example, the driving circuit may include a first thin-film transistor (TFT) 200, a second TFT 300, and a storage capacitor 400.

[0038] The first TFT 200 may include a first semiconductor pattern 210, a first gate insulating layer 220, a first gate 230, a first interlayer insulating layer 240, a first source 250, and a first drain 260.

[0039] The first semiconductor pattern 210 may be disposed close to the substrate 100. The first semiconductor pattern 210 may include a semiconductor material. For example, the first semiconductor pattern 210 may include polycrystalline silicon (poly-Si) as a polycrystalline semiconductor material. In the specification, the first semiconductor pattern 210 may include low-temperature polycrystalline silicon (LTPS).

[0040] The first semiconductor pattern 210 may include a first source region, a second drain region, and a first channel region. The first channel region may be disposed between the first source region and the first drain region. The first channel region may have a relatively low conductivity compared to the conductivity of each of the first source region and the first drain region. For example, the first source region and the first drain region may have a higher conductive impurity content than the first channel region.

[0041] A first gate insulating layer 220 may be disposed on the first semiconductor pattern 210. The first gate insulating layer 220 may extend outward from the first semiconductor pattern 210. The first gate insulating layer 220 may include an insulating material. For example, the first gate insulating layer 220 may include a silicon oxide (SiOx) material. The SiOx material may include silicon dioxide (SiO2).

[0042] The first gate 230 may be disposed on the first gate insulating layer 220. For example, the first gate 230 may overlap with the first channel region of the first semiconductor pattern 210. The first gate 230 may be insulated from the first semiconductor pattern 210 through the first gate insulating layer 220. The first gate 230 may include a conductive material. For example, the first gate 230 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W).

[0043] A first interlayer insulating layer 240 may be disposed on the first gate insulating layer 220 and the first gate 230. The first interlayer insulating layer 240 may extend along the first gate insulating layer 220. The first interlayer insulating layer 240 may include an insulating material. The first interlayer insulating layer 240 may include a material different from that of the first gate insulating layer 220. For example, the first interlayer insulating layer 240 may include a silicon oxide (SiOx) material.

[0044] The first source 250 may be electrically connected to the first source region of the first semiconductor pattern 210. The first interlayer insulating layer 240 may include a first source contact hole that partially exposes the first source region of the first semiconductor pattern 210. The source 250 may include a region that overlaps with the first source region of the first semiconductor pattern 210.

[0045] The first source 250 may include a conductive material. For example, the first source 250 may include a metal such as Al, Cr, Mo, W, Ti, or Cu.

[0046] The first drain 260 may be electrically connected to a first drain region of the first semiconductor pattern 210. The first interlayer insulating layer 240 may include a first drain contact hole that partially exposes the first drain region of the first semiconductor pattern 210. The first drain 260 may include a region that overlaps with the first drain region of the first semiconductor pattern 210.

[0047] The first drain 260 may include a conductive material. For example, the first drain 260 may include a metal such as Al, Cr, Mo, W, Ti, or Cu. The first drain 260 may include the same material as the first source 250. For example, the first drain 260 may be formed in the same process as the first source 250.

[0048] The first source 250 and the first drain 260 can each be formed as a multilayer structure. For example, the first source 250 and the first drain 260 can each be formed as three layers. In the case where each of the first source 250 and the first drain 260 is formed as three layers, the lower layer and the upper layer can each be formed as Ti metal layers, and the intermediate layer disposed between the lower layer and the upper layer can be formed as an Al metal layer.

[0049] The second TFT 300 can be formed using a different process than that used for the first TFT 200. For example, the second TFT 300 can be disposed on the second isolation layer 130 of the first TFT 200. The second isolation layer 130 may include an insulating material. The second isolation layer 130 may include a material different from that of the first interlayer insulating layer 240. For example, the second isolation layer 130 may include a material different from that of the first interlayer insulating layer 240. For example, the second isolation layer 130 may include a silicon nitride (SiNx) material.

[0050] The structure of the second TFT 300 can be the same as that of the first TFT 200. For example, the second TFT 300 may include a second semiconductor pattern 310, a second gate insulating layer 320, a second gate 330, a second interlayer insulating layer 340, a second source 350, and a second drain 360.

[0051] The second semiconductor pattern 310 may be disposed close to the second isolation layer 130. For example, the second semiconductor pattern 310 may directly contact the second isolation layer 130. The second semiconductor pattern 310 may include a semiconductor material. The second semiconductor pattern 310 may include a material different from that of the first semiconductor pattern 210. For example, the second semiconductor pattern 310 may include an oxide semiconductor such as indium gallium zinc oxide (IGZO).

[0052] The second semiconductor pattern 310 may include a second source region, a second drain region, and a second channel region. The second channel region may be disposed between the second source region and the second drain region. The resistance of the second source region and the resistance of the second drain region may be lower than the resistance of the second channel region. For example, the second source region and the second drain region may each be a conductive region. The second channel region may be a non-conductive region.

[0053] The second gate insulating layer 320 may be disposed on the second semiconductor pattern 310. The second gate insulating layer 320 may include an insulating material. For example, the second gate insulating layer 320 may include a SiOx material, a SiNx material, and / or a material with a high dielectric constant (high-k material). The second gate insulating layer 320 may have a multilayer structure.

[0054] The second gate insulating layer 320 may expose the second source region and the second drain region of the second semiconductor pattern 310. The second source region and the second drain region of the second semiconductor pattern 310 may not overlap with the second gate insulating layer 320. For example, the second source region and the second drain region of the second semiconductor pattern 310 may be conductive based on the etching process used in the patterning process of the second gate insulating layer 320.

[0055] The second gate 330 may be disposed on the second gate insulating layer 320. For example, the second gate 330 may overlap with the second channel region of the second semiconductor pattern 310. The second gate 330 may include a conductive material. For example, the second gate 330 may include metals such as Al, Cr, Cu, Ti, Mo, and W. The second gate 330 may include the same material as the first gate 230.

[0056] The second interlayer insulating layer 340 may be disposed on the second semiconductor pattern 310 and the second gate 330. The second interlayer insulating layer 340 may include an insulating material. The second interlayer insulating layer 340 may include a material different from that of the first interlayer insulating layer 240. For example, the second interlayer insulating layer 340 may include a SiNx material.

[0057] The second source 350 may be disposed on the second interlayer insulating layer 340. The second source 350 may be electrically connected to the second source region of the second semiconductor pattern 310. For example, the second interlayer insulating layer 340 may include a second source contact hole that partially exposes the second source region of the second semiconductor pattern 310. The second source 350 may include a region that overlaps with the second source region of the second semiconductor pattern 310.

[0058] The second source 350 may include a conductive material. For example, the second source 350 may include a metal such as Al, Cr, Mo, W, Ti, or Cu. The second source 350 may include the same material as the first source 250.

[0059] The second drain 360 may be disposed on the second interlayer insulating layer 340. The second drain 360 may be electrically connected to the second drain region of the second semiconductor pattern 310. For example, the second interlayer insulating layer 340 may include a second drain contact hole that partially exposes the second drain region of the second semiconductor pattern 310. The second drain 360 may include a region that overlaps with the second drain region of the second semiconductor pattern 310.

[0060] The second drain 360 may include a conductive material. For example, the second drain 360 may include a metal such as Al, Cr, Mo, W, Ti, or Cu. The second drain 360 may include the same material as the second source 350. For example, the second drain 360 may be formed using the same process as the second source 350.

[0061] The second source 350 and the second drain 360 can each be formed in a multilayer structure. For example, the second source 350 and the second drain 360 can each be formed in three layers. In the case where each of the second source 350 and the second drain 360 is formed in three layers, the lower layer and the upper layer can each be formed in Ti metal layer, and the intermediate layer disposed between the lower layer and the upper layer can be formed in Al metal layer.

[0062] The first source 250, the first drain 260, the second source 350, and the second drain 360 can be disposed on the second interlayer insulating layer 340 and can be formed from the same material through the same process.

[0063] The storage capacitor 400 may be formed between the substrate 100 and the second TFT 300. For example, the storage capacitor 400 may include a first storage electrode 410 disposed on the same layer as the first gate 230 and a second storage electrode 420 disposed on a first interlayer insulating layer 240 above the first storage electrode 410.

[0064] The first storage electrode 410 may include a conductive material. The first storage electrode 410 may include a metal such as Al, Cr, Mo, W, Ti, or Cu. The first storage electrode 410 may include the same material as the first gate 230. For example, the first storage electrode 410 may be formed using the same process as the first gate 230.

[0065] The second storage electrode 420 may include a conductive material. The second storage electrode 420 may include a metal such as Al, Cr, Mo, W, Ti, or Cu. The first interlayer insulating layer 240 may extend into the region between the first storage electrode 410 and the second storage electrode 420. The second storage electrode 420 may be disposed on the first interlayer insulating layer 240.

[0066] The first source 250 and the first drain 260 can be disposed on a different layer than the first storage electrode 420. For example, the first isolation layer 120 covering the second storage electrode 420 can extend to the region between the first interlayer insulating layer 240 and the first source 250, and to the region between the first interlayer insulating layer 240 and the first drain 260. The first isolation layer 120 is disposed between the second isolation layer 130 and the first interlayer insulating layer 240.

[0067] The first interlayer insulating layer 240 and the first isolation layer 120 may be sequentially stacked between the first gate 230 and the first source 250 and between the first gate 230 and the first drain 260. The second storage electrode 420 may include a material different from that of each of the first source 250 and the first drain 260.

[0068] The first isolation layer 120 may include an insulating material. For example, the first isolation layer 120 may include SiOx and / or SiNx. The first isolation layer 120 may have a multilayer structure. The first source 250 and the first drain 260 may be disposed on the second interlayer insulating layer 340. However, this disclosure is not limited thereto.

[0069] The first storage electrode 410 may be electrically connected to the second drain 360 of the second TFT 300. For example, the first intermediate electrode 610 passes through the first interlayer insulating layer 240, the first isolation layer 120, the second isolation layer 130, and the second interlayer insulating layer 340. The first intermediate electrode 610 is connected to the first storage electrode 410, and the second drain 360 may be connected to the first intermediate electrode 610. The first intermediate electrode 610 may include a conductive material. For example, the first intermediate electrode 610 may include a metal such as Al, Cr, Mo, W, Ti, or Cu. The first intermediate electrode 610 may include the same material as each of the first source 250, the first drain 260, the second source 350, and the second drain 360. For example, the first intermediate electrode 610 may be formed using the same process as the first source 250, the first drain 260, the second source 350, and the second drain 360.

[0070] A buffer insulating layer 110 may be disposed between the device substrate 100 and the driving circuitry (e.g., TFTs and storage capacitors) of each pixel region PA. The buffer insulating layer 110 prevents contamination caused by the device substrate 100 during the process of forming the driving circuitry. For example, the buffer insulating layer 110 may extend into the region between the device substrate 100 and the first semiconductor pattern 210 of each pixel region PA. The buffer insulating layer 110 may include an insulating material. For example, the buffer insulating layer 110 may include SiOx and / or SiNx materials. The buffer insulating layer 110 may have a multilayer structure. For example, the buffer insulating layer 110 may have a stacked structure of a first buffer insulating layer 111 and a second buffer insulating layer 112, the second buffer insulating layer 112 comprising a material different from that of the first buffer insulating layer 111.

[0071] The first planarization layer 140 and the second planarization layer 150 may be sequentially stacked between the second TFT 300 and the light-emitting device 500 in each pixel region PA. The first planarization layer 140 and the second planarization layer 150 can remove the step height caused by the driving circuitry of each pixel region PA. For example, the surface of the second planarization layer 150 facing the light-emitting device 500 in each pixel region PA may be a flat surface. The first planarization layer 140 and the second planarization layer 150 may include an insulating material. The first planarization layer 140 and the second planarization layer 150 may include a material different from the material of the second interlayer insulating layer 340. For example, the first planarization layer 140 and the second planarization layer 150 may include an organic insulating material. The second planarization layer 150 may include a material different from the material of the first planarization layer 140.

[0072] The light-emitting device 500 of each pixel region PA can be electrically connected to the first TFT 200 of the corresponding pixel region PA, and the first electrode 510 can be electrically connected to the first drain 260 through the first connection electrode 620. For example, the first connection electrode 620 can be disposed between the first planarization layer 140 and the second planarization layer 150. The first connection electrode 620 can pass through the first planarization layer 140 and can be connected to the first drain 260, and the first electrode 510 can pass through the second planarization layer 150 and can be connected to the first connection electrode 620.

[0073] The first connecting electrode 620 may include a conductive material. For example, the first connecting electrode 620 may include a metal such as Al, Cr, Mo, W, Ti, or Cu.

[0074] The light-emitting device 500 of each pixel region PA can be driven independently. For example, the first electrode 510 of each pixel region PA can be insulated from the first electrode 510 of adjacent pixel regions PA. The edge of each first electrode 510 can be covered by a dam / spacer insulating layer 160 including a dam insulating layer 161 and a spacer insulating layer 162. The dam / spacer insulating layer 160 can be disposed on the second planarization layer 150. The light-emitting layer 520 and the second electrode 530 of each pixel region PA can be stacked on the corresponding first electrode 510 exposed through the dam / spacer insulating layer 160. The dam / spacer insulating layer 160 can include an insulating material. For example, the dam / spacer insulating layer 160 can include an organic insulating material. The dam / spacer insulating layer 160 can include a material different from the material of the second planarization layer 150.

[0075] At least a portion of the light-emitting layer 520 of each pixel region PA may extend into the dike / spacer insulating layer 160. For example, the first organic layer 521 and the second organic layer 523 of each pixel region PA may be connected to the first organic layer 521 and the second organic layer 523 of adjacent pixel region PAs. The light-emitting material layer 522 of each pixel region PA may be spaced apart from the light-emitting material layers 522 of adjacent pixel region PAs. The second electrode 530 of each pixel region PA may extend into the dike / spacer insulating layer 160. For example, the second electrode 530 of each pixel region PA may be connected to the second electrode 530 of adjacent pixel region PAs.

[0076] According to embodiments of this disclosure, the first TFT 200 can perform the function of driving a transistor. Therefore, the first electrode 510 of the light-emitting device 500 can be connected to the first TFT 200, but is not limited thereto. For example, the first electrode 510 of the light-emitting device 500 can be connected to the second TFT 300. Moreover, the second TFT 300 can perform the function of driving a transistor.

[0077] A substrate hole CH can be formed in the device substrate 100. The substrate hole CH can pass through the device substrate 100. The substrate hole CH can be disposed between pixel regions PA. For example, the substrate hole CH can be formed between light-emitting devices 500. The device substrate 100 may include a periphery region HA, which includes the area where the substrate hole CH is formed. The light-emitting devices 500 can be disposed outside the periphery region HA. In the periphery region HA, the gate line GL and the data line DL can bypass the edge of the substrate hole CH.

[0078] The periphery region HA may include an isolation region SA surrounding the through region CA on which the substrate hole CH is formed. For example, the isolation region SA may be disposed between the through region CA and the pixel region PA.

[0079] At least one isolation structure 700A and a dam 900 may be disposed in the isolation zone SA. In each isolation structure 700A, a first structure 710 and a second structure 720 may be sequentially stacked and disposed. For example, the first structure 710 may include the same material as the first planarization layer 140, and the second structure 720 may include the same material as the first connecting electrode 620.

[0080] The upper region of the first structure 710 that contacts the second structure 720 may be formed to be smaller than the lower region of the second structure 720 that contacts the first structure 710. For example, based on the width (x1) difference between the first structure 710 and the second structure 720, the isolation structure 700A may include an undercut structure.

[0081] Each undercut structure may have a depth h1 that is the same as the thickness of the corresponding first structure 710. For example, the depth h1 of the undercut structure formed by the first structure 710 and the second structure 720 may be the same as the thickness of the first structure 710. The depth h1 of the undercut structure may be greater than the thickness of the light-emitting layer 520 extending into the periphery region HA of the aperture. For example, the depth h1 of each undercut structure may be greater than the sum of the thickness of the first organic layer 521 and the thickness of the second organic layer 523.

[0082] Therefore, in the organic light-emitting display device according to the embodiments of the present disclosure, the light-emitting layer 520 deposited on the isolation region SA can be completely isolated by the isolation structure 700A. For example, the first organic layer 521 and the second organic layer 523 of the light-emitting layer 520 can be completely isolated from each other by the isolation structure 700A. Therefore, in the display device according to the embodiments of the present disclosure, external moisture can be prevented from penetrating through the light-emitting layer 520 by the isolation structure 700A.

[0083] Furthermore, in the organic light-emitting display device according to the embodiments of this disclosure, the isolation structure 700A disposed between the dam 900 and the through region CA can prevent the dam 900 and the second encapsulation layer 172 including organic material from being diffused into the through region CA. Therefore, the thin film layer including organic material may not be disposed in the through region CA, thereby facilitating the laser trimming process for forming substrate holes CH. The isolation structure 700A can be formed by the process of forming the first TFT 200 and the second TFT 300 and the process of forming the light-emitting device 500. For example, the process of forming the isolation structure 700A may include etching the second insulating buffer layer 112, the first gate insulating layer 220, the first interlayer insulating layer 240, the first isolation layer 120, the second isolation layer 130, and the second interlayer insulating layer 340 in the isolation region SA using the mask pattern of the process of forming the first source contact hole and the second source contact hole, as well as the first drain contact hole and the second drain contact hole.

[0084] Multiple isolation structures 700A disposed in the isolation region SA can be removed by an etching process, and then the multiple isolation structures 700A can be placed on the remaining first buffer insulating layer 111. The light-emitting layer 5207 isolated by the multiple isolation structures 700A disposed in the isolation region SA can be arranged in an island shape on the first buffer insulating layer 111 exposed between the isolation structures 700A.

[0085] The island-shaped isolated light-emitting layer 5207 can extend along the same horizontal line as the device substrate 100. For example, the two ends 7E and the central portion 7C of the isolated light-emitting layer 5207 can be disposed on the same horizontal line.

[0086] The light-emitting device 500 and at least one isolation structure 700A can be covered and protected by the encapsulation portion 170. For example, to prevent moisture from penetrating into the light-emitting device 500 disposed in the pixel region PA, the encapsulation portion 170 can extend and be stacked on the isolation structure 700A disposed in the isolation region SA. The side surfaces of each of the second buffer insulating layer 112, the first gate insulating layer 220, the first interlayer insulating layer 240, the first isolation layer 120, the second isolation layer 130, and the second interlayer insulating layer 340 exposed by an etching process between the isolation region SA and the pixel region PA can contact the first encapsulation layer 171, which includes inorganic materials.

[0087] Reference Figure 6 and Figure 7 This illustrates another embodiment of a different isolation structure for a display device DP according to the present disclosure. The configuration of the first TFT 200, the second TFT 300, and the light-emitting device 500 in the pixel region PA can be... Figures 1 to 3 The configurations are basically the same.

[0088] At least one isolation structure 800A and dam section 900 can be installed Figure 6 and Figure 7 In the isolation region SA. Each isolation structure 800A may include a first structure 810 and a second structure 820 sequentially stacked and arranged. For example, the first structure 810 may include the same material as the first planarization layer 140, and the second structure 820 may include the same material as the first connection electrode 620.

[0089] The upper region of the first structure 810 that contacts the second structure 820 may be smaller than the lower region of the second structure 820 that contacts the first structure 810. For example, based on the width (x2) difference between the first structure 810 and the second structure 820, the isolation structure 800A may include an undercut structure.

[0090] Each undercut structure may have a depth h2 that is the same as the thickness of the corresponding first structure 810. For example, the depth h2 of the undercut structure formed by the first structure 810 and the second structure 820 may be the same as the thickness of the first structure 810. The depth h2 of the undercut structure may be greater than the thickness of the light-emitting layer 520 extending into the periphery region HA of the aperture. For example, the depth h2 of each undercut structure may be greater than the sum of the thickness of the first organic layer 521 and the thickness of the second organic layer 523.

[0091] Therefore, in the organic light-emitting display device according to the embodiments of the present disclosure, the light-emitting layer 520 deposited on the isolation region SA can be completely isolated by the isolation structure 800A. For example, the first organic layer 521 and the second organic layer 523 of the light-emitting layer 520 can be completely isolated from each other by the isolation structure 800A. Therefore, in the display device according to the embodiments of the present disclosure, external moisture can be prevented from penetrating through the light-emitting layer 520 by the isolation structure 800A.

[0092] The isolation structure 800A can be formed by the process of forming the first TFT 200 and the second TFT 300 and the process of forming the light-emitting device 500. For example, the process of forming the isolation structure 800A may include etching the second insulating buffer layer 112, the first gate insulating layer 220, the first interlayer insulating layer 240, the first isolation layer 120, the second isolation layer 130 and the second interlayer insulating layer 340 in the isolation region SA by using the mask pattern of the process of forming the first source contact hole and the second source contact hole, as well as the first drain contact hole and the second drain contact hole.

[0093] Multiple isolation structures 800A disposed in the isolation region SA can be removed by an etching process, and then the multiple isolation structures 800A can be placed on the remaining first buffer insulating layer 111. For example, the light-emitting layer 5208 isolated by the multiple isolation structures 800A disposed in the isolation region SA can be arranged in an island shape on the first buffer insulating layer 111 exposed between the isolation structures 800A.

[0094] The island-shaped isolated light-emitting layer 5208 can extend along the same horizontal line as the device substrate 100. For example, the isolated light-emitting layer 5208 can be stacked in a curved shape, and the two ends 8E of the light-emitting layer 5208 on the vertical line can be located further away from the device substrate 100 than the central portion 8C of the light-emitting layer 5208.

[0095] The light-emitting device 500 and at least one isolation structure 800A can be covered and protected by the encapsulation portion 170. For example, to prevent moisture from penetrating into the light-emitting device 500 disposed in the pixel region PA, the encapsulation portion 170 can extend and be stacked on the isolation structure 800A disposed in the isolation region SA. The side surfaces of each of the second buffer insulating layer 112, the first gate insulating layer 220, the first interlayer insulating layer 240, the first isolation layer 120, the second isolation layer 130, and the second interlayer insulating layer 340 exposed by an etching process between the isolation region SA and the pixel region PA can contact the first encapsulation layer 171 comprising inorganic material.

[0096] Reference Figure 8 and Figure 9This illustrates another embodiment of a different isolation structure for a display device DP according to the present disclosure. The configuration of the first TFT 200, the second TFT 300, and the light-emitting device 500 in the pixel region PA can be... Figures 1 to 3 The configurations are basically the same. Furthermore, the shape of each of the first and second structures of the isolation device can be similar to... Figure 5 and Figure 7 They are basically the same.

[0097] Multiple isolation structures disposed in the isolation zone SA can be disposed on the second interlayer insulating layer 340. For example, multiple light-emitting layers 5207 and 5208 isolated by the multiple isolation structures disposed in the isolation zone SA can be arranged in an island shape on the second interlayer insulating layer 340 exposed between the isolation structures.

[0098] Reference Figure 10 and Figure 11 This illustrates another embodiment of a different isolation structure for a display device DP according to the present disclosure. The configuration of the first TFT 200, the second TFT 300, and the light-emitting device 500 in the pixel region PA can be... Figures 1 to 3 The configurations are basically the same. Furthermore, the shape of each of the first and second structures of the isolation device can be similar to... Figure 5 and Figure 7 They are essentially the same. Furthermore, the isolation structure according to this embodiment can have… Figure 4 and Figure 8 or Figure 6 and Figure 9 The connection structure. For example, the isolation structure between the dam 900 and the pixel area PA can be disposed on one of the first buffer insulating layer 111 and the second interlayer insulating layer 340, and the isolation structure between the dam 900 and the through area CA can be disposed on one of the first buffer insulating layer 111 and the second interlayer insulating layer 340.

[0099] Therefore, in the display device DP according to the present disclosure, at least one isolation structure 700 can be provided in the through region CA where the substrate hole CH is formed and the isolation region SA provided between the pixel regions PA. Each isolation structure 700 can include at least one undercut structure, and the depth of each undercut structure can be greater than the thickness of the light-emitting layer 520 of the light-emitting device 500 provided in each pixel region PA. Therefore, in the display device DP according to the present disclosure, the light-emitting layer 520 can be completely isolated by the isolation structures 700A and 800A. That is, in the display device DP according to the present disclosure, damage to the light-emitting device 500 caused by external moisture penetrating through the substrate hole CH can be effectively prevented. Moreover, in the display device DP according to the present disclosure, the isolation structures 700A and 800A can be formed by using the process of forming the driving circuit and the light-emitting device 500 in each pixel region PA. Therefore, in the display device DP according to the present disclosure, the reduction in process efficiency caused by the process of forming the isolation structures 700A and 800A can be prevented.

[0100] In the display device according to the present disclosure, at least one isolation structure may be disposed between a substrate aperture and a plurality of light-emitting devices. Each light-emitting device may include a light-emitting layer disposed between a first electrode and a second electrode of the light-emitting device. Each of the at least one isolation structure may have at least one undercut structure, and the depth of each of the at least one undercut structure may be greater than the thickness of the light-emitting layer. Therefore, in the display device according to the present disclosure, the isolation structure can block the movement path of external moisture that seeps in through the substrate aperture. Therefore, in the display device according to the present disclosure, the lifespan and reliability of the light-emitting devices can be improved.

[0101] The effects of this disclosure are not limited to the examples above, and various other effects may be included in the specification.

[0102] Although this disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as defined by the following claims.

[0103] Cross-references to related applications

[0104] This application claims priority to Korean Patent Application No. 10-2020-0142879, filed on October 30, 2020, which is incorporated herein by reference as if fully set forth herein.

Claims

1. A display device, the display device comprising: A substrate hole that passes through the substrate; At least one thin-film transistor disposed on the substrate; A light-emitting device is disposed on the substrate and spaced apart from the substrate hole, the light-emitting device including a first electrode, a light-emitting layer and a second electrode; A planarization layer is disposed between the at least one thin-film transistor and the light-emitting device; Multiple isolation structures are disposed between the substrate hole and the light-emitting device; as well as A connection electrode is provided that connects the at least one thin-film transistor to the first electrode. in, Each of the plurality of isolation structures includes a first structure and a second structure. The first structure comprises the same material as the planarization layer, and the second structure is on the same layer as the connection electrode, and the second structure is disposed on the upper surface of the first structure. The width of the second structure is wider than the width of the first structure to define at least one undercut structure. The first height, defined by the distance between the upper and lower surfaces of the first structure, is greater than the second height, defined by the distance between the upper and lower surfaces of the second structure, and The first height is greater than the thickness of the light-emitting layer.

2. The display device according to claim 1, wherein, The second structure comprises the same material as the connecting electrode.

3. The display device according to claim 1, further comprising an insulating layer on the substrate, in, The plurality of isolation structures are arranged on the insulating layer.

4. The display device according to claim 1, wherein, The light-emitting layer is disposed on the second structure of the plurality of isolation structures.

5. The display device according to claim 3, wherein, The light-emitting layer is further arranged in an island-like configuration on the insulating layer exposed between the plurality of isolation structures.

6. The display device according to claim 5, wherein, The island-shaped light-emitting layer has two ends and a central portion disposed on the same horizontal line.

7. The display device according to claim 5, wherein, The island-shaped light-emitting layer has a central portion and two ends, and Compared to the central portion of the light-emitting layer, the two ends are farther from the substrate.

8. The display device according to claim 1, wherein, The at least one thin-film transistor includes a first thin-film transistor and a second thin-film transistor, and The semiconductor pattern of the first thin-film transistor comprises low-temperature polycrystalline silicon, and the semiconductor pattern of the second thin-film transistor comprises oxide semiconductor.

9. The display device according to claim 1, wherein, The at least one undercut structure has the same depth as the corresponding first structure.

10. A display device, the display device comprising: A substrate, the substrate including a substrate hole region and a pixel region; A thin-film transistor and a light-emitting device, wherein the thin-film transistor and the light-emitting device are disposed in each pixel of the pixel region; A planarization layer is disposed between the thin-film transistor and the light-emitting device; A connecting electrode that connects the thin-film transistor to the light-emitting device; A substrate hole is disposed in the substrate hole region; Multiple isolation structures are disposed between the substrate hole and the pixel region; as well as An encapsulation portion is disposed on the light-emitting device and the plurality of isolation structures. Each of the plurality of isolation structures includes a first structure and a second structure that are connected to each other to configure the undercut structure. The planarization layer includes a first planarization layer and a second planarization layer on the first planarization layer, and The first structure comprises the same material as the first planarization layer, and the second structure is on the same layer as the connecting electrode.

11. The display device according to claim 10, wherein, The thin-film transistor includes: Active layer; Gate; A gate insulating layer, wherein the gate insulating layer is located between the active layer and the gate; Source and drain; and An interlayer insulating layer and an isolation layer are disposed between the gate insulating layer and the source and drain electrodes. The light-emitting device includes a first electrode, a light-emitting layer, and a second electrode. The encapsulation section includes a first encapsulation layer containing inorganic materials, a second encapsulation layer containing organic materials, and a third encapsulation layer containing inorganic materials.

12. The display device according to claim 11, in, The connection electrode connects one of the source and drain electrodes of the thin-film transistor to the first electrode of the light-emitting device; and The second planarization layer is located between the connecting electrode and the light-emitting device.

13. The display device according to claim 12, wherein, The substrate hole region includes the hole periphery region. The area surrounding the hole includes an isolation zone. The plurality of isolation structures are arranged in the isolation zone, and The gate insulating layer, the interlayer insulating layer, and the isolation layer in the pixel region do not extend into the isolation region.

14. The display device according to claim 13, wherein, The first encapsulation layer covers, in a contact manner, the side surface of each of the gate insulating layer, the interlayer insulating layer, and the isolation layer exposed between the pixel region and the isolation region.

15. The display device according to claim 10, wherein, The upper region of the first structure that contacts the second structure is formed to be smaller than the lower region of the second structure that contacts the first structure, and the undercut structure is formed based on the width difference between the first structure and the second structure.

16. The display device according to claim 10, wherein, Each undercut structure has the same depth as the corresponding first structure.

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