Display device

Abstract

A display device is provided. The display device includes a first substrate; a first charge trap film disposed on the first substrate and including silicon nitride; a semiconductor layer disposed on the first charge trap film and including a first active layer of a first transistor and a second active layer of a second transistor; and a light emitting element electrically connected to the first transistor, a ratio of a content of Si element with respect to a content of N element of the first charge trap film being in a range of 1.6 to 2.5.

Description

Technical Field

[0001] This invention relates to display devices. Background Technology

[0002] Electronic devices that provide images to users, such as smartphones, tablet PCs, digital cameras, laptops, navigators, and smart TVs, include display devices used to display images.

[0003] The display device can be a flat panel display device such as a liquid crystal display device, a field emission display device, or an organic light-emitting display device. Among these flat panel display devices, organic light-emitting display devices include light-emitting elements in which each pixel of the display panel emits its own light, so images can be displayed even without a backlight unit that provides light to the display panel. Summary of the Invention

[0004] The problem to be solved by the present invention is to provide a display device that improves the element characteristics of a semiconductor element used to drive a light-emitting element.

[0005] The subject matter of this invention is not limited to the subject matter mentioned above, and those skilled in the art should be able to clearly understand other technical subject matter not mentioned from the following description.

[0006] An embodiment of a display device for addressing the aforementioned problem includes: a first substrate; a first charge trapping film disposed on the first substrate and comprising silicon nitride; a semiconductor layer disposed on the first charge trapping film and comprising a first active layer of a first transistor and a second active layer of a second transistor; and a light-emitting element electrically connected to the first transistor, wherein the ratio of Si content to N content in the first charge trapping film is in the range of 1.6 to 2.5.

[0007] It is possible that the Si element content of the first charge trapping film is in the range of 60 at% to 70 at% and the N element content of the first charge trapping film is in the range of 25 at% to 35 at%.

[0008] Alternatively, the Si and N element contents can be analyzed using energy dispersion x-ray spectrometry (EDS).

[0009] It is possible that the Si-H binding ratio of the first charge trapping film is in the range of 8 at% to 15 at%.

[0010] It is possible that the ratio of Si-H binding to NH binding in the first charge trapping film is in the range of 8 to 15.

[0011] It is possible that the NH binding rate of the first charge trapping film is in the range of 0.1 at% to 15 at%.

[0012] It is possible that the first charge trap film is formed under conditions of free ammonia (NH3 free).

[0013] It is possible that the refractive index of the first charge trap film is in the range of 2.3 to 3.0.

[0014] Alternatively, the display device may further include: a second charge trapping film disposed between the first charge trapping film and the semiconductor layer and comprising silicon oxide, wherein the NH binding ratio of the second charge trapping film is in the range of 0.7 at% to 1.5 at%.

[0015] Alternatively, the display device may further include: a second substrate disposed on the first substrate, wherein the second substrate is disposed between the first substrate and the first charge trapping film.

[0016] Alternatively, the display device may further include a lower semiconductor layer disposed between the first substrate and the second substrate.

[0017] Alternatively, the display device may further include: a second substrate disposed on the first substrate, wherein the first charge trapping film is disposed between the first substrate and the second substrate.

[0018] Alternatively, the first charge trapping film may overlap with the first active layer but not with the second active layer.

[0019] Alternatively, the first charge trapping film may include an opening extending through the thickness direction, the opening at least overlapping the channel region of the second transistor.

[0020] Alternatively, the display device may further include a light-emitting element, wherein the first transistor controls a drive current flowing from a first electrode to a second electrode based on a voltage applied to the gate electrode of the first transistor, the second transistor is disposed between the gate electrode of the first transistor and the second electrode of the first transistor, and the light-emitting element is electrically connected to the second electrode of the first transistor and emits light according to the drive current.

[0021] An embodiment of a display device for addressing the aforementioned problem includes: a first substrate; a first charge trapping film disposed on the first substrate and comprising silicon nitride; a second substrate disposed on the first substrate and having the first charge trapping film disposed between the first substrate and the second substrate; a second charge trapping film disposed on the second substrate and comprising silicon oxide; a semiconductor layer disposed on the second charge trapping film and comprising a first active layer of a first transistor and a second active layer of a second transistor; and a light-emitting element electrically connected to the first transistor, wherein the NH binding ratio of the second charge trapping film is in the range of 0.7 at% to 1.5 at%.

[0022] Alternatively, the first charge trapping film may overlap with the first active layer but not with the second active layer.

[0023] It is possible that the ratio of Si content to N content in the first charge trapping film is in the range of 1.6 to 2.5.

[0024] An embodiment of a display device for addressing the aforementioned problem includes: a first substrate; a first charge trapping film disposed on the first substrate and comprising silicon nitride; a semiconductor layer disposed on the first charge trapping film and comprising a first active layer of a first transistor and a second active layer of a second transistor; and a light-emitting element electrically connected to the first transistor, wherein the Si content of the first charge trapping film is in the range of 60 at% to 70 at% and the N content of the first charge trapping film is in the range of 25 at% to 35 at%.

[0025] Alternatively, the first charge trapping film may overlap with the first active layer but not with the second active layer.

[0026] Specific details of other embodiments are included in the detailed description and accompanying drawings.

[0027] (Invention Effects)

[0028] According to one embodiment of the display device, the element characteristics of the semiconductor element used to drive the light-emitting element can be improved.

[0029] The effects involved in each embodiment are not limited to those illustrated above, and more effects are included in this specification. Attached Figure Description

[0030] Figure 1 This is a plan view of a display device according to an embodiment.

[0031] Figure 2 yes Figure 1The side view of the display device shows the side shape of the display device when it is bent in the thickness direction.

[0032] Figure 3 This is a circuit diagram illustrating in detail a pixel involved in one embodiment.

[0033] Figure 4 This is a layout diagram of the pixels of a display device according to one embodiment.

[0034] Figure 5 This is a layout diagram of the first charge trapping film, semiconductor layer, and first conductive layer of a display device according to an embodiment.

[0035] Figure 6 This is a layout diagram of the second charge trapping film, semiconductor layer, and first conductive layer of a display device according to an embodiment.

[0036] Figure 7 It is along Figure 4 A sectional view taken from line VII-VII′.

[0037] Figure 8 Indicates along Figure 4 A portion of the sectional view taken by line VIII-VIII′.

[0038] Figure 9 This represents the spin density related to the amount of ammonia (NH3) introduced during the formation of the first charge trapping film according to one embodiment.

[0039] Figure 10 This is a graph showing the drive current related to the data voltage of the first transistor in one embodiment.

[0040] Figure 11 It is a graph that measures the change in the driving range of the first transistor, ΔDR1, in relation to the configuration of the first charge trapping film and the second charge trapping film according to an embodiment.

[0041] Figure 12 This is a graph showing the drive current associated with the gate voltage of the third transistor in one embodiment.

[0042] Figure 13 It is a graph that measures the threshold voltage change ΔVth of a third transistor in relation to the configuration of a first charge trapping membrane and a second charge trapping membrane in one embodiment.

[0043] Figure 14 This is a cross-sectional view of a display device involved in other embodiments.

[0044] Figure 15 This is a cross-sectional view of a display device according to yet another embodiment.

[0045] (Symbol Explanation)

[0046] 1: Display device; 10: Display panel; SUB1: First substrate; BA1: First barrier layer; AI1: First charge trapping film; SUB2: Second substrate; BA2: Second barrier layer; BF: Buffer layer; AI2: Second charge trapping film; 100: Semiconductor layer; 200: First conductive layer; 300: Second conductive layer; 400: Third conductive layer; 500: Fourth conductive layer; 600: Fifth conductive layer. Detailed Implementation

[0047] References and Appendix Figure 1 As will become clear from the detailed description of the embodiments described below, the advantages, features, and methods of achieving these advantages and features of the invention will become apparent. However, the invention is not limited to the embodiments disclosed below and may be implemented in various forms. The embodiments are provided merely to complete the disclosure of the invention and to fully inform those skilled in the art of the scope of the invention. The invention should be defined only by the scope of the claims.

[0048] The presence of elements or layers on other elements or layers includes not only cases where they are directly on other elements, but also cases where other layers or elements exist between them. Throughout the specification, the same symbol refers to the same constituent element.

[0049] Although terms such as "first" and "second" are used to describe the constituent elements, the constituent elements are certainly not limited to these terms. These terms are used only for the purpose of distinguishing one constituent element from the others. Therefore, within the technical concept of this invention, the "first constituent element" mentioned below can certainly also be a "second constituent element."

[0050] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0051] Figure 1 This is a plan view of a display device according to an embodiment. Figure 2 yes Figure 1 Side view of the display device. Figure 2 The side shape of the display device when it is bent in the thickness direction.

[0052] Display device 1 is a device for displaying dynamic or static images. Display device 1 can be used not only as a display screen for portable electronic devices such as mobile phones, smartphones, tablet PCs (Personal Computers), smartwatches, watch phones, mobile communication terminals, electronic manuals, e-books, PMPs (Portable Multimedia Players), navigators, UMPCs (Ultra Mobile PCs), etc., but also as a display screen for various products such as televisions, laptops, displays, advertising boards, and the Internet of Things.

[0053] One embodiment of the display device 1 may be formed in a substantially rectangular shape on a plane. The display device 1 may be a rectangle with vertical corners on the plane. However, it is not limited to this; the display device 1 may be a rectangular shape with rounded corners on the plane.

[0054] In the accompanying drawings, the first direction DR1 represents the horizontal direction of the display device 1 in a plan view, and the second direction DR2 represents the vertical direction of the display device 1 in a plan view. Furthermore, the third direction DR3 represents the thickness direction of the display device 1. The first direction DR1 and the second direction DR2 intersect each other perpendicularly, and the third direction DR3 is the direction that intersects the plane containing both the first direction DR1 and the second direction DR2, and intersects both the first direction DR1 and the second direction DR2 perpendicularly. However, it should be understood that the directions mentioned in the embodiments are relative directions, and the embodiments are not limited to the mentioned directions.

[0055] Unless otherwise defined, in this specification, “upper,” “upper surface,” and “upper side,” as indicated by a third-party reference DR3, refer to the display surface side based on the display panel 10, while “lower,” “lower surface,” and “lower side” refer to the opposite side of the display surface based on the display panel 10.

[0056] Reference Figure 1 and Figure 2 The display device 1 may include a display panel 10. The display panel 10 may be a flexible substrate comprising a flexible polymer material such as polyimide. Thus, the display panel 10 can be bent, folded, rolled up.

[0057] Display panel 10 may be an organic light-emitting display panel. In the following embodiments, an organic light-emitting display panel is used as an example of display panel 10, but it is not limited to this. Other types of display panels, such as liquid crystal displays (LCDs), quantum dot organic light-emitting display panels (QD-OLEDs), quantum dot liquid crystal displays (QD-LCDs), quantum dot nano light-emitting display panels (nano NEDs), and micro LEDs, may also be used.

[0058] The display panel 10 may include a display area DA for displaying the image and a non-display area NDA that does not display anything. The display panel 10 may be divided into the display area DA and the non-display area NDA in a plan view. The non-display area NDA may be configured to surround the display area DA. The non-display area NDA may form a border.

[0059] The display area DA can be a rectangular shape with vertical corners or a rectangular shape with rounded corners on a plane. However, the planar shape of the display area DA is not limited to a rectangle; it can be circular, elliptical, or various other shapes.

[0060] The display area DA may include multiple pixels. These pixels may be arranged in a matrix. Each pixel may include a light-emitting layer and a circuit layer that controls the amount of light emitted by the light-emitting layer. The circuit layer may include wiring, electrodes, and at least one transistor. The light-emitting layer may include an organic light-emitting material. The light-emitting layer may be sealed with an encapsulation film. The specific structure of the pixels will be described later.

[0061] The non-display area NDA can surround all the edges of the display area DA and form the border of the display area DA. However, it is not limited to this.

[0062] The display panel 10 may include a main region MA and a curved region BD connected to one side of the main region MA in a second direction DR2. The display panel 10 may also include a sub-region SA connected to the curved region BD in the second direction DR2 and curved in the thickness direction, overlapping the main region MA in the thickness direction.

[0063] The display area DA can be located within the main area MA. The non-display area NDA can be located at the peripheral edge of the display area DA within the main area MA.

[0064] The main region MA can have a shape similar to that of the display device 1 in a plane. The main region MA can be a flat area located in a plane. However, it is not limited to this, and at least one of the edges of the main region MA other than the edge (edge) connected to the curved region BD can be bent to form a curved surface or bent in the vertical direction.

[0065] In the case where at least one of the edges in the main region MA, excluding the edge (edge) connected to the curved region BD, forms a curved surface or is bent, a display region DA may also be configured on the corresponding edge. However, this is not a limitation; the curved or bent edge may also be configured with a non-display region NDA that does not display an image, or both a display region DA and a non-display region NDA may be configured.

[0066] The non-display area NDA of the main area MA can extend from the outer boundary of the display area DA to the edge of the display panel 10. Signal wiring or driving circuitry for applying signals to the display area DA can be configured in the non-display area NDA of the main area MA.

[0067] The curved region BD can be connected to the main region MA via a short side. The width of the curved region BD (width in the first direction DR1) can be smaller than the width of the main region MA (width of the short side). The connection between the main region MA and the curved region BD can have an L-shaped cut to reduce the width of the border.

[0068] In the curved region BD, the display panel 10 can be bent in the opposite direction of the display surface according to its curvature. As the display panel 10 is bent in the curved region BD, the surface of the display panel 10 can be reversed. That is, the side of the display panel 10 facing upwards can be changed in such a way that it first faces outwards to the side and then downwards again through the curved region BD.

[0069] Sub-region SA extends from the curved region BD. Sub-region SA may begin extending in a direction parallel to the main region MA after the curvature is completed. Sub-region SA may overlap with the main region MA in the thickness direction of the display panel 10. Sub-region SA may overlap with the non-display area NDA at the edge of the main region MA, and further may overlap with the display area DA of the main region MA. The width of sub-region SA may be the same as the width of the curved region BD, but is not limited thereto.

[0070] A pad portion (not shown) can be configured on a sub-region SA of the display panel 10. External devices can be mounted (or attached) to the pad portion (not shown). Examples of external devices include a driver chip 20, a driver substrate 30 formed from a flexible printed circuit board or a rigid printed circuit board, etc. In addition, wiring connection films, connectors, etc., can also be mounted on the pad portion as external devices. There can be one or more external devices mounted on the sub-region SA. For example, such as... Figure 1 and Figure 2 As an example, a driver chip 20 may be configured in a sub-region SA of the display panel 10, and a driver substrate 30 may be attached to the end of the sub-region SA. In this case, the display panel 10 may include pad portions connected to the driver chip 20 and pad portions connected to the driver substrate 30. As another embodiment, the driver chip may be mounted on a film, and the film may be attached to the sub-region SA of the display panel 10.

[0071] The driver chip 20 can be mounted on one side of the display panel 10, which is the same side as the display surface, and as described above, it is reversed as the curved area BD is bent, so that it is mounted on the side of the display panel 10 facing downward along the thickness direction, thereby the upper surface of the driver chip 20 faces downward.

[0072] The driver chip 20 can be attached to the display panel 10 via an anisotropic conductive film or via ultrasonic bonding. The driver chip 20 may include an integrated circuit that drives the display panel 10.

[0073] Figure 3 This is a circuit diagram illustrating in detail a pixel involved in one embodiment.

[0074] Reference Figure 3 The circuitry of a pixel PX includes multiple transistors T1 to T7, capacitor Cst, and a light-emitting element (LE). Data signals DATA, GW (first scan signal), GI (second scan signal), GB (third scan signal), EM (light emission control signal), ELVDD (first power supply voltage), ELVSS (second power supply voltage), and VINT (initialization voltage) are applied to the circuitry of a pixel PX.

[0075] The light-emitting element (LE) may, for example, include a first electrode (or anode, see reference). Figure 7 "ANO" and the light-emitting layer (refer to) Figure 7 The "EL" and the second electrode (or cathode, see reference) Figure 7 Organic light-emitting diodes (OLEDs) are those that use the "CAT" designation, but are not limited to these.

[0076] The plurality of transistors may include transistors T1 through T7. Each transistor T1 through T7 includes a gate electrode, a first electrode, and a second electrode. Either the first electrode or the second electrode of each transistor T1 through T7 is a source electrode, and the other is a drain electrode.

[0077] The first transistor T1 can act as a driving transistor, and the second transistor T2 to the seventh transistor T7 can act as switching transistors.

[0078] Each transistor T1 to T7 can be a thin-film transistor. Each transistor T1 to T7 can be either a PMOS transistor or an NMOS transistor. In one embodiment, the first transistor T1 as a driving transistor, the second transistor T2 as a data transmission transistor, the third transistor T3 as a compensation transistor, the fourth transistor T4 as a first initialization transistor, the fifth transistor T5 as a first light-emitting control transistor, the sixth transistor T6 as a second light-emitting control transistor, and the seventh transistor T7 as a second initialization transistor are all PMOS transistors.

[0079] However, it is not limited to this. For example, the third transistor T3, which serves as a compensation transistor, and the fourth transistor T4, which serves as a first initialization transistor, can be NMOS transistors, and the first transistor T1, which serves as a driving transistor, the second transistor T2, which serves as a data transmission transistor, the fifth transistor T5, which serves as a first light-emitting control transistor, the sixth transistor T6, which serves as a second light-emitting control transistor, and the seventh transistor T7, which serves as a second initialization transistor, can be PMOS transistors.

[0080] In this case, the active layers of the third transistor T3 and the fourth transistor T4, as well as the active layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, may comprise materials different from each other. For example, the active layers of the third transistor T3 and the fourth transistor T4 may comprise oxide semiconductors, and the active layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may comprise polysilicon, but are not limited thereto.

[0081] The following is a detailed explanation of each component.

[0082] The gate electrode of the first transistor T1 is connected to the first electrode of the capacitor Cst. The first electrode of the first transistor T1 is connected to the first power supply voltage ELVDD terminal via the fifth transistor T5. The second electrode of the first transistor T1 is connected to the anode of the light-emitting element LE via the sixth transistor T6. The first transistor T1 receives the data signal DATA according to the switching operation of the second transistor T2, thereby supplying driving current to the light-emitting element LE.

[0083] The gate electrode of the second transistor T2 is connected to the first scan signal GW terminal. The first electrode of the second transistor T2 is connected to the data signal DATA terminal. Simultaneously, the second electrode of the second transistor T2 is connected to the first electrode of the first transistor T1, and is also connected to the first power supply voltage ELVDD terminal via the fifth transistor T5. When the second transistor T2 is turned on according to the first scan signal GW, it performs a switching operation to transmit the data signal DATA to the first electrode of the first transistor T1.

[0084] The third transistor T3 can be configured as a dual transistor comprising a first sub-transistor T3_1 and a second sub-transistor T3_2. The gate electrode of the first sub-transistor T3_1 is connected to the first scan signal GW terminal, its first electrode is connected to the second electrode of the second sub-transistor T3_2, and its second electrode is connected together with the first electrode of capacitor Cst, the first electrode of the third sub-transistor T4_1, and the gate electrode of the first transistor T1. The gate electrode of the second sub-transistor T3_2 can be connected to the first scan signal GW terminal, its first electrode can be connected to the second electrode of the first transistor T1, and its second electrode can be connected to the first electrode of the first sub-transistor T3_1.

[0085] The first sub-transistor T3_1 and the second sub-transistor T3_2 are turned on according to the first scan signal GW, thereby connecting the gate electrode and the second electrode of the first transistor T1, and performing a diode connection on the first transistor T1. As a result, a voltage difference corresponding to the threshold voltage of the first transistor T1 is generated between the first electrode and the gate electrode. By supplying a data signal DATA that compensates for the threshold voltage to the gate electrode of the first transistor T1, the threshold voltage deviation of the first transistor T1 can be compensated.

[0086] The fourth transistor T4 can be configured as a dual transistor comprising a third sub-transistor T4_1 and a fourth sub-transistor T4_2. The gate electrode of the third sub-transistor T4_1 can be connected to the second scan signal GI terminal. Its first electrode can be connected together with the first electrode of capacitor Cst, the second electrode of the first sub-transistor T3_1, and the gate electrode of the first transistor T1. Its second electrode can be connected to the first electrode of the fourth sub-transistor T4_2. The gate electrode of the fourth sub-transistor T4_2 can be connected to the second scan signal GI terminal. Its first electrode can be connected to the second electrode of the third sub-transistor T4_1, and its second electrode can be connected to the initialization voltage VINT. When the third sub-transistor T4_1 and the fourth sub-transistor T4_2 are turned on according to the second scan signal GI, they perform the operation of transferring the initialization voltage VINT to the gate electrode of the first transistor T1 to initialize the voltage of the gate electrode of the first transistor T1.

[0087] The gate electrode of the fifth transistor T5 is connected to the light emission control signal EM terminal, the first electrode is connected to the first power supply voltage ELVDD terminal, and the second electrode is connected to the first electrode of the first transistor T1. The fifth transistor T5 is turned on according to the light emission control signal EM, thereby connecting the first electrode of the first transistor T1 to the first power supply voltage ELVDD terminal.

[0088] The sixth transistor T6 is connected between the second electrode of the first transistor T1 and the first electrode of the light-emitting element LE. The gate electrode of the sixth transistor T6 is connected to the light-emitting control signal EM terminal, the first electrode is connected to the second electrode of the first transistor T1 and the first electrode of the second sub-transistor T3_2, and the second electrode is connected to the first electrode of the light-emitting element LE.

[0089] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the light-emitting control signal EM, thereby driving current flows through the light-emitting element LE.

[0090] The gate electrode of the seventh transistor T7 is connected to the third scan signal GB terminal. The first electrode of the seventh transistor T7 is connected to the anode of the light-emitting element LE. The second electrode of the seventh transistor T7 is connected to the initialization voltage VINT terminal. The seventh transistor T7 is turned on according to the third scan signal GB, thereby initializing the anode of the light-emitting element LE.

[0091] In this embodiment, the gate electrode of the seventh transistor T7 is shown to receive the application of the third scan signal GB. However, in other embodiments, the circuit of the pixel PX may also be configured such that the gate electrode of the seventh transistor T7 receives the application of the light emission control signal EM or the application of the second scan signal GI.

[0092] A capacitor Cst is formed between the gate electrode of the first transistor T1 and the first power supply voltage ELVDD terminal, and includes a first electrode and a second electrode. The first electrode of capacitor Cst can be connected together with the gate electrode of the first transistor T1, the second electrode of the third transistor T3, and the first electrode of the fourth transistor T4, and the second electrode of capacitor Cst can be connected to the first power supply voltage ELVDD terminal. Capacitor Cst serves to maintain a constant data voltage applied to the gate electrode of the first transistor T1.

[0093] The cathode of the light-emitting element LE is connected to the second power supply voltage ELVSS terminal. The light-emitting element LE receives the drive current from the first transistor T1 and emits light, thereby displaying an image.

[0094] The following details the planar configuration and cross-sectional structure of the aforementioned pixel PX.

[0095] Figure 4 This is a layout diagram of the pixels of a display device according to one embodiment. Figure 5 This is a layout diagram of the first charge trapping film, semiconductor layer, and first conductive layer of a display device according to an embodiment. Figure 6 This is a layout diagram of the second charge trapping film, semiconductor layer, and first conductive layer of a display device according to an embodiment. Figure 7 It is along Figure 4 A sectional view taken from line VII-VII′. Figure 8 Indicates along Figure 4 A portion of the sectional view taken by line VIII-VIII′.

[0096] Figure 7 and Figure 8 express Figure 4 A sectional view, but shown together Figure 5 The first charge trapping film AI1 and Figure 6 The second charge trapping film AI2. Meanwhile... Figure 7 exist Figure 4 The layout diagram further shows the fourth conductive layer 500 including the anode ANO, the light-emitting layer EL, the cathode CAT, and the thin-film encapsulation layer 770.

[0097] Reference Figures 4 to 8 As mentioned above, each pixel PX includes multiple transistors T1 to T7 and capacitors ( Figure 2 The “Cst” (hereinafter the same) and the light-emitting element ( Figure 2 (The "LE" is the same below).

[0098] The capacitor Cst includes multiple conductive layers forming electrodes and an insulating layer disposed between the conductive layers. The light-emitting element LE includes conductive layers forming an anode and a cathode, and a light-emitting layer disposed therebetween. Electrical connections between the components are achieved through wiring formed by the conductive layers and / or vias formed by the conductive material. The aforementioned conductive material or conductive layers, semiconductor layers, insulating layers, light-emitting layers, etc., are disposed on a substrate.

[0099] The layers of a pixel (PX) can be arranged in the following order: first substrate SUB1, first barrier layer BA1, first charge trapping film AI1, second substrate SUB2, second barrier layer BA2, buffer layer BF, second charge trapping film AI2, semiconductor layer 100, first insulating layer 710, first conductive layer 200, second insulating layer 720, second conductive layer 300, third insulating layer 730, third conductive layer 400, protective film 740, first via layer VIA1, fourth conductive layer 500, second via layer VIA2, fifth conductive layer 600, pixel definition film PDL, light-emitting layer EL, and cathode CAT. Each of these layers can be formed from a single film, or it can be formed from a stack of multiple films. Other layers can also be disposed between the individual layers.

[0100] The first substrate SUB1 supports the layers disposed thereon. When the display device 1 is a back-emitting or dual-emitting type, a transparent substrate can be used. When the display device 1 is a front-emitting type, in addition to a transparent substrate, a semi-transparent or opaque substrate can also be used.

[0101] The first substrate SUB1 can be formed of an insulating material such as glass, quartz, or a polymer resin. Examples of the polymer resin include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or combinations thereof. The first substrate SUB1 may also include a metallic material.

[0102] The first substrate SUB1 can be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. Examples of materials used to form a flexible substrate include polyimide (PI), but it is not limited to this.

[0103] The first barrier layer BA1 can be disposed on the first substrate SUB1. The first barrier layer BA1 can be disposed over the entire area of ​​the first substrate SUB1. The first barrier layer BA1 can prevent the diffusion of impurity ions and the penetration of moisture or external gases, and can perform surface planarization. The first barrier layer BA1 may comprise silicon oxide (SiO2). x However, it is not limited to this and can include silicon nitrides (SiN). x ) or silicon nitride oxide (SiO) x N y The first barrier layer BA1 may also be omitted depending on the type of the first substrate SUB1 or the process conditions.

[0104] A first charge trapping film AI1 can be disposed on the first barrier layer BA1. The first charge trapping film AI1 may include an inorganic material. The inorganic material may, for example, include silicon nitride (SiN). x However, it is not limited to this.

[0105] The first charge trapping film AI1 serves to more firmly bond the components stacked on top of and below it. For example, by distributing the first charge trapping film AI1 between the first substrate SUB1 and the second substrate SUB2, the first substrate SUB1 and the second substrate SUB2 can be bonded more firmly, thereby improving the reliability of the display device 1.

[0106] When the first charge trapping film Al1 comprises silicon nitride (SiNx), the NH binding ratio in the first charge trapping film Al1 can be 1.05 at%, or in the range of 1 at% to 5 at%, or in the range of 0.1 at% to 15 at%. However, it is not limited to these. Here, the NH binding ratio refers to the ratio of the number of nitrogen (N) and hydrogen (H) atoms bound together among all the bonds in the entire region.

[0107] In the first charge trap film Al1, the Si-H bonding ratio can be 10.02 at%, or in the range of 8 at% to 12 at%, or 8 at% to 15 at%. However, it is not limited to these values. Here, the Si-H bonding ratio refers to the ratio of the number of silicon (Si) and hydrogen (H) atoms bonded together among all bonds in the entire region.

[0108] In the first charge trapping film Al1, the ratio of Si-H binding to NH binding (i.e., the value of [Si-H] / [NH]) can be 9.54 or in the range of 8 to 12 or in the range of 8 to 15.

[0109] The ratio of NH binding, the ratio of Si-H binding, and / or the ratio of Si-H binding to NH binding can be analyzed using a Fourier transform infrared spectrometer (FT-IR spectrometer), but is not limited to this method.

[0110] Furthermore, in the first charge trapping film Al1, the Si content can be 65.05 at%, or in the range of 60 at% to 70 at%, or in the range of 50 at% to 80 at%. The N content can be 31.85 at%, or in the range of 25 at% to 35 at%, or in the range of 20 at% to 40 at%. The ratio of Si content to N content can be 2.04, or in the range of 1.6 to 2.5, or in the range of 1.1 to 3.0.

[0111] The content of Si, the content of N, and the ratio of Si to N can be analyzed using energy dispersion x-ray spectrometry (EDS), but are not limited to this method.

[0112] When the ratio of NH binding, the ratio of Si-H binding, the ratio of Si-H binding to NH binding, the content of Si element, the content of N element, and the ratio of Si element content to N element content in the first charge trapping film Al1 are at the values ​​described above or within the ranges described above, the characteristics of the first transistor T1 can be improved. For example, if the ratios, element contents, and ratios are less than the ranges described above, it may be detrimental to improving the characteristics of the first transistor T1; if they are greater than the ranges described above, the first charge trapping film Al1 may not be formed smoothly.

[0113] The first charge trapping film Al1 includes silicon nitride (SiN) x In the case of [condition], the first charge trapping film Al1 can be formed under NH3-free conditions. In other words, the first charge trapping film Al1 can be formed by chemical vapor deposition (CVD). In this case, the first charge trapping film Al1 can be formed by adjusting the amounts of nitrogen (N2) and silane (SiH4). Ammonia (NH3) can be omitted during this process.

[0114] When the first charge trapping film AI1 is formed under free ammonia (NH3 free) conditions, the refractive index of the first charge trapping film AI1 can be 2.7774 or in the range of 2.3 to 3.0 or in the range of 2.0 to 3.5, but is not limited thereto.

[0115] Figure 9 This represents the spin density related to the amount of ammonia (NH3) introduced during the formation of the first charge trapping film according to one embodiment. Figure 9 The X-axis of the chart represents the amount of ammonia input, and the Y-axis represents the spin density.

[0116] Block S1 represents the case where the ammonia input is 2000 sccm (standard cubic centimeter per minute), block S2 represents the case where the ammonia input is 1000 sccm (standard cubic centimeter per minute), block S3 represents the case where the ammonia input is 500 sccm (standard cubic centimeter per minute), block S4 represents the case where the ammonia input is 100 sccm (standard cubic centimeter per minute), and block S5 represents the case where no ammonia is input (free ammonia).

[0117] Reference Figure 9 It can be seen that during the formation of the first charge trap film AI1, the spin density increases in the case without ammonia (S5) compared to the cases with ammonia added (S1, S2, S3, S4). Spin density is a factor associated with defect density and can be used as a standard for judging defect density.

[0118] In other words, the spin density of the first charge trap film AI1 formed from free NH3 can be increased. This increases the defect density of the first charge trap film AI1 and the amount of charge trapping within it. For example, when the first charge trap film AI1 is formed from free NH3, the number of Si atoms in the first charge trap film AI1 that are bonded to three or fewer N atoms can be increased. A portion of the outermost electrons of the Si atoms that are not bonded to N atoms and not to other atoms may have a tendency to bond with external electrons (-) for stabilization. Therefore, the number of electrons (-) trapped in the first charge trap film AI1 can be increased. That is, when the first charge trap film AI1 is formed from free NH3, the amount of charge trapping within it can be increased.

[0119] This improves the component characteristics of the first transistor T1, and further improves the display device 1 (refer to...). Figure 1 It can improve the brightness of images and also improve image retention (instantaneous and long-term image retention).

[0120] Meanwhile, the lower semiconductor layer AS (reference) Figure 14 and Figure 15 The lower semiconductor layer AS can be disposed below the first transistor T1, but not below the third transistor T3 (T3_1, T3_2). The lower semiconductor layer AS can overlap with the channel region CH1 of the first transistor T1 at least in the thickness direction, and can at least not overlap with the channel regions CH3_1, CH3_2 of the third transistor T3 (T3_1, T3_2).

[0121] For example, the first charge trapping film AI1 can be disposed on the entire surface of the first substrate SUB1, and can include a first opening OP1 extending through the thickness direction, but is not limited thereto. That is, the first charge trapping film AI1 can define a first opening OP1 extending through the thickness direction. The first opening OP1 can be formed in various shapes on the plane. For example, the first opening OP1 can be formed as a quadrilateral, but is not limited thereto, and can also include polygonal shapes such as rectangles, squares, pentagons, or even circular or elliptical shapes. The first opening OP1 can be disposed in the region of the third transistor T3 (T3_1, T3_2) where the channel regions CH3_1 and CH3_2 are disposed. The first charge trapping film AI1 can be disposed on the entire surface of the first substrate SUB1, and can be selectively removed in the region where the third transistor T3 is disposed.

[0122] In this case, the first charge trapping film AI1 can overlap with the channel region CH1 of the first transistor T1 in the thickness direction. Furthermore, the first charge trapping film AI1 can overlap with the channel regions of the second transistor T2, the fourth transistor T4 (T4_1, T4_2), the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 in the thickness direction. The channel regions CH3_1 and CH3_2 of the third transistor T3 (T3_1, T3_2) can overlap with the first opening OP1 in the thickness direction, and the third transistor T3 (T3_1, T3_2) may not overlap with the first charge trapping film AI1. In other words, on the plane, the first opening OP1 can surround the channel regions CH3_1 and CH3_2 of the third transistor T3 (T3_1, T3_2).

[0123] The first charge trapping film AI1 can be disposed at the lower part of the first transistor T1, but not at the lower part of the third transistor T3 (T3_1, T3_2), thereby allowing independent control of the device characteristics of the first transistor T1 and the third transistor T3 (T3_1, T3_2). For example, the first charge trapping film AI1 can be disposed at the lower part of the first transistor T1 to improve the device characteristics of the first transistor T1, and the first charge trapping film AI1 can be selectively omitted at the lower part of the third transistor T3 to prevent a deterioration in the device characteristics of the third transistor T3. A detailed explanation of this will follow later.

[0124] The second substrate SUB2 can be disposed on the first charge trapping film AI1. The description of the first substrate SUB1 is equally applicable to the second substrate SUB2. Therefore, a detailed description of it is omitted.

[0125] The second barrier layer BA2 can be disposed on the second substrate SUB2. The description of the first barrier layer BA1 can be applied to the second barrier layer BA2 in the same way. Therefore, a detailed description of it is omitted.

[0126] The buffer layer BF can be disposed on the second barrier layer BA2. The buffer layer BF can be disposed on the entire surface of the second barrier layer BA2. The buffer layer BF can prevent the diffusion of impurity ions and prevent the penetration of moisture or external gases, and can perform surface planarization. The buffer layer BF may include, but is not limited to, silicon nitride, or silicon oxide or silicon oxide nitride, etc. The buffer layer BF may also be omitted depending on the type of the first substrate SUB1 and / or the second substrate SUB2 or the process conditions, etc.

[0127] The second charge trapping film AI2 can be disposed on the buffer layer BF. The second charge trapping film AI2 may include an inorganic material. The inorganic material may include silicon oxide (SiO2). x However, it is not limited to this.

[0128] The second charge trapping film Al2 includes silicon oxide (SiO2). x In the case of the second charge trap film Al2, the NH binding ratio can be 0.73 at%, or in the range of 0.7 at% to 1.3 at%, or in the range of 0.7 at% to 1.5 at%. However, it is not limited to this. Here, the NH binding ratio can mean the ratio of the number of nitrogen (N) atoms bound to hydrogen (H) atoms among all the bonds in the entire region.

[0129] The NH binding ratio can be analyzed using a Fourier transform infrared spectrometer (FT-IR spectrometer), but is not limited to this method.

[0130] When the NH binding ratio is at or within the range described above, the characteristics of the first transistor T1 can be improved. For example, if the ratio is greater than the range described above, it may be detrimental to improving the characteristics of the first transistor T1, and if it is greater than the range described above, the second charge trapping film AI2 may not be formed smoothly.

[0131] The second charge trapping film Al2 includes silicon oxide (SiO2). x In the case of [missing information], the second charge trapping film Al2 can be formed by chemical vapor deposition (CVD). In this case, the second charge trapping film Al2 can be formed by adjusting the amount of nitrous oxide (N2O) and silane (SiH4) added.

[0132] N can be configured at the interface between the second charge trapping film AI2 and the semiconductor layer 100. In the N located at the interface, a portion of the outermost electrons of the N that are not bonded to other atoms may have a tendency to bond with external electrons (-) to achieve stabilization, and more electrons (-) can be trapped by the second charge trapping film AI2. Therefore, when the NH bonding ratio in the second charge trapping film AI2 has the above-mentioned value or is within the above-mentioned range, the amount of charge trapping in the second charge trapping film AI2 can be increased.

[0133] This improves the component characteristics of the first transistor T1, and further improves the display device 1 (refer to...). Figure 1 This improves the brightness of the transistor and reduces image retention (both momentary and long-term). Simultaneously, doping of the channel regions of the active layers of the first transistor T1 through the seventh transistor T7 can be omitted. Therefore, the channel region of the active layer of at least any one of the first transistors T1 through the seventh transistor T7 may not contain impurities such as boron (B) or fluorine (F). A detailed explanation of this will follow later.

[0134] Semiconductor layer 100 may be disposed on second charge trapping film AI2. Semiconductor layer 100 is an active layer forming a first region, a second region, and a channel (or channel region) in contact with the first electrode and second electrode of each of the first transistors T1 to the seventh transistors T7. Either the first region or the second region is called the source region, and the other is called the drain region.

[0135] In the following plan view, the right side refers to one side of the first direction DR1, the left side refers to the other side of the first direction DR1, and the upper side refers to one side of the second direction DR2, and the lower side refers to the other side of the second direction DR2.

[0136] The semiconductor layer 100 may be connected in each pixel PX instead of being separated. The semiconductor layer 100 may have a specific pattern on a plane. For example, the semiconductor layer 100 may include a first vertical portion 110, a second vertical portion 120, a third vertical portion 150, a fourth vertical portion 160, and a fifth vertical portion 170 extending generally in the second direction DR2; a first horizontal portion 130 and a second horizontal portion 140 extending generally in the first direction DR1; and a first connecting portion 181, a second connecting portion 182, and a third connecting portion 183 connecting a portion of the plurality of vertical portions 110, 120, 150, 160, 170 and a portion of the plurality of horizontal portions 130, 140. The plurality of vertical portions 110, 120, 150, 160, 170, the plurality of horizontal portions 130, 140, and the first connecting portions 181 to the third connecting portions 183 may be physically connected.

[0137] The first vertical portion 110 may be configured adjacent to the other side of the first direction DR1 of a pixel PX, and the second vertical portion 120 may be configured adjacent to one side of the first direction DR1 of the pixel PX. The first vertical portion 110 and the second vertical portion 120 may be configured to be spaced apart from each other. The length of the first vertical portion 110 in the second direction DR2 may be longer than that of the second vertical portion 120. The first horizontal portion 130 may connect the middle portion of the first vertical portion 110 and the second vertical portion 120. In this specification, the "upper portions 111, 121" of the first vertical portion 110 and the second vertical portion 120 may refer to portions on the plane that are closer to the side of the second direction DR2 than the portion connected to the first horizontal portion 130, and the "lower portions 112, 122" of the first vertical portion 110 and the second vertical portion 120 may refer to portions on the plane that are closer to the other side of the second direction DR2 than the portion connected to the first horizontal portion 130. The planar shapes of the first longitudinal portion 110, the second longitudinal portion 120, and the first transverse portion 130 can be roughly similar to the shape of an "H".

[0138] Although the first transverse portion 130 can also connect the first longitudinal portion 110 and the second longitudinal portion 120 with the shortest distance, as shown in the figure, it can include a first bend portion 131 on the other side of the first direction DR1 and a second bend portion 132 on one side of the first direction DR1. By bending multiple times, the total length of the first transverse portion 130 can be increased.

[0139] The second transverse portion 140 can extend from one end of the upper portion 121 of the second longitudinal portion 120 in the second direction DR2 to the other side in the first direction DR1, and can be configured to be closer to the side in the second direction DR2 than the first transverse portion 130. The width of the region on the other side of the first direction DR1 of the second transverse portion 140 in the second direction DR2 can be thicker than that of other regions, but is not limited thereto.

[0140] The third vertical portion 150, the fourth vertical portion 160, and the fifth vertical portion 170 can be disposed on one side of the second direction DR2 of the second horizontal portion 140. The third vertical portion 150 can be disposed on the other side of the second direction DR2 of the fifth vertical portion 170, and the fourth vertical portion 160 can be disposed between the third vertical portion 150 and the fifth vertical portion 170. The other end of the fourth vertical portion 160 in the second direction DR2 can be connected to the fifth vertical portion 170, but one end of the second direction DR2 can be connected to the lower portion 122 of the second vertical portion 120 of the adjacent pixel PX.

[0141] The first connecting portion 181 may be disposed between the other end of the second transverse portion 140 in the first direction DR1 and the other end of the third longitudinal portion 150 in the second direction DR2. The first connecting portion 181 may connect the second transverse portion 140 and the third longitudinal portion 150, and may be formed to be inclined relative to the first direction DR1 and the second direction DR2.

[0142] The second connecting portion 182 may be disposed between one end of the third longitudinal portion 150 in the second direction DR2 and one end of the fourth longitudinal portion 160 in the second direction DR2. The second connecting portion 182 may connect the third longitudinal portion 150 and the fourth longitudinal portion 160.

[0143] The third connecting portion 183 may be disposed between the other end of the second direction DR2 of the fourth longitudinal portion 160 and the other end of the second direction DR2 of the fifth longitudinal portion 170. The third connecting portion 183 may connect the fourth longitudinal portion 160 and the fifth longitudinal portion 170.

[0144] The planar shapes of the third longitudinal section 150, the fourth longitudinal section 160, the fifth longitudinal section 170, the second connecting section 182, and the third connecting section 183 can be similar to an "S" shape that is roughly reversed and placed horizontally.

[0145] The channel of the second transistor T2 can be disposed on the upper side 111 of the first vertical portion, and the channel of the fifth transistor T5 can be disposed on the lower side 112 of the first vertical portion. The channel of the second sub-transistor T3_2 can be disposed on the upper side 121 of the second vertical portion. The channel of the first transistor T1 can be disposed on the first horizontal portion 130. The channel of the first sub-transistor T3_1 can be disposed on the second horizontal portion 140. The channel of the third sub-transistor T4_1 can be disposed on the third vertical portion 150, and the channel of the fourth sub-transistor T4_2 can be disposed on the fourth vertical portion 160. The channel of the seventh transistor T7 can be disposed on the fifth vertical portion 170.

[0146] Semiconductor layer 100 may include polycrystalline silicon. Polycrystalline silicon may be formed by crystallizing amorphous silicon. Examples of crystallization methods include RTA (rapid thermal annealing), SPC (solid phase crystallization), ELA (excimer laser annealing), MIC (metal induced crystallization), MILC (metal induced lateral crystallization), and SLS (sequential lateral solidification), but are not limited to these. Other examples include monocrystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, and oxide semiconductors.

[0147] The first insulating layer 710 may be disposed on the semiconductor layer 100 and may be disposed substantially on the entire surface of the first substrate SUB1 and / or the second substrate SUB2. The first insulating layer 710 may be a gate insulating film with gate insulation function.

[0148] The first insulating layer 710 may include silicon compounds, metal oxides, etc. For example, the first insulating layer 710 may include silicon oxide, silicon nitride, silicon nitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. These materials may be used alone or in combination with each other.

[0149] A first conductive layer 200 is disposed on a first insulating layer 710. The first conductive layer 200 may include a component for transmitting a first scan signal. Figure 3 The first scan line 210 (hereinafter the same as "GW"), the gate electrode 240 of the first transistor T1, and the transmission of the light emission control signal ( Figure 3 The light emission control line 220 (hereinafter the same) and the supply of the second scan signal (EM) Figure 3 The second scan line 230 (the “GI”, hereinafter the same).

[0150] The first scan line 210 may include the gate electrodes of the second transistor T2, the first sub-transistor T3_1, and the second sub-transistor T3_2. The light emission control line 220 may include the gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6. In addition, the second scan line 230 may include the gate electrodes of the third sub-transistor T4_1, the fourth sub-transistor T4_2, and the seventh transistor T7.

[0151] The first scan line 210, the light emission control line 220, and the second scan line 230 can each extend along the first direction DR1. The first scan line 210, the light emission control line 220, and the second scan line 230 can each extend along the first direction DR1, crossing the boundary of pixel PX and reaching the adjacent pixel PX.

[0152] The first scan line 210 may be located near the center of pixel PX and overlap with the upper portion 111 of the first vertical portion and the upper portion 121 of the second vertical portion of semiconductor layer 100.

[0153] The first scan line 210 can form the gate electrode of the second transistor T2 at the location where it overlaps with the upper portion 111 of the first vertical portion of the semiconductor layer 100. Based on the overlapping region, the first vertical portion 110 of the semiconductor layer 100 closer to the second direction DR2 can become the first region of the second transistor T2, and the first vertical portion 110 of the semiconductor layer 100 closer to the other side of the second direction DR2 can become the second region of the second transistor T2.

[0154] The first scan line 210 can form the gate electrode of the second sub-transistor T3_2 at the location where it overlaps with the upper portion 121 of the second vertical portion of the semiconductor layer 100. Based on the overlapping region, the second vertical portion 120 of the semiconductor layer 100 closer to the second direction DR2 can become the second region of the second sub-transistor T3_2, and the second vertical portion 120 of the semiconductor layer 100 closer to the other side of the second direction DR2 can become the first region of the second sub-transistor T3_2.

[0155] The first scan line 210 may further include a first scan line protrusion 211. The first scan line protrusion 211 may protrude from the first scan line 210 extending in the first direction DR1 toward one side in the second direction DR2.

[0156] The first scan line protrusion 211 can overlap with the second lateral portion 140 of the semiconductor layer 100, and the gate electrode of the first sub-transistor T3_1 can be formed at the corresponding overlapping location. Based on the overlapping location, the second lateral portion 140 of the semiconductor layer 100 closer to the first direction DR1 can become the first region of the first sub-transistor T3_1, and the second lateral portion 140 of the semiconductor layer 100 closer to the other side of the first direction DR1 can become the second region of the first sub-transistor T3_1.

[0157] The light-emitting control line 220 can be located on the other side of the second direction DR2 of the pixel PX on the plane, and can overlap with the lower part of the first vertical portion 112 and the lower part of the second vertical portion 122 of the semiconductor layer 100.

[0158] The light-emitting control line 220 can form the gate electrode of the fifth transistor T5 at the location where it overlaps with the lower portion 112 of the first vertical portion of the semiconductor layer 100. Based on the overlapping region, the first vertical portion 110 of the semiconductor layer 100 closer to the second direction DR2 can become the second region of the fifth transistor T5, and the first vertical portion 110 of the semiconductor layer 100 closer to the other side of the second direction DR2 can become the first region of the fifth transistor T5.

[0159] The light-emitting control line 220 can form the gate electrode of the sixth transistor T6 at the location where it overlaps with the upper portion 121 of the second vertical portion. Based on the overlapping region, the second vertical portion 120 of the semiconductor layer 100 closer to the side of the second direction DR2 can become the first region of the sixth transistor T6, and the second vertical portion 120 of the semiconductor layer 100 closer to the other side of the second direction DR2 can become the second region of the sixth transistor T6.

[0160] The second scan line 230 can be located on one side of the second direction DR2 of the pixel PX on the plane, and can overlap with the third vertical portion 150, the fourth vertical portion 160 and the fifth vertical portion 170 of the semiconductor layer 100.

[0161] The second scan line 230 can form the gate electrode of the third sub-transistor T4_1 at the location where it overlaps with the third vertical portion 150 of the semiconductor layer 100. Based on the overlapping region, the third vertical portion 150 of the semiconductor layer 100 closer to the second direction DR2 can become the second region of the third sub-transistor T4_1, and the third vertical portion 150 of the semiconductor layer 100 closer to the other side of the second direction DR2 can become the first region of the third sub-transistor T4_1.

[0162] The second scan line 230 can form the gate electrode of the fourth sub-transistor T4_2 at the location where it overlaps with the fourth vertical portion 160 of the semiconductor layer 100. Based on the overlapping region, the fourth vertical portion 160 of the semiconductor layer 100 closer to the second direction DR2 can become the first region of the fourth sub-transistor T4_2, and the fourth vertical portion 160 of the semiconductor layer 100 closer to the other side of the second direction DR2 can become the second region of the fourth sub-transistor T4_2.

[0163] The second scan line 230 can form the gate electrode of the seventh transistor T7 at the location where it overlaps with the fifth vertical portion 170 of the semiconductor layer 100. Based on the overlapping region, the fifth vertical portion 170 of the semiconductor layer 100 closer to the side of the second direction DR2 can become the second region of the seventh transistor T7, and the fifth vertical portion 170 of the semiconductor layer 100 closer to the other side of the second direction DR2 can become the first region of the seventh transistor T7.

[0164] The gate electrodes of transistors T2 through T7 can be widened relative to the peripheral lines at the corresponding locations, but are not limited to this.

[0165] The gate electrode 240 of the first transistor T1 can be located in the center of pixel PX. The gate electrode 240 of the first transistor T1 can be located on a plane between the first scan line 210 and the light emission control line 220. The gate electrode 240 of the first transistor T1 can be separated for each pixel PX.

[0166] The gate electrode 240 of the first transistor T1 overlaps with the first lateral portion 130 of the semiconductor layer 100. Based on the overlapping portion, the first lateral portion 130 of the semiconductor layer 100 that is closer to the other side of the first direction DR1 can become the first region of the first transistor T1, and the first lateral portion 130 of the semiconductor layer 100 that is closer to the other side of the first direction DR1 can become the second region of the first transistor T1.

[0167] The first conductive layer 200 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0168] The second insulating layer 720 serves to insulate the first conductive layer 200 from the second conductive layer 300. It can be disposed on the first conductive layer 200 and generally across the entire surface of the first substrate SUB1 and / or the second substrate SUB2. The second insulating layer 720 can be an interlayer insulating film.

[0169] The second insulating layer 720 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon nitride oxide, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, and zinc oxide, or organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). The second insulating layer 720 may be a single film or a multilayer film formed by stacking films of different materials.

[0170] The second conductive layer 300 is disposed on the second insulating layer 720. The second conductive layer 300 may include capacitor electrode lines 310 and a supply initialization voltage (…). Figure 3 The initialization voltage line 320 (hereinafter the same) is "VINT".

[0171] The capacitor electrode line 310 and the initialization voltage line 320 can extend along the first direction DR1, respectively. The capacitor electrode line 310 and the initialization voltage line 320 can extend along the first direction DR1, crossing the boundary of pixel PX and reaching the adjacent pixel PX.

[0172] The capacitor electrode line 310 traverses the center of pixel PX and is configured to overlap with the gate electrode 240 of the lower first transistor T1, with a second insulating layer 720 sandwiched between them, thereby forming capacitor Cst. The gate electrode 240 of the first transistor T1 can serve as the first electrode of capacitor Cst, and the extended region of the capacitor electrode line 310 overlapping with it can serve as the second electrode of capacitor Cst, with the second insulating layer 720 in between serving as the dielectric of capacitor Cst.

[0173] In the region where the capacitor electrode line 310 overlaps with the gate electrode 240 of the first transistor T1, the width of the capacitor electrode line 310 can be extended. The extended region of the capacitor electrode line 310 may include an opening that overlaps with the gate electrode 240 of the lower first transistor T1.

[0174] The initialization voltage line 320 can be located on one side of the second direction DR2 of the pixel PX on the plane. The initialization voltage line 320 can overlap with the fifth vertical portion 170 of the semiconductor layer 100.

[0175] The second conductive layer 300 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0176] The third insulating layer 730 covers the second conductive layer 300. The third insulating layer 730 may be configured substantially across the entire surface of the first substrate SUB1 and / or the second substrate SUB2. The third insulating layer 730 may be an interlayer insulating film. The third insulating layer 730 may include the same material as the second insulating layer 720, or may include one or more materials selected from those exemplified as constituent materials of the second insulating layer 720.

[0177] The third conductive layer 400 is disposed on the third insulating layer 730. The third conductive layer 400 may include multiple data patterns 410, 420, and a light-emitting element LE (see reference). Figure 3 The first anode connection electrode 430, which is electrically connected to the anode ANO of the semiconductor layer 100, is supplied with a first power supply voltage ( Figure 3 The first power supply voltage line 440 (hereinafter referred to as "ELVDD") and the data transmission signal ( Figure 3 The data line 450 (hereinafter the same) is for the “DATA”.

[0178] The third conductive layer 400 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The third conductive layer 400 may be a single film or a multilayer film. For example, the third conductive layer 400 may be formed from a stacked structure such as Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, or Ti / Cu.

[0179] Multiple data patterns may include a first data pattern 410 and a second data pattern 420. Each data pattern 410, 420 may generally have a shape extending in the second direction DR2, and the length of each data pattern 410, 420 in the second direction DR2 may be less than the length of the pixel PX in the second direction DR2. Each data pattern 410, 420 is physically spaced apart from each other. Each data pattern 410, 420 may have electrically connected portions thereof.

[0180] The first data pattern 410 may overlap with the gate electrode 240 of the first transistor T1. The first data pattern 410 may be electrically connected to the gate electrode 240 of the first transistor T1 in the overlapping area through a first contact hole CNT1 that exposes the gate electrode 240 of the first transistor T1 by penetrating the third insulating layer 730 and the second insulating layer 720. The first contact hole CNT1 may be located within the opening of the capacitor electrode line 310. The first data pattern 410 inside the first contact hole CNT1 and the adjacent capacitor electrode line 310 may be insulated from each other through the third insulating layer 730.

[0181] Furthermore, the first data pattern 410 can extend upwards from the overlapping region with the gate electrode 240 of the first transistor T1, intersecting the first scan line 210 in an insulated manner, and can overlap with a portion of the second lateral portion 140 of the semiconductor layer 100. The first data pattern 410 can be electrically connected to the second lateral portion 140 of the semiconductor layer 100 in the overlapping region through a second contact hole CNT2 that exposes a portion of the second lateral portion 140 of the semiconductor layer 100 by penetrating the third insulating layer 730, the second insulating layer 720, and the first insulating layer 710. A portion of the second lateral portion 140 can be the second region of the first sub-transistor T3_1, but is not limited thereto.

[0182] In other words, the first data pattern 410 can electrically connect the gate electrode 240 of the first transistor T1 to the second lateral portion 140 of the semiconductor layer 100.

[0183] The second data pattern 420 may overlap with the third connection portion 183 of the semiconductor layer 100. The second data pattern 420 may be electrically connected to the third connection portion 183 of the semiconductor layer 100 in the overlapping area through a fourth contact hole CNT4 that exposes the third connection portion 183 of the semiconductor layer 100 by penetrating the third insulating layer 730, the second insulating layer 720 and the first insulating layer 710.

[0184] Furthermore, the second data pattern 420 can extend upwards from the overlapping area with the third connection portion 183 of the semiconductor layer 100 and intersect the second scan line 230 in an insulated manner, and can overlap with the initialization voltage line 320. The second data pattern 420 can be electrically connected to the initialization voltage line 320 in the overlapping area through a fifth contact hole CNT5 that exposes the initialization voltage line 320 by penetrating the third insulating layer 730.

[0185] In other words, the second data pattern 420 can electrically connect the third connection portion 183 of the semiconductor layer 100 to the initialization voltage line 320.

[0186] The first anode connection electrode 430 generally has a shape extending in the second direction DR2, and the length of the first anode connection electrode 430 in the second direction DR2 is less than the length of the pixel PX in the second direction DR2. The first anode connection electrode 430 and the plurality of data patterns 410, 420 are physically spaced apart from each other. The first anode connection electrode 430 can be used together with the second anode connection electrode 530 (described later) to connect the semiconductor layer 100 to the anode ANO.

[0187] The first anode connection electrode 430 can overlap with the lower side portion 122 of the second vertical portion of the semiconductor layer 100. The first anode connection electrode 430 can be electrically connected to the lower side portion 122 of the second vertical portion of the semiconductor layer 100 through a sixth contact hole CNT6 that exposes the lower side portion 122 of the second vertical portion of the semiconductor layer 100 by penetrating the third insulating layer 730, the second insulating layer 720 and the first insulating layer 710.

[0188] The first power supply voltage line 440 can extend along the second direction DR2. The first power supply voltage line 440 can extend along the second direction DR2 across the boundary of pixel PX to an adjacent pixel PX. The first power supply voltage line 440 is generally adjacent to the left side of pixel PX and is disposed on one side of the data line 450 in the first direction DR1, but is not limited thereto. The first power supply voltage line 440 can be electrically connected to the capacitor electrode line 310 through the eighth contact hole CNT8, which exposes the capacitor electrode line 310 by penetrating the third insulating layer 730.

[0189] Furthermore, the first power supply voltage line 440 can be electrically connected to the lower side portion 112 of the first vertical portion of the semiconductor layer 100 through the seventh contact hole CNT7, which exposes the lower side portion 112 of the first vertical portion of the semiconductor layer 100 by passing through the third insulating layer 730, the second insulating layer 720 and the first insulating layer 710.

[0190] The data line 450 can extend along the second direction DR2. The data line 450 can extend along the second direction DR2 across the boundary of pixel PX to an adjacent pixel PX. The data line 450 can be arranged adjacent to the other side of the first direction DR1 of pixel PX. The data line 450 can overlap with the first vertical portion 110 of semiconductor layer 100.

[0191] The data line 450 can contact the upper portion 111 of the first vertical portion of the semiconductor layer 100 through a third contact hole CNT3 that exposes the upper portion 111 of the first vertical portion of the semiconductor layer 100 by passing through the third insulating layer 730, the second insulating layer 720 and the first insulating layer 710. The third contact hole CNT3 may be located below the second scan line 230 in the plane, but is not limited to this.

[0192] The protective film 740 may be formed on the third conductive layer 400. The protective film 740 may be formed of an inorganic film (e.g., a silicon nitride layer, a silicon oxide nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer). However, the protective film 740 may be omitted in some embodiments.

[0193] A first via layer VIA1 is disposed on the protective film 740. The first via layer VIA1 may be a planarization film. The first via layer VIA1 may include inorganic insulating materials or organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylenesulfide resin, or benzocyclobutene (BCB).

[0194] A fourth conductive layer 500 is disposed on the first via layer VIA1. The fourth conductive layer 500 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0195] The fourth conductive layer 500 may include a second anode connection electrode 530. A first anode contact hole ACNT1 may be configured in the first via layer VIA1, penetrating the first via layer VIA1 and the protective film 740 to expose the first anode connection electrode 430. The second anode connection electrode 530 can be connected to the first anode connection electrode 430 through the first anode contact hole ACNT1.

[0196] A second via layer VIA2 is disposed on the fourth conductive layer 500. The second via layer VIA2 can be a planarization film. The second via layer VIA2 can include inorganic insulating materials or organic insulating materials such as acrylic resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, unsaturated polyester resins, polyphenylene resins, polyphenylenesulfides resins, or benzocyclobutene (BCB).

[0197] A fifth conductive layer 600 is disposed on the second via layer VIA2. The fifth conductive layer 600 may include an anode ANO. The anode ANO may be disposed separately in each pixel PX. The anode ANO is electrically connected to the second anode connection electrode 530 through a second anode contact hole ACNT2 that exposes the second anode connection electrode 530 by penetrating the second via layer VIA2.

[0198] The anode ANO can have a multilayer structure containing layers of high work function materials such as indium-tin-Oxide (ITO), indium-zinc-Oxide (IZO), zinc oxide (ZnO), and indium oxide (In₂O₃), as well as reflective material layers such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or mixtures thereof, but is not limited to these. Layers with high work function can be placed on layers higher than the reflective material layers, thus placing them closer to the light-emitting layer (EL). The anode ANO can have multilayer structures such as ITO / Mg, ITO / MgF, ITO / Ag, and ITO / Ag / ITO, but is not limited to these.

[0199] A pixel-defining film (PDL) can be disposed on the fifth conductive layer 600. The PDL may include an opening that exposes the anode (ANO) portion. The PDL may be formed from an organic or inorganic insulating material. For example, the PDL may be formed from at least one of a polyimide resin, an acrylic resin, a silicone compound, or a polyacrylic resin.

[0200] An emitting layer EL is disposed on the anode ANO that exposes the pixel definition film PDL. The emitting layer EL may include an organic material layer. The organic material layer of the emitting layer EL may include an organic emitting layer, and may also include a hole injection / transport layer and / or an electron injection / transport layer.

[0201] A cathode (CAT) can be configured on the light-emitting layer (EL). The cathode CAT can be a common electrode configured across the entire surface without pixel differentiation (PX). The anode (ANO), the light-emitting layer (EL), and the cathode CAT can constitute a light-emitting element (LE) (see reference). Figure 3 ).

[0202] The cathode CAT may include a layer of material with a low work function, such as Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba, or compounds or mixtures thereof (e.g., mixtures of Ag and Mg). The cathode CAT may also include a transparent metal oxide layer disposed on the material layer with the low work function.

[0203] A thin-film encapsulation layer 770, comprising a first inorganic film 771, a first organic film 772, and a second inorganic film 773, is disposed on the upper part of the cathode CAT. At the ends of the thin-film encapsulation layer 770, the first inorganic film 771 and the second inorganic film 773 can be connected to each other. The first organic film 772 can be sealed by the first inorganic film 771 and the second inorganic film 773.

[0204] The first inorganic membrane 771 and the second inorganic membrane 773 may respectively include silicon nitride, silicon oxide, or silicon nitride. The first organic membrane 772 may include an organic insulating material.

[0205] As described above, display device 1 (refer to) Figure 1 It includes a first charge trapping film AI1 and a second charge trapping film AI2, which can increase brightness and improve image retention.

[0206] To illustrate the change in the component characteristics of the first transistor T1, refer to... Figure 10 and Figure 11 .

[0207] Figure 10 This is a graph showing the drive current related to the data voltage of the first transistor in one embodiment. Figure 11 It is a graph that measures the change in the driving range of the first transistor, ΔDR1, in relation to the configuration of the first charge trapping film and the second charge trapping film according to an embodiment.

[0208] Reference Figure 10Curve A represents the IV (current-voltage) curve of the first transistor T1, and curve B represents the IV (current-voltage) curve when the driving range of the first transistor T1 is increased compared to curve A.

[0209] Curves A and B intersect at data voltages P1 and P2. In the data voltage range less than P1 or greater than P2, curve B exhibits a larger drive current Id value than curve A. In the range between P1 and P2, curve A exhibits a larger drive current Id value than curve B. Furthermore, the first transistor T1 can be driven between the first drive current value Id1 and the second drive current value Id2.

[0210] The driving range DB of the first transistor T1 in curve B is greater than the driving range DA of the first transistor T1 in curve A. In other words, between the first driving current value Id1 and the second driving current value Id2, the absolute value of the slope of curve B is less than the absolute value of the slope of curve A, which is sufficient to drive the light-emitting element LE (refer to...). Figure 3 The range of data voltage Vdata that can be adjusted by the drive current Id is increased. Therefore, it is easier to adjust the drive current Id, and further, it is easier to adjust the data voltage Vdata of a pixel PX (refer to...). Figure 3 (brightness).

[0211] Furthermore, even when the same data voltage Vdata is applied between P1 and P2, the first transistor T1 in curve B will experience a larger drive current Id than the first transistor T1 in curve A. Therefore, by increasing the drive range (curve B) when the same data voltage Vdata is applied, the drive current Id can be increased, and further, the number of pixels PX can be increased (see reference). Figure 3 The brightness of the display device 1 (refer to) can be increased. Figure 1 It can improve light efficiency and reduce image retention.

[0212] Further reference Figure 11 , Figure 11 The X-axis of the graph represents the configuration of the first charge trapping film AI1 and the second charge trapping film AI2, and the Y-axis represents the change in the driving range of the first transistor T1, ΔDR1.

[0213] exist Figure 11 In the diagram, N1 represents the case where amorphous silicon is disposed at the location of the first charge trapping film AI1 instead of the first charge trapping film AI1, and an inorganic film is disposed at the location of the second charge trapping film AI2 instead of the second charge trapping film AI2.

[0214] The diagram of N2 represents the case where a first charge trapping membrane AI1 is configured and an inorganic membrane, instead of the second charge trapping membrane AI2, is configured at the location of the second charge trapping membrane AI2.

[0215] The diagram for N3 shows a case where the first charge trapping membrane AI1 is not configured, and an inorganic membrane is configured instead of the second charge trapping membrane AI2 at the location of the second charge trapping membrane AI2.

[0216] The diagram for N4 represents the case where the first charge trapping membrane AI1 is not configured and the second charge trapping membrane AI2 is configured.

[0217] In the diagrams N1, N2, and N3, the channel region of the active layer of the first transistor T1 is doped with either B (boron) or F (fluorine). The diagram N4 indicates the case where the doping of the channel region of the active layer of the first transistor T1 is omitted.

[0218] The inorganic film not representing the second charge trapping film AI2 located at the position of the second charge trapping film AI2 in the N1, N2, and N3 diagrams may include silicon oxide (SiO2). x However, the NH binding rate can be less than 0.7 at%. For example, the NH binding rate of the inorganic membrane can be 0.3 at%, but it is not limited to this.

[0219] In graph N1, the average value of the change in the driving range of the first transistor T1, ΔDR1, is 0.14. In graph N2, the average value of the change in the driving range of the first transistor T1, ΔDR1, is 0.338. In graph N3, the average value of the change in the driving range of the first transistor T1, ΔDR1, is 0.014. In graph N4, the average value of the change in the driving range of the first transistor T1, ΔDR1, is 0.056.

[0220] Comparing the graphs of N1, N2, and N3, it can be seen that the change in the driving range ΔDR1 of the first transistor T1 is greater when the first charge trapping film AI1 is configured (graph of N2) than when amorphous silicon is configured at the position of the first charge trapping film AI1 (graph of N1) and when the first charge trapping film AI1 is not configured (graph of N3).

[0221] Comparing the graphs of N3 and N4, it can be seen that the change in the driving range ΔDR1 of the first transistor T1 is greater when the second charge trapping membrane AI2 is configured (graph of N4) than when an inorganic membrane is configured at the position of the second charge trapping membrane AI2 instead of the second charge trapping membrane AI2 (graph of N3).

[0222] Therefore, with the first charge trapping film AI1 and the second charge trapping film AI2 configured, the driving range of the first transistor T1 can be further increased. This makes it easier to adjust the driving current and also makes it easier to adjust the value of a pixel PX (refer to...). Figure 3 The brightness of a pixel PX (refer to...) can be increased even when the same data voltage Vdata is applied. Figure 3 It emits light with greater brightness, which can improve poor image retention, etc.

[0223] Furthermore, even if the doping of the channel regions of the active layers of each transistor T1 to T7 is omitted, the driving range of the first transistor T1 can be further increased when the second charge trapping film AI2 is configured. Therefore, the doping of the channel regions of the active layers of each transistor T1 to T7 can be omitted, thereby simplifying the process and reducing process costs.

[0224] Next, to illustrate the change in the element characteristics of the third transistor T3 according to one embodiment, refer to... Figure 12 and Figure 13 .

[0225] Figure 12 This is a graph showing the drive current associated with the gate voltage of the third transistor in one embodiment. Figure 13 It is a graph that measures the threshold voltage change ΔVth of a third transistor in relation to the configuration of a first charge trapping membrane and a second charge trapping membrane in one embodiment.

[0226] Reference Figure 12 Curve C represents the drive current Id for the gate voltage Vg of the third transistor T3. Curve D represents the drive current Id for the gate voltage Vg when the threshold voltage change ΔVth of the third transistor T3 is increased by the amount shown in curve C.

[0227] Curve D is shifted more positively than curve C. In other words, as the threshold voltage change ΔVth of the third transistor T3 increases, the curve of the drive current Id for the gate voltage Vg of the third transistor T3 will shift more positively. With the curve of the drive current Id for the gate voltage Vg of the third transistor T3 shifting more positively, the kickback of the third transistor T3 may increase. Therefore, for a pixel PX (refer to...) Figure 3 The brightness of the display device 1 (refer to) may decrease. Figure 1 The light efficiency may decrease.

[0228] Reference Figure 13 ,exist Figure 13 In the chart, the X-axis represents whether the first charge trapping film AI1 and the second charge trapping film AI2 are configured, and the Y-axis represents the threshold voltage change ΔVth of the third transistor T3.

[0229] exist Figure 13 In the diagram, P1 represents the case where the first charge trapping membrane AI1 and the second charge trapping membrane AI2 are configured, while P2 represents the case where the first charge trapping membrane AI1 is not configured and the second charge trapping membrane AI2 is configured.

[0230] In the graph P1, the threshold voltage change ΔVth of the third transistor T3 has an average value of 1.786. In the graph P2, the threshold voltage change ΔVth of the third transistor T3 has an average value of 0.733. That is, the threshold voltage change ΔVth of the third transistor T3 with the first charge trapping film AI1 configured (graph P1) can be greater than the threshold voltage change ΔVth of the third transistor T3 without the first charge trapping film AI1 configured (graph P2). In other words, with the first charge trapping film AI1 configured, the curve of the drive current Id for the gate voltage Vg of the third transistor T3 can be shifted in the positive direction.

[0231] However, as the first charge trapping film AI1 includes a first opening OP1 (see reference) Figure 8 In this case, the first charge trapping film AI1 may not be disposed below the active layer of the third transistor T3. Therefore, a positive shift in the curve of the drive current Id for the gate voltage Vg of the third transistor T3 can be suppressed or prevented, thereby suppressing or preventing kickback of the third transistor T3, and suppressing or preventing a pixel PX (refer to...) Figure 3 The brightness of the display device 1 (refer to) decreases. Furthermore, it is possible to suppress or prevent the display device 1 (refer to) from decreasing. Figure 1 It reduces the decrease in light efficiency and can improve image retention.

[0232] That is, by arranging a first charge trapping film AI1 at the lower part of the first transistor T1 and selectively not arranging the first charge trapping film AI1 at the lower part of the third transistor T3, the device characteristics of the first transistor T1 can be improved and the device characteristics of the third transistor T3 can be prevented from deteriorating.

[0233] Other embodiments are described below. In the following embodiments, for configurations that are the same as those previously described, repeated descriptions are omitted or simplified, and the differences are mainly described.

[0234] Figure 14 This is a cross-sectional view of a display device involved in other embodiments.

[0235] Reference Figure 14 ,and Figure 7 The difference in the embodiments is that the first charge trapping film AI1_1 of the display device 1_1 involved in this embodiment is disposed between the second substrate SUB2 and the second barrier layer BA2.

[0236] Specifically, the first charge trapping film AI1_1 involved in this embodiment can be disposed between the second substrate SUB2 and the second barrier layer BA2. In this case, the display device 1_1 may further include a lower semiconductor layer AS. The lower semiconductor layer AS can be disposed between the first substrate SUB1 and the second substrate SUB2. The lower semiconductor layer AS can be disposed on the first barrier layer BA1 and can be disposed between the first barrier layer BA1 and the second substrate SUB2.

[0237] The lower semiconductor layer AS may include amorphous silicon. However, it is not limited to this; the lower semiconductor layer AS may also include at least one of polycrystalline silicon and silicon oxide. The lower semiconductor layer AS serves to more firmly bond the components stacked on top of it. For example, by configuring the lower semiconductor layer AS, the first substrate SUB1 and the second substrate SUB2 disposed on the upper and lower parts of the lower semiconductor layer AS can be more firmly bonded, thereby improving the reliability of the display device 1_1.

[0238] In this case, the device characteristics of the first transistor T1 can be improved by configuring a first charge trapping film AI1_1 and a second charge trapping film AI2, and the brightness can be increased to improve image retention. Furthermore, as the spacing between the first charge trapping film AI1_1 and the semiconductor layer 100 decreases, the device characteristics of the first transistor T1 can be further improved. Simultaneously, by further configuring a lower semiconductor layer AS between the first substrate SUB1 and the second substrate SUB2, the reliability of the display device 1_1 can be improved.

[0239] Figure 15 This is a cross-sectional view of a display device according to yet another embodiment.

[0240] Reference Figure 15 ,and Figure 14The difference in this embodiment lies in that the first charge trapping film AI1_2 of the display device 1_2 is disposed between the second barrier layer BA2 and the buffer layer BF. In this case, the device characteristics of the first transistor T1 can also be improved by configuring the first charge trapping film AI1_2 and the second charge trapping film AI2, and the brightness can be increased to improve image retention. Furthermore, as the spacing between the first charge trapping film AI1_2 and the semiconductor layer 100 decreases, the device characteristics of the first transistor T1 can be further improved. At the same time, by also disposing a lower semiconductor layer AS between the first substrate SUB1 and the second substrate SUB2, the reliability of the display device 1_2 can be improved.

[0241] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, those skilled in the art should understand that the invention can be implemented in other specific forms without changing the technical concept or essential features of the invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not limiting.

Claims

1. A display device, comprising: First substrate; A first charge trapping film is disposed on the first substrate and includes silicon nitride; A semiconductor layer is disposed on the first charge trapping film and includes a first active layer of a first transistor and a second active layer of a second transistor; as well as The light-emitting element is electrically connected to the first transistor. The ratio of Si content to N content in the first charge trapping film is in the range of 1.6 to 2.

5. in, The Si content of the first charge trapping film is in the range of 60 at% to 70 at%, and the N content of the first charge trapping film is in the range of 25 at% to 35 at%.

2. The display device according to claim 1, wherein, The Si-H binding ratio of the first charge trap film is in the range of 8 at% to 15 at%.

3. The display device according to claim 2, wherein, The ratio of Si-H binding to NH binding in the first charge trapping film is in the range of 8 to 15, and the ratio of NH binding in the first charge trapping film is in the range of 0.1 at% to 15 at%.

4. The display device according to claim 1, further comprising: A second charge trapping film is disposed between the first charge trapping film and the semiconductor layer, and comprises silicon oxide. The NH binding rate of the second charge trapping film is in the range of 0.7 at% to 1.5 at%.

5. The display device according to claim 4, further comprising: The second substrate is disposed between the first substrate and the first charge trapping film; as well as The lower semiconductor layer is disposed between the first substrate and the second substrate.

6. The display device according to claim 1, wherein, The first charge trapping film overlaps with the first active layer but does not overlap with the second active layer.

7. A display device, comprising: First substrate; A first charge trapping film is disposed on the first substrate and includes silicon nitride; A second substrate is disposed on the first substrate, and the first charge trapping film is disposed between the first substrate and the second substrate; A second charge trapping film is disposed on the second substrate and comprises silicon oxide; A semiconductor layer is disposed on the second charge trapping film and includes a first active layer of the first transistor and a second active layer of the second transistor; as well as The light-emitting element is electrically connected to the first transistor. The NH binding rate of the second charge trapping film is in the range of 0.7 at% to 1.5 at%.

8. The display device according to claim 7, wherein, The first charge trapping film overlaps with the first active layer but does not overlap with the second active layer.

9. A display device, comprising: First substrate; A first charge trapping film is disposed on the first substrate and includes silicon nitride; A semiconductor layer is disposed on the first charge trapping film and includes a first active layer of a first transistor and a second active layer of a second transistor; as well as The light-emitting element is electrically connected to the first transistor. The Si content of the first charge trapping film is in the range of 60 at% to 70 at%, and the N content of the first charge trapping film is in the range of 25 at% to 35 at%.

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