Epitaxial structure of high electron mobility transistor and method for manufacturing the same
By introducing a stress compensation layer on the back side of the substrate, the problems of small process window and complex stress control layer in the epitaxial structure of GaN HEMT devices are solved, the thickness of the buffer layer is reduced and the crystal quality is improved, thereby increasing production efficiency and chip process flatness.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SINO NITRIDE SEMICON
- Filing Date
- 2022-01-06
- Publication Date
- 2026-07-21
AI Technical Summary
In the existing technology, the epitaxial structure of GaN high electron mobility transistor (HEMT) devices has problems such as a small process window, the time-consuming and complex manufacturing process of existing stress modulation layers, and limited improvement in crystal quality.
A stress compensation layer is introduced on the back side of the substrate. The stress in the epitaxial layer is compensated by pre-bending the substrate under pre-stress. The stress compensation layer, including a buffer layer and a device functional layer, is grown using hydride vapor phase epitaxy (HVPE) and metal-organic chemical vapor deposition (MOCVD) processes. The thickness of the buffer layer is reduced and the epitaxial growth conditions are optimized.
It significantly reduces the thickness of the buffer layer, shortens the time of the high-cost MOCVD process, expands the process window, improves crystal quality and production efficiency, and provides a flat substrate to facilitate subsequent chip processes.
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Figure CN114447099B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor device design and manufacturing, and in particular relates to an epitaxial structure of a GaN high electron mobility transistor and its fabrication method. Background Technology
[0002] With the development of science and technology, semiconductor devices with excellent properties such as high frequency, high efficiency, and high power are being applied in more and more fields. Third-generation semiconductor materials, represented by gallium nitride, have excellent physicochemical properties such as wide bandgap, high thermal conductivity, and corrosion resistance, and have broad application prospects in optoelectronic devices and microelectronic devices.
[0003] Gallium nitride (GaN) devices are conventionally fabricated by growing gallium nitride epitaxial layers on heterogeneous substrates such as sapphire, silicon carbide, and silicon. However, due to the use of heterogeneous substrates, lattice and thermal mismatches between the materials result in a high dislocation density in the epitaxial material, hindering the improvement of device performance and stability. In particular, the epitaxy of GaN high electron mobility transistors (HEMTs) on silicon substrates suffers from numerous microcracks in the epitaxial layer due to lattice and thermal mismatches. Existing solutions involve growing stress-modulating layers, such as multi-superlattices or compositionally graded AlGaN, between the epitaxial device layer and the substrate. However, these stress-modulating layers suffer from complex processes, large thicknesses, low production efficiency, and limited effectiveness. Summary of the Invention
[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an epitaxial structure of a high electron mobility transistor and its fabrication method, in order to solve the problems of small process window of HEMT epitaxial structure, time-consuming and complex existing stress modulation layer manufacturing process, and limited effect on improving crystal quality in the prior art.
[0005] To achieve the above and other related objectives, the present invention provides an epitaxial structure for a high electron mobility transistor, the epitaxial structure comprising: a substrate having a first principal plane and a second principal plane opposite to each other; a stress compensation layer located on the second principal plane of the substrate, the stress compensation layer comprising a first buffer layer for compensating stress in the epitaxial layer on the first principal plane opposite to the second principal plane; a second buffer layer located on the first principal plane of the substrate; and a device functional layer located on the second buffer layer, the device functional layer comprising a carbon-doped GaN high-resistivity layer, an undoped GaN channel layer, and an AlGaN barrier layer epitaxially grown on the second buffer layer.
[0006] Optionally, the substrate is a double-sided polished silicon substrate with a crystal orientation of (111), and the substrate has a size of 6 inches, 8 inches, or 12 inches.
[0007] Optionally, the stress compensation layer further includes a first nucleation layer disposed between the substrate and the first buffer layer, the first buffer layer comprising an AlN or AlGaN buffer layer.
[0008] Optionally, the first nucleation layer includes a polycrystalline AlN layer with a preferred orientation.
[0009] Optionally, the stress compensation layer further includes a capping layer disposed on the first buffer layer, the capping layer including a GaN capping layer.
[0010] Optionally, the epitaxial structure includes a second nucleation layer disposed between the first main surface of the substrate and the second buffer layer, the second buffer layer including one or more AlGaN buffer layers, and the second buffer layer having a thickness of less than 0.5 μm.
[0011] Optionally, the device functional layer further includes an AlN space layer, which is disposed between the undoped GaN channel layer and the AlGaN barrier layer.
[0012] Optionally, the device functional layer further includes a capping layer located on the AlGaN barrier layer, the capping layer comprising a GaN capping layer, wherein the AlGaN barrier layer contains an Al component with a molar percentage of 25%.
[0013] The present invention also provides a GaN high electron mobility transistor, wherein the GaN high electron mobility transistor is fabricated based on the epitaxial structure of the high electron mobility transistor described above.
[0014] This invention provides a method for fabricating an epitaxial structure of a high electron mobility transistor. The method includes: providing a substrate having a first main surface and a second main surface opposite to each other; depositing a stress compensation layer on the second main surface of the substrate, the stress compensation layer including a first buffer layer; epitaxially growing a second buffer layer on the first main surface of the substrate using a metal-organic chemical vapor deposition process; and epitaxially growing a device functional layer on the second buffer layer, the device functional layer including a carbon-doped GaN high-resistivity layer, an undoped GaN channel layer, and an AlGaN barrier layer.
[0015] Optionally, the step of depositing a stress compensation layer on the second main surface of the substrate further includes: after depositing a first nucleation layer on the second main surface of the substrate, depositing a first buffer layer on the first nucleation layer, wherein the first buffer layer includes an AlN or AlGaN buffer layer.
[0016] Optionally, the first nucleation layer is deposited on the second main surface of the substrate using a sputtering deposition process. The first nucleation layer includes a polycrystalline AlN layer with a preferred orientation.
[0017] Optionally, the first buffer layer is deposited on the first nucleation layer using a hydride vapor phase epitaxy (HVPE) process.
[0018] Optionally, a capping layer is deposited on the first buffer layer using a hydride vapor phase epitaxy process, the capping layer comprising a GaN capping layer.
[0019] Optionally, before the step of depositing the second buffer layer, the preparation method further includes: heat-treating the first main surface of the substrate for 3-10 minutes; epitaxially growing a second nucleation layer on the first main surface of the substrate; epitaxially growing a second buffer layer on the second nucleation layer, wherein the second buffer layer includes one or more AlGaN buffer layers and the second buffer layer has a thickness of less than 0.5 μm.
[0020] Optionally, the preparation method further includes: epitaxially growing an AlN space layer on the undoped GaN channel layer; and subsequently epitaxially growing an AlGaN barrier layer on the AlN space layer.
[0021] Optionally, the preparation method further includes: epitaxially growing a GaN capping layer on the AlGaN barrier layer, wherein the AlGaN barrier layer contains an Al component with a molar percentage of 25%.
[0022] As described above, the epitaxial structure of the high electron mobility transistor and its fabrication method of the present invention have the following beneficial effects:
[0023] This invention introduces a stress compensation layer on the back side of a substrate to impart a prestress to the substrate. Under the action of the prestress, the substrate is pre-bent. Thus, the introduction of the stress compensation layer can compensate for the stress in the epitaxial layer on the front side of the substrate, greatly reduce the thickness of the buffer layer on the front side of the substrate, and also help improve the crystal quality of epitaxial growth.
[0024] The stress compensation layer can be deposited using hydride vapor phase epitaxy, which can significantly shorten the time of the high-cost MOCVD process and has a cost advantage, thereby widening the process window of the HEMT epitaxial structure. Attached Figure Description
[0025] Figures 1-9 The diagram shows the structural schematics of each step in the preparation method of HEMT according to Embodiment 1 of the present invention.
[0026] Figure 10 The diagram shows a structural schematic of the steps in the preparation method of HEMT according to Embodiment 1 of the present invention to form a stress compensation layer.
[0027] Figure 11 The diagram shows a structural schematic representing the steps of forming a stress compensation layer in the HEMT preparation method of Embodiment 2 of the present invention.
[0028] Component designation explanation
[0029] 10 Silicon substrate
[0030] 10a First Main Face
[0031] 10b Second Main Face
[0032] 20 Stress Compensation Layer
[0033] 201 First nucleation layer
[0034] 202 First Buffer Layer
[0035] 203 Covering layer
[0036] 302 Second nucleation layer
[0037] 303 Second Buffer Layer
[0038] 304 carbon-doped GaN high-resistivity layer
[0039] 305 Undoped GaN Channel Layer
[0040] 306 AlN spatial layer
[0041] 307 AlGaN barrier layer
[0042] 308 GaN cap layer Detailed Implementation
[0043] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0044] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.
[0045] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.
[0046] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0047] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0048] In the fabrication process of GaN high electron mobility transistors, GaN is generally grown heteroepitaxially using MOCVD, where a nitrogen source reacts with a gallium source at high temperature for deposition. To suppress dislocations caused by lattice mismatch, an AlN or AlGaN buffer layer is first grown on the substrate before GaN epitaxial growth; this is one of the main methods for GaN heteroepitaxial growth. However, when GaN is epitaxially grown on silicon-based or silicon carbide substrates, the nitrogen source reacts with the Si element on the substrate at high temperature to form amorphous SiN. X This layer can reduce the quality of subsequent epitaxial layers. To address this issue, an Al source (e.g., trimethylaluminum; TMAl) is pre-channeled during the early stages of growth, depositing a layer of Al on the substrate surface to isolate the direct reaction between Si on the substrate and the nitrogen source, thereby suppressing the amorphous SiN layer. X The Al layer forms, and the pre-deposited Al layer can also serve as nucleation sites in the early stages of AlN growth, affecting the growth quality of AlN.
[0049] However, a strong pre-reaction exists between the aluminum source (TMAl) and the nitrogen source (e.g., ammonia (NH3)) during the growth of AlN films, which severely affects the crystal quality of the resulting particles. In practical processes, to ensure high-quality surface morphology and better crystal quality, a thick AlN or AlGaN buffer layer needs to be deposited, for example, a buffer layer with a thickness of more than 2.5 μm, which will account for more than half of the entire HEMT fabrication process time. To address the limitations of existing HEMT fabrication processes, such as small fabrication window and poor crystal quality of epitaxial materials in the fabricated HEMT devices, this invention provides an epitaxial structure of a high electron mobility transistor and its fabrication method. The epitaxial structure of the high electron mobility transistor includes: a substrate having opposing first and second principal planes; a stress compensation layer located on the second principal plane of the substrate, the stress compensation layer comprising a first buffer layer for compensating stress in the epitaxial layer on the first principal plane opposite to the second principal plane; a second buffer layer located on the first principal plane of the substrate; and a device functional layer located on the second buffer layer, the device functional layer comprising a carbon-doped GaN high-resistivity layer, an undoped GaN channel layer, and an AlGaN barrier layer epitaxially grown on the second buffer layer. By introducing a stress compensation layer on the back side of the substrate, a prestress is applied to the substrate. The application of the stress compensation layer can greatly reduce the thickness of the buffer layer on the front side of the substrate, which can significantly shorten the time of the high-cost MOCVD process. In addition, the pre-bending of the substrate under the prestress can compensate for the stress in the epitaxial layer that is subsequently grown, thereby providing a flatter substrate to facilitate subsequent chip processing.
[0050] The term "substrate" as used in this invention includes, but is not limited to, sapphire, silicon carbide, silicon substrates, and similar substrates. The specific structure and fabrication process of the HEMT of this invention will be described in detail below, using the epitaxial growth of a gallium nitride structure on a silicon substrate as an example.
[0051] Example 1
[0052] See Figures 1-9 and Figure 10 This embodiment provides a method for preparing a HEMT epitaxial structure, the method comprising:
[0053] like Figure 1 As shown, step 1) is performed first, providing a silicon substrate 10. Preferably, the silicon substrate 10 can be a double-sided polished silicon substrate, and its size can be 6 inches, 8 inches, or 12 inches.
[0054] In this embodiment, the silicon substrate is selected as a 6-inch double-sided polished silicon substrate 10 with a crystal orientation of (111), and the silicon substrate has a first main surface 10a and a second main surface 10b.
[0055] Then proceed to step 2), see [link]. Figure 2 A stress compensation layer 20 is deposited on the second main surface 10b of the silicon substrate. Specifically, the step of depositing the stress compensation layer includes at least: depositing a first nucleation layer 201 on the second main surface 10b of the silicon substrate, and subsequently growing a first buffer layer 202 on the first nucleation layer, as follows. Figure 10 As shown.
[0056] In this embodiment, the first buffer layer 202 is an AlN or AlGaN buffer layer, which can be deposited using hydride vapor phase epitaxy (HVPE) or metal-organic chemical vapor deposition (MOCVD). For example, the first nucleation layer 201 can be an AlN nucleation layer, which is beneficial for suppressing SiN nucleation. x To form and improve crystal quality, the first nucleation layer can be prepared by sputtering deposition or MOCVD process. Specifically, the first nucleation layer 201 is epitaxially grown on the second main surface 10b of a silicon substrate at 1165°C using MOCVD process.
[0057] As an example, AlN or AlGaN buffer layers can be deposited at 1085°C using an MOCVD process. Alternatively, for cost reasons, AlN or AlGaN buffer layers can be deposited at 1300°C using an HVPE process.
[0058] Next, see Figures 3 to 9 Step 3) involves forming an epitaxial structure of a GaN high electron mobility transistor on the first main surface of the substrate using a metal-organic chemical vapor deposition (MOCVD) process. This includes: epitaxially growing a second buffer layer 303 above the first main surface 10a of the silicon substrate; and subsequently epitaxially growing a device functional layer on the second buffer layer. Before depositing the second buffer layer, the fabrication method further includes: heat-treating the first main surface 10a of the silicon substrate for 3-10 minutes to remove oxides from the surface of the silicon substrate. This is beneficial for forming a high-quality AlN thin film on the silicon substrate.
[0059] like Figure 3 As shown, step 3-1) is performed, in which a second nucleation layer 302 is epitaxially grown on the silicon substrate 10 at 1165°C; in this embodiment, the second nucleation layer includes an AlN nucleation layer.
[0060] like Figure 4As shown, in step 3-2), a second buffer layer 303 is epitaxially grown on the second nucleation layer 302 at 1085°C. In this embodiment, the second buffer layer 303 includes one or more AlGaN buffer layers. The number and composition of the second buffer layer can be flexibly set according to actual needs to provide the desired compressive stress for the subsequent GaN epitaxial layer. Since a stress compensation layer is provided on the second main surface of the silicon substrate (i.e., the back side of the silicon substrate), the stress in the grown second buffer layer 302 (i.e., the front side of the silicon substrate) can be compensated by introducing a stress compensation layer with tensile stress in advance. Due to the application of the stress compensation layer on the back side of the silicon substrate, the second buffer layer has a thickness reduced to less than 0.5 μm.
[0061] like Figure 5 As shown, step 3-3) is performed, in which a carbon-doped GaN high-resistivity layer 304 is epitaxially grown on the buffer layer 303.
[0062] like Figure 6 As shown, in steps 3-4), an undoped GaN channel layer 305 is epitaxially grown on the carbon-doped GaN high-resistivity layer 304.
[0063] like Figure 7 As shown, in steps 3-5), an AlN space layer 306 is epitaxially grown on the undoped GaN channel layer 305.
[0064] like Figure 8 As shown, in steps 3-6), an AlGaN barrier layer 307 is epitaxially grown on the AlN space layer 306. In this embodiment, the AlGaN barrier layer 307 contains an Al component with a molar percentage of 25%.
[0065] like Figure 9 As shown, in steps 3-7), a GaN capping layer 308 is epitaxially grown on the AlGaN barrier layer 307; the GaN capping layer 308 is used to prevent the AlGaN barrier layer 307 from being oxidized.
[0066] Since the first buffer layer 202 deposited in step 2) has tensile stress, it can compensate for the tensile stress in the second buffer layer when the second buffer layer 303 is epitaxially grown on the first main surface of the silicon substrate, so that the device functional layer to be deposited is epitaxially grown on an almost flat plane.
[0067] As an alternative, a first nucleation layer 201 can be deposited on the second main surface 10b of a silicon substrate by a sputtering deposition process. For example, the first nucleation layer is a polycrystalline AlN layer with a preferred orientation.
[0068] In some examples, the first buffer layer 202 has cracks in which some of the tensile stress is released, but the residual tensile stress still compensates for the second buffer layer epitaxially grown on the first main surface 10a.
[0069] See Figure 9 This invention provides an epitaxial structure for a high electron mobility transistor, the epitaxial structure comprising: a substrate 10 having opposing first main surfaces 10a and second main surfaces 10b; a stress compensation layer 20 located on the second main surface of the substrate, the stress compensation layer comprising a first buffer layer 201; a second buffer layer 303 located on the first main surface of the substrate and a device functional layer, the device functional layer being disposed on the second buffer layer, the device functional layer comprising a carbon-doped GaN high-resistivity layer 304, an undoped GaN channel layer 305 and an AlGaN barrier layer 307 epitaxially grown sequentially on the second buffer layer.
[0070] The epitaxial structure further includes a second nucleation layer 302 located on a first main surface 10a of the substrate. The second nucleation layer is disposed between the substrate and a second buffer layer 303. The second nucleation layer can provide complete coverage of the first main surface, which is beneficial for improving crystal quality. In one example, an AlN nucleation layer can be disposed on the first main surface 10a of the substrate, and the second buffer layer 303 can be one or more AlGaN buffer layers. Similarly, the stress compensation layer 20 located on the second main surface 20b of the substrate further includes a first nucleation layer 201 disposed between the second main surface 10b of the substrate and the first buffer layer 202. In some examples, the first nucleation layer 201 can be an AlN nucleation layer; in other examples, the first nucleation layer 201 can be a polycrystalline AlN layer with a preferred orientation.
[0071] In this embodiment, the second buffer layer 303 includes one or more AlGaN buffer layers. Due to the presence of the back stress compensation layer of the silicon substrate, the second buffer layer has a thickness reduced to less than 0.5 μm, which can greatly shorten the process time for epitaxially growing the HEMT epitaxial structure.
[0072] Example 2
[0073] like Figures 1-9 and Figure 11 As shown, this embodiment provides a method for fabricating a HEMT epitaxial structure, the basic steps of which are as described in Embodiment 1, except that:
[0074] At step 2), a stress compensation layer 20 is deposited on the second main surface 10b of the silicon substrate. See also Figure 11The step of depositing the stress compensation layer includes at least: 2-1) depositing a first nucleation layer 201 on the second main surface 10b of the silicon substrate, followed by growing a first buffer layer 202 on the first nucleation layer; 2-2) growing a capping layer 203 on the first buffer layer. The capping layer 203 can be deposited by HVPE or MOCVD processes. For example, the capping layer 203 is a GaN capping layer. Specifically, in step 2-2), the GaN capping layer can be deposited at 1050°C using an MOCVD process; or, the cost-effective HVPE process can be used to deposit the GaN capping layer, for example, at 1000°C using an HVPE process.
[0075] In the HEMT epitaxial structure provided in this embodiment, the stress compensation layer 20 is located on the second main surface of the substrate. Besides the first buffer layer 202, the stress compensation layer also includes a capping layer 203 disposed on the first buffer layer 202, for example, a GaN capping layer. The capping layer 203 provides a compressive stress, which can further balance the compressive stress of the device functional layer grown on the first main surface of the substrate, thereby resulting in an epitaxial wafer that is almost flat after the epitaxial process of the device functional layer.
[0076] In this embodiment, the capping layer 203 deposited on the second main surface of the silicon substrate has compressive stress. After the device functional layer is epitaxially grown on the first main surface of the silicon substrate, the compressive stress in the device functional layer can be compensated, so that the stress on the two opposing main surfaces of the substrate is balanced. This reduces the thermal mismatch between the substrate and the GaN epitaxial layer during the cooling to room temperature process and thereby suppresses the possible warping. As a result, an almost flat epitaxial wafer can be obtained after the epitaxial process of the device functional layer.
[0077] As described above, the GaN-HEMT epitaxial structure and its preparation method of the present invention have the following beneficial effects:
[0078] This invention introduces a stress compensation layer on the back side of a substrate, imparting a prestress to the substrate. Under this prestress, the substrate is pre-bent. The introduction of this stress compensation layer can significantly reduce the thickness of the buffer layer on the front side of the substrate. Due to the introduction of the stress compensation layer, the thickness of the buffer layer can be reduced to below 0.5 μm.
[0079] The application of stress compensation layers can significantly shorten the time of high-cost MOCVD processes, widen the epitaxial process window of HEMT, improve production efficiency, and the relatively flat substrate also facilitates subsequent chip processes.
[0080] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.
[0081] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. An epitaxial structure for a high electron mobility transistor, characterized in that, The epitaxial structure includes: The substrate has a first principal plane and a second principal plane that are opposite to each other. A stress compensation layer is located on the second main surface of the substrate. The stress compensation layer includes a first buffer layer for compensating the stress in the epitaxial layer on the first main surface opposite to the second main surface. The stress compensation layer is deposited using a hydride vapor phase epitaxy process. A second buffer layer is located on the first main surface of the substrate, the second buffer layer having a thickness of less than 0.5 μm, and the first main surface has undergone heat treatment; The device functional layer is located on the second buffer layer and includes a carbon-doped GaN high-resistivity layer, an undoped GaN channel layer, and an AlGaN barrier layer epitaxially grown on the second buffer layer.
2. The epitaxial structure of the high electron mobility transistor according to claim 1, characterized in that: The substrate is a double-sided polished silicon substrate with a crystal orientation of (111), and the substrate size is 6 inches, 8 inches, or 12 inches.
3. The epitaxial structure of the high electron mobility transistor according to claim 1, characterized in that: The stress compensation layer further includes a first nucleation layer, which is disposed between the substrate and the first buffer layer. The first buffer layer includes an AlN or AlGaN buffer layer.
4. The epitaxial structure of the high electron mobility transistor according to claim 3, characterized in that: The first nucleation layer includes a polycrystalline AlN layer with a preferred orientation.
5. The epitaxial structure of the high electron mobility transistor according to claim 3, characterized in that: The stress compensation layer further includes a capping layer disposed on the first buffer layer, the capping layer including a GaN capping layer.
6. The epitaxial structure of the high electron mobility transistor according to claim 1, characterized in that: The epitaxial structure includes a second nucleation layer disposed between the first main surface of the substrate and the second buffer layer, the second buffer layer including one or more AlGaN buffer layers.
7. A GaN high electron mobility transistor, characterized in that: The GaN high electron mobility transistor is fabricated based on the epitaxial structure of the high electron mobility transistor according to any one of claims 1 to 6.
8. A method for fabricating an epitaxial structure of a high electron mobility transistor, characterized in that, The preparation method includes: A substrate is provided, the substrate having opposing first and second principal surfaces; A stress compensation layer is deposited on the second main surface of the substrate. The stress compensation layer includes a first buffer layer. The stress compensation layer is deposited using a hydride vapor phase epitaxy process. A second buffer layer is epitaxially grown on the first main surface of the substrate using a metal-organic chemical vapor deposition process, and a device functional layer is epitaxially grown on the second buffer layer. The device functional layer includes a carbon-doped GaN high-resistivity layer, an undoped GaN channel layer, and an AlGaN barrier layer. The second buffer layer has a thickness of less than 0.5 μm, and the first main surface has undergone heat treatment.
9. The preparation method according to claim 8, characterized in that, The step of depositing a stress compensation layer on the second main surface of the substrate further includes: after depositing a first nucleation layer on the second main surface of the substrate, depositing a first buffer layer on the first nucleation layer, wherein the first buffer layer includes an AlN or AlGaN buffer layer.
10. The preparation method according to claim 9, characterized in that: The first nucleation layer is deposited on the second main surface of the substrate using a sputtering deposition process. The first nucleation layer includes a polycrystalline AlN layer with a preferred orientation.
11. The preparation method according to claim 8, characterized in that: The first buffer layer is deposited on the first nucleation layer using a hydride vapor phase epitaxy process.
12. The preparation method according to claim 8, characterized in that, The preparation method further includes: depositing a capping layer on the first buffer layer by a hydride vapor phase epitaxy process, wherein the capping layer includes a GaN capping layer.
13. The preparation method according to claim 8, characterized in that: Prior to the step of depositing the second buffer layer, the preparation method further includes: The first main surface of the substrate is heat-treated for 3-10 minutes. A second nucleation layer is epitaxially grown on the first main surface of the substrate; A second buffer layer is epitaxially grown on the second nucleation layer, wherein the second buffer layer includes one or more AlGaN buffer layers and the second buffer layer has a thickness of less than 0.5 μm.