Semiconductor device and semiconductor module

Abstract

The present invention discloses a semiconductor device and a semiconductor module. A semiconductor device and a semiconductor module capable of reducing loss are provided. According to an embodiment, the semiconductor device includes a first electrode, a second electrode, a third electrode, a fourth electrode, a semiconductor component, a first insulating component and a second insulating component. The semiconductor component is arranged between the second electrode and the first electrode. The first semiconductor component includes first to seventh semiconductor regions. The fourth semiconductor region has a first impurity concentration, a first carrier concentration and a first volume ratio of the volume of the fourth semiconductor region to the volume of the semiconductor component. The seventh semiconductor region has at least one of a second impurity concentration of a second conductivity type higher than the first impurity concentration, a second carrier concentration of a second conductivity type higher than the first carrier concentration, and a second volume ratio higher than the first volume ratio. The second volume ratio is the volume ratio of the seventh semiconductor region to the volume of the semiconductor component.

Description

[0001] This application is based on Japanese Patent Application No. 2020-183559 (filing date November 2, 2020) and claims priority from the present application. The present application incorporates all the contents of the application by reference to the application. Technical Field

[0002] Embodiments of the present invention relate to a semiconductor device and a semiconductor module. Background Art

[0003] For example, in semiconductor devices such as transistors, it is desirable to reduce loss. Summary of the invention

[0004] Embodiments of the present invention provide a semiconductor device and a semiconductor module capable of reducing loss.

[0005] According to an embodiment of the present invention, a semiconductor device includes a first electrode, a second electrode, a third electrode, a fourth electrode, a semiconductor component, a first insulating component, and a second insulating component. The direction from the second electrode to the first electrode is along the first direction. The semiconductor component is arranged between the second electrode and the first electrode in the first direction. The first semiconductor component includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type arranged between the first semiconductor region and the first electrode, a third semiconductor region of the first conductivity type arranged between the second semiconductor region and the first electrode, a fourth semiconductor region of the second conductivity type arranged between the second semiconductor region and the first electrode, a fifth semiconductor region of the second conductivity type arranged between the first semiconductor region and the second electrode, a sixth semiconductor region of the first conductivity type arranged between the fifth semiconductor region and the second electrode, and a seventh semiconductor region of the second conductivity type arranged between the fifth semiconductor region and the second electrode. The fourth semiconductor region has a first impurity concentration of the second conductivity type, a first carrier concentration of the second conductivity type, and a first volume ratio of the volume of the fourth semiconductor region to the volume of the semiconductor component. The seventh semiconductor region has at least one of a second impurity concentration of the second conductivity type higher than the first impurity concentration, a second carrier concentration of the second conductivity type higher than the first carrier concentration, and a second volume ratio higher than the first volume ratio. The second volume ratio is a volume ratio of the seventh semiconductor region to the volume of the semiconductor component. A second direction from a portion of the third electrode to the second semiconductor region intersects with the first direction. At least a portion of the third semiconductor region is located at least one of a first position between a portion of the third electrode and the fourth semiconductor region in the second direction and a second position between the portion of the third electrode and a portion of the second semiconductor region in the second direction. A third direction from a portion of the fourth electrode to the fifth semiconductor region intersects with the first direction. At least a portion of the sixth semiconductor region is located at least at a third position between a portion of the fourth electrode and the seventh semiconductor region in the third direction and a fourth position between the portion of the fourth electrode and a portion of the fifth semiconductor region in the third direction. At least a portion of the first insulating member is located between the third electrode and the semiconductor member. At least a portion of the second insulating member is located between the fourth electrode and the semiconductor member.

[0006] According to the semiconductor device having the above structure, it is possible to provide a semiconductor device and a semiconductor module capable of reducing loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 (a) to (c) are schematic cross-sectional views illustrating the semiconductor device according to the first embodiment.

[0008] Figure 2 (a) to (c) are schematic cross-sectional views illustrating the semiconductor device according to the first embodiment.

[0009] Figure 3 It is a graph illustrating the characteristics in a semiconductor device.

[0010] Figure 4 It is a graph illustrating the characteristics in a semiconductor device.

[0011] Figure 5 It is a graph illustrating the characteristics in a semiconductor device.

[0012] Figure 6 (a) to (c) are schematic cross-sectional views illustrating the semiconductor device according to the first embodiment.

[0013] Figure 7 (a) to (c) are schematic cross-sectional views illustrating the semiconductor device according to the first embodiment.

[0014] Figure 8 (a) to (c) are schematic cross-sectional views illustrating the semiconductor device according to the first embodiment.

[0015] Fig. 9 (a) to (c) are schematic cross-sectional views illustrating the semiconductor device according to the first embodiment.

[0016] Fig.10 (a) to (c) are schematic cross-sectional views illustrating the semiconductor device according to the first embodiment.

[0017] Fig.11 It is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.

[0018] Fig.12 It is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.

[0019] Fig.13 It is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.

[0020] Fig.14 It is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.

[0021] Fig.15 This is a schematic diagram illustrating a semiconductor module according to the second embodiment.

[0022] Fig.16 (a) and (b) are schematic diagrams illustrating the operation of the semiconductor module according to the second embodiment.

[0023] Fig.17 It is a graph illustrating the characteristics in a semiconductor device.

[0024] Explanation of symbols

[0025] 10: semiconductor component; 11-19: first to ninth semiconductor regions; 11p: a portion; 41-44: first to fourth insulating components; 51-54: first to fourth electrodes; 51C, 52C: connecting components; 51L, 52L: connecting components; 51T, 52T: terminals; 61, 62: first and second conductive components; 61C, 62C: connecting components; 61T, 62T: terminals; 70: control unit; 110, 110a-110i: semiconductor device; 210 : Semiconductor module; CR: ratio; E3, E4: potential; Eoff: turn-off switching loss; Eoff_1: reduction; L1, L2: 1st, 2nd length; PL1, PL2: 1st, 2nd plane; V1~V4: 1st to 4th potential; VCE(sat)_1: reduction; d1~d4: 1st to 4th distance; t1, t2: 1st, 2nd moment; td: time difference; tm: time; w1, w2: 1st, 2nd width; z1, z2: 1st, 2nd thickness. DETAILED DESCRIPTION

[0026] Hereinafter, various embodiments of the present invention will be described with reference to the drawings.

[0027] The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the size between the parts, etc. are not necessarily the same as in reality. Even when the same part is shown, the sizes and ratios of each other may be shown differently due to different drawings.

[0028] In the present specification and each drawing, the same reference numerals are given to the same elements as those described previously with respect to the drawings already shown, and the detailed description is appropriately omitted.

[0029] (First embodiment)

[0030] Figure 1 (a) to (c) and Figure 2 (a) to (c) are schematic cross-sectional views illustrating the semiconductor device according to the first embodiment.

[0031] Figure 1 (b) is Figure 1 (a) A1-A2 line cross-sectional view. Figure 1 (c) is Figure 1(a) A3-A4 line sectional view. Figure 2 (b) is Figure 2 (a) A1-A2 line cross-sectional view. Figure 2 (c) is Figure 2 (a) A3-A4 line sectional view.

[0032] like Figure 1 As shown in FIG. 1 ( a ), the semiconductor device 110 according to the embodiment includes a first electrode 51 , a second electrode 52 , a third electrode 53 , a fourth electrode 54 , the semiconductor member 10 , a first insulating member 41 , and a second insulating member 42 .

[0033] The direction from the second electrode 52 to the first electrode 51 is along the first direction. The first direction is referred to as the Z-axis direction. A direction perpendicular to the first direction is referred to as the X-axis direction. A direction perpendicular to the Z-axis direction and the X-axis direction is referred to as the Y-axis direction.

[0034] The semiconductor component 10 is disposed in the first direction (Z-axis direction) between the second electrode 52 and the first electrode 51. The semiconductor component 10 includes a first semiconductor region 11 of the first conductivity type, a second semiconductor region 12 of the second conductivity type, a third semiconductor region 13 of the first conductivity type, a fourth semiconductor region 14 of the second conductivity type, a fifth semiconductor region 15 of the second conductivity type, a sixth semiconductor region 16 of the first conductivity type, and a seventh semiconductor region 17 of the second conductivity type.

[0035] For example, the first conductivity type is n-type and the second conductivity type is p-type. In the embodiment, the first conductivity type may be p-type and the second conductivity type may be n-type. In the following example, the first conductivity type is n-type and the second conductivity type is p-type.

[0036] The first semiconductor region 11 is located between the second electrode 52 and the first electrode 51. The second semiconductor region 12 is provided between the first semiconductor region 11 and the first electrode 51. The third semiconductor region 13 is provided between the second semiconductor region 12 and the first electrode 51. The fourth semiconductor region 14 is provided between the second semiconductor region 12 and the first electrode 51. In this example, the direction from the third semiconductor region 13 to the fourth semiconductor region 14 intersects the Z-axis direction. For example, the direction from the third semiconductor region 13 to the fourth semiconductor region 14 is along the X-axis direction.

[0037] The fifth semiconductor region 15 is provided between the first semiconductor region 11 and the second electrode 52. The sixth semiconductor region 16 is provided between the fifth semiconductor region 15 and the second electrode 52. The seventh semiconductor region 17 is provided between the fifth semiconductor region 15 and the second electrode 52. In this example, the direction from the sixth semiconductor region 16 to the seventh semiconductor region 17 intersects the Z-axis direction. For example, the direction from the sixth semiconductor region 16 to the seventh semiconductor region 17 is along the X-axis direction.

[0038] In this example, the semiconductor component 10 includes an eighth semiconductor region 18 and a ninth semiconductor region 19. The eighth semiconductor region 18 is provided between the first semiconductor region 11 and the second semiconductor region 12. The eighth semiconductor region 18 is of the first conductivity type. The ninth semiconductor region 19 is provided between the first semiconductor region 11 and the fifth semiconductor region 15. The ninth semiconductor region 19 is of the first conductivity type.

[0039] The second direction from a portion of the third electrode 53 to the second semiconductor region 12 intersects the first direction. The second direction is, for example, the X-axis direction. In this example, at least a portion of the third semiconductor region 13 is between a portion of the third electrode 53 and the fourth semiconductor region 14 in the second direction (for example, the X-axis direction).

[0040] The third direction from a portion of the fourth electrode 54 to the fifth semiconductor region 15 intersects the first direction. In this example, the third direction is along (the X-axis direction). The direction from the fourth electrode 54 to the fifth semiconductor region 15 is, for example, along the third direction (for example, the X-axis direction). In this example, at least a portion of the sixth semiconductor region 16 is between a portion of the fourth electrode 54 and the seventh semiconductor region 17 in the third direction (for example, the X-axis direction). In this example, the third direction is along the second direction.

[0041] The position of the portion 11p of the first semiconductor region 11 in the first direction (Z-axis direction) is between the position of the fourth electrode 54 in the first direction and the position of the third electrode 53 in the first direction. In this example, the third electrode 53 and the fourth electrode 54 are between the second electrode 52 and the first electrode 51. In this example, the portion 11p of the first semiconductor region 11 is between the fourth electrode 54 and the third electrode 53 in the first direction (Z-axis direction).

[0042] At least a portion of the first insulating member 41 is located between the third electrode 53 and the semiconductor component 10. A portion of the first insulating member 41 may be provided between the third electrode 53 and the first electrode 51.

[0043] At least a portion of the second insulating member 42 is located between the fourth electrode 54 and the semiconductor component 10. A portion of the second insulating member 42 may be provided between the fourth electrode 54 and the second electrode 52.

[0044] In the semiconductor device 110, the following first and second actions can be performed. In the first action, the current flowing between the first electrode 51 and the second electrode 52 can be controlled by the potential of the third electrode 53. The potential of the third electrode 53 is, for example, a potential based on the potential of the first electrode 51. In the first action, the current flows in the direction from the second electrode 52 to the first electrode 51. In the second action, the fourth electrode 54 is made to have a high potential, so that the current flows in the direction from the first electrode 51 to the second electrode 52. The semiconductor device 110 is, for example, an RC-IGBT (Reverse-Conducting Insulated Gate Bipolar Transistor). The first action corresponds to, for example, an IGBT action. The second action corresponds to, for example, a diode action. The first electrode 51 is, for example, an emitter electrode. The second electrode 52 is, for example, a collector electrode. The third electrode 53 is, for example, a gate electrode. The fourth electrode 54 is, for example, a control electrode. The first and second actions may also be performed repeatedly.

[0045] like Figure 2 As shown in (a), the distance between the second electrode 52 and the third electrode 53 along the first direction (Z-axis direction) is set as a first distance d1. The distance between the second electrode 52 and the second semiconductor region 12 along the first direction is set as a second distance d2. The first distance d1 is shorter than the second distance d2.

[0046] like Figure 2 As shown in (a), the distance between the first electrode 51 and the fourth electrode 54 along the first direction (Z-axis direction) is set as the third distance d3. The distance between the first electrode 51 and the fifth semiconductor region 15 along the first direction is set as the fourth distance d4. The third distance d3 is shorter than the fourth distance.

[0047] For example, the lower end of the third electrode 53 is located below the upper end of the first semiconductor region 11. For example, the upper end of the fourth electrode 54 is located above the lower end of the first semiconductor region 11.

[0048] In this example, the direction from the third semiconductor region 13 to the fourth semiconductor region 14 intersects with the first direction (Z-axis direction). The direction from the third semiconductor region 13 to the fourth semiconductor region 14 is, for example, along the second direction (for example, X-axis direction). The direction from the sixth semiconductor region 16 to the seventh semiconductor region 17 intersects with the first direction (Z-axis direction). The direction from the sixth semiconductor region 16 to the seventh semiconductor region 17 is, for example, along the second direction (for example, X-axis direction).

[0049] In this example, at least a portion of the third semiconductor region 13 is located between a portion of the third electrode 53 and the fourth semiconductor region 14 . At least a portion of the sixth semiconductor region 16 is located between a portion of the fourth electrode 54 and the seventh semiconductor region 17 .

[0050] The third semiconductor region 13 and the fourth semiconductor region 14 are electrically connected to the first electrode 51 . The sixth semiconductor region 16 and the seventh semiconductor region 17 are electrically connected to the second electrode 52 .

[0051] For example, the second conductivity type carrier concentration (for example, the first carrier concentration) of the fourth semiconductor region 14 is higher than the second conductivity type carrier concentration of the second semiconductor region 12. As a result, the resistance of the connection with the first electrode 51 is reduced. For example, the collector-emitter saturation voltage VCE(sat) can be reduced.

[0052] For example, the second conductivity type carrier concentration (for example, the second carrier concentration) of the seventh semiconductor region 17 is higher than the second conductivity type carrier concentration in the fifth semiconductor region 15. As a result, the resistance of the connection with the second electrode 52 is reduced. For example, the collector-emitter saturation voltage VCE(sat) can be reduced.

[0053] For example, the first conductivity type carrier concentration in the third semiconductor region 13 is higher than the first conductivity type carrier concentration in the first semiconductor region 11. This reduces the resistance of the connection with the first electrode 51. For example, the collector-emitter saturation voltage VCE(sat) can be reduced.

[0054] For example, the first conductivity type carrier concentration in the sixth semiconductor region 16 is higher than the first conductivity type carrier concentration in the first semiconductor region 11. This reduces the resistance of the connection with the second electrode 52. For example, the collector-emitter saturation voltage VCE(sat) can be reduced.

[0055] For example, the first conductivity type impurity concentration in the eighth semiconductor region 18 is higher than that in the first semiconductor region 1. For example, the first conductivity type impurity concentration in the ninth semiconductor region 19 is higher than that in the first semiconductor region 11.

[0056] For example, the first semiconductor region 11 is n － The third semiconductor region 13 and the sixth semiconductor region 16 are, for example, n ++ The eighth semiconductor region 18 and the ninth semiconductor region 19 are, for example, n + area.

[0057] For example, the second semiconductor region 12 and the fifth semiconductor region 15 are, for example, p-type regions. For example, the fourth semiconductor region 14 may be, for example, p-type regions. + The seventh semiconductor region 17 may be, for example, a p ++ Region, etc.

[0058] In one example of the embodiment, the carrier concentration of the second conductivity type in the fourth semiconductor region 14 is different from the carrier concentration of the second conductivity type in the seventh semiconductor region 17. As described below, in the embodiment, at least one of the conductive characteristics and the shape is different between the fourth semiconductor region 14 and the seventh semiconductor region 17.

[0059] For example, the fourth semiconductor region 14 has a first impurity concentration of the second conductivity type. The fourth semiconductor region 14 has a first carrier concentration of the second conductivity type. The fourth semiconductor region 14 has a first thickness z1 along the first direction (see Figure 2 (a)). The fourth semiconductor region 14 has a first area ratio. The first area ratio is the area ratio of the fourth semiconductor region 14 relative to the first plane PL1 (refer to Figure 1 The first plane PL1 passes through the fourth semiconductor region 14 along the XY plane, for example. The fourth semiconductor region 14 has a first volume ratio. The first volume ratio is a ratio of the volume of the fourth semiconductor region 14 to the volume of the semiconductor component 10.

[0060] For example, the seventh semiconductor region 17 has a second impurity concentration of the second conductivity type. The seventh semiconductor region 17 has a second carrier concentration of the second conductivity type. The seventh semiconductor region 17 has a second thickness z2 along the first direction (see Figure 2 (a)). The seventh semiconductor region 17 has a second area ratio. The second area ratio is the area of ​​the seventh semiconductor region 17 relative to the second plane PL2 (refer to Figure 2The second plane PL2 passes through the seventh semiconductor region 17 along the XY plane, for example. The seventh semiconductor region 17 has a second volume ratio. The second volume ratio is a ratio of the volume of the seventh semiconductor region 17 to the volume of the semiconductor component 10.

[0061] For example, the second impurity concentration is higher than the first impurity concentration. For example, the second carrier concentration is higher than the first carrier concentration. For example, the second thickness z2 is thicker than the first thickness z1. For example, the second area ratio is higher than the first area ratio. For example, the second volume ratio is higher than the first volume ratio.

[0062] As described below, the turn-off switching loss Eoff can be reduced. For example, the collector-emitter saturation voltage VCE(sat) can be reduced. The second conductivity type carrier concentration in the fourth semiconductor region 14 is low, so that, for example, the switching loss Err during the reverse recovery operation can be reduced.

[0063] Hereinafter, an example of the characteristics of the semiconductor device will be described. Hereinafter, the relationship between the characteristics of the IGBT at the time of off-state operation and the difference in carrier concentration between the fourth semiconductor region 14 and the seventh semiconductor region 17 will be described.

[0064] Figure 3 It is a graph illustrating the characteristics in a semiconductor device.

[0065] Figure 3 The horizontal axis is the ratio CR of carrier concentration. The ratio CR is the ratio of the carrier concentration of the second conductivity type in the seventh semiconductor region 17 (the second carrier concentration C2) to the carrier concentration of the second conductivity type in the fourth semiconductor region 14 (the first carrier concentration C1). The ratio CR is C2 / C1. Figure 3 The vertical axis is the reduction amount Eoff_1 of the turn-off switching loss Eoff. The reduction amount Eoff_1 of the turn-off switching loss Eoff is the reduction amount based on the turn-off switching loss Eoff in the structure without the fourth electrode 54. A larger reduction amount Eoff_1 of the turn-off switching loss Eoff corresponds to a smaller turn-off switching loss Eoff. Figure 3 In the embodiment, at the time when the potential of the third electrode 53 becomes the off state, the potential of the fourth electrode 54 becomes the on state.

[0066] like Figure 3 As shown in FIG. 1 , when the ratio CR becomes higher, the reduction amount Eoff_1 of the turn-off switching loss Eoff becomes larger. Figure 3 It can be seen that by increasing the ratio CR, the turn-off switching loss Eoff can be reduced. When the ratio CR is higher, it is considered that more carriers are accumulated in the on state. Therefore, when the ratio CR is higher, the total amount of carriers that can be discharged by turning on the fourth electrode 54 increases. Therefore, it is considered that the turn-off switching loss Eoff is reduced.

[0067] Figure 4 It is a graph illustrating the characteristics in a semiconductor device.

[0068] exist Figure 4 In the embodiment, before the potential of the third electrode 53 becomes the off state, the potential of the fourth electrode 54 becomes the on state. Figure 4 In the example of , the difference between the time when the potential of the fourth electrode 54 becomes the on state and the time when the potential of the third electrode 53 becomes the off state is 60 μs. Figure 4 The horizontal axis is the ratio CR. Figure 4 The vertical axis is the reduction in the turn-off switching loss Eoff_1. Figure 4 In the example shown, as the ratio CR becomes higher, the reduction amount Eoff_1 of the turn-off switching loss Eoff becomes larger.

[0069] Figure 5 It is a graph illustrating the characteristics in a semiconductor device.

[0070] Figure 5 The horizontal axis is the ratio CR. Figure 5 The vertical axis of is the reduction amount VCE(sat)_1 of the collector-emitter saturation voltage VCE(sat). The reduction amount VCE(sat)_1 of the collector-emitter saturation voltage VCE(sat) is the reduction amount based on the collector-emitter saturation voltage VCE(sat) in the structure where the fourth electrode 54 is not provided. Figure 5 It is known that when the ratio CR increases, the decrease amount VCE(sat)_1 of the collector-emitter saturation voltage VCE(sat) increases. By increasing the ratio CR, the collector-emitter saturation voltage VCE(sat) can be reduced.

[0071] according to Figure 3 to Figure 5 It is preferred that the ratio CR of the second conductivity type carrier concentration (second carrier concentration C2) in the seventh semiconductor region 17 to the second conductivity type carrier concentration (first carrier concentration C1) in the fourth semiconductor region 14 is 20 or more. Thus, for example, the turn-off switching loss Eoff can be reduced. For example, the collector-emitter saturation voltage VCE(sat) can be reduced.

[0072] In the embodiment, for example, the amount of carriers of the second conductivity type in the seventh semiconductor region 17 is greater than the amount of carriers of the second conductivity type in the fourth semiconductor region 14. For example, in IGBT operation, the injection efficiency of holes in the second electrode 52 is high. For example, the injection efficiency of holes in the second electrode 52 in IGBT operation is higher than the injection efficiency of holes in the first electrode 51 in diode operation. It is easy to reduce the switching loss Err during the reverse recovery operation in the diode operation. On the other hand, at the turn-off of the IGBT operation, the turn-off switching loss Eoff can be reduced by the second electrode 52 with a high carrier concentration.

[0073] In the embodiment, for example, the turn-off switching loss Eoff can be effectively reduced. For example, the collector-emitter saturation voltage VCE(sat) can be effectively reduced.

[0074] Thus, the carrier concentration of the second conductivity type in the seventh semiconductor region 17 (the second carrier concentration) is made higher than the carrier concentration of the second conductivity type in the fourth semiconductor region 14 (the first carrier concentration), thereby, for example, being able to reduce loss. According to the embodiment, a semiconductor device capable of reducing loss can be provided.

[0075] In an embodiment, the second carrier concentration is preferably 20 times or more of the first carrier concentration. Thus, the loss can be effectively reduced. For example, the second carrier concentration may be 2000 times or less of the first carrier concentration.

[0076] In the embodiment, the fourth semiconductor region 14 and the seventh semiconductor region 17 may be formed by introducing the second conductivity type impurities into the first conductivity type region. In this case, the difference in carrier concentration may be formed by the difference in the concentration of the second conductivity type impurities in these regions.

[0077] In an embodiment, for example, the second impurity concentration is preferably 20 times or more of the first impurity concentration. This can effectively reduce the loss. For example, the second impurity concentration may be 2000 times or less of the first impurity concentration.

[0078] exist Figure 3 In the example of FIG. 1 , the relationship between the difference in impurity concentration between the fourth semiconductor region 14 and the seventh semiconductor region 17 and the electrical characteristics is shown. Figure 3 The characteristics shown as an example can also be obtained by the difference in volume between the fourth semiconductor region 14 and the seventh semiconductor region 17 .

[0079] For example, the second thickness z2 of the seventh semiconductor region 17 is thicker than the first thickness z1 of the fourth semiconductor region 14, so that the loss can be reduced.

[0080] For example, the ratio of the area of ​​the seventh semiconductor region 17 to the unit area in the second plane PL2 (the second area ratio) is higher than the ratio of the area of ​​the fourth semiconductor region 14 to the unit area in the first plane PL1 (the first area ratio), so that the loss can be reduced. In the embodiment, for example, the second area ratio is 20 times or more of the first area ratio. Thus, the loss can be effectively reduced. For example, the second area ratio can be 2000 times or less of the first area ratio.

[0081] For example, the ratio of the volume of the seventh semiconductor region 17 to the volume of the semiconductor component 10 (the second volume ratio) is higher than the ratio of the volume of the fourth semiconductor region 14 to the volume of the semiconductor component 10 (the first volume ratio), thereby reducing the loss. In an embodiment, for example, the second volume ratio is 20 times or more of the first volume ratio. Thus, the loss can be effectively reduced.

[0082] For example, the length in the X-axis direction (the first width w1 and the second width w2: see Figure 2 The length in the Y-axis direction between the fourth semiconductor region 14 and the seventh semiconductor region 17 may also be changed (the first length L1 and the second length L2: see Figure 2 (c)), thereby changing the volume ratio.

[0083] Several examples of semiconductor devices according to the embodiments are described below. Hereinafter, descriptions of parts to which the same structure as the semiconductor device 110 can be applied are omitted.

[0084] Figure 6 (a) to (c) are schematic cross-sectional views illustrating the semiconductor device according to the first embodiment.

[0085] Figure 6 (b) is Figure 6 (a) A1-A2 line cross-sectional view. Figure 6 (c) is Figure 6 (a) A3-A4 line sectional view.

[0086] like Figure 6 As shown in (a), in the semiconductor device 110a, the second thickness z2 of the seventh semiconductor region 17 is thicker than the first thickness z1 of the fourth semiconductor region 14. In an embodiment, for example, the second thickness z2 is more than 20 times the first thickness z1. Thus, the loss can be effectively reduced. The second thickness z2 can be less than 2000 times the first thickness z1.

[0087] Figure 7 (a) to (c) are schematic cross-sectional views illustrating the semiconductor device according to the first embodiment.

[0088] Figure 7 (b) is Figure 7 (a) A1-A2 line cross-sectional view. Figure 7 (c) is Figure 7 (a) A3-A4 line sectional view.

[0089] like Figure 7 (b) and Figure 7 As shown in (c), in the semiconductor device 110b, the second width w2 of the seventh semiconductor region 17 along the second direction (X-axis direction) is larger than the first width w1 of the fourth semiconductor region 14 along the second direction. In the embodiment, for example, the second width w2 is greater than 20 times and less than 2000 times the first width w1. Thus, the loss can be effectively reduced.

[0090] Figure 8 (a) to (c) are schematic cross-sectional views illustrating the semiconductor device according to the first embodiment.

[0091] Figure 8 (b) is Figure 8 (a) A1-A2 line cross-sectional view. Figure 8 (c) is Figure 8 (a) A3-A4 line sectional view.

[0092] like Figure 8 (b) and Figure 8 As shown in (c), in the semiconductor device 110c, the second width w2 of the seventh semiconductor region 17 is also larger than the first width w1. In the semiconductor device 110c, a portion of the second semiconductor region 12 exists between the third semiconductor region 13 and the fourth semiconductor region 14. In the semiconductor device 110c, the loss can also be reduced.

[0093] Fig. 9 (a) to (c) are schematic cross-sectional views illustrating the semiconductor device according to the first embodiment.

[0094] Fig. 9 (b) is Fig. 9 (a) A1-A2 line cross-sectional view. Fig. 9 (c) is Fig. 9 (a) A3-A4 line sectional view.

[0095] like Fig. 9 (b) and Fig. 9As shown in (c), in the semiconductor device 110d, a plurality of fourth semiconductor regions 14 and a plurality of seventh semiconductor regions 17 are provided. The plurality of fourth semiconductor regions 14 and the plurality of seventh semiconductor regions 17 are each island-shaped. A portion of the second semiconductor region 12 exists between one of the plurality of fourth semiconductor regions 14 and another of the plurality of fourth semiconductor regions 14. A portion of the fifth semiconductor region 15 exists between one of the plurality of seventh semiconductor regions 17 and another of the plurality of seventh semiconductor regions 17.

[0096] In the semiconductor device 110d, the lengths in the Y-axis direction are different between the fourth semiconductor region 14 and the seventh semiconductor region 17. For example, a direction intersecting a plane including a first direction (Z-axis direction) and a second direction (for example, X-axis direction) is set as the fourth direction. The fourth direction is, for example, the Y-axis direction. The second length L2 of the seventh semiconductor region 17 along the fourth direction is longer than the first length L1 of the fourth semiconductor region 14 along the fourth direction. In the semiconductor device 110d, the loss can also be reduced. In an embodiment, for example, the second length L2 is 20 times the first length L1. Thus, the loss can be effectively reduced. For example, the second length L2 can be less than 2000 times the first length L1.

[0097] Fig.10 (a) to (c) are schematic cross-sectional views illustrating the semiconductor device according to the first embodiment.

[0098] Fig.10 (b) is Fig.10 (a) A1-A2 line cross-sectional view. Fig.10 (c) is Fig.10 (a) A3-A4 line sectional view.

[0099] like Fig.10 (b) and Fig.10 As shown in (c), in the semiconductor device 110e, a plurality of fourth semiconductor regions 14 and a plurality of seventh semiconductor regions 17 are also provided. In the semiconductor device 110e, the length of the second semiconductor region 12 between the plurality of fourth semiconductor regions 14 in the Y-axis direction is longer than the length of the fifth semiconductor region 15 between the plurality of seventh semiconductor regions 17 in the Y-axis direction. The ratio of the area of ​​the seventh semiconductor region 17 to the unit area in the X-Y plane (the second area ratio) is higher than the ratio of the area of ​​the fourth semiconductor region 14 to the unit area in the X-Y plane (the first area ratio). In the semiconductor device 110e, the loss can also be reduced.

[0100] In the embodiment, the area ratio can be changed by changing at least one of the width and the length of the fourth semiconductor region 14 and the seventh semiconductor region 17. By changing the area ratio, the volume ratio can be changed. The volume ratio can be changed by changing the thickness of the fourth semiconductor region 14 and the seventh semiconductor region 17.

[0101] In the embodiment, at least any one of the impurity concentration, the carrier concentration, and the volume ratio may be changed. For example, the seventh semiconductor region 17 may have at least any one of a second impurity concentration of the second conductivity type higher than the first impurity concentration, a second carrier concentration of the second conductivity type higher than the first carrier concentration, and a second volume ratio higher than the first volume ratio.

[0102] Fig.11 It is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.

[0103] like Fig.11 As shown, in the semiconductor device 110f, at least a portion of the third semiconductor region 13 is located between a portion of the third electrode 53 and a portion of the second semiconductor region 12 in the second direction (e.g., the X-axis direction). At least a portion of the sixth semiconductor region 16 is located between a portion of the fourth electrode 54 and a portion of the fifth semiconductor region 15 in the third direction (e.g., the X-axis direction). In the Z-axis direction, the third semiconductor region 13 is located between the second semiconductor region 12 and the fourth semiconductor region 14. In the Z-axis direction, the sixth semiconductor region 16 is located between the fifth semiconductor region 15 and the seventh semiconductor region 17.

[0104] Thus, at least a portion of the third semiconductor region 13 is located at least at any one of the first position between a portion of the third electrode 53 and the fourth semiconductor region 14 in the second direction (X-axis direction) and the second position between a portion of the third electrode 53 and a portion of the second semiconductor region 12 in the second direction. At least a portion of the sixth semiconductor region 16 is located at least at any one of the third position between a portion of the fourth electrode 54 and the seventh semiconductor region 17 in the third direction (X-axis direction) and the fourth position between a portion of the fourth electrode 54 and a portion of the fifth semiconductor region 15 in the third direction.

[0105] Fig.12 It is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.

[0106] like Fig.12As shown, in the semiconductor device 110g, a plurality of third electrodes 53 are arranged in the X-axis direction. A plurality of fourth electrodes 54 are arranged in the X-axis direction. The position of one of the plurality of third electrodes 53 in the X-axis direction is between the position of one of the plurality of fourth electrodes 54 in the X-axis direction and the position of another of the plurality of fourth electrodes 54 in the X-axis direction. The position of one of the plurality of fourth electrodes 54 in the X-axis direction is between the position of one of the plurality of third electrodes 53 in the X-axis direction and the position of another of the plurality of third electrodes 53 in the X-axis direction.

[0107] Fig.13 It is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.

[0108] like Fig.13 As shown, the semiconductor device 110h includes, in addition to the first electrode 51 , the second electrode 52 , the third electrode 53 , the fourth electrode 54 , the first insulating member 41 , and the second insulating member 42 , a first conductive member 61 , a second conductive member 62 , a third insulating member 43 , and a fourth insulating member 44 .

[0109] The position of a portion 11p of the first semiconductor region 11 in the first direction (Z-axis direction) is between the position of the second conductive member 62 in the first direction and the position of the first conductive member 61 in the first direction. At least a portion of the third insulating member 43 is between the first conductive member 61 and the semiconductor member 10. At least a portion of the fourth insulating member 44 is between the second conductive member 62 and the semiconductor member 10. The first conductive member 61 is electrically connected to the first electrode 51. As described later, the first conductive member 61 may also be electrically connected to the first electrode 51. The second conductive member 62 is electrically connected to the second electrode 52. As described later, the second conductive member 62 may also be electrically connected to the second electrode 52. The first conductive member 61 and the second conductive member 62 may also function as field plates, for example. For example, the concentration of the electric field is suppressed. For example, a high withstand voltage can be obtained.

[0110] Fig.14 It is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.

[0111] like Fig.14As shown, in the semiconductor device 110i, the first conductive member 61, the second conductive member 62, the third insulating member 43 and the fourth insulating member 44 are also provided. In the semiconductor device 110i, the first conductive member 61 is electrically connected to the first electrode 51 via the connecting member 61C, the connecting member 51C and the connecting member 51L. A terminal 61T electrically connected to the first conductive member 61 may be provided. A terminal 51T electrically connected to the first electrode 51 may also be provided. The terminal 51T and the terminal 61T may be electrically connected by the connecting member 51L. The connecting member 51L may not be included in the semiconductor device 110i. In this way, the first conductive member 61 may also be electrically connected to the first electrode 51.

[0112] The second conductive member 62 is electrically connected to the second electrode 52 via the connecting member 62C, the connecting member 52C, and the connecting member 52L. A terminal 62T electrically connected to the second conductive member 62 may be provided. A terminal 52T electrically connected to the second electrode 52 may be provided. The terminal 52T and the terminal 62T may be electrically connected by the connecting member 52L. The connecting member 52L may not be included in the semiconductor device 110i. In this way, the second conductive member 62 may be electrically connected to the second electrode 52. For example, the concentration of the electric field is suppressed. For example, a high withstand voltage can be obtained.

[0113] In the semiconductor devices 110a to 110i, for example, the seventh semiconductor region 17 may have at least one of a second impurity concentration of the second conductivity type higher than the first impurity concentration, a second carrier concentration of the second conductivity type higher than the first carrier concentration, and a second volume ratio higher than the first volume ratio. This can reduce loss.

[0114] (Second embodiment)

[0115] The second embodiment relates to a semiconductor module.

[0116] Fig.15 This is a schematic diagram illustrating a semiconductor module according to the second embodiment.

[0117] like Fig.15 As shown, the semiconductor module 210 of the second embodiment includes the semiconductor device of the first embodiment (in this example, the semiconductor device 110) and the control unit 70. The control unit 70 is electrically connected to the first electrode 51, the second electrode 52, the third electrode 53, and the fourth electrode 54. The control unit 70 can control the potential of the third electrode 53 and the potential of the fourth electrode 54. The potential of the third electrode 53 and the potential of the fourth electrode 54 are, for example, potentials based on the potential of the first electrode 51.

[0118] Fig.16 (a) and Fig.16(b) is a schematic diagram illustrating the operation of the semiconductor module according to the second embodiment.

[0119] Fig.16 (a) and Fig.16 The horizontal axis of (b) is time tm. Fig.16 The vertical axis of (a) represents the potential E3 of the third electrode 53 . Fig.16 The vertical axis of (b) is the potential E4 of the fourth electrode 54 . These potentials are controlled by the control unit 70 .

[0120] like Fig.16 As shown in (a), the control unit 70 can implement a first action of setting the third electrode 53 from the first potential V1 to the second potential V2 lower than the first potential V1. The first action corresponds to a "cut-off action" of transferring the IGBT action from the "on state" to the "off state". In the first action, the control unit 70 changes the third electrode 53 from the first potential V1 to the second potential V2 at the first moment t1. The first potential V1 is, for example, +15V. The second potential V2 is, for example, -15V. In such a first action, the control unit 70 changes the fourth electrode 54 from the third potential V3 to the fourth potential V4 higher than the third potential V3 at the second moment t2 before the first moment t1. The third potential V3 is, for example, 0V. The fourth potential V4 is, for example, +15V. Through such an action, the turn-off switching loss Eoff can be reduced.

[0121] like Fig.16 As shown in (b), the time between the first time t1 and the second time t2 is defined as the time difference td. Hereinafter, an example of a change in the turn-off switching loss Eoff when the time difference td is changed will be described.

[0122] Fig.17 It is a graph illustrating the characteristics in a semiconductor device.

[0123] Fig.17 The horizontal axis is the time difference td between the moment when the potential of the third electrode 53 changes and the moment when the potential of the fourth electrode 54 changes when the IGBT is turned off. When the time difference td is 0, when the potential of the third electrode 53 becomes the cut-off potential, the potential of the fourth electrode 54 becomes the on-potential. When the time difference td is positive, after the potential of the third electrode 53 becomes the cut-off potential, the potential of the fourth electrode 54 becomes the on-potential. When the time difference td is negative, before the potential of the third electrode 53 becomes the cut-off potential, the potential of the fourth electrode 54 becomes the on-potential. Fig.17As shown in the figure, when the time difference td is negative, the turn-off switching loss Eoff is reduced. This effect is believed to be caused by the fact that the carriers accumulated in the on state are discharged just before the turn-off. The time difference td is negative and the absolute value of the time difference td is greater than 1μs, so that the turn-off switching loss Eoff can be reduced. The time difference td is negative and the absolute value of the time difference td is greater than 5μs, so that the turn-off switching loss Eoff can be reduced. The time difference td is negative and the absolute value of the time difference td is greater than 10μs, which can effectively reduce the turn-off switching loss Eoff.

[0124] In an embodiment, it is preferred that the time difference td is negative, and the absolute value of the time difference td is greater than 10 μs. Thus, the turn-off switch loss Eoff can be reduced. It is more preferred that the time difference td is negative, and the absolute value of the time difference td is greater than 20 μs. Thus, the turn-off switch loss Eoff can be effectively reduced. It is preferred that the time difference td is negative and the absolute value of the time difference td is less than 200 μs. When the time difference td is too long, for example, the power-on loss in the IGBT operation becomes large. The time difference td is negative and the absolute value of the time difference td is less than 200 μs, which makes it easy to suppress the power-on loss in the IGBT operation.

[0125] For example, before the third electrode 53 is set to the off potential and the IGBT is turned off, the fourth electrode 54 is transferred to the on potential. At this time, the amount of the second conductivity type carriers in the seventh semiconductor region 17 is greater than the amount of the second conductivity type carriers in the fourth semiconductor region 14, so that the effect of reducing the turn-off switching loss Eoff becomes greater. This is believed to be caused by the fact that more carriers are discharged just before the turn-off.

[0126] In the above embodiment, the carrier concentration of the first conductivity type in the first semiconductor region 11 is preferably 1×10 12 / cm 3 Above and 1×10 14 / cm 3 The carrier concentration of the second conductivity type in the second semiconductor region 12 is preferably 1×10 16 / cm 3 Above and 1×10 18 / cm 3 The carrier concentration of the first conductivity type in the third semiconductor region 13 is preferably 1×10 18 / cm 3 Above and 5×10 20 / cm 3 The carrier concentration of the second conductivity type in the fourth semiconductor region 14 is preferably 1×10 18 / cm 3 Above and 1×10 20 / cm3 The carrier concentration of the second conductivity type in the fifth semiconductor region 15 is preferably 1×10 16 / cm 3 Above and 1×10 18 / cm 3 The carrier concentration of the first conductivity type in the sixth semiconductor region 16 is preferably 1×10 18 / cm 3 Above and 5×10 20 / cm 3 The carrier concentration of the second conductivity type in the seventh semiconductor region 17 is preferably 1×10 18 / cm 3 Above and 1×10 20 / cm 3 The carrier concentration of the first conductivity type in the eighth semiconductor region 18 is preferably 1×10 15 / cm 3 Above and 1×10 17 / cm 3 The carrier concentration of the first conductivity type in the ninth semiconductor region 19 is preferably 1×10 15 / cm 3 Above and 1×10 17 / cm 3 the following.

[0127] In the above embodiment, the impurity concentration of the first conductivity type in the first semiconductor region 11 is preferably 1×10 12 / cm 3 Above and 1×10 14 / cm 3 The second conductivity type impurity concentration in the second semiconductor region 12 is preferably 1×10 16 / cm 3 Above and 1×10 18 / cm 3 The concentration of the first conductivity type impurity in the third semiconductor region 13 is preferably 1×10 18 / cm 3 Above and 5×10 20 / cm 3 The second conductivity type impurity concentration in the fourth semiconductor region 14 is preferably 1×10 18 / cm 3 Above and 1×10 20 / cm 3 The second conductivity type impurity concentration in the fifth semiconductor region 15 is preferably 1×10 16 / cm 3 Above and 1×1018 / cm 3 The impurity concentration of the first conductivity type in the sixth semiconductor region 16 is preferably 1×10 18 / cm 3 Above and 5×10 20 / cm 3 The second conductivity type impurity concentration in the seventh semiconductor region 17 is preferably 1×10 18 / cm 3 Above and 1×10 20 / cm 3 The impurity concentration of the first conductivity type in the eighth semiconductor region 18 is preferably 1×10 15 / cm 3 Above and 1×10 17 / cm 3 The impurity concentration of the first conductivity type in the ninth semiconductor region 19 is preferably 1×10 15 / cm 3 Above and 1×10 17 / cm 3 the following.

[0128] The semiconductor member includes, for example, silicon. The semiconductor member may also include, for example, a compound semiconductor. The first electrode 51 includes, for example, aluminum. The second electrode 52 includes, for example, aluminum. At least one of the third electrode 53, the fourth electrode 54, the first conductive member 61, and the second conductive member 62 includes, for example, conductive silicon. The first to fourth insulating members 41 to 44 include, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and the like.

[0129] In an embodiment, information related to the shape of the semiconductor region can be obtained, for example, by electron microscope observation. Information related to the impurity concentration in the semiconductor region can be obtained, for example, by EDX (Energy Dispersive X-ray Spectroscopy) or SIMS (Secondary Ion Mass Spectrometry). Information related to the carrier concentration in the semiconductor region can be obtained, for example, by SCM (Scanning Capacitance Microscopy).

[0130] The implementation method may also include the following technical solutions.

[0131] (Technical Solution 1)

[0132] A semiconductor device comprising:

[0133] 1st electrode;

[0134] a second electrode, the direction from the second electrode to the first electrode being along a first direction;

[0135] A semiconductor component, arranged between the second electrode and the first electrode in the first direction, the semiconductor component comprising a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type, a third semiconductor region of the first conductivity type, a fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the second conductivity type, a sixth semiconductor region of the first conductivity type, and a seventh semiconductor region of the second conductivity type, the second semiconductor region of the second conductivity type being arranged between the first semiconductor region and the first electrode, the third semiconductor region of the first conductivity type being arranged between the second semiconductor region and the first electrode, the fourth semiconductor region of the second conductivity type being arranged between the second semiconductor region and the first electrode, and the fourth semiconductor region having a first impurity of the second conductivity type concentration, a first carrier concentration of the second conductivity type, and a first volume ratio of the volume of the fourth semiconductor region relative to the volume of the semiconductor component, the fifth semiconductor region of the second conductivity type is arranged between the first semiconductor region and the second electrode, the sixth semiconductor region of the first conductivity type is arranged between the fifth semiconductor region and the second electrode, the seventh semiconductor region of the second conductivity type is arranged between the fifth semiconductor region and the second electrode, the seventh semiconductor region has at least any one of a second impurity concentration of the second conductivity type higher than the first impurity concentration, a second carrier concentration of the second conductivity type higher than the first carrier concentration, and a second volume ratio higher than the first volume ratio, the second volume ratio being the volume ratio of the seventh semiconductor region relative to the volume of the semiconductor component;

[0136] a third electrode, wherein a second direction from a portion of the third electrode toward the second semiconductor region intersects the first direction, and at least a portion of the third semiconductor region is located at at least one of a first position between a portion of the third electrode and the fourth semiconductor region in the second direction and a second position between the portion of the third electrode and a portion of the second semiconductor region in the second direction;

[0137] a fourth electrode, wherein a third direction from a portion of the fourth electrode to the fifth semiconductor region intersects the first direction, and at least a portion of the sixth semiconductor region is located at at least one of a third position between a portion of the fourth electrode in the third direction and the seventh semiconductor region and a fourth position between the portion of the fourth electrode in the third direction and a portion of the fifth semiconductor region;

[0138] a first insulating member, at least a portion of which is located between the third electrode and the semiconductor member; and

[0139] a second insulating member, at least a portion of which is located between the fourth electrode and the semiconductor member.

[0140] (Technical Solution 2)

[0141] According to the semiconductor device described in claim 1,

[0142] The second carrier concentration is greater than or equal to 20 times the first carrier concentration.

[0143] (Technical Solution 3)

[0144] A semiconductor device according to claim 1 or 2, wherein:

[0145] The second impurity concentration is 20 times or more of the first impurity concentration.

[0146] (Technical Solution 4)

[0147] A semiconductor device according to any one of claims 1 to 3, wherein:

[0148] The second volume ratio is 20 times or more of the first volume ratio.

[0149] (Technical Solution 5)

[0150] A semiconductor device according to any one of claims 1 to 4, wherein:

[0151] A second thickness of the seventh semiconductor region along the first direction is thicker than a first thickness of the fourth semiconductor region 14 along the first direction.

[0152] (Technical Solution 6)

[0153] A semiconductor device according to any one of claims 1 to 5, wherein:

[0154] A second area ratio of the seventh semiconductor region to a unit area in a second plane intersecting the first direction is higher than a first area ratio of the fourth semiconductor region to a unit area in a first plane intersecting the first direction.

[0155] (Technical Solution 7)

[0156] A semiconductor device according to any one of claims 1 to 6, wherein:

[0157] A second width of the seventh semiconductor region along the second direction is larger than a first width of the fourth semiconductor region along the second direction.

[0158] (Technical Solution 8)

[0159] A semiconductor device according to any one of claims 1 to 7, wherein:

[0160] A second length of the seventh semiconductor region along a fourth direction intersecting a plane including the first direction and the second direction is longer than a first length of the fourth semiconductor region along the fourth direction.

[0161] (Technical Solution 9)

[0162] A semiconductor device according to any one of claims 1 to 8, wherein:

[0163] A first distance between the second electrode and the third electrode along the first direction is shorter than a second distance between the second electrode and the second semiconductor region along the first direction.

[0164] A third distance between the first electrode and the fourth electrode along the first direction is shorter than a fourth distance between the first electrode and the fifth semiconductor region along the first direction.

[0165] (Technical Solution 10)

[0166] A semiconductor device according to any one of claims 1 to 9, wherein:

[0167] The first carrier concentration is higher than the second conductivity type carrier concentration in the second semiconductor region,

[0168] The second carrier concentration is higher than the second conductivity type carrier concentration in the fifth semiconductor region.

[0169] (Technical Solution 11)

[0170] A semiconductor device according to any one of claims 1 to 10, wherein:

[0171] The carrier concentration of the first conductivity type in the third semiconductor region is higher than the carrier concentration of the first conductivity type in the first semiconductor region.

[0172] A concentration of carriers of the first conductivity type in the sixth semiconductor region is higher than a concentration of carriers of the first conductivity type in the first semiconductor region.

[0173] (Technical Solution 12)

[0174] A semiconductor device according to any one of claims 1 to 11, wherein:

[0175] The semiconductor component further comprises:

[0176] The eighth semiconductor region of the first conductivity type is disposed between the first semiconductor region and the second semiconductor region; and

[0177] The ninth semiconductor region of the first conductivity type is disposed between the first semiconductor region and the fifth semiconductor region.

[0178] The impurity concentration of the first conductivity type in the eighth semiconductor region is higher than the impurity concentration of the first conductivity type in the first semiconductor region,

[0179] A concentration of the impurity of the first conductivity type in the ninth semiconductor region is higher than a concentration of the impurity of the first conductivity type in the first semiconductor region.

[0180] (Technical Solution 13)

[0181] A semiconductor device according to any one of claims 1 to 12, wherein:

[0182] The third semiconductor region and the fourth semiconductor region are electrically connected to the first electrode.

[0183] The sixth semiconductor region and the seventh semiconductor region are electrically connected to the second electrode.

[0184] (Technical Solution 14)

[0185] A semiconductor device according to any one of claims 1 to 13, wherein:

[0186] A portion of the first semiconductor region is located between the fourth electrode and the third electrode in the first direction.

[0187] (Technical Solution 15)

[0188] A semiconductor device according to any one of claims 1 to 14, wherein:

[0189] A direction from the third semiconductor region to the fourth semiconductor region intersects the first direction.

[0190] A direction from the sixth semiconductor region to the seventh semiconductor region intersects with the first direction.

[0191] (Technical Solution 16)

[0192] A semiconductor device according to any one of claims 1 to 15, wherein:

[0193] At least a portion of the third semiconductor region is located between a portion of the third electrode and the fourth semiconductor region.

[0194] (Technical Solution 17)

[0195] A semiconductor device according to any one of claims 1 to 16, wherein:

[0196] At least a portion of the sixth semiconductor region is located between a portion of the fourth electrode and the seventh semiconductor region.

[0197] (Technical Solution 18)

[0198] The semiconductor device according to any one of claims 1 to 17, further comprising:

[0199] a first conductive member;

[0200] a second conductive member;

[0201] a third insulating member; and

[0202] The fourth insulating member,

[0203] The position of the portion of the first semiconductor region in the first direction is between the position of the second conductive member in the first direction and the position of the first conductive member in the first direction.

[0204] At least a portion of the third insulating member is located between the first conductive member and the semiconductor member.

[0205] At least a portion of the fourth insulating member is located between the second conductive member and the semiconductor member.

[0206] The first conductive member is electrically connected to the first electrode or can be electrically connected to the first electrode.

[0207] The second conductive member is electrically connected to the second electrode or can be electrically connected to the second electrode.

[0208] (Technical Solution 19)

[0209] A semiconductor module comprising:

[0210] A semiconductor device according to any one of claims 1 to 18; and

[0211] a control unit electrically connected to the third electrode and the fourth electrode,

[0212] In the first operation of setting the third electrode from the first potential to the second potential lower than the first potential, the control unit changes the fourth electrode from the third potential to a fourth potential higher than the third potential at a second time before the first time when the third electrode is changed from the first potential to the second potential.

[0213] (Technical Solution 20)

[0214] According to the semiconductor module described in technical solution 19,

[0215] The time between the first time point and the second time point is greater than or equal to 1 μs and less than or equal to 200 μs.

[0216] According to the embodiments, a semiconductor device and a semiconductor module capable of reducing loss can be provided.

[0217] The above describes the embodiments of the present invention with reference to specific examples. However, the present invention is not limited to these specific examples. For example, in terms of the specific structure of each element such as a semiconductor component, a semiconductor region, a conductive component, an electrode, and an insulating component included in a semiconductor device, as long as a person skilled in the art can implement the present invention in the same manner and obtain the same effect by appropriately selecting from the known range, it is included in the scope of the present invention.

[0218] Furthermore, examples in which two or more arbitrary elements of each specific example are combined within a technically possible range are included in the scope of the present invention as long as the gist of the present invention is included.

[0219] In addition, as embodiments of the present invention, all semiconductor devices that can be implemented by appropriately changing the design of the semiconductor device described above by a person skilled in the art also belong to the scope of the present invention as long as they include the gist of the present invention.

[0220] In addition, it should be understood that within the scope of the concept of the present invention, a person skilled in the art can conceive of various changes and modifications, and these changes and modifications also belong to the scope of the present invention.

[0221] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their variations are included in the scope and gist of the invention, and are included in the invention described in the claims and their equivalents.

Claims

1. A semiconductor device comprising: 1st electrode; a second electrode, the direction from the second electrode to the first electrode being along a first direction; A semiconductor component, arranged between the second electrode and the first electrode in the first direction, the semiconductor component comprising a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type, a third semiconductor region of the first conductivity type, a fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the second conductivity type, a sixth semiconductor region of the first conductivity type, and a seventh semiconductor region of the second conductivity type, the second semiconductor region of the second conductivity type being arranged between the first semiconductor region and the first electrode, the third semiconductor region of the first conductivity type being arranged between the second semiconductor region and the first electrode, the fourth semiconductor region of the second conductivity type being arranged between the second semiconductor region and the first electrode, and the fourth semiconductor region having a first impurity of the second conductivity type concentration, a first carrier concentration of the second conductivity type, and a first volume ratio of the volume of the fourth semiconductor region relative to the volume of the semiconductor component, the fifth semiconductor region of the second conductivity type is arranged between the first semiconductor region and the second electrode, the sixth semiconductor region of the first conductivity type is arranged between the fifth semiconductor region and the second electrode, the seventh semiconductor region of the second conductivity type is arranged between the fifth semiconductor region and the second electrode, the seventh semiconductor region has at least any one of a second impurity concentration of the second conductivity type higher than the first impurity concentration, a second carrier concentration of the second conductivity type higher than the first carrier concentration, and a second volume ratio higher than the first volume ratio, the second volume ratio being the volume ratio of the seventh semiconductor region relative to the volume of the semiconductor component; a third electrode, wherein a second direction from a portion of the third electrode toward the second semiconductor region intersects the first direction, and at least a portion of the third semiconductor region is located at at least one of a first position between a portion of the third electrode and the fourth semiconductor region in the second direction and a second position between the portion of the third electrode and a portion of the second semiconductor region in the second direction; a fourth electrode, wherein a third direction from a portion of the fourth electrode to the fifth semiconductor region intersects the first direction, and at least a portion of the sixth semiconductor region is located at at least one of a third position between a portion of the fourth electrode in the third direction and the seventh semiconductor region and a fourth position between the portion of the fourth electrode in the third direction and a portion of the fifth semiconductor region; a first insulating member, at least a portion of which is located between the third electrode and the semiconductor member; as well as a second insulating member, at least a portion of which is located between the fourth electrode and the semiconductor member, A second thickness of the seventh semiconductor region along the first direction is thicker than a first thickness of the fourth semiconductor region along the first direction.

2. The semiconductor device according to claim 1, wherein A second area ratio of the seventh semiconductor region to a unit area in a second plane intersecting the first direction is higher than a first area ratio of the fourth semiconductor region to a unit area in a first plane intersecting the first direction.

3. The semiconductor device according to claim 1, wherein A second width of the seventh semiconductor region along the second direction is larger than a first width of the fourth semiconductor region along the second direction.

4. The semiconductor device according to claim 1, wherein A second length of the seventh semiconductor region along a fourth direction intersecting a plane including the first direction and the second direction is longer than a first length of the fourth semiconductor region along the fourth direction.

5. The semiconductor device according to claim 1, wherein A first distance between the second electrode and the third electrode along the first direction is shorter than a second distance between the second electrode and the second semiconductor region along the first direction. A third distance between the first electrode and the fourth electrode along the first direction is shorter than a fourth distance between the first electrode and the fifth semiconductor region along the first direction.

6. A semiconductor device comprising: 1st electrode; a second electrode, the direction from the second electrode to the first electrode being along a first direction; A semiconductor component, arranged between the second electrode and the first electrode in the first direction, the semiconductor component comprising a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type, a third semiconductor region of the first conductivity type, a fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the second conductivity type, a sixth semiconductor region of the first conductivity type, and a seventh semiconductor region of the second conductivity type, the second semiconductor region of the second conductivity type being arranged between the first semiconductor region and the first electrode, the third semiconductor region of the first conductivity type being arranged between the second semiconductor region and the first electrode, the fourth semiconductor region of the second conductivity type being arranged between the second semiconductor region and the first electrode, and the fourth semiconductor region having a first impurity of the second conductivity type concentration, a first carrier concentration of the second conductivity type, and a first volume ratio of the volume of the fourth semiconductor region relative to the volume of the semiconductor component, the fifth semiconductor region of the second conductivity type is arranged between the first semiconductor region and the second electrode, the sixth semiconductor region of the first conductivity type is arranged between the fifth semiconductor region and the second electrode, the seventh semiconductor region of the second conductivity type is arranged between the fifth semiconductor region and the second electrode, the seventh semiconductor region has at least any one of a second impurity concentration of the second conductivity type higher than the first impurity concentration, a second carrier concentration of the second conductivity type higher than the first carrier concentration, and a second volume ratio higher than the first volume ratio, the second volume ratio being the volume ratio of the seventh semiconductor region relative to the volume of the semiconductor component; a third electrode, wherein a second direction from a portion of the third electrode toward the second semiconductor region intersects the first direction, and at least a portion of the third semiconductor region is located at at least one of a first position between a portion of the third electrode and the fourth semiconductor region in the second direction and a second position between the portion of the third electrode and a portion of the second semiconductor region in the second direction; a fourth electrode, wherein a third direction from a portion of the fourth electrode to the fifth semiconductor region intersects the first direction, and at least a portion of the sixth semiconductor region is located at at least one of a third position between a portion of the fourth electrode in the third direction and the seventh semiconductor region and a fourth position between the portion of the fourth electrode in the third direction and a portion of the fifth semiconductor region; a first insulating member, at least a portion of which is located between the third electrode and the semiconductor member; as well as a second insulating member, at least a portion of which is located between the fourth electrode and the semiconductor member, The first carrier concentration is higher than the second conductivity type carrier concentration in the second semiconductor region, The second carrier concentration is higher than the second conductivity type carrier concentration in the fifth semiconductor region.

7. The semiconductor device according to claim 6, wherein: The carrier concentration of the first conductivity type in the third semiconductor region is higher than the carrier concentration of the first conductivity type in the first semiconductor region. A concentration of carriers of the first conductivity type in the sixth semiconductor region is higher than a concentration of carriers of the first conductivity type in the first semiconductor region.

8. The semiconductor device according to claim 6, wherein: The semiconductor component further comprises: The eighth semiconductor region of the first conductivity type is disposed between the first semiconductor region and the second semiconductor region; and The ninth semiconductor region of the first conductivity type is disposed between the first semiconductor region and the fifth semiconductor region. The impurity concentration of the first conductivity type in the eighth semiconductor region is higher than the impurity concentration of the first conductivity type in the first semiconductor region, A concentration of the impurity of the first conductivity type in the ninth semiconductor region is higher than a concentration of the impurity of the first conductivity type in the first semiconductor region.

9. A semiconductor module comprising: A semiconductor device comprising: 1st electrode; a second electrode, the direction from the second electrode to the first electrode being along a first direction; A semiconductor component, arranged between the second electrode and the first electrode in the first direction, the semiconductor component comprising a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type, a third semiconductor region of the first conductivity type, a fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the second conductivity type, a sixth semiconductor region of the first conductivity type, and a seventh semiconductor region of the second conductivity type, the second semiconductor region of the second conductivity type being arranged between the first semiconductor region and the first electrode, the third semiconductor region of the first conductivity type being arranged between the second semiconductor region and the first electrode, the fourth semiconductor region of the second conductivity type being arranged between the second semiconductor region and the first electrode, and the fourth semiconductor region having a first impurity of the second conductivity type concentration, a first carrier concentration of the second conductivity type, and a first volume ratio of the volume of the fourth semiconductor region relative to the volume of the semiconductor component, the fifth semiconductor region of the second conductivity type is arranged between the first semiconductor region and the second electrode, the sixth semiconductor region of the first conductivity type is arranged between the fifth semiconductor region and the second electrode, the seventh semiconductor region of the second conductivity type is arranged between the fifth semiconductor region and the second electrode, the seventh semiconductor region has at least any one of a second impurity concentration of the second conductivity type higher than the first impurity concentration, a second carrier concentration of the second conductivity type higher than the first carrier concentration, and a second volume ratio higher than the first volume ratio, the second volume ratio being the volume ratio of the seventh semiconductor region relative to the volume of the semiconductor component; a third electrode, wherein a second direction from a portion of the third electrode toward the second semiconductor region intersects the first direction, and at least a portion of the third semiconductor region is located at at least one of a first position between a portion of the third electrode and the fourth semiconductor region in the second direction and a second position between the portion of the third electrode and a portion of the second semiconductor region in the second direction; a fourth electrode, wherein a third direction from a portion of the fourth electrode to the fifth semiconductor region intersects the first direction, and at least a portion of the sixth semiconductor region is located at at least one of a third position between a portion of the fourth electrode in the third direction and the seventh semiconductor region and a fourth position between the portion of the fourth electrode in the third direction and a portion of the fifth semiconductor region; a first insulating member, at least a portion of which is located between the third electrode and the semiconductor member; as well as a second insulating member, at least a portion of which is located between the fourth electrode and the semiconductor member; and a control unit electrically connected to the third electrode and the fourth electrode, In the first operation of setting the third electrode from the first potential to the second potential lower than the first potential, the control unit changes the fourth electrode from the third potential to a fourth potential higher than the third potential at a second time before the first time when the third electrode is changed from the first potential to the second potential.

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