Semiconductor device including a chalcogenide compound and semiconductor apparatus including the same

Abstract

The present invention relates to a semiconductor device including a chalcogenide compound and a semiconductor apparatus including the same. A chalcogenide compound layer exhibiting a bidirectional threshold switching property is provided, a switching device including the same, a semiconductor device, and / or a semiconductor apparatus. The switching device and / or the semiconductor device can include two or more chalcogenide compound layers having different energy bandgaps. Alternatively, the switching device and / or semiconductor device can include a chalcogenide compound layer having a concentration gradient of elements of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and / or indium (In) in a thickness direction thereof. The switching device and / or semiconductor device can exhibit stable switching characteristics while having a low off-current value (leakage current value).

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0145526 filed on November 3, 2020 and Korean Patent Application No. 10-2021-0001064 filed on January 5, 2021, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to semiconductor devices including chalcogenide compound layers and semiconductor apparatuses including said semiconductor devices. Background Technology

[0004] Driven by the trend towards lighter and smaller electronic products, the demand for high integration in semiconductor devices is increasing. Consequently, various types of semiconductor devices have been proposed, and as examples, semiconductor devices incorporating variable resistance layers and selector layers have been proposed. Summary of the Invention

[0005] A chalcogenide compound layer exhibiting bidirectional threshold switching characteristics and a switching device including the chalcogenide compound layer are provided.

[0006] Provide semiconductor devices and / or semiconductor apparatuses with low shutdown current and high reliability (durability).

[0007] Other aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments presented in this disclosure.

[0008] According to one aspect of the implementation, the semiconductor device includes a selection device layer exhibiting bidirectional threshold switching characteristics. The selection device layer may include two or more chalcogenide compound layers with different band gaps.

[0009] Specifically, the selection device layer may include a first chalcogenide compound layer and a second chalcogenide compound layer having different compositions from each other, and the first and second chalcogenide compound layers may each independently include: a first element including germanium (Ge) and / or tin (Sn), and a second element including sulfur (S), selenium (Se), and / or tellurium (Te).

[0010] In some embodiments, the first chalcogenide compound layer and / or the second chalcogenide compound layer may further each independently include a third element, said third element including one or more selected from arsenic (As), antimony (Sb), silicon (Si), and bismuth (Bi). Furthermore, the second chalcogenide compound layer may further include a fourth element, said fourth element including one or more selected from boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and indium (In), and the first chalcogenide compound layer may further include a fifth element, said fifth element including one or more selected from carbon (C), nitrogen (N), oxygen (O), phosphorus (P), and sulfur (S).

[0011] In some embodiments, the first chalcogenide compound layer may have a band gap greater than 0.1 eV or more and less than 1.0 eV of the second chalcogenide compound layer.

[0012] In some embodiments, the first chalcogenide compound layer may include compounds of formula 1, formula 3 and / or formula 4, and the second chalcogenide compound layer may include compounds of formula 1 and / or formula 2.

[0013] [Formula 1]

[0014] A a B b C c

[0015] [Equation 2]

[0016] A a B b C c D d

[0017] [Formula 3]

[0018] A a B b

[0019] [Formula 4]

[0020] A a B b C c E e

[0021] In Equations 1, 2, 3, or 4, A is the first element, B is the second element, C is the third element, D is the fourth element, and E is the fifth element. In Equation 1, a + b + c = 1; in Equation 2, a + b + c + d = 1; in Equation 3, a + b = 1; and in Equation 4, a + b + c + e = 1. In Equations 1, 2, or 4, 0.05 ≤ a ≤ 0.30, 0.20 ≤ b ≤ 0.70, 0.05 ≤ c ≤ 0.50, 0.01 ≤ d ≤ 0.10, and 0.01 ≤ e ≤ 0.10. In Equation 3, 0.05 ≤ a ≤ 0.95 and 0.05 ≤ b ≤ 0.95.

[0022] In some embodiments, the semiconductor device may further include a variable resistance layer. Specifically, the semiconductor device may further include a first electrode layer, a second electrode layer, and a third electrode layer, and the selection device layer may be disposed between the first electrode layer and the second electrode layer, and the variable resistance layer may be disposed between the second electrode layer and the third electrode layer.

[0023] In some embodiments, the variable resistance layer may include a material capable of reversibly changing phase between crystalline and amorphous states in response to temperature changes. The variable resistance layer may include compounds in which Te and / or Se are combined with one or more elements from Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, P, B, O, and C. Attached Figure Description

[0024] The above and other aspects, features, and advantages of some embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, wherein:

[0025] Figure 1 This is an equivalent circuit diagram of a semiconductor device according to an embodiment;

[0026] Figure 2 A plot illustrating the voltage-current curves of a material with bidirectional threshold switching characteristics;

[0027] Figures 3A-3C A schematic diagram of a semiconductor device and / or switching device according to an embodiment;

[0028] Figure 4A This is a perspective view of a semiconductor device according to an embodiment;

[0029] Figure 4B For along Figure 4A Cross-sectional views of lines 1X-1X' and 1Y-1Y' of the semiconductor device;

[0030] Figure 4C A schematic cross-sectional view of a semiconductor device according to another embodiment; and

[0031] Figures 5A-5C This is a schematic diagram illustrating the manufacturing process of a semiconductor device according to an embodiment. Detailed Implementation

[0032] The embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this respect, the embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, the embodiments are described below only by reference to the accompanying drawings to illustrate aspects. As used herein, the term "and / or" includes any and all combinations of one or more of the associated enumerated items. Expressions such as "at least one of" modify the entire list of elements when preceding or following it, without modifying any individual element of the list.

[0033] The terminology used herein is for the purpose of describing embodiments only and is not intended to limit the embodiments. When the position of an element is described as “above” or “on”, the position of the element may include not only the element being “directly on / below / to the left / to the right of” in contact with the element, but also the element being “on / below / to the left / to the right of” in a non-contact manner.

[0034] The singular form also includes the plural form, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising” and / or “including” as used herein indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more additional features, integrals, steps, operations, elements, components, and / or collections thereof.

[0035] It will be understood that although the terms “first,” “second,” “third,” etc., may be used in this document to describe various elements, these terms are only used to distinguish one element from another, and the order and type of these elements should not be limited by these terms. Furthermore, terms such as “unit,” “tool,” “module,” and “…unit” refer to a complexly constructed unit that performs a certain function or operation and can be implemented by hardware, software, or a combination of hardware and software.

[0036] The inventive concept will be described more fully below with reference to the accompanying drawings. In the drawings, the same reference numerals refer to the same elements, and for clarity and ease of explanation, dimensions (width and thickness of layers and regions) may be enlarged. Embodiments of the inventive concept are capable of various modifications and can be implemented in different forms.

[0037] According to one aspect of the embodiments, a semiconductor device with high reliability (durability) and a semiconductor apparatus including the thereof are provided. Specifically, the semiconductor apparatus may include a plurality of semiconductor devices between two separate electrode lines, and the semiconductor devices may include a variable resistance layer and a selectable device layer electrically connected to each other. Additionally, the semiconductor apparatus may have a three-dimensional structure in which the two electrode lines have intersection points. The semiconductor device and / or the semiconductor apparatus may be a memory device.

[0038] Figure 1 This is an equivalent circuit diagram of the semiconductor device 100 according to an embodiment.

[0039] refer to Figure 1 The semiconductor device 100 may include a plurality of first electrode lines WL1 and WL2 extending parallel to each other in a first direction (X direction). Additionally, the semiconductor device 100 may include second electrode lines BL1, BL2, BL3, and BL4 extending parallel to each other in a second direction (Y direction) and separated from the first electrode lines WL1 and WL2 in a third direction (Z direction). A semiconductor device MC may be disposed between the first electrode lines WL1 and WL2 and the second electrode lines BL1, BL2, BL3, and BL4. Specifically, the semiconductor device MC may be electrically connected to the first electrode lines WL1 and WL2 and the second electrode lines BL1, BL2, BL3, and BL4, and may be disposed at their respective intersections. Furthermore, each semiconductor device MC may include a variable resistor layer ME and a selector layer SW electrically connected to each other. For example, the variable resistance layer ME and the selector layer SW can be connected in series in the third direction (Z direction), the selector layer SW can be electrically connected to one of the first electrode lines WL1 and WL2 and the second electrode lines BL1, BL2, BL3 and BL4, and the variable resistance layer ME can be electrically connected to the other one.

[0040] The driving method of the semiconductor device 100 will be briefly described. A voltage is applied to the variable resistance layer ME of the semiconductor device MC via first electrode lines WL1 and WL2 and second electrode lines BL1, BL2, BL3, and BL4, allowing current to flow within the semiconductor device MC. Specifically, any semiconductor device MC can be addressed by selecting the first electrode lines WL1 and WL2 and the second electrode lines BL1, BL2, BL3, and BL4, and the semiconductor device MC can be programmed by applying desired and / or alternatively predetermined signals between the first electrode lines WL1 and WL2 and the second electrode lines BL1, BL2, BL3, and BL4. Furthermore, by measuring the current values ​​through the second electrode lines BL1, BL2, BL3, and BL4, information about the programming can be read based on the resistance values ​​of the variable resistance layers ME of the respective semiconductor devices MC.

[0041] The variable resistance layer ME can store information. Specifically, the resistance value of the variable resistance layer ME can change according to the applied voltage. The semiconductor device MC can store and erase digital information, such as "0" or "1", according to the change in resistance of the variable resistance layer ME. For example, the semiconductor device MC can write data as "0" when the variable resistance layer ME is in a high resistance state and write data as "1" when the variable resistance layer ME is in a low resistance state. Here, writing from the high resistance state "0" to the low resistance state "1" can be called a "set operation", and writing from the low resistance state "1" to the high resistance state "0" can be called a "reset operation".

[0042] The selector layer SW can function as follows: it selects (addresses) the corresponding semiconductor device MC by controlling the flow of current through a variable resistor layer ME electrically connected to the respective selector layer SW. Specifically, the selector layer SW may comprise a material whose resistance changes according to the magnitude of the voltage applied to its two ends. For example, the selector layer SW may have bidirectional threshold switching characteristics.

[0043] Figure 2 A plot illustrating the voltage-current profile of the selectable device layer SW with bidirectional threshold switching characteristics. (Reference) Figure 2 The first curve, 21, represents the voltage-current relationship when very little current flows through the selector layer SW. As the voltage gradually increases from the state where both voltage and current are zero, the selector layer SW remains in a high-resistance state until the voltage reaches the threshold voltage V. th (First voltage level 23) and almost no current can flow through it. However, the voltage exceeds the threshold voltage V. th By selecting the device layer SW, it can be in a low-resistance state, and the current flowing through the device layer SW can increase rapidly, while the voltage applied to the device layer SW decreases to the saturation voltage V. S (Second voltage level 24). The second curve 22 shows the voltage-current relationship in a state where current flows more smoothly through the selector layer SW. When the current flowing through the selector layer SW becomes greater than the first current level 26, the voltage applied to the selector layer SW can be slightly increased compared to the second voltage level 24. For example, when the current flowing through the selector layer SW increases significantly from the first current level 26 to the second current level 27, the voltage applied to the selector layer SW can be slightly increased compared to the second voltage level 24. In other words, once current flows through the selector layer SW, the voltage applied to the selector layer SW can be maintained at the saturation voltage V. SIf the current drops below the sustaining current level (first current level 26), the selected device layer SW switches back to a high-resistance state, and the current can be effectively blocked or limited until the voltage increases to the threshold voltage V. th Due to this characteristic, selecting device layer SW can achieve a threshold voltage V with a first voltage level 23. th The function of switching devices.

[0044] However, even when the voltage is less than the threshold voltage V th When a voltage is applied to the semiconductor device (when the semiconductor device is in the off state), such as Figure 2 As shown, a certain level of current can also flow in the selected device layer SW. When the off-state current (leakage current) is large, it becomes difficult to operate the semiconductor device simultaneously (at one time) as the number of semiconductor devices included in the semiconductor device increases. Additionally, when the threshold voltage V... th Based on the cumulative usage time and cumulative on / off counts of the semiconductor device, or the ratio of on-current to off-current (I... 导通 / I 关断 When changes occur, the reliability and durability of the selected device layer (SW) can deteriorate.

[0045] The selector layer SW according to the embodiment may include two or more chalcogenide compound layers, and therefore, stable switching characteristics can be achieved while having a low turn-off current value (leakage current value). In particular, the selector layer SW according to the embodiment may include two or more chalcogenide compound layers with different compositions, each of which independently includes: a first element including germanium (Ge) and / or tin (Sn), and a second element including sulfur (S), selenium (Se), and / or tellurium (Te).

[0046] A single-layer selector layer SW comprising a tricomponent GeAsSe chalcogenide compound can exhibit bidirectional threshold switching characteristics, but it can also have high turn-off current (leakage current) and insufficient durability, thus making it difficult to apply the single-layer selector layer SW to practical semiconductor devices. The selector layer SW according to an embodiment comprises two or more chalcogenide compound layers with different band gaps Eg and / or different compositions, and therefore can have low turn-off current (leakage current) and improved durability. Although not intended to be bound by a particular theory, the selector layer SW according to an embodiment can achieve low leakage current and improved durability by controlling electron movement between the band gap differences between the chalcogenide compound layers exhibiting bidirectional threshold switching characteristics.

[0047] Figures 3A-3C This is a schematic diagram of a semiconductor device according to an embodiment. (Reference) Figure 3A The selected device layer SW may comprise two or more chalcogenide compound layers having different band gaps from each other. In other words, the first chalcogenide compound layer SWA may have a larger band gap than the second chalcogenide compound layer SWb. For example, the first chalcogenide compound layer SW may have a band gap that is 0.1 eV or greater, 0.2 eV or greater, 0.3 eV or greater, 0.4 eV or greater, 0.5 eV or greater, 0.6 eV or greater, 1.0 eV or less, 0.9 eV or less, 0.8 eV or less, or 0.7 eV or less than the band gap of the second chalcogenide compound layer SWb.

[0048] The first chalcogenide compound layer SWA and the second chalcogenide compound layer SWb may each independently include: a first element including germanium (Ge) and / or tin (Sn), and a second element including sulfur (S), selenium (Se), and / or tellurium (Te).

[0049] The content of the first element in the first chalcogenide compound layer SGa and the second chalcogenide compound layer SWb can each independently be 5.0 atomic% or greater and 30.0 atomic% or less, based on the total element content. For example, the content of the first element can be 7.0 atomic% or greater, 10.0 atomic% or greater, 25.0 atomic% or less, 23.0 atomic% or less, or 20.0 atomic% or less, based on the total element content.

[0050] The content of the second element in the first chalcogenide compound layer SGa and the second chalcogenide compound layer SWb can each independently be greater than 0.0 atomic% and less than 70.0 atomic%, based on the total element content. For example, the content of the second element can be 10.0 atomic% or greater, 15.0 atomic% or greater, 20.0 atomic% or greater, 25.0 atomic% or greater, 30.0 atomic% or greater, 35.0 atomic% or greater, 40.0 atomic% or greater, 65.0 atomic% or less, 60.0 atomic% or less, or 55.0 atomic% or less of the total element content.

[0051] The first chalcogenide compound layer SWA and / or the second chalcogenide compound layer SWb may further and independently include a third element selected from arsenic (As), antimony (Sb), silicon (Si), and bismuth (Bi). The content of the third element in the first chalcogenide compound layer SWA and / or the second chalcogenide compound layer SWb may each be independently 5.0 atomic% or greater and 50.0 atomic% or less, based on the total elemental content. For example, the content of the third element may be 7.0 atomic% or greater, 10.0 atomic% or greater, 15.0 atomic% or greater, 20.0 atomic% or greater, 45.0 atomic% or less, 40.0 atomic% or less, or 35.0 atomic% or less, based on the total elemental content.

[0052] The second chalcogenide compound layer SWb may further include a metal dopant. Specifically, the second chalcogenide compound layer SWb may further include a fourth element selected from boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and indium (In). The content of said fourth element in the second chalcogenide compound layer SWb may be 0.1 atomic% or greater and 10.0 atomic% or less, based on the total elemental content. For example, the content of said fourth element may be 0.5 atomic% or greater, 1.0 atomic% or greater, 1.5 atomic% or greater, 2.0 atomic% or greater, 7.0 atomic% or less, 6.0 atomic% or less, or 5.0 atomic% or less of the total elemental content.

[0053] The first chalcogenide compound layer SGa may further include a nonmetallic dopant. Specifically, the first chalcogenide compound layer SGa may further include a fifth element selected from carbon (C), nitrogen (N), oxygen (O), phosphorus (P), and sulfur (S). The content of said fifth element in the first chalcogenide compound layer SGa may be 0.1 atomic% or greater and 10.0 atomic% or less, based on the total elemental content. For example, the content of said fifth element may be 0.5 atomic% or greater, 1.0 atomic% or greater, 1.5 atomic% or greater, 2.0 atomic% or greater, 7.0 atomic% or less, 6.0 atomic% or less, or 5.0 atomic% or less, based on the total elemental content.

[0054] The first chalcogenide compound layer SWA may include compounds of formula 1, formula 3, and / or formula 4. Additionally, the second chalcogenide compound layer SWb may include compounds of formula 1 and / or formula 2.

[0055] [Formula 1]

[0056] A a B b C c

[0057] [Equation 2]

[0058] A a B b C c D d

[0059] [Formula 3]

[0060] A a B b

[0061] [Formula 4]

[0062] A a B b C c E e

[0063] In Equations 1, 2, 3, or 4, A represents the first element, B represents the second element, C represents the third element, D represents the fourth element, and E represents the fifth element. Furthermore, in Equation 1, a + b + c = 1; in Equation 2, a + b + c + d = 1; in Equation 3, a + b = 1; and in Equation 4, a + b + c + e = 1. In Equations 1, 2, or 4, 0.05 ≤ a ≤ 0.30, 0.20 ≤ b ≤ 0.70, 0.05 ≤ c ≤ 0.50, 0.01 ≤ d ≤ 0.10, and 0.01 ≤ e ≤ 0.10. In Equation 3, 0.05 ≤ a ≤ 0.70 and 0.05 ≤ b ≤ 0.70.

[0064] According to one embodiment, the second chalcogenide compound layer SWb may include a compound of formula 1, and the first chalcogenide compound layer SWa may include a compound of formula 3 and / or a compound of formula 4. According to another embodiment, the second chalcogenide compound layer SWb may include a compound of formula 2, and the first chalcogenide compound layer SWa may include a compound of formula 1, a compound of formula 3, and / or a compound of formula 4.

[0065] The first chalcogenide compound layer SWa and / or the second chalcogenide compound layer SWb may have an appropriate thickness according to the required performance. For example, the thickness of the first chalcogenide compound layer SWa and / or the second chalcogenide compound layer SWb may independently be 0.5 nm or greater, 1.0 nm or greater, 2.0 nm or greater, 3.0 nm or greater, 5.0 nm or greater, 7.0 nm or greater, 10.0 nm or greater, 15.0 nm or greater, 30.0 nm or less, 28.0 nm or less, 25.0 nm or less, 23.0 nm or less, 20.0 nm or less, 17.0 nm or less, 15.0 nm or less, 13.0 nm or less, 10.0 nm or less, or 8.0 nm or less. Additionally, the second chalcogenide compound layer SWb may have a volume ratio (or thickness ratio) of 0.1 times or greater, 0.2 times or greater, 0.3 times or greater, 0.5 times or greater, 1.5 times or less, 1.2 times or less, 1.0 times or less, 0.8 times or less with respect to the first chalcogenide compound layer SWa.

[0066] For example, the ratio of the first chalcogenide compound layer is Ge 7 - 40%, As 5 - 50%, Se 30 - 70%, and the ratio of the second chalcogenide compound layer is Ge 7 - 40%, As 5 - 50%, Se 30 - 70%, In 0.5 - 10%. The thickness of the first chalcogenide compound layer is 1 - 19 nm, the thickness of the second chalcogenide compound layer is 1 - 19 nm, and the thickness of the first and second chalcogenide compound layers is 2 - 20 nm. The energy band gap of the first chalcogenide compound layer is 1.5 eV < Eg < 2.5 eV, and the energy band gap of the second chalcogenide compound layer is 1.2 eV < Eg < 2.2 eV.

[0067] Reference Figure 3B Referring to, the selection device layer SW may further include a third chalcogenide compound layer SWc that is adjacent to the second chalcogenide compound layer SWb and is arranged separately from the first chalcogenide compound layer SWa. In other words, the selection device layer SW may have a stacked structure of the first chalcogenide compound layer SWa / the second chalcogenide compound layer SWb / the third chalcogenide compound layer SWc.

[0068] The third chalcogenide compound layer SWc may include the compounds of the aforementioned Formula 1, Formula 3, and / or Formula 4. The third chalcogenide compound layer SWc may have an energy band gap larger than that of the second chalcogenide compound layer SWb. Additionally, the energy band gap of the third chalcogenide compound layer SWc may be greater than or equal to the energy band gap of the first chalcogenide compound layer SWa.

[0069] According to another embodiment, the selected device layer SW includes a first element, a second element, a third element, and a fourth element, and the fourth element has a concentration gradient in the thickness direction of the selected device layer SW. Specifically, refer to... Figure 3C The selected device layer SW has a first surface SW1 facing the first electrode 10 and a second surface SW2 facing the second electrode 20, and the fourth element may have a concentration gradient in the thickness direction between the first surface SW1 and the second surface SW2. For example, the concentration of the fourth element in the second surface SW2 may be greater than the concentration of the fourth element in the first surface SW1, and the concentration of the fourth element in the first surface SW1 may be 0. In addition, the concentration of the fourth element may be at a maximum value at a desired and / or alternatively predetermined thickness position (between SW1' and SW2'), and may decrease or become 0 towards the first surface SW1 and / or the second surface SW2. Furthermore, the concentration gradient of the fourth element may begin from positions SW1' and SW2' that are separated from the first surface SW1 (or the second surface SW2) by a desired and / or alternatively predetermined thickness. In other words, the fourth element may not be located at the first surface SW1 (or the second surface SW2) and / or between desired and / or alternatively predetermined thicknesses from the first surface SW1 (and / or the second surface SW2) to locations SW1' and / or SW2'. Locations SW1' and SW2' are not particularly limited, but, for example, may be greater than 0%, 1% or more, 3% or more, 5% or more, 7% or more, 10% or more, 15% or more, 20% or more, 75% or less, 70% or less, 65% or less, 60% or less, 58% or less, 55% or less, 53% or less, 50% or less, 48% or less, 45% or less, 43% or less, 40% or less, 38% or less, or 35% or less, respectively.

[0070] The selected device layer SW may further include a fifth element, and the fifth element may also have a concentration gradient in the thickness direction of the selected device layer SW. For example, the concentration of the fifth element in the first surface SW1 may be greater than that in the second surface SW2, and the concentration of the fifth element in the second surface SW2 may be 0. Additionally, the fifth element may have a minimum concentration or 0 at a desired and / or alternatively predetermined thickness location (between SW1' and SW2'). The direction of the concentration gradient of the fifth element may be different from the direction of the concentration gradient of the fourth element, and for example, it may be in the opposite direction to the fourth element. In particular, the concentration of the fifth element may decrease from the first surface SW1 to the second surface SW2, and the concentration of the fourth element may increase in this direction.

[0071] The selective device layer SW according to the embodiment has high thermal stability and is less prone to damage or deterioration during the manufacturing process of semiconductor devices, etc. Specifically, the crystallization temperature of each chalcogenide compound layer or selective device layer SW can be 350°C or higher and 600°C or lower. For example, the crystallization temperature can be 380°C or higher, 400°C or higher, 580°C or lower, or 550°C or lower. Furthermore, the sublimation temperature of each of the chalcogenide compound layer and selective device layer SW can be 250°C or higher and 400°C or lower. For example, the sublimation temperature can be 280°C or higher, 300°C or higher, 380°C or lower, or 350°C or lower.

[0072] The semiconductor device and semiconductor apparatus according to the embodiments may further include electrodes that electrically connect the components. Figure 4A and 4B This is a perspective and cross-sectional view of the semiconductor device 100 according to an embodiment. (Reference) Figure 4A and 4B The semiconductor device 100 may include a first electrode line layer 110L, a second electrode line layer 120L, and a semiconductor device layer MCL on a substrate 101.

[0073] The first electrode line layer 110L may include a plurality of first electrode lines 110 extending parallel to each other in a first direction (X direction). The second electrode line layer 120L may include a plurality of second electrode lines 120 arranged separately from the first electrode line layer 110L and extending parallel to each other in a second direction (Y direction). The first direction and the second direction may be different from each other and may intersect each other perpendicularly, as shown in... Figure 4A In the X and Y directions, but not limited thereto. Given the driving of the semiconductor device, multiple first electrode lines 110 may correspond to one of word lines and bit lines, and multiple second electrode lines 120 may correspond to the other.

[0074] The plurality of first electrode lines 110 and the plurality of second electrode lines 120 may each independently comprise a metal, a conductive metal nitride, a conductive metal oxide, or a combination of these materials. For example, the plurality of first electrode lines 110 and the plurality of second electrode lines 120 may each independently comprise W, WN, Au, Ag, Cu, Al, TiAlN, Ir, Pt, Pd, Ru, Zr, Rh, Ni, Co, Cr, Sn, Zn, ITO, alloys of these materials, or combinations of these materials. Additionally, the plurality of first electrode lines 110 and the plurality of second electrode lines 120 may each independently comprise a metal film and a conductive barrier layer covering part or all of the metal film. The conductive barrier layer may include, for example, Ti, TiN, Ta, TaN, or combinations thereof.

[0075] The semiconductor device layer MCL may include multiple semiconductor devices MC. The semiconductor devices MC may be arranged separately from each other and may have a three-dimensional structure in the region where the multiple first electrode lines 110 and the multiple second electrode lines 120 intersect.

[0076] The semiconductor device MC may be further included in the selected device layer 143 ( Figure 1 SW) and variable resistor layer 149 ( Figure 1 An electrode layer is provided between the first electrode line 110 and the select device layer 143 to electrically connect the select device layer 143 to the variable resistor layer 149. Additionally, an electrode layer may be further included between the first electrode line 110 and the select device layer 143 and / or between the second electrode line 120 and the variable resistor layer 149. Specifically, the select device layer 143 may be disposed between the first electrode layer 141 and the second electrode layer 145, and the variable resistor layer 149 may be disposed between the second electrode layer 145 and the third electrode layer 148.

[0077] The first electrode layer 141, the second electrode layer 145, and the third electrode layer 148 may serve as channels through which current flows and may include conductive materials. Each of the first electrode layer 141, the second electrode layer 145, and the third electrode layer 148 may independently include a metal, a conductive metal nitride, a conductive metal oxide, or a combination of these materials. For example, each of the first electrode layer 141, the second electrode layer 145, and the third electrode layer 148 may independently include one or more of the following: carbon (C), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium carbon nitride (TiCN), titanium silicon carbon nitride (TiCSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), and tungsten nitride (WN).

[0078] The selection device layer 143 may be one of the selection device layers described above. For example, although there are no particular restrictions on the introduction positions of the first chalcogenide compound layer 143a and the second chalcogenide compound layer 143b, the first chalcogenide compound layer 143a may be arranged closer to the first electrode layer 141 than the second chalcogenide compound layer 143b, or the second chalcogenide compound layer 143b may be arranged closer to the variable resistor layer 149 and / or the second electrode layer 145 than the first chalcogenide compound layer 143a. According to another embodiment, in the selection device layer 143, the concentration of the fourth element is greater at a position adjacent to the second electrode layer 145 compared to the first electrode layer 141, or the concentration of the fourth element may be at a maximum value at a position in the selection device layer 143 with a desired and / or alternatively predetermined thickness. Additionally, in the selected device layer 143, the concentration of the fifth element is smaller in the position adjacent to the second electrode layer 145 compared to the first electrode layer 141, or the concentration of the fifth element may be at a minimum at a position in the selected device layer 143 with a desired and / or alternatively predetermined thickness.

[0079] Furthermore, the semiconductor device MC may not include an insulating material between the first electrode layer 141 and the select device layer 143 and / or between the second electrode layer 145 and the select device layer 143. The insulating material may include metal oxides and / or metal nitrides, or may include silicon oxide, silicon nitride, or silicon oxynitride.

[0080] The variable resistance layer 149 may include a material that has resistance variation characteristics depending on the applied conditions.

[0081] According to an embodiment, the variable resistance layer 149 may include a material capable of reversibly changing phase with temperature. In other words, the variable resistance layer 149 may include a material capable of reversibly changing phase between crystalline and amorphous states with respect to heating time (applied heat). Specifically, the variable resistance layer 149 may include a material capable of reversibly changing phase between a crystalline and amorphous state by Joule heating generated when an external electrical pulse is applied (to the variable resistance layer 149), and whose resistance changes due to the phase transition. For example, the phase transition material may be in a high-resistivity state in the amorphous phase and a low-resistivity state in the crystalline phase. Data can be stored in the variable resistance layer 149 by defining the high-resistivity state as "0" and the low-resistivity state as "1".

[0082] The phase change material may include selenium (Se) and / or tellurium (Te), and may include one or more selected from Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, P, B, O, and C. The phase change material may include Ge-Sb-Te (GST). For example, Ge-Sb-Te (GST) is a compound containing Ge, Sb, and Te, and may include Ge2Sb2Te5, Ge2Sb2Te7, Ge1Sb2Te4, and / or Ge1Sb4Te7.

[0083] The phase change material may further include one or more metallic elements selected from the following: aluminum (Al), zinc (Zn), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), molybdenum (Mo), ruthenium (Ru), palladium (Pd), hafnium (Hf), tantalum (Ta), iridium (Ir), platinum (Pt), zirconium (Zr), thallium (Tl), and polonium (Po). These metallic elements can improve the electrical and thermal conductivity of the variable resistivity layer 149 and increase the crystallization rate.

[0084] The elements constituting the phase change material may have different chemical composition ratios (stoichiometry). Based on the chemical composition of each element, the crystallization temperature, melting point, phase transition rate based on crystallization energy, and information retention capacity of the phase change material can be controlled. For example, the chemical composition can be controlled so that the melting point of the phase change material is in the range of approximately 500°C to approximately 800°C.

[0085] The variable resistance layer 149 may have a multilayer structure in which multiple layers comprising different materials are alternately stacked. For example, the variable resistance layer 149 may have a structure in which layers comprising Ge-Te and layers comprising Sb-Te are alternately stacked. The stacked structure may be a superlattice structure. In addition, a barrier layer may be further included between the multiple layers. The barrier layer may limit and / or prevent material diffusion between the multiple layers.

[0086] The semiconductor device MC may further include a heating electrode layer 147 capable of heating the variable resistance layer 149. The heating electrode layer 147 may be disposed between the second electrode layer 145 and the variable resistance layer 149 to contact the variable resistance layer 149. The heating electrode layer 147 may include a conductive material capable of generating sufficient heat to induce a phase change in the variable resistance layer 149 without reacting with the variable resistance layer 149. For example, the heating electrode layer 147 may include TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, TiAlON, WON, TaON, or combinations of these materials. Furthermore, the heating electrode layer 147 may include a carbon-based conductive material. For example, the heating electrode layer 147 may include carbon (C), silicon carbide (SiC), silicon carbon nitride (SiCN), carbon nitride (CN), titanium carbon nitride (TiCN), tantalum carbon nitride (TaCN), or a combination of these materials.

[0087] The second electrode layer 145 may be formed with a thickness such that the heat generated by the heated electrode layer 147 substantially does not affect the selection device layer 143. The second electrode layer 145 may be formed with a thickness greater than that of the first electrode layer 141 or the third electrode layer 148, and may have a thickness in the range of about 10 nm to about 100 nm. Additionally, the second electrode layer 145 may further include a heat-blocking layer and may have a structure in which the heat-blocking layer and the electrode material layers are alternately stacked. The heated electrode layer 147 is used to heat a variable resistance layer 149 comprising a material capable of changing phase by heat, and in the following embodiments where the material of the variable resistance layer 149 is a different material, the heated electrode layer 147 may be omitted.

[0088] According to another embodiment, the variable resistance layer 149 may comprise a material capable of reversibly changing its resistance as defects in the compound move in response to an externally applied voltage. For example, the variable resistance layer 149 may comprise a transition metal oxide. The transition metal oxide is a metal oxide in which electrical channels are formed / depleted as oxygen vacancies move in response to an externally applied voltage and can reversibly change to a low-resistance state and a high-resistance state. The transition metal oxide may comprise one or more metals selected from the group consisting of: Ta, Zr, Ti, Hf, Mn, Y, Ni, Co, Zn, Nb, Cu, Fe, and Cr. For example, the transition metal oxide may comprise one or more of the following: Ta₂O. 5-x ZrO 2-x TiO 2-x HfO 2-xMnO 2-x Y2O 3-x NiO 1-y Nb2O 5-x CuO 1-y and Fe2O 3-x (0≤x≤1.5 and 0≤y≤0.5).

[0089] According to another embodiment, the variable resistance layer 149 may include a material capable of reversibly changing its resistance while altering its polarization state according to an externally applied voltage. For example, the variable resistance layer 149 may include a perovskite compound. The variable resistance layer 149 may include one or more of the following: niobium oxide, titanium oxide, nickel oxide, zirconium oxide, vanadium oxide, (Pr,Ca)MnO3 (PCMO), strontium titanium oxide (strontium titanium oxide), barium strontium titanium oxide (barium strontium titanium oxide), strontium zirconium oxide (strontium zirconium oxide), barium zirconium oxide (barium zirconium oxide), and barium strontium zirconium oxide (barium strontium zirconium oxide).

[0090] According to another embodiment, the variable resistance layer 149 may be a material capable of reversibly changing its resistance while its magnetization state changes according to an externally applied voltage. The variable resistance layer 149 may have a magnetic tunnel junction (MTJ) structure. Specifically, the variable resistance layer 149 may include two electrodes containing magnetic material and a dielectric between the two magnetic electrodes. The two electrodes containing magnetic material may be a magnetization fixed layer and a magnetization free layer, respectively, and the dielectric between them may be a tunnel blocking layer. The magnetization fixed layer has a magnetization direction fixed in one direction, and the magnetization direction of the magnetization free layer may be changed by the spin torque of the internal electrons. Specifically, the magnetization direction of the magnetization free layer may be reversibly changed to be parallel or antiparallel to the magnetization direction of the magnetization fixed layer, and the variable resistance layer 149 may reversibly change to a high-resistance state and a low-resistance state according to the magnetization direction of the magnetization free layer. The magnetization fixed layer and the magnetization free layer may include ferromagnetic materials, and the magnetization fixed layer may further include an antiferromagnetic material that fixes the magnetization direction of the internal ferromagnetic material. In addition, the tunnel blocking layer may include one or more oxides selected from Mg, Ti, Al, MgZn and MgB.

[0091] Semiconductor devices (MC) can have a cylindrical shape. For example, such as... Figure 4A and 4B As shown, the semiconductor device MC can have a rectangular column shape, and can have different column shapes such as cylindrical, elliptical, and polygonal column shapes.

[0092] In addition, such as Figure 4A and 4BAs shown, the side surface of the semiconductor device MC may be perpendicular to the substrate 101. In other words, the area of ​​the cross-section perpendicular to the stacking direction (Z direction) of the semiconductor device MC may be constant, but this is just an example, and the semiconductor device MC may have a structure in which the lower portion may have a larger area than the upper portion, or the upper portion may have a larger area than the lower portion. Furthermore, the areas of the upper and lower portions of the first electrode layer 141, the second electrode layer 145, the heating electrode layer 147, the third electrode layer 148, the selection device layer 143, and the variable resistor layer 149 may be independently the same or different from each other. This shape may vary depending on how the portions are formed. For example, the first electrode layer 141 and the selection device layer 143 may be formed by a damascene process to have a structure in which the area of ​​the upper portion is larger than the area of ​​the lower portion, and the second electrode layer 145, the heating electrode layer 147, the third electrode layer 148, and the variable resistance layer 149 may be formed by a relief etching process to have a structure in which their side surfaces are perpendicular to the substrate 101.

[0093] Insulating layers may be further disposed between the first electrode lines 110, between the second electrode lines 120, and / or between the semiconductor devices MC. Specifically, a first insulating layer 160a may be disposed between the first electrode lines 110, a second insulating layer 160b may be disposed between the separate semiconductor devices MC of the semiconductor device layer MCL, and a third insulating layer 160c may be disposed between the second electrode lines 120. The first insulating layer 160a, the second insulating layer 160b, and / or the third insulating layer 160c may contain dielectric materials comprising oxides and / or nitrides, and may contain the same or different materials. Furthermore, the first insulating layer 160a, the second insulating layer 160b, and / or the third insulating layer 160c may be an air gap. In this case, an insulating liner (not shown) may be formed between the first electrode lines 110, the second electrode lines 120, or the semiconductor devices MC and the air gap.

[0094] The substrate 101 may include semiconductor materials, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), etc., and may include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0095] The semiconductor device 100 may further include an interlayer insulating layer 105 on the substrate 101. The interlayer insulating layer 105 may be disposed between the substrate 101 and the first electrode line layer 110L to electrically isolate them. The interlayer insulating layer 105 may include oxides such as silicon oxide and / or nitrides such as silicon nitride.

[0096] The semiconductor device may include at least two semiconductor device layers (MCLs). Figure 4C This is a schematic cross-sectional view of a semiconductor device 400 according to another embodiment. (See reference...) Figure 4C The semiconductor device 400 may include a first electrode line layer 110L, a second electrode line layer 120L, a third electrode line layer 130L, a first semiconductor device layer MCL1, and a second semiconductor device layer MCL2 on a substrate 101. The first semiconductor device layer MCL1 may include a plurality of first semiconductor devices MC-1, and the second semiconductor device layer MCL2 may include a plurality of second semiconductor devices MC-2. The first semiconductor device MC-1 may include a first electrode layer 141-1, a selection device layer 143-1, a second electrode layer 145-1, a heating electrode layer 147-1, a variable resistor layer 149-1, and a third electrode layer 148-1, and the second semiconductor device MC-2 includes a first electrode layer 141-2, a selection device layer 143-2, a second electrode layer 145-2, a heating electrode layer 147-2, a variable resistor layer 149-2, and a third electrode layer 148-2. The materials of these layers may be substantially the same as those of the first electrode layer 141, the selector device layer 143, the second electrode layer 145, the heating electrode layer 147, the variable resistor layer 149, and the third electrode layer 148 described above. The first semiconductor device layer MCL1 may be disposed between the first electrode line layer 110L and the second electrode line layer 120L, and the second semiconductor device layer MCL2 may be disposed between the second electrode line layer 120L and the third electrode line layer 130L. The fourth insulating layer 160d may be disposed between the second semiconductor devices MC-2, and the fifth insulating layer 160e may be disposed between the third electrode lines 130.

[0097] Specifically, the first electrode line layer 110L and the third electrode line layer 130L may extend in the same direction (first direction, X direction) and may be separated from each other in a third direction (Z direction). Additionally, the second electrode line layer 120L may extend in a second direction (Y direction) and may be arranged to be separated from each other in a third direction (Z direction) between the first electrode line layer 110L and the third electrode line layer 130L. The first semiconductor device layer MCL1 may be disposed at the intersection between the first electrode line layer 110L and the second electrode line layer 120L, and the second semiconductor device layer MCL2 may be disposed at the intersection between the second electrode line layer 120L and the third electrode line layer 130L. For the driving of the semiconductor device 400, the first electrode line layer 110L and the third electrode line layer 130L may be word lines (or bit lines), and the second electrode line layer 120L may be a common bit line (or common word line).

[0098] Figure 4CThe semiconductor device 400 has two semiconductor device layers, MCL1 and MCL2, and the number of semiconductor device layers and the number of electrode line layers can be appropriately adjusted according to the desired performance level.

[0099] The semiconductor device 400 may further include a driving circuit region on the substrate 101. (Reference) Figure 4C The driving circuit region 410 may include circuit units such as peripheral circuits, driving circuits, and core circuits, which drive semiconductor devices MC-1 and MC-2 or perform arithmetic processing. The circuits may include, for example, page buffers, latch circuits, cache circuits, column decoders, sense amplifiers, and data input / output circuits, row decoders, etc. Furthermore, the circuits may be arranged between the substrate 101 and the semiconductor device layers MCL. In other words, the driving circuit region 410 and the semiconductor device layers MCL1 and MCL2 may be sequentially arranged on the substrate 101, and this arrangement may be a cell-on-periphery (COP) structure.

[0100] The driving circuit region 410 may include one or more transistors TR and wiring structure 414 electrically connected to the transistors TR.

[0101] A transistor TR may be disposed on the active region AC of a substrate 101 defined by a device isolation layer 104. The transistor TR may include a gate G, a gate insulating layer GD, and source / drain electrodes SD. Additionally, an insulating spacer 106 may be disposed on both sidewalls of the gate G, and an etch stop layer 108 may be disposed on the gate G and / or the insulating spacer 106. The etch stop layer 108 may include an insulating material such as silicon nitride or silicon oxynitride.

[0102] The wiring structure 414 can be arranged in appropriate quantity and location according to the layout of the drive circuit region 410 and the type and arrangement of the gate G. The wiring structure 414 can have a multilayer structure with two or more layers. In particular, such as Figure 4C As shown, the wiring structure 414 includes a first contact 416A, a first wiring layer 418A, a second contact 416B, and a second wiring layer 418B that are electrically connected to each other and can be sequentially stacked on the substrate 101. The first contact 416A, the first wiring layer 418A, the second contact 416B, and the second wiring layer 418B may each independently include a metal, a conductive metal nitride, a metal silicide, or a combination thereof, or a conductive material, such as tungsten, molybdenum, titanium, cobalt, tantalum, nickel, tungsten silicide, titanium silicide, cobalt silicide, tantalum silicide, nickel silicide, etc.

[0103] The wiring structure 414 may include interlayer insulation layers 412A, 412B, and 412C to electrically isolate the components. (See reference) Figure 4CInterlayer insulating layers 412A, 412B, and 412C may be disposed between multiple transistor TRs, between multiple wiring layers 418A and 418B, and / or between multiple contacts 416A and 416B. Interlayer insulating layers 412A, 412B, and 412C may include silicon oxide, silicon oxynitride, etc.

[0104] The semiconductor device 400 may further include a wiring structure (not shown) electrically connecting the semiconductor devices MC-1 and MC-2 to the drive circuit region 410, and the wiring structure (not shown) may be arranged through the interlayer insulating layer 105.

[0105] The selection device layer described above, together with the two electrodes arranged on both sides thereon, can constitute a switching device, such as... Figures 3A-3C As shown in the diagram. Specifically, the switching device can be used in various technical fields to control the flow of current based on changes in current and / or voltage. For example, the switching device can be used in place of a PN diode in technical fields where a PN diode is used. For the two electrodes and the selection device layer of the switching device, refer to... Figure 4A Description of the first electrode layer 141, the second electrode layer 145, and the selection device layer 143.

[0106] The switching device, semiconductor device, and / or semiconductor apparatus according to the embodiments may have a threshold voltage V of 2.5V or greater, 2.6V or greater, 2.7V or greater, 2.8V or greater, 2.9V or greater, 3.0V or greater, 5.0V or less, 4.9V or less, 4.7V or less, 4.6V or less, or 4.5V or less. th .

[0107] The switching device, semiconductor device, and / or semiconductor apparatus according to the embodiments may have high durability. For example, the switching device, semiconductor device, and / or semiconductor apparatus may have a 5.0 × 10⁻⁶ Ω·cm² design strength. 7 Times or more, 1.0 × 10 8 More than once, 5.0 × 10 8 Times or more, 1.0 × 10 9 More than once, or 5.0 × 10 8 Durability can be defined as the threshold voltage V within ±15% of the initial threshold voltage by using pulses with voltage rise and fall times of 10 ns and a width of 100 ns. th The number of on-off operations (the average threshold voltage of the device over 1000 on-off cycles). Additionally, the switching device, semiconductor device, and / or semiconductor apparatus may have a threshold voltage variation of 60 mV / dec or 55 mV / dec or less (V). th (drift value).

[0108] The switching device, semiconductor device, and / or semiconductor apparatus may be manufactured according to methods in the relevant field. Figures 5A-5C A cross-sectional view illustrating the process of manufacturing a semiconductor device according to an embodiment.

[0109] refer to Figure 5A An interlayer insulating layer 105 is formed on a substrate 101. A first electrode line layer 110L is formed on the interlayer insulating layer 105, comprising a plurality of first electrode lines 110 extending in a first direction (X direction) and separated from each other. The first electrode line layer 110L can be formed by forming a conductive layer for the first electrode lines and patterning the conductive layer by etching. A first insulating layer 160a can be filled between the first electrode lines 110. The first insulating layer 160a can be formed by planarizing the resulting product after filling the gaps between the first electrode lines 110 with an insulating material, such that the upper surface of the first electrode lines 110 is exposed by a CMP process or the like. A stacked structure 140k is formed by sequentially stacking a first electrode material layer 141k, a selection device material layer 143k, a second electrode material layer 145k, a heating electrode material layer 147k, a variable resistor material layer 149k, and a third electrode material layer 148k on the first electrode line layer 110L and the first insulating layer 160a.

[0110] refer to Figure 5B A mask pattern (not shown) is formed on the stacked structure 140k, separated from each other in a first direction (X direction) and a second direction (Y direction). Using the mask pattern, the stacked structure 140k is etched, exposing portions of the upper surfaces of the first insulating layer 160a and the first electrode line 110. Depending on the structure of the mask pattern, a plurality of semiconductor devices MC separated from each other in the first and second directions can be formed. Each of the plurality of semiconductor devices MC includes a first electrode layer 141, a selectable device layer 143, a second electrode layer 145, a heating electrode layer 147, a variable resistor layer 149, and a third electrode layer 148, and is electrically connected to the first electrode line 110. Furthermore, the remaining mask pattern can be removed by an ashing and stripping process.

[0111] refer to Figure 5C A second insulating layer 160b may be filled between multiple semiconductor devices MC. A second electrode line layer 120L comprising multiple second electrode lines 120 extending in a second direction (X direction) and separated from each other is formed on the semiconductor devices MC and the second insulating layer 160b. A third insulating layer 160c may be filled between the second electrode lines 120.

[0112] The first and second electrode lines 110 and 120, the first, second, and third electrode layers 141, 145, and 148, the heating electrode layer 147, the insulating layers 105, 160a, 160b, and 160c, the selective device layer 143, and the variable resistance layer 149 can be formed by methods known in the relevant art. Each of the components can be independently topographically formed with a desired composition and thickness using deposition methods such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or sputtering. For example, the selective device material layer 143k can be formed on the first electrode layer 141 using a source or target including a first element, a second element, a third element, and a fifth element, and a source or target including a first element, a second element, a third element, and a fourth element via physical vapor deposition (PVD) or sputtering.

[0113] Furthermore, each of the components can be independently patterned using methods known in the relevant art. In particular, not only the patterning methods described above can be used, but also damascene methods can be used. For example, in the case of forming the second electrode line 120 using a damascene process, after forming a thick insulating material layer between and above multiple semiconductor devices MC, a trench is formed by etching the insulating material layer. The trench can extend in the second direction and be formed to expose the upper surface of the variable resistance layer 149. The second electrode line 120 can be formed by filling the trench with a conductive material and planarizing the trench. The second insulating layer 160b and the third insulating layer 160c can be formed as a single unit.

[0114] The technical aspects of the semiconductor device will be described in more detail below through the implemented embodiments. However, the description of the embodiments should not be construed as limiting the scope of the claims.

[0115] Implementation Method 1

[0116] The first electrode layer is formed by DC sputtering or ALD. The thickness of the first electrode layer (cathode) is 5–30 nm.

[0117] A selection device layer is formed on the first electrode layer by sputtering. Specifically, a first chalcogenide compound layer is formed on the first electrode layer using a target comprising germanium (Ge), arsenic (As), and selenium (Se), and a second chalcogenide compound layer is formed using a target comprising indium (In), germanium (Ge), arsenic (As), and selenium (Se). As a result, in the selection device layer, the concentration of indium (In) is greater near the second electrode layer than near the first electrode layer.

[0118] A second electrode layer is formed on the selected device layer by DC sputtering or ALD method. The thickness of the second electrode layer (anode) is 5–30 nm.

[0119] Implementation Method 2

[0120] The semiconductor device is manufactured in the same manner as in Embodiment 1, except that the target introduction order is changed when forming the selectable device layer. Specifically, on the first electrode layer, a first chalcogenide compound layer is formed using a target comprising indium (In), germanium (Ge), arsenic (As), and selenium (Se), and a second chalcogenide compound layer is formed using a target comprising germanium (Ge), arsenic (As), and selenium (Se). As a result, in the selectable device layer, the concentration of indium (In) is greater near the first electrode layer than near the second electrode layer.

[0121] The atomic ratio, thickness, and band gap (Eg) of the first and second chalcogenide compound layers in Embodiments 1 and 2 are shown in the table below.

[0122]

[0123] Comparative Example 1

[0124] During the manufacturing process of a semiconductor device, the composition of the target is not changed, and the semiconductor device is manufactured in the same manner as in Embodiment 1, except that a selective device is formed by using only a target comprising germanium (Ge), arsenic (As), and selenium (Se).

[0125] Comparative Example 2

[0126] During the manufacturing process of a semiconductor device, the composition of the target is not changed, and the semiconductor device is manufactured in the same manner as in Embodiment 1, except that: a selective device is formed by using only a target including indium (In), germanium (Ge), arsenic (As), and selenium (Se).

[0127] Electrical characteristic evaluation 1

[0128] For each of the semiconductor devices according to Embodiment 1, Embodiment 2, Comparative Example 1, and Comparative Example 2, the threshold voltage V is measured. th Turn-off current I 关断 The rate of change of threshold voltage V th The drift value and durability characteristics are summarized in Table 1.

[0129] Referring to Table 1, the semiconductor devices of Embodiments 1 and 2 exhibit high threshold voltages V similar to those of Comparative Examples 1 and / or 2. th Furthermore, the semiconductor devices of Embodiments 1 and 2 exhibit greater durability characteristics compared to Comparative Examples 1 and 2. Additionally, the semiconductor devices of Embodiments 1 and 2 demonstrate a better rate of change of threshold voltage V compared to Comparative Example 1. thThe drift value, and the semiconductor device of Embodiment 1 exhibits a smaller turn-off current value I than that of Embodiment 2. 关断 .

[0130] [Table 1]

[0131]

[0132]

[0133] Although the embodiments have been described in detail, the scope of the claims is not limited to the embodiments described, and various modifications and improvements made by those skilled in the art using the basic concept defined in the appended claims are also within the scope of the claims.

[0134] Chalcogenide compound layers exhibiting bidirectional threshold switching characteristics can be provided.

[0135] Switching devices, semiconductor devices, and / or semiconductor apparatuses with low turn-off current (leakage current) and high durability are available. These devices and / or apparatuses enable improved integration and contribute to the miniaturization of electronic devices.

[0136] It should be understood that the embodiments described herein are to be considered in the descriptive sense only and are not intended for limiting purposes. The descriptions of features or aspects in each embodiment should typically be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. Semiconductor devices, including: First electrode; A second electrode separate from the first electrode; as well as A first chalcogenide compound layer and a second chalcogenide compound layer between the first electrode and the second electrode, wherein The first chalcogenide compound layer and the second chalcogenide compound layer each independently include a first element selected from germanium (Ge) and tin (Sn), and a second element selected from sulfur (S), selenium (Se), and tellurium (Te). The first chalcogenide compound layer and the second chalcogenide compound layer have different compositions from each other. The first chalcogenide compound layer has a band gap that is 0.1 eV or more larger than that of the second chalcogenide compound layer and 1.0 eV or less.

2. The semiconductor device of claim 1, wherein the semiconductor device has bidirectional threshold switching characteristics.

3. The semiconductor device of claim 1, wherein at least one of the first chalcogenide compound layer and the second chalcogenide compound layer further comprises a third element, said third element comprising one or more selected from arsenic (As), antimony (Sb), silicon (Si), and bismuth (Bi).

4. The semiconductor device of claim 1, wherein the second chalcogenide compound layer further comprises a fourth element, the fourth element comprising one or more selected from boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and indium (In).

5. The semiconductor device of claim 1, wherein the first chalcogenide compound layer further comprises a fifth element, the fifth element comprising one or more selected from carbon (C), nitrogen (N), oxygen (O), phosphorus (P), and sulfur (S).

6. The semiconductor device of claim 1, wherein the second chalcogenide compound layer comprises a compound represented by formula 1 or formula 2: [Formula 1] A a B b C c [Equation 2] A a B b C c D d in, In equation 1 or equation 2, A is the first element. B is the second element. C is a third element, which includes one or more selected from arsenic (As), antimony (Sb), silicon (Si), and bismuth (Bi). D is a fourth element, which includes one or more selected from boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and indium (In). In equation 1, a + b + c = 1, and In equation 2, a+b+c+d=1.

7. The semiconductor device of claim 1, wherein the first chalcogenide compound layer comprises a compound represented by any one of Formula 1, Formula 3, and Formula 4: [Formula 1] A a B b C c [Formula 3] A a B b [Formula 4] A a B b C c E e in, In equation 1, equation 3, or equation 4, A is the first element. B is the second element. C is a third element, which includes one or more selected from arsenic (As), antimony (Sb), silicon (Si), and bismuth (Bi). E is the fifth element, which includes one or more selected from carbon (C), nitrogen (N), oxygen (O), phosphorus (P), and sulfur (S). In equation 1, a + b + c = 1. In equation 3, a + b = 1, and In equation 4, a + b + c + e = 1.

8. The semiconductor device of claim 1, wherein the second chalcogenide compound layer has a volume ratio of 0.1 times or greater and 1.5 times or less than that of the first chalcogenide compound layer.

9. The semiconductor device of claim 1, further comprising: A third chalcogenide compound layer that is adjacent to the second chalcogenide compound layer and separate from the first chalcogenide compound layer.

10. The semiconductor device of claim 9, wherein the third chalcogenide compound layer comprises one or more compounds represented by formulas 1, 3, and 4: [Formula 1] A a B b C c [Formula 3] A a B b [Formula 4] A a B b C c E e in, In equation 1, equation 3, or equation 4, A is the first element. B is the second element. C is a third element, which includes one or more selected from arsenic (As), antimony (Sb), silicon (Si), and bismuth (Bi). E is the fifth element, which includes one or more selected from carbon (C), nitrogen (N), oxygen (O), phosphorus (P), and sulfur (S). In equation 1, a + b + c = 1. In equation 3, a + b = 1, and In equation 4, a + b + c + e = 1.

11. The semiconductor device of claim 9, wherein the third chalcogenide compound layer has a larger band gap than the second chalcogenide compound layer.

12. The semiconductor device of claim 1, further comprising: Variable resistance layer; and The selected device layer is arranged to be electrically connected to the variable resistor layer, and The selected device layer includes the first chalcogenide compound layer and the second chalcogenide compound layer.

13. The semiconductor device of claim 12, wherein the second chalcogenide compound layer is arranged adjacent to the variable resistor layer compared to the first chalcogenide compound layer.

14. The semiconductor device of claim 12, further comprising: The third electrode, in which The selection device layer is disposed between the first electrode and the second electrode, and The variable resistance layer is disposed between the second electrode and the third electrode.

15. The semiconductor device of claim 14, wherein the first chalcogenide compound layer is located adjacent to the first electrode layer compared to the second chalcogenide compound layer.

16. The semiconductor device of claim 14, wherein the first electrode, the second electrode, and the third electrode each independently comprise one or more of the following: carbon (C), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium carbon nitride (TiCN), titanium silicon carbon nitride (TiCSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), and tungsten nitride (WN).

17. The semiconductor device of claim 12, wherein the variable resistance layer comprises a material capable of reversibly changing phase between crystalline and amorphous states in response to temperature changes.

18. The semiconductor device of claim 17, wherein the variable resistance layer comprises a compound in which at least one of Te and Se is combined with at least one selected from Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, P, B, O, and C.

19. The semiconductor device of claim 18, wherein the variable resistance layer further comprises one or more of the following: aluminum (Al), zinc (Zn), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), molybdenum (Mo), ruthenium (Ru), palladium (Pd), hafnium (Hf), tantalum (Ta), iridium (Ir), platinum (Pt), zirconium (Zr), thallium (Tl), and polonium (Po).

20. The semiconductor device of claim 17, further comprising: A heating electrode layer arranged to contact the variable resistance layer.

21. The semiconductor device of claim 12, wherein the variable resistance layer comprises a material capable of reversibly changing the resistance according to an externally applied voltage.

22. The semiconductor device of claim 21, wherein the variable resistance layer comprises an oxide of one or more metals selected from Ta, Zr, Ti, Hf, Mn, Y, Ni, Co, Zn, Nb, Cu, Fe, and Cr.

23. The semiconductor device of claim 12, wherein the variable resistance layer comprises a material capable of reversibly changing its polarization state according to an externally applied voltage.

24. The semiconductor device of claim 23, wherein the variable resistance layer comprises one or more perovskite compounds selected from: niobium oxide, titanium oxide, nickel oxide, zirconium oxide, vanadium oxide, (Pr, Ca)MnO3 (PCMO), strontium titanium oxide, barium strontium titanium oxide, strontium zirconium oxide, barium zirconium oxide, and barium strontium zirconium oxide.

25. The semiconductor device of claim 12, wherein the variable resistance layer comprises a material capable of reversibly changing its magnetization state according to an externally applied voltage.

26. The semiconductor device of claim 25, wherein the variable resistance layer comprises two electrodes comprising a magnetic material and a dielectric between the two electrodes.

27. A semiconductor device, comprising: Multiple first electrode lines on the substrate, which are parallel to the upper surface of the substrate and extend in a first direction; The plurality of second electrode lines on the plurality of first electrode lines are parallel to the upper surface of the substrate and extend in a second direction different from the first direction; as well as A first semiconductor device disposed at the intersection of the plurality of first electrode lines and the plurality of second electrode lines, wherein the first semiconductor device comprises the semiconductor device as described in any one of claims 1-26.

28. The semiconductor device of claim 27, further comprising: Multiple third electrode lines are provided on the multiple first electrode lines and the multiple second electrode lines, and the multiple third electrode lines extend in the first direction; as well as A second semiconductor device located at the intersection of the plurality of second electrode lines and the plurality of third electrode lines.

29. The semiconductor device of claim 27, further comprising: Circuit units used to drive the semiconductor device or perform computational operations.

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