Method for manufacturing a capacitor

Abstract

The application relates to the field of semiconductor processing and manufacturing, in particular to a preparation method of a capacitor, which comprises the following steps: sequentially forming a first oxide layer, a support layer and a second oxide layer on the upper part of a semiconductor substrate; forming a groove penetrating through the first oxide layer, the support layer and the second oxide layer; sequentially forming a lower electrode layer, a dielectric layer and an upper electrode layer in the groove; wherein the support layer exerts a lateral pressure on the capacitor by continuously increasing the temperature during the formation of the support layer. In this way, the cylindrical capacitor can store more electric quantity without changing the shape (for example, thickness and structure) and material of the cylindrical capacitor, so that the capacitance of the capacitor is increased.

Description

Technical Field

[0001] This application relates to the field of semiconductor processing and manufacturing, and specifically to a method for preparing a capacitor. Background Technology

[0002] In the DRAM manufacturing process, the production of transistors and capacitors is a crucial step, especially in products with drastically reduced area, where numerous technical challenges arise. In particular, increasing capacitor capacitance has been achieved through improvements to high-k dielectric materials and increasing the capacitor's aspect ratio. However, given the already very large aspect ratios of capacitors, further increasing their size remains technically difficult. Summary of the Invention

[0003] This application addresses, to at least partly, the aforementioned technical problems in related technologies. To this end, this application proposes a method for manufacturing a capacitor to solve the problem of increasing the capacitance of the capacitor.

[0004] To achieve the above objectives, the first aspect of this application provides a method for manufacturing a capacitor, comprising the following steps:

[0005] A first oxide layer, a support layer, and a second oxide layer are sequentially formed on the upper part of a semiconductor substrate;

[0006] A trench is formed that penetrates the first oxide layer, the support layer, and the second oxide layer;

[0007] A lower electrode layer, a dielectric layer, and an upper electrode layer are sequentially formed within the trench.

[0008] During the formation of the support layer, the temperature is continuously increased so that the support layer applies lateral pressure to the capacitor. Attached Figure Description

[0009] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0010] Figure 1 A schematic diagram of the structure after depositing an etch barrier layer, a first oxide layer, a support layer, and a second oxide layer on a semiconductor substrate is shown.

[0011] Figure 2 It shows the Figure 1 A schematic diagram of the structure after the grooves have been patterned.

[0012] Figure 3 It shows Figure 2 A schematic diagram of the structure after the electrode layer has been deposited;

[0013] Figure 4 It shows Figure 3 A schematic diagram of the structure after removing the lower electrode layer and the second oxide layer. Detailed Implementation

[0014] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0015] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0016] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0017] The first aspect of this application provides a method for fabricating a cylindrical (PILLAR) capacitor, comprising the following steps:

[0018] like Figure 1 As shown, a semiconductor substrate 11 with a memory node plug 10 is provided; specifically, the memory node plug 10 is formed by forming a polysilicon layer, performing a chemical mechanical polishing (CMP) process, and performing an etch-back process after forming contact holes;

[0019] Next, an etch barrier layer 12, a first oxide layer 13, a first support layer 14, a second oxide layer 15, a second support layer 16, and a third oxide layer 17 are sequentially deposited on the semiconductor substrate 11. The first support layer 14 and the second support layer 16 can be formed by plasma-enhanced chemical vapor deposition, and the material of the first support layer 14 and the second support layer 16 can be silicon nitride. The etch barrier layer 12 can include a silicon layer. The first oxide layer 13 and the second oxide layer 15 respectively comprise plasma-enhanced tetraethyl orthosilicate (PE-TEOS), borosilicate glass (BPSG), phosphosilicate glass (PSG), and undoped silicate glass (USG).

[0020] It is worth mentioning that during the deposition of the support layer 14, the temperature is continuously increased, which causes the first support layer 14 and the second support layer 16 of silicon nitride to generate a certain tensile stress.

[0021] Furthermore, in this embodiment, silicon nitride is used as the material for the first support layer 14 and the second support layer 16. It should be noted that the first support layer 14 and the second support layer 16 can also be other materials with tensile stress. This embodiment does not limit them, and those skilled in the art can choose flexibly as needed.

[0022] Next, patterning is performed using mask 200, specifically, as follows: Figure 2 As shown, the third oxide layer 17, the second support layer 16, the second oxide layer 15, the first support layer 14, the first oxide layer 13, and the etch barrier layer 12 are etched sequentially to form a trench 18 that penetrates the etch barrier layer 12, the first oxide layer 13, the first support layer 14, the second oxide layer 15, the second support layer 16, and the third oxide layer 17. It is worth mentioning that when the first support layer 14 and the second support layer 16 are etched, a mesh structure is formed.

[0023] Next, as Figure 3 As shown, a lower electrode layer 19 is deposited on the third oxide layer 17 and on the sidewalls and bottom wall of the trench 18. Specifically, the lower electrode layer 19 comprises a metallic material, such as TiN, ruthenium (Ru), ruthenium oxide (RuO2), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), iridium (Ir), iridium oxide (IrO2), platinum (Pt), or combinations thereof. The lower electrode layer 19 can be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). Furthermore, the lower electrode layer 19 can be formed by pulsed CVD (PCVD), sequential flow deposition (SFD), or modified ALD (MALD) employing partial CVD or ALD methods.

[0024] Next, as Figure 4As shown, wet etching is used to remove the lower electrode layer 19 and the third oxide layer 17 on the third oxide layer 17, exposing the second support layer 16. At this time, the exposed second support layer 16 can also serve as a wet stopper for wet etching. Specifically, the etching solution for wet etching includes: HF solution, or a mixed solution of ammonium fluoride and hydrofluoric acid.

[0025] Next, a dielectric layer and an upper electrode layer (not shown in the figure) are deposited sequentially on the lower electrode layer 19 to form a cylindrical capacitor.

[0026] It is worth mentioning that this embodiment only uses the deposition of two support layers as an example for illustration. Of course, multiple support layers can also be deposited. Those skilled in the art can flexibly select the number of support layers to be deposited according to process requirements.

[0027] Compared with existing technologies, by continuously heating the support layer, a certain tensile stress is created in the support layer, which in turn applies lateral pressure to the cylindrical capacitor in the trench. This allows the cylindrical capacitor to store more charge without changing its shape (e.g., thickness, structure) and material, thereby increasing the capacitor's capacitance.

[0028] The capacitor in this embodiment can be applied to volatile memory devices such as DRAM devices and SRAM devices, or non-volatile memory devices such as Flash devices, PRAM devices, MRAM devices, and RRAM devices.

[0029] Furthermore, the semiconductor device having the above-mentioned capacitor can be used in various electronic devices, specifically, such electronic devices as smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, power banks, etc.

[0030] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0031] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for manufacturing a capacitor, characterized in that, Includes the following steps: A first oxide layer, a support layer, and a second oxide layer are sequentially formed on the upper part of a semiconductor substrate; A trench is formed that penetrates the first oxide layer, the support layer, and the second oxide layer, and the support layer is etched when the trench is formed to make the support layer form a mesh structure; A lower electrode layer, a dielectric layer, and an upper electrode layer are sequentially formed within the trench. The support layer comprises two layers, and the support layer comprises silicon nitride. During the formation of the support layer, the temperature is continuously increased to generate tensile stress in the support layer, so that the support layer with the mesh structure applies lateral pressure to the capacitor.

2. The method for preparing a capacitor according to claim 1, characterized in that, Forming the lower electrode layer includes the following steps: An electrode layer is deposited on the second oxide layer and on the sidewalls and bottom wall of the trench; Remove the lower electrode layer on the second oxide layer; The support layer is exposed.

3. The method for preparing a capacitor according to claim 2, characterized in that, The lower electrode layer was removed using wet etching.

4. The method for preparing a capacitor according to claim 3, characterized in that, The etching solution used in the wet etching process includes: HF solution, or a mixed solution of ammonium fluoride and hydrofluoric acid.

5. The method for preparing a capacitor according to claim 1, characterized in that, The support layer is formed by a plasma-enhanced chemical vapor deposition process.

6. The method for manufacturing a capacitor according to any one of claims 1-5, characterized in that, The first oxide layer and the second oxide layer respectively comprise phosphosilicate glass (PSG), borosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), undoped silicate glass (USG), or a combination thereof.

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