Segmented resistor digital-to-analog converter

Abstract

An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC, 408) having a resistor network. The resistor network includes a first segment and a second segment (B0-B9, T1-T15). The first segment (B0-B9, T1-T15) includes a first switch (SW) coupled between a first supply voltage node and a first set of resistors (R). The second segment (T13, T14) includes a second switch (SW) coupled between the first supply voltage node and a second set of resistors (450). The first segment includes a third switch coupled in series with a second resistor. The series combination of the third switch and the second resistor is coupled in parallel with at least one resistor of the first set of resistors. The second segment includes a fourth switch coupled in series with a third resistor. The series combination of the fourth switch and the third resistor is coupled in parallel with at least one resistor of the second set of resistors.

Description

Technical Field

[0001] This disclosure relates generally to the field of circuits, and more specifically to analog-to-digital converters. Background Technology

[0002] One type of analog-to-digital converter (ADC) is the successive approximation register (SAR) ADC. A SAR ADC determines the output digital code iteratively, starting with the most significant bit (MSB), then the next most significant bit, and so on, until the least significant bit (LSB) is determined. Each cycle of the SAR ADC compares the input analog signal to a threshold voltage, which is reset at the end of each successive iteration. In the first cycle, the threshold voltage is set to the midpoint of the input voltage range. If the input voltage is higher than the threshold voltage, the MSB is determined to be "1"; if the input voltage is lower than the threshold voltage, the MSB is determined to be "0". Once the MSB is known, if the MSB is determined to be 1, the threshold voltage is reset at the midpoint of the range between the previous midpoint voltage and the maximum input voltage in the cycle; or if the MSB is determined to be 0, the threshold voltage is reset at the midpoint of the range between 0V (i.e., the lower limit of the input voltage range) and the previous midpoint voltage in the cycle. This process repeats, resetting the threshold voltage each cycle until the LSB is determined. At this point, the complete digital output code has been determined.

[0003] A SAR ADC includes a digital-to-analog converter (DAC) for converting a digital value into a threshold voltage, which is compared with an analog input signal by a comparator. The digital value supplied to the DAC changes in each cycle, and therefore the analog output threshold voltage from the DAC also changes in each cycle, as described above. Summary of the Invention

[0004] In one example, an analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) with a resistor network. The resistor network includes a first segment and a second segment. The first segment includes a first switch coupled between a first power supply voltage node and a first set of resistors. The second segment includes a second switch coupled between the first power supply voltage node and the second set of resistors. The first segment includes a third switch coupled in series with the second resistor. The series combination of the third switch and the second resistor is coupled in parallel with at least one resistor in the first set of resistors. The second segment includes a fourth switch coupled in series with the third resistor. The series combination of the fourth switch and the third resistor is coupled in parallel with at least one resistor in the second set of resistors. Attached Figure Description

[0005] For a detailed description of the various examples, reference will now be made to the accompanying drawings, in which:

[0006] Figure 1An example of an analog-to-digital converter (ADC) based on a successive approximation register (SAR) is illustrated.

[0007] Figure 2 It shows in Figure 1 An example implementation of a resistor-based digital-to-analog converter (DAC) used in a SAR ADC.

[0008] Figure 3 The diagram shows the use of... Figure 1 An example of a server computer using an integrated circuit (IC) for a SAR ADC.

[0009] Figure 4 It shows in Figure 1 Another example implementation of a resistor-based DAC used in SAR ADCs.

[0010] Figure 5 An example implementation of a unit resistor used in the DAC of a SAR ADC is shown.

[0011] Figure 6 The diagram illustrates a series connection (e.g.) Figure 5 (in the middle) Two unit resistors.

[0012] Figure 7 Including, for example Figure 6 The circuit model of two adjacent segments of a resistor-based DAC.

[0013] Figure 8 It shows in Figure 1 This is yet another example implementation of a resistor-based DAC used in a SAR ADC.

[0014] Figure 9 Including, for example Figure 8 The circuit model of two adjacent segments of a resistor-based DAC.

[0015] Figure 10 The illustration is shown. Figure 2 Timing diagram of the stable time period of a resistor-based DAC segment.

[0016] Figure 11 Alternative examples of individual segments of a resistor-based DAC are shown, along with timing diagrams illustrating the stable time periods.

[0017] Figure 12 An example implementation is shown for reducing the integral nonlinearity of a pair of series-connected resistors due to switching resistor mismatch within the DAC. Detailed Implementation

[0018] Figure 1An example implementation of a SAR ADC 100 is shown. The example SAR ADC 100 includes a sample-and-hold circuit 102, a comparator 104, a SAR 106, and a DAC 108. The sample-and-hold circuit 102 samples and holds the input voltage VIN, which is then compared by the comparator 104 with a threshold voltage 109 from the DAC 108. The output of the comparator 104 is either high or low depending on whether VIN is greater than or less than the output voltage of the DAC. The output from the comparator 104 in each cycle represents the next most significant bit of the output digital code. The output digital code is stored in the SAR 106 and can be retrieved from it as a digital output code 110. The SAR 106 also provides a digital value 107 to the DAC 108. The DAC 108 converts the digital value 107 into an analog threshold voltage 109 to be provided to the comparator 104. The digital value 107 is updated with each cycle of the conversion process until all bits of the digital output code 110 are determined.

[0019] Figure 2 An example implementation of DAC 108 is shown. In this example, DAC 108 includes a resistor network and a binary-to-temperature converter 235. The resistor network includes multiple binary segments 210 and multiple temperature segments 240. In this example, each binary segment 210 includes a switch SW and two resistors R connected in series. As shown, another resistor R connects a binary segment 210 to the binary segment 210. Each resistor R is referred to as a “unit” resistor. The architecture of the binary segment 210 can be referred to as an R-2R resistor network. Each temperature segment 240 also includes a switch SW and two resistors R connected in series, but there are no additional resistors connected between the temperature segments 240.

[0020] Each switch SW couples the corresponding series-connected resistor of that segment to either the reference voltage (VREF) or ground (VGND). In this example, the DAC 108 includes 10 binary segments 210 and 15 temperature segments 240. Figure 2In the example, DAC108 is a 14-bit DAC where the 10 least significant bits [B9:B0] of the digital value 107 from SAR 106 control the switches SW of binary segment 210, as shown at 236. A binary bit, for example, being "1" causes the corresponding switch to couple VREF to the resistor of that segment, while a binary bit being "0" causes the corresponding switch to couple VGND to the resistor of that segment. The high four bits of digital value 107 are converted by binary-to-temperature converter 235 into a 15-bit temperature code to control the switches SW of 15 temperature segments T1 to T15. In each cycle, based on the value of the high four bits of digital value 107, one (or none) temperature bit is high (coupling the resistor of that segment to VREF), and the rest are low (coupling the resistors of those segments to VGND). Node N1, which connects temperature segments 240 together, provides a threshold voltage 109 from DAC 108 to comparator 104.

[0021] Figure 3 An example of a server 300 (or other type of computer) is shown, which includes a pulse width modulation (PWM) integrated circuit (IC) 301, multiple power stages 320, multiple inductors L1, a central processing unit (CPU) 390, and a memory 392. Other components may also be included. The PWM IC 301 includes a multiphase PWM. Multiple PWM control circuits 310 are provided within the PWM IC 301, and each PWM control circuit 310 is coupled to a corresponding power stage 320. Each power stage 320 may include, for example, a pair of transistors connected between a power node and ground. Each power stage 320 is coupled to a corresponding inductor L1. As shown, the inductors L1 are connected together to generate a supply voltage (VOUT) to the CPU 390. This supply voltage can also be used to power other devices within the server 300, such as the memory 392. Each PWM control circuit 310 controls when each transistor within the corresponding power stage 320 is turned on and off, thereby regulating the voltage to the CPU 390.

[0022] Each power stage 320 generates a current sensing (CS) signal and a temperature sensing (TS) signal. The CS signal represents the current of the corresponding power stage 320. The CS signals are added together by adder 345 to generate a combined current (IMON). The TS signal indicates the temperature of the corresponding power stage 320. The TS signals are connected together as a single input to PWM IC 301 to provide a signal indicating the hottest power stage 320.

[0023] exist Figure 3The PWM IC 301 in the example also includes a SAR ADC 350, which can be used to convert any one of a plurality of analog signals 355 into a digital value 357. Examples of such analog signals 355 include the input voltage (VIN) to the PWM IC 300, the IMON signal, the TEMP signal, etc. A communication interface 360 ​​(e.g., conforming to the power management bus (“PMBus”) protocol) is coupled to the SAR ADC 350 and can transmit the digital value 355 to an external device.

[0024] Differential nonlinearity (DNL) of a DAC is a measure of the deviation between two analog voltages corresponding to adjacent input digital values ​​and measures the error in the digital-to-analog conversion process. In some applications (e.g., PWM IC 301), a single SARADC 350 is used to digitize multiple different analog signals. Therefore, different DNL requirements can be imposed on the SAR ADC 355 for different voltage ranges. For example, for one of the analog signals 355, the DAC DNL requirement of the SAR ADC could be half the LSB DNL of a 14-bit converter with a voltage range of 1.5V to 1.75V and a reference voltage (VREF) within the DAC at 1.92V. Other analog signals 355 may have less stringent DNL requirements.

[0025] Besides the DNL requirements of SAR ADCs for a specific voltage range, the settling time of the DAC in a SAR ADC limits the conversion speed of the SAR ADC. Settling time is the time after the state change of switch SW must occur before the voltage at node N1 is guaranteed to reach its final voltage level. A longer settling time means slower digital-to-analog conversion. Another issue to consider is the on-resistance of switch SW, which can be large enough to cause a relatively large integral nonlinearity (INL). The DAC described below addresses one or more of these three issues: (1) the DNL requirements for a specific voltage range, (2) the settling time, and (3) the effect of switch on-resistance on INL. As a result, the analog-to-digital conversion process within server 300 will have fewer errors (for at least one or more of the analog signals 355), a faster settling time, and / or a lower INL without increasing the switch size (as described below). In one example, CPU 390 reads the digitized values ​​of IMON, TEMP, VIN, etc., and modifies its operating environment according to the magnitude of one or more of these parameters. For example, if the current or temperature exceeds a corresponding threshold, the CPU 390 may cause its operating frequency or operating voltage to decrease. The CPU 390 can submit signals or messages to the PWM IC 301 via interface 360 ​​to cause changes in VOUT. Therefore, the more accurate the digitized value of IMON, for example (due to improved DNL performance), the more effective the control over the CPU's operating environment. In this example, the DAC within the SAR ADC 350 is configured with a predetermined DNL for the signal range of the IMON signal, allowing the server 300 to more effectively monitor and control its operating environment.

[0026] The DNL of a resistor network-based DAC is worse at transitions from one digital value to the next when all switches SW in binary segment 210 change state. For example, for a 14-bit DAC, for the digital value 1023 (decimal), the lowest 10 bits are all "1", so all 10 switches SW in binary segment 210 are controlled to connect resistors R in those segments to VREF. The next adjacent digital value is 1024, which means all the lowest 10 bits are "0", so all 10 switches SW in binary segment 210 are controlled to connect resistors R to VGND. The state changes of all 10 switches SW within binary segment 210 also occur during transitions from 2047 to 2048, 3071 to 3072, etc.—each time the lowest 10 bits change from all "1"s to all "0".

[0027] If all resistors R had identical resistances, the DAC's DNL would be lower. However, in practice, resistor-based DACs do not include identical resistances for all their resistors. The resistance of the resistors within the DAC 108 can be modeled as R(1+σ), where σ is the resistor's mismatch factor. For a given resistor size, the resistor mismatch across a resistor in a DAC is typically random. That is, the IC manufacturer that includes the DAC will guarantee a specific value for the mismatch factor (σ) of all resistors of a given size. For this reason, the resistors within the example DAC 108 all have the same size and therefore the same area (area refers to the cross-sectional area of ​​the resistor along the current path through it). The mismatch factor σ of a unit resistor R is inherently Gaussian. The mismatch factor σ is inversely proportional to the square root of the resistor's area. For example, the effective resistance of two unit resistors R connected in series is 2R(1+σ / Therefore, increasing the resistor area leads to an effective mismatch factor (i.e., σ / The reduction of the mismatch factor of the DAC internal resistor will lead to a decrease in the expected DNL.

[0028] As mentioned above, a lower DNL may be desired for a specific voltage range of a DAC. In the example above, for a 14-bit converter with a voltage range of 1.5V to 1.75V and a reference voltage (VREF) of 1.92V, a DNL of half the LSB DNL might be desired. For a 14-bit DAC (10 binary bits and 15 temperature bits) with a 1.92V reference voltage, the main digital value conversions (where all 10 binary segments 210 switches SW change state) occur at 1.56V and 1.68V DAC analog output voltages within the 1.5V to 1.75V range. These voltages are generated when the control switch T13 SW connects its resistor to VREF (producing 1.56V) and when the control switch T14 SW connects its resistor to VREF (producing 1.68V).

[0029] Figure 4 An example implementation of DAC 408 is shown, which has similar characteristics to... Figure 2 The architecture of the DAC 108 in the text, but Figure 2 The binary segment 210 is connected to the single unit resistor R of the temperature segment 240 as implemented in the example. Figure 4 Four examples of a unit resistor R (shown at 401), and Figure 2 Each of the two unit resistors R in the temperature ranges T13 and T14 is in Figure 4The example is replaced with two sets of four series-connected unit resistors R connected in parallel (shown at 450). The four unit resistors R at 401 consist of two series-connected resistors 402 and two series-connected resistors 403. The series-connected resistors 402 and 403 are connected in parallel. The effective resistance generated between nodes N1 and N3 is still the resistance of a single unit resistor R, but the area of ​​this set of resistors 402 and 403 is four times the area of ​​a single unit resistor. Similarly, reference numeral 450 illustrates four series-connected unit resistors R, which have a combined resistance of 4R. When every four series-connected unit resistors are connected in parallel with another set of four series-connected unit resistors R, the effective resistance generated in this segment is 2R.

[0030] Therefore, the effective resistance between nodes N1 and N2 remains R, and within the temperature ranges T13 and T14, the effective resistance remains 2R. However, the total area of ​​the four unit resistors at 401 is four times the area (A) of the unit resistor R (i.e., 4A), so the effective resistance of the two sets of parallel series-connected unit resistors at 401 is R(1+σ / 2), thus the resistance mismatch is smaller compared to a single unit resistor. Furthermore, the total area of ​​the eight unit resistors in the temperature ranges T13 and T14 at 450 is as follows: Figure 2 The area of ​​the two unit resistors connected in series is four times that of the two units connected in parallel. Advantageously, at 450°, the effective resistance of the two sets of parallel unit resistors connected in series is 2R(1+σ' / 2), while for Figure 2 The two unit resistors connected in series in the diagram have an effective resistance of 2R(1+σ') for each such segment, where σ' is the effective mismatch factor of the two unit resistors connected in series. Therefore, with Figure 2 Compared to the corresponding resistor in the middle, Figure 4 The effective resistance mismatch is smaller at 401 and 450.

[0031] The DAC 408 therefore has a lower DNL at certain digital values ​​corresponding to the analog output voltage of interest, and may have a higher DNL at other digital values. Given the specific analog signal being digitized and its usage, the higher DNL for other digital values ​​will not adversely affect the performance of the SAR ADC using the DAC 408.

[0032] Figure 5An example implementation of a single unit resistor R is shown. In this example, the unit resistor is the resistance of polysilicon 502 within a silicon dioxide (or other type of dielectric) layer 502. The dielectric layer 502 is formed on a doped (e.g., n-doped) well 520, and the doped well 520 is formed within a substrate 518 (e.g., a p-doped substrate). Electrical contacts 530 and 535 (e.g., vias) are provided to opposite ends of the polysilicon 502. Resistor 515 represents the resistance of the polysilicon 502. Electrical contact 540 is also provided to an n-doped region 545 within the n-well 520. The n-doped region 545 has a higher doping concentration than the n-well 520. In the example shown, the well 520 and region 545 are n-doped, but in other examples they may be p-doped. In one example, region 545 is p-doped and substrate 518 is n-doped, thus forming a pn junction. To avoid forward biasing the pn junction formed between the p-doped region 545 and the n-doped substrate 518, the same voltage applied to the substrate is also applied to the electrical contact 545. This voltage... Figure 5 It is displayed as PBKG. The n-well 520 can also be connected to the PBKG voltage.

[0033] Figure 5 In the figure, capacitor C represents the parasitic capacitance formed between polysilicon 502 and n-well 520. The parasitic capacitance is distributed along the length of polysilicon 502 and the underlying n-well 520, but can be mathematically modeled as two capacitors C with the same capacitance, as shown at opposite ends of polysilicon 502.

[0034] Figure 6 The diagram illustrates two polysilicon-based unit resistors connected in series. As shown, contact 530 of one resistor is connected to contact 535 of the other. The effective resistance between contact 535 on the polysilicon-based resistor on the right and contact 530 on the polysilicon-based resistor on the left is 2R. Capacitors 560 and 562 represent parasitic capacitance C; they are connected in parallel via conductor 558, and both n-wells 520 are biased at the same voltage PBKG.

[0035] Figure 7 The circuit model 715 of the two binary or temperature segments 210 and 240 of the DAC 108 is shown. Circuit model 715 includes the parasitic capacitance of capacitor C1. Each segment includes two unit resistors R in series, as described above. Capacitor C is connected between each end of resistor R and the PBKG voltage. Reference numerals 702 and 704 indicate 2C capacitors, which are represented as described above regarding... Figure 6 The parallel combination of capacitors 560 and 562 between the adjacent resistors.

[0036] Circuit model 715 in Figure 7The diagram has been redrawn to represent 720 to more easily illustrate the distributed RC network of the DAC. Due to the parasitic capacitance of the unit resistor R based on polysilicon, the DAC's settling time is a function of the product of R and C.

[0037] Figure 8 The diagram illustrates the DAC 808, whose architecture is similar to... Figure 2 However, the electrical contact 540 of each unit resistor R (which connects to the n-well 520 and thus to one terminal of the capacitor C) is connected to the corresponding switch SW instead of to the PBKG voltage. Through the switch SW of a given segment 810 or 840, the electrical contact 540 of the unit resistor is connected to VREF or VGND depending on the state of the switch. As shown, resistors between binary segments 810 and between binary segments 810 and temperature segment 840 have electrical contacts 540 connected to the PBKG. Figure 8 In the DAC 808, the unit resistor is placed in a well separate from the resistor connecting the adjacent binary segment 810 and the resistor between the binary and temperature segments, as well as in a well separate from the wells of other structures in the IC.

[0038] As a result of connecting electrical contact 540 to switch SW, the circuit model from Figure 7 The model 715 / 720 shown is changed to Figure 9 Models 910 / 920 / 930 are shown. Due to the connection of electrical contact 540 to switch SW, Figure 7 Capacitor 770 in Figure 8 The middle is short-circuited, therefore in Figure 9 Not shown in the image. Figure 9 A 2C capacitor in parallel is connected across the upper resistor in each segment, as better illustrated in circuit model 920. A lower capacitor C at the bottom of each segment is connected across a unit resistor in series, as better illustrated in circuit model 920. Each segment comprises two unit resistors R connected in series, a capacitor C across the two unit resistors, and a 2C capacitor across one of the unit resistors. Each segment has the same impedance and is represented as impedance Z in circuit model 930. Circuit model 930 illustrates that the temperature segment is a voltage divider and the voltage at node 931 between impedance Z is VREF / 2.

[0039] The resistors used in the DAC include n-wells 520, which are separate from the n-wells used to connect adjacent binary segments 810 and between binary and temperature segments, and also separate from the wells of other structures in the IC. By using separate n-wells and connecting these wells to the switching nodes, each such temperature branch includes a matching impedance network, as described above, when a specific temperature branch is turned on. Figure 9As explained, any changes in the switch state will be independent of R and C, resulting in a greater... Figure 2 The example shows a faster stabilization time.

[0040] Refer again Figure 2 Each switch SW connects its segment to either VREF or VGND. Each switch SW can be implemented as a pair of transistors, such as a p-type metal-oxide-semiconductor field-effect transistor (PMOS) and an n-type metal-oxide-semiconductor field-effect transistor (NMOS). The PMOS transistor is connected to VREF, which, when turned on, connects to a resistor in series. The NMOS transistor is connected to VGND, which, when turned on, connects to a resistor in series. Generally, the on-resistance of the PMOS transistor on the IC tracks consistently between them in the face of changes in temperature or VREF voltage. Similarly, the on-resistance of the NMOS transistor on the IC also tracks consistently between them.

[0041] The on-resistance between PMOS and NMOS transistors will not cross process and temperature tracking constraints. It can be seen that the INL due to switching resistor mismatch is equal to:

[0042] (1)

[0043] In equation (1), R' is the resistance over a single temperature range (e.g., 2R in the example described herein), INL SWITCH The INL contribution is due to switching resistor mismatch. One way to reduce INL due to switching resistor mismatch is to choose a larger resistor for the unit resistor R. However, a larger resistor leads to a longer settling time, and the value of R is usually determined by the stability requirements of the DAC. Alternatively, INL can be reduced by increasing the size of the PMOS and NMOS transistors. SWITCH This results in lower on-resistance values ​​for them. However, unfortunately, increasing the transistor size leads to a larger DAC area.

[0044] Figure 10 and Figure 11 Different mechanisms for reducing INL are described. Figure 10 The diagram illustrates a single segment 1010 (e.g., a binary segment or a temperature segment). Resistor R represents the resistance of the segment that achieves the target settling time t. That is, when switch 1012 is configured to connect resistor R to VREF, the voltage at node 1015 should stabilize within time t due to the sudden change from VGND to VREF.

[0045] Figure 11One embodiment is shown in which resistor R is replaced by two resistors R2 and R3 coupled in parallel via switch 1111. R2 can be implemented as a polysilicon-based resistor, for example... Figure 5 The resistor R3 shown can be implemented as a polysilicon-based resistor with a relatively high sheet resistivity and a relatively small width (compared to resistor R2). The settling time t (also known as the operating time) is divided into two parts—t1 and t2. During t1, switch 1111 is closed, and the effective resistance of the parallel combination of R2 and R3 is less than that of R2 or R3, respectively, and less than R. During t2, switch 1111 is open, and only resistor R2, which is greater than R, receives current. With this arrangement, the settling time is generally constant (t) because R2||R3 (less than R) is used during t1, while R2 is used during t2. Eventual stability occurs at R2 (greater than R), therefore, according to equation (1) above, the larger R' is, the smaller INL is.

[0046] The equation below illustrates an example of how to choose the values ​​of resistors R2 and R3. Switch 1111 is on for time t1, and the parallel combination of R2 and R3 (effective resistance R1) is coupled to VREF via switch 1012. The effective body capacitance of R1 (e.g., as shown in the figure) Figure 5 The parasitic capacitance of R2 shown in the diagram is C. The charging equation during time interval t1 is:

[0047] (2)

[0048] Where V1 is the intermediate voltage value (i.e., the voltage across R1 at the end of time t1), and Vx is the final voltage at the end of time period t2.

[0049] After time tl, switch 1111 is turned off, and the resistance value becomes R2. According to the following equation, final stability occurs from the intermediate voltage V1 to the final voltage value (VF):

[0050] (3)

[0051] (4)

[0052] (5)

[0053] (6)

[0054] According to equation (6), the target stable value of R can be obtained at time t1+t2 by using resistor R1 at time t1 and resistor R2 at time t2. For example, assume that the target stable time requires a resistor of 60KΩ. Resistor R2 can be a 100KΩ resistor, and R3 can be another 100KΩ resistor. When switch 1111 is closed, the effective resistance of the parallel combination of R2 and R3 is 50KΩ. If switch 1111 is turned on for 2t / 3 and turned off for t / 3, the stable time will be the same as when using a single 60KΩ resistor over the entire time period t. Because the resistance at the end of time period t is 100KΩ, INL will decrease without increasing the size of the transistor used for switch 1012.

[0055] In one example Figure 2 Each unit resistor R in the equation can be like... Figure 11 The implementation is shown in the example. In another example, as... Figure 12 As illustrated, switch 111 and resistor R5 can be connected across each pair of series-connected unit resistors R4, rather than across each individual unit resistor. As mentioned above, the resistance of each resistor R4 is greater than... Figure 2 The effective parallel resistance of R, 2*R4 and R5 in the figure is less than R.

[0056] The term "coupled" is used throughout this specification. This term can encompass connection, communication, or signaling paths that achieve a functional relationship consistent with the description of this disclosure. For example, if device A generates a signal to control device B to perform an action, in a first example, device A is coupled to device B; or in a second example, if intermediate component C does not significantly alter the functional relationship between device A and device B, device A is coupled to device B via intermediate component C, such that device B is controlled by device A via a control signal generated by device A.

Claims

1. An analog-to-digital converter (ADC), comprising: A digital-to-analog converter (DAC) includes a resistor network comprising a first segment and a second segment. The first segment includes a first switch coupled between a first power supply voltage node and a first set of resistors, and the second segment includes a second switch coupled between the first power supply voltage node and the second set of resistors. The first segment includes a third switch coupled in series with the second resistor, the series combination of the third switch and the second resistor being coupled in parallel with at least one resistor in the first group of resistors; and The second segment includes a fourth switch coupled in series with a third resistor, and the series combination of the fourth switch and the third resistor is coupled in parallel with at least one resistor in the second group of resistors.

2. The ADC of claim 1, wherein the series combination of the third switch and the second resistor is coupled in parallel with the series combination of at least two resistors in the first group of resistors, and wherein the series combination of the fourth switch and the third resistor is coupled in parallel with the series combination of at least two resistors in the second group of resistors.

3. The ADC of claim 1, wherein the first segment includes a binary segment and the second segment includes a temperature segment, and the resistor network further includes a third set of resistors coupled between the binary segment and the temperature segment, the third set of resistors including a fourth and a fifth resistor coupled in series, a sixth and a seventh resistor coupled in series, the series combination of the fourth and the fifth resistors being coupled in parallel with the series combination of the sixth and the seventh resistors.

4. The ADC of claim 1, wherein the second set of resistors comprises: A fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor are connected in series between the second switch and the output node of the DAC; as well as The eighth, ninth, tenth, and eleventh resistors are coupled in series, and the series combination of the fourth to the seventh resistors is coupled in parallel with the series combination of the eighth to the eleventh resistors.

5. The ADC of claim 4, wherein the first set of resistors comprises fewer resistors than the second set of resistors.

6. The ADC of claim 1, wherein each resistor in the first group of resistors comprises: Polycrystalline silicon resistors formed on n-wells; p-doped substrate; An n-doped region having a higher doping concentration than the n-well; An electrical connection to the n-doped region, the electrical connection being coupled to the first switch.

7. The ADC of claim 1 further includes a comparator coupled to the output node of the DAC, and includes a register coupled to the output of the comparator and the input of the DAC.

8. An analog-to-digital converter, i.e., an ADC, comprising: A digital-to-analog converter (DAC) includes a resistor network comprising multiple binary segments and multiple temperature segments. The first temperature range includes a first switch and a unit resistor pair series coupled between the first switch and the output node of the DAC; as well as The second temperature range includes a second switch and more than two unit resistors coupled between the second switch and the output node.

9. The ADC of claim 8, wherein the second temperature band comprises eight unit resistors coupled between the second switch and the output node.

10. The ADC of claim 9, wherein four of the eight unit resistors are coupled in series, the other four of the eight unit resistors are also coupled in series, and two unit resistors coupled in series are coupled in parallel to each other.

11. The ADC of claim 8, wherein the first temperature range includes a third switch coupled in series with a second resistor, the series combination of the third switch and the second resistor being coupled in parallel with at least one of the corresponding unit resistor pairs of the first temperature range.

12. The ADC of claim 9, wherein the second temperature segment includes a fourth switch coupled in series with a third resistor, the series combination of the fourth switch and the third resistor being coupled in parallel with at least one of the unit resistors of the second temperature segment.

13. The ADC of claim 8, wherein the first binary segment of the plurality of binary segments comprises a plurality of unit resistors and a third switch coupled in series with a second resistor, the series combination of the third switch and the second resistor being coupled in parallel with at least one of the plurality of unit resistors of the first binary segment.

14. The ADC of claim 8, wherein each unit resistor in the first temperature range and the second temperature range comprises: Polycrystalline silicon resistors formed on n-wells; p-doped substrate; An n-doped region having a higher doping concentration than the n-well; An electrical connection to the n-doped region, the electrical connection being coupled to a corresponding first switch or second switch.

15. An analog-to-digital converter, i.e., an ADC, comprising: A digital-to-analog converter (DAC) includes a resistor network comprising multiple segments, including a first segment comprising a first switch and a first set of resistors, wherein the first switch is coupled between a power supply voltage node and the first set of resistors. The first segment further includes a second switch coupled in series with the second resistor, the series combination of the second switch and the second resistor being coupled in parallel with at least one resistor in the first group of resistors, and wherein when the first switch is controlled to apply a power supply voltage to the first group of resistors during an operating time period, the second switch is configured to close for a period less than the operating time period and then turn off for the remainder of the operating time period.

16. The ADC of claim 15, wherein the series combination of the second switch and the second resistor is coupled in parallel to the series combination of at least two resistors in the first group of resistors.

17. The ADC of claim 15, wherein the plurality of segments includes a second segment, the second segment including a third switch and a second set of resistors, the third switch being coupled between the power supply voltage node and the second set of resistors, and the resistor network further including a third set of resistors coupled between the first segment and the second segment, the third set of resistors including a fourth and a fifth resistor coupled in series, a sixth and a seventh resistor coupled in series, and the series combination of the fourth and the fifth resistors being coupled in parallel with the series combination of the sixth and the seventh resistors.

18. The ADC of claim 17, wherein the first set of resistors comprises more resistors than the second set of resistors, and the first set of resistors has the same effective resistance as the second set of resistors.

19. The ADC of claim 15, wherein the first set of resistors comprises: A fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor are connected in series between the first switch and the output node of the DAC; as well as The eighth, ninth, tenth, and eleventh resistors are coupled in series, and the series combination of the fourth to the seventh resistors is coupled in parallel with the series combination of the eighth to the eleventh resistors.

20. The ADC of claim 15, wherein each resistor in the first group of resistors comprises: Polycrystalline silicon resistors formed on n-wells; p-doped substrate; An n-doped region having a higher doping concentration than the n-well; An electrical connection to the n-doped region, the electrical connection being coupled to the first switch.

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