Systems, methods, and apparatus for high speed input / output tolerance testing

Abstract

Systems, methods, and apparatus for high-speed input / output tolerance testing are disclosed. These systems, apparatus, and methods for high-speed I / O tolerance testing can screen high-volume pre-production and production components and identify situations where electrical characteristics have changed sufficiently to affect operation. The disclosed tolerance testers are less costly, easier to use, and faster than conventional BERTs and oscilloscopes, and can operate on a full multi-channel I / O link under standard operating conditions with full load and crosstalk. The tolerance testers simultaneously evaluate the electrical receiver tolerance of the operating multi-channel high-speed I / O link of the device under test in either or both directions. In a particular form, embodiments of the tolerance tester can be implemented as an insert card tolerance tester to test the motherboard slot of the motherboard under test, or as a motherboard with slots to test insert cards.

Description

[0001] priority

[0002] This disclosure is a continuation-in-part of U.S. Patent Application No. 16 / 778,249, filed January 31, 2020, entitled "Systems, methods, and devices for high-speed input / output tolerance testing," and is also a continuation-in-part of U.S. Patent Application No. 16 / 778,262, filed January 31, 2020, entitled "Systems, methods, and devices for high-speed input / output tolerance testing," and also claims U.S. Patent Application No. 16 / 778,262, filed November 9, 2020, entitled "Systems, methods, and devices for high-speed input / output tolerance testing." The rights to U.S. Provisional Application No. 63 / 111,533 entitled “MARGINTESTING” are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to test and measurement systems, and more particularly to systems and methods for performing high-speed electrical tolerance tests on electrical devices under test (DUTs). Attached Figure Description

[0004] The components in the accompanying drawings are not necessarily proportional to each other. The same reference numerals are used throughout several views to indicate the corresponding parts.

[0005] Figure 1 This is a general block view of an example environment illustrating an embodiment of a system, apparatus, and method for high-speed input / output (I / O) tolerance testing, according to an example embodiment.

[0006] Figure 2 This is a block diagram illustrating an example-specific insert card tolerance tester according to an example embodiment, which conforms to the Peripheral Component Interconnect PCI Express high-speed serial computer expansion bus standard to perform tolerance testing on PCI Express (Fast PCI) motherboard slots.

[0007] Figure 3This is a block diagram illustrating a motherboard with slots conforming to the PCI Express high-speed serial computer expansion bus standard for tolerance testing of PCI Express insert cards, according to an example embodiment.

[0008] Figure 4 This is a diagram showing the results of an example tolerance test performed on a device under test (DUT) by a high-speed I / O tolerance tester according to an example embodiment, and a graph identifying possible DUT assembly or manufacturing problems based on the results of the tolerance test.

[0009] Figure 5 This is a diagram showing the results of another example tolerance test performed by a high-speed I / O tolerance tester according to an example embodiment, and a graph identifying possible DUT assembly or manufacturing problems based on the tolerance test results.

[0010] Figure 6 This is a block diagram illustrating a general-purpose tolerance tester with multiple interfaces according to an example embodiment. The multiple interfaces are configured to be cable-connected to at least one test fixture to evaluate the electrical tolerance of the DUT's multi-channel high-speed I / O link in both the transmit (Tx) and receive (Rx) directions.

[0011] Figure 7 This is a lower-level block diagram of a tolerance tester for testing the electrical tolerance of a multi-channel high-speed I / O link of a DUT in both the Tx and Rx directions, according to an example embodiment.

[0012] Figure 8 This is a block diagram of an example field-programmable gate array (FPGA) configured according to an example embodiment, which can be used in the controller of a tolerance tester for testing the electrical tolerance of a multi-channel high-speed I / O link of a DUT in both the Tx and Rx directions.

[0013] Figure 9 This is a block diagram of example output drive options for an FPGA according to an example embodiment, which can be used in the controller of a tolerance tester for testing the electrical tolerance of a multi-channel high-speed I / O link of a DUT in the Tx direction.

[0014] Figure 10 This is a flowchart of an example method for performing tolerance testing on a DUT according to an example embodiment.

[0015] Figure 11 This is a flowchart of an example method, according to an example embodiment, for identifying potential DUT assembly or manufacturing problems based on tolerance testing of the electrical tolerances of the multi-channel high-speed I / O links of the DUT in both the Tx and Rx directions.

[0016] Figure 12 This is a flowchart of an example method, according to an example embodiment, for initiating an assessment of electrical tolerance performed by a tolerance tester based on user-selectable options.

[0017] Figure 13 This is a flowchart of an example method for providing a calibration tolerance tester according to an example embodiment.

[0018] Figure 14 This is a flowchart of an example method for configuring a DUT for running tolerance tests, according to an example embodiment.

[0019] Figure 15 This is another lower-level block diagram of a tolerance tester for testing the electrical tolerance of a multi-channel high-speed I / O link of a DUT in both the Tx and Rx directions, according to an example embodiment.

[0020] Figure 16A and Figure 16B The diagrams illustrate the tolerances for the link training state in the transmitting and receiving directions, respectively. Detailed Implementation

[0021] Designers and manufacturers of electrical equipment require testing and measuring instruments and appropriate testing procedures to ensure that the equipment functions correctly. Such testing can be performed during the engineering characterization phase of designing new equipment, to compare, for example, the actual electrical performance of the equipment with simulated performance to ensure that the equipment performs as designed. Alternatively, such testing can be performed in a manufacturing environment after the engineering design is completed to identify any manufacturing defects in each piece of equipment produced.

[0022] Many electrical devices are designed to include high-speed I / O signal paths or buses. For example, modern personal computer (PC) motherboards and other types of electrical devices often include high-speed serial PCI Express (also simply PCIe or PCI-e) buses, which are buses that conform to and implement the PCI Express high-speed serial computer extension bus standard. The format specifications for the PCI Express standard are maintained and developed by the PCI Special Interest Group (PCI-SIG). These buses are typically used for communication between the motherboard and insert cards / daughter cards plugged into PCIe connector slots or ports on the motherboard. Many other electrical devices besides the motherboard also use PCIe buses and connectors for high-speed I / O. Generation 4 (Gen4 or version 4) PCIe devices can achieve bandwidths of up to 16 gigabits per second (GT / s). Generation 5 (Gen5 or version 5) PCIe devices can achieve bandwidths of up to 32 GT / s.

[0023] PCIe devices communicate via logical connections known as interconnects or links. A link is a point-to-point communication channel between two PCIe ports, allowing simultaneous bidirectional traffic. At the physical layer, a link consists of one or more channels. Low-speed PCIe devices use single-channel (x1) links, while high-speed PCIe devices, such as graphics adapters, typically use much wider and faster 16-channel (x16) links. A channel consists of two differential signaling pairs, one for receiving data and the other for transmitting. Therefore, each channel consists of four wires or signal traces. Typically, a Bit Error Rate Tester (BERT) and / or a high-speed signal generator and an oscilloscope (oscilloscope) are used to test the performance of the channels of a PCIe device.

[0024] In the engineering bench testing and / or engineering characterization phase of printed circuit board (PCB) development, high-speed routing of the board design (e.g., PCIe interconnects) is simulated, or a design “recipe” or benchmark design is followed. Pre-production board samples are then typically built and tested. However, testing every board sample and every channel for all high-speed I / O using bit error rate test instruments (BERTs) and oscilloscopes is typically impractical due to cost, time, and complexity constraints. In particular, traditional BERTs and oscilloscopes used for testing high-speed I / O standards such as PCIe continue to increase in cost and complexity with increasing data rates. A single Tx and Rx test station for testing a single PCIe channel at a time can cost over a million dollars. These instruments are also difficult to use for traditional Tx and Rx testing and calibration, as well as for expert (often PhD-level) users, and require significant time to ensure correct measurements and keep the instruments in good working order. As a result of these constraints, traditional BERTs and oscilloscopes are rarely used in batch electrical testing of pre-production silicon, boards, PCBs, and cables, and are typically not used at all in production testing.

[0025] However, with the increasing data rates of PCI Express 5.0 I / O links, such as at 32.0 GT / s, the risk that even small or minor issues can significantly impact the performance of these I / O links increases, and the importance of conducting tests to flag electrical performance issues on each pre-production sample, port, and channel to prevent problems before production, and testing the electrical performance on each unit on the production line to catch production-related issues (defective parts, etc.) before they cause customer problems and returns, increases. Furthermore, conventional BERTs and oscilloscopes only allow testing on a single channel at a time, so testing occurs in an environment different from the actual operation of these I / O links—which typically form multi-channel links and may suffer from significant crosstalk and loading issues during real operation—and these problems may be missed even when conventional BERT and oscilloscope testing does / may occur. Similarly, in manufacturing test environments, when assembling and testing multiple PCBs of a given design, production lines typically do not use BERTs and oscilloscopes for high-speed I / O testing due to cost, time, and complexity constraints.

[0026] Therefore, there is a growing need for new instruments capable of screening high-volume pre-production and production parts and identifying situations where electrical characteristics have changed significantly enough to affect operation. An instrument is most valuable if it is low-cost, very easy to use, and very fast compared to conventional BERTs and oscilloscopes, and can operate all multi-channel I / O links at full load and with crosstalk under standard operating conditions. In summary, knowing the electrical tolerances (statistically effective operating tolerances) for each high-speed I / O channel in each direction is valuable in increasing the likelihood of discovering problems across all production samples in both design (e.g., each channel across all production samples) and assembly (e.g., a specific board / channel instance).

[0027] Some conventional solutions rely solely on functional testing as the best approximation (e.g., simply plugging it into a "gold" or benchmark device and having the test link run at full speed). Other companies use on-die electrical tolerances in silicon for their boards, but this only informs them in one direction and is not calibrated / characterized like test instruments, leaving a significant amount of work to process and understand cell-to-cell variations in the insert card—which is why they choose the insert card for this purpose.

[0028] Systems, apparatus, and methods for high-speed input / output (I / O) tolerance testing that address the technical problems described above are disclosed herein.

[0029] Figure 1This is a general block diagram illustrating an example environment for implementing an embodiment of a system, apparatus, and method for high-speed I / O tolerance testing, according to an example embodiment. In one embodiment, a tolerance tester 102 is shown, which evaluates the electrical receiver tolerance of an example DUT 104's operational multi-channel high-speed I / O link 110 in either or both of the Tx and Rx directions. Figure 1 The tolerance tester 102 represents one or more embodiments of the tolerance tester disclosed herein.

[0030] The tolerance tester 102 can be coupled to a test station, PC, terminal, or other display device 106, which can process, reproduce, and / or present an eye pattern display or data eye diagram 108 representing various aspects of the multi-channel high-speed I / O link 110. In some embodiments, the test station, PC, terminal, or other display device 106 can be integrated with or as part of the tolerance tester 102. The eye pattern display or data eye diagram 108 is a representation of a high-speed digital signal that allows key parameters of the signal's electrical quality to be quickly visualized and determined, and therefore the data derived from it can be used to determine the statistically valid operating tolerances of the DUT. The eye pattern display or data eye diagram 108 is constructed from a digital waveform by folding portions of the waveform corresponding to each individual bit into a single graphic, having amplitude on the vertical axis and time on the horizontal axis. Signal amplitude is on the vertical axis and time is on the horizontal axis. By repeating this construction over many samples of the waveform, the resulting graphic will represent the average statistics of the signal and will resemble an eye. The eye opening corresponds to one bit period and is typically referred to as the cell spacing (UI) width of the eye pattern display or data eye diagram 108. The bit period is a measurement of the horizontal opening of the eye diagram at the eye crossover point and is usually measured in picoseconds for high-speed digital signals (i.e., 200 ps for a 5 Gbps signal). The data rate is the reciprocal of the bit period (1 / bit period). When describing an eye diagram, the bit period is usually referred to as the cell spacing (UI). The advantage of using UI on the horizontal axis instead of actual time is that it is normalized and eye diagrams with different data rates can be easily compared. The eye width is a measurement of the horizontal opening of the eye diagram. It is calculated by measuring the difference between the statistical averages of the eye crossover points. The rise time is a measurement of the average transition time of the data on the upward slope of the eye diagram. Typically, it is measured at the 20% and 80% levels of the slope or the 10% and 90% levels. The fall time is a measurement of the average transition time of the data on the downward slope of the eye diagram. Typically, measurements are taken at the 20% and 80% levels of the ramp, or at the 10% and 90% levels. Jitter is the time deviation from the ideal timing of data bit events and is an important characteristic of high-speed digital data signals. To calculate jitter, the time deviation of the transition between the rising and falling edges of the eye diagram at the crossover point is measured. Fluctuations can be random and / or deterministic. The time histogram of the deviation can be analyzed to determine the amount of jitter. Peak-to-peak (pp) jitter is defined as the full width of the histogram, meaning that all data points are present. Root mean square (RMS) jitter is defined as the standard deviation of the histogram. The unit for jitter measurement on high-speed digital signals is typically measured in picoseconds.

[0031] Embodiments of the tolerance tester 102 can take at least two forms: technology-specific and general-purpose. The tolerance tester 102 can be used with any high-speed I / O protocol link of any link width (number of channels) and using any form of high-speed differential signaling, including, but not limited to, Non-Return-to-Zero (NRZ), Pulse Amplitude Modulation-3 (PAM-3), and Pulse Amplitude Modulation-4 (PAM-4). For a specific example embodiment used for testing, PCI Express will be used. However, different high-speed serial bus standards, hardware, and protocols can be used.

[0032] Figure 2 This is a block diagram illustrating an example-specific insert card tolerance tester 202 according to an example embodiment, which conforms to the PCI Express high-speed serial computer expansion bus standard to perform tolerance testing on a PCI Express motherboard slot 206.

[0033] In a specific technical embodiment, the tolerance tester can be implemented as a PCI Express insert card tolerance tester 202 to test the PCI Express motherboard slot 206 of the motherboard 204 under test. For example, the PCI Express insert card tolerance tester 202 may be a PCI Express x16 card electromechanical specification (CEM) form factor insert card. In another embodiment of the specific technical embodiment, the tolerance tester can be implemented as a motherboard having (multiple) PCI Express slots to test PCI Express insert cards (which in...) Figure 3 (as shown in the image).

[0034] The PCI Express insert card tolerance tester 202 may have a form factor for a standard PCI Express compliant insert card for a specific PCI Express form factor (e.g., CEM or M.2 (formerly known as Next Generation Form Factor (NGFF) or U.2 (formerly known as SFF-8639))). The PCI Express insert card tolerance tester 202 may include one or more printed circuit boards (PCBs) (such as PCB 212) and one or more components implementing PCI Express compliant physical and logical link layers for each channel. The PCI Express insert card tolerance tester 202 may include multiple interfaces (such as connector 208) coupled to PCB 212 and a controller 210. As those skilled in the art will understand, the controller 210 is not limited to a single controller but may include one or more controllers working in concert. Such an interface may include multiple connectors 208 that connect to the motherboard slot 206 and a tolerance tester transmitter, which, under the control of the controller 210, optionally includes the ability to inject controlled noise, for example, through voltage swings and sinusoidal jitter, so that the expected eye tolerance at the receiver of the motherboard under test 204 can be varied to a specific target for timing or voltage tolerance without requiring software running on the motherboard under test 204. The controller 210 may also be coupled to a memory 214, which may store instructions and other data that the controller 210 can read, use, and / or execute to implement the functions described herein.

[0035] Various embodiments of the tolerance tester 102 (including the technology-specific PCI Express insert card tolerance tester 202, the technology-specific motherboard tolerance tester 302, and the general-purpose tolerance tester 602) may or may not have noise injection. For cost-conscious production testing, embodiments without noise injection may be more attractive. A tolerance tester receiver in a physical layer compliant implementation may include the ability to perform tolerance settings on the link as defined in the PCIExpress 4.0 / 5.0 lane tolerance specification, but may also include additional and more complex on-die tolerance setting capabilities. In one embodiment, the tolerance tester receiver can measure eye tolerance by moving a separate error detector and comparing it against a data sampler for mismatch. In one implementation, the controller 210—which causes the tolerance tester 102 (including the technology-specific PCI Express insert card tolerance tester 202, the technology-specific motherboard tolerance tester 302, and the general-purpose tolerance tester 602) to perform the functions described herein—may be implemented using a field-programmable gate array (FPGA) and FPGA I / O, which in Figures 7 to 9This is illustrated in further detail below. However, other combinations of configurable controller hardware, firmware, and / or software can be used.

[0036] Figure 3 This is a block diagram illustrating an example technology-specific motherboard tolerance tester 302 with slots conforming to the PCI Express high-speed serial computer expansion bus standard for tolerance testing of PCI Express insert cards, according to an example embodiment.

[0037] Motherboard tolerance tester 302 is another example of an embodiment of a particular technology of the tolerance tester 102 disclosed herein, which is implemented as a motherboard tolerance tester 302 having one or more PCI Express slots 306 to test, for example, Figure 3 The PCIe x16 insertion card DUT 304 shown is a PCI Express insertion card. The motherboard tolerance tester 302 may include multiple interfaces (e.g., one or more PCI Express slots 306) coupled to the PCB 312 and controller 210. For example, such interfaces may include multiple or more PCI Express slots 306 into which the PCIe x16 insertion card DUT 304 can be inserted for testing. The tolerance tester transmitter is controlled by controller 210 and may optionally include the ability to inject controlled noise, for example, through voltage swings and sinusoidal jitter (see below and regarding...). Figure 8 and Figure 9(Further description) to enable the eye tolerance expected at the receiver of the PCIe x16 insert card DUT 304 to be varied for a specific target of timing or voltage tolerance without requiring software running on the PCIe x16 insert card DUT 304. For example, controller 210 can be configured to evaluate the electrical tolerance of a single-channel or multi-channel high-speed I / O link by at least being configured to inject a reduction in eye width aperture (or implement other eye width aperture reduction methods) by injecting jitter on a tolerance test transmitter, the jitter injection being optionally applied simultaneously on all channels of the single-channel or multi-channel high-speed I / O link or applied independently for each channel of the single-channel or multi-channel high-speed I / O link. Additionally, controller 210 can be configured to evaluate the electrical tolerance of a single-channel or multi-channel high-speed I / O link by at least injecting a reduction in eye height aperture (or implementing other eye height aperture reduction methods) by injecting noise into the tolerance test transmitter. The noise injection can be selectively applied simultaneously to all channels of the single-channel or multi-channel high-speed I / O link or applied independently for each channel of the single-channel or multi-channel high-speed I / O link. Controller 210 can also be configured to evaluate the electrical tolerance of a single-channel or multi-channel high-speed I / O link by at least introducing varying channel-to-channel offsets across multiple channels.

[0038] The controller 210 may also be coupled to a memory 214, which may store instructions and other data that the controller 210 may read, use and / or execute to implement the functions described herein.

[0039] Durability and insertion count are important issues for specific technology embodiments of tolerance tester 102 (including specific technology PCI Express card tolerance tester 202 and specific technology motherboard tolerance tester 302). Therefore, PCBs 212 and 312 can be implemented and characterized using adapters configured to be replaced at low cost when worn out without replacing the rest of the tolerance test unit. For example, a replaceable adapter can be coupled to one or more PCI Express slots 306 and / or connectors 208 and configured to wear out after a certain amount of use. Once the adapter wears out, it can be replaced without replacing the rest of the PCI Express card tolerance tester 202 or motherboard tolerance tester 302, as applicable.

[0040] Figure 4This is a diagram 402 illustrating the results of an example tolerance test performed on several Devices Under Test (DUTs) by a high-speed I / O tolerance tester according to an example embodiment, and identifying possible DUT assembly or manufacturing problems based on the tolerance test results. In the example embodiment, the tolerance test may include: evaluating timing eye width tolerance for each of the multiple DUTs by the tolerance tester 102 for each high-speed input / output (I / O) channel of the multi-channel high-speed I / O link of that DUT in either or both of the Tx and Rx directions. The tolerance tester 102 may then detect timing eye width tolerance measurements for multiple of the multiple DUTs where each measurement is below a predetermined threshold for different channels across the multiple DUTs. Possible DUT assembly or manufacturing problems may then be detected (visually or automatically by the tolerance tester 102) based on the detection of timing eye width tolerance measurements for the multiple DUTs where each measurement is below a predetermined threshold for different channels across the multiple DUTs.

[0041] As an example, in one embodiment, such as in Figure 2 The insert card tolerance tester 202 shown can be used for tabletop testing / characterizing pre-production samples of motherboards with one PCIe x8 slot. The example test procedure below can be performed using the insert card tolerance tester 202 with E-6 timing eye width tolerance (left + right) measured simultaneously for the slot on each channel for a few milliseconds. This example includes timing for simplicity only, but other embodiments may include other measurements. Each measurement in this example is performed three times. However, in various embodiments, this can be user-programmable. The measurements shown in Figure 402 are performed at the tolerance tester receiver and at the motherboard DUT receiver. The measurements performed at the motherboard DUT receiver can be performed in two ways. The first way can be using tolerance tester jitter (Sj) and voltage swing sweep. The second way can be using on-die tolerance testing at the motherboard receiver. For example, die-on tolerance testing at the motherboard receiver can be controlled by controller 210 of insert card tolerance tester 202, and run via software on a bootable driver connected to the motherboard DUT or the basic input / output system (BIOS) software on the motherboard DUT for the supported speeds. In this example, the measurement is performed at 16GT / s, but this can vary and can be user-configurable.

[0042] The example test procedure above can produce example results for the average tolerance at the test receiver, as shown in Figure 402. As illustrated in Figure 402, a consistent low tolerance across all five DUTs (DUT#1 to DUT#5) on channel 2 can be an indicator of potential design problems. In contrast, low tolerances on DUT#1 on channel 4, on DUT#3 on channel 0, and on DUT#4 on channel 6 can be indicators of potential assembly or manufacturing problems on these particular channels of these particular DUTs.

[0043] Figure 5 This is a diagram showing the results of another example tolerance test performed by a high-speed I / O tolerance tester according to an example embodiment, and a graph identifying possible DUT assembly or manufacturing problems based on the tolerance test results.

[0044] exist Figure 5 The example results for voltage swing and average Sj tolerance at the DUT receiver shown in Figure 502 also reveal similar indicators of potential design and / or assembly problems: as illustrated in Figure 502, a consistent low tolerance across all five DUTs (DUT#1 to DUT#5) on channel 1 can be an indicator of potential design problems. In contrast, low tolerances on DUT#1 on channel 0, on DUT#1 on channel 5, and on DUT#2 on channel 7 can be indicators of potential assembly or manufacturing problems on these specific channels of these specific DUTs.

[0045] Additional features of embodiments of the disclosed technology may include the following functions, which may be performed under the control of controller 210 (e.g., executing instructions according to the configured FPGA and / or executing instructions read from another non-transitory computer-readable storage medium): selecting one or more different high-speed I / O protocols for performing tolerance testing of a multi-channel high-speed I / O link based on the DUT; simultaneously testing multiple ports of the DUT using a hybrid protocol; outputting a tolerance tester to operate on tolerances to variations on any number of tolerance test runs on the multi-channel high-speed I / O link; and implementing a fixed Tx equalization (EQ) on the DUT to test how much tolerance variation is due to Tx. Due to EQ training variations; using a fixed continuous-time linear equalization (CTLE) in the receiver of the tolerance tester to test the impact of receiver equalization on the tolerance of the DUT's multi-channel high-speed I / O link; using decision feedback equalization (DFE) in the receiver of the tolerance tester to test the impact of receiver equalization on the tolerance of the DUT's multi-channel high-speed I / O link; calculating the expected tolerance for the tolerance tester based on the target channel; automatically generating debugging information when low tolerance is detected as a result of evaluating the electrical tolerance of the multi-channel high-speed I / O link; switching to use a variable inter-symbol interference (ISI) source to find out how much ISI causes channel failure of the multi-channel high-speed I / O link; testing each channel individually to identify the amount of tolerance loss due to crosstalk of the DUT's multi-channel high-speed I / O link; disabling the DFE in the receiver of the tolerance tester to evaluate the tolerance with and without DFE, as well as the nonlinear discontinuities associated with the multi-channel high-speed I / O link in each channel; showing the baseline receiver and typical... The expected tolerance in the case of a channel allows marking below-expected tolerance even when all channels of a multi-channel high-speed I / O link across one or more DUTs are consistently below the expected tolerance; selection from multiple speeds of the multi-channel high-speed I / O link for which electrical tolerance assessment is performed; using protocol-specific knowledge, the tolerance tester infers when an error occurs at the receiver of the DUT based on the flow traveling in opposite directions on the multi-channel high-speed I / O link, so that the tolerance tester can perform tolerance testing on the production line without software on the DUT; automatic capture of time domain reflectometer readings (TDR) of low-tolerance channels detected as a result of assessing the electrical tolerance of the multi-channel high-speed I / O link; automatic connection to an oscilloscope to automatically capture digitized waveforms when low tolerance is detected as a result of assessing the electrical tolerance of the multi-channel high-speed I / O link; and provision of software plug-ins to configure one or more user-selectable options for the DUT by configuring the DUT silicon to implement one or more user-selectable options. Under the control of controller 210, some or all of the above functions can also be provided as user-selectable options for operating tolerance tester 102.

[0046] Additional features of embodiments of the disclosed technology may include triggering functions that can be executed under the control of controller 210. That is, the tolerance tester 102 may include programmable trigger inputs and / or programmable trigger outputs, meaning that a signal received at controller 210 may cause a test to be performed or a signal may be generated at controller 210 if a specific event occurs during testing. In some examples, programmable triggering may be configurable via user-selectable options. For example, as mentioned above, controller 210 may automatically capture time-domain reflectometer readings (TDRs) of low-tolerance channels detected as a result of evaluating the electrical tolerance of a multi-channel high-speed I / O link, and / or trigger automatic connection to an oscilloscope to automatically capture digitized waveforms when low tolerance is detected as a result of evaluating the electrical tolerance of a multi-channel high-speed I / O link.

[0047] That is, when the controller 210 is subjected to a specific event or measurement, the controller 210 can output a trigger, or the controller 210 can operate based on a trigger signal that is a receiver at the controller 210.

[0048] For example, a trigger signal may be generated by controller 210 when the transmitter or receiver measurement is below a specified eye width and / or a specified eye height. Additionally or alternatively, controller 210 may generate a trigger signal when the transmitter or receiver's two-dimensional eye measurement is below a specified eye shape or masking. Controller 210 may also generate a trigger signal when the receiver tolerance is less than a certain voltage amount or any other measurement. The trigger signal may also be generated as part of PCIe link training during any link training and state machine (LTSSM) state transitions, or when an error is injected into one or more specific LTSSM states or on any specific channel within a specific PCIe packet.

[0049] In some examples, a user-selectable control between the specified event and the trigger can also be used to specify a programmable delay. Additionally or alternatively, an alternative triggering mode can be provided with low-speed coding for the event type and can be limited to a specific tolerance tester model such that triggers using this mode reach the oscilloscope, which can be automatically configured and post-processed accordingly, such as using the same clock data recovery, continuous-time linear equalization, and decision feedback equalization as tolerance outputs.

[0050] The trigger input settings for controller 210 can be programmed in many different modes. For example, the trigger input signal can be received by controller 210 based on configuration or settings, including link speed with or without reset / link training. When a configuration setting occurs, controller 210 can perform tolerance measurements. Additionally or alternatively, controller 210 can receive the trigger input signal when a programmable error has been injected, and perform tolerance measurements when the trigger input signal is received at controller 210.

[0051] Figure 6 This is a block diagram illustrating a general tolerance tester 602 with multiple interfaces 604 according to an example embodiment. The multiple interfaces 604 are configured, for example, to be connected via one or more cables to at least one test fixture to evaluate the electrical tolerance of the DUT's multi-channel high-speed I / O links in either the Tx or Rx directions, or in both directions.

[0052] The general-purpose tolerance tester 602 includes a controller 210 and an associated memory 214 that can store instructions and other data that the controller 210 can read, use, and / or execute to implement the functions described herein. The general-purpose tolerance tester 602 may include a number of channels that can be connected (e.g., cable-connected) to a standard test fixture via an interface 604 (such as a standard PCI Express compliant load board (CLB)) to perform the same tests as embodiments of the tolerance tester's specific technology (e.g., insert card tolerance tester 202 and motherboard tolerance tester 302) under the control of the controller 210. Furthermore, the general-purpose tolerance tester 602 supports multiple protocols, and its configuration software includes options for configuring channels for different protocols and host / device roles. The general-purpose tolerance tester 602 can also be used to test insert cards by connecting via cable to a test fixture—including a standard PCI Express compliant board (CBB) for testing insert cards. The interface 604 of the universal tolerance tester 602 may include standard coaxial connectors and cables for each high-speed differential signal, or in various other embodiments, custom high-density connectors and fixtures to minimize cable count and make switching from one DUT to another more efficient.

[0053] In some examples, the DUT can be the interconnect under test, which is traditionally tested using a vector network analyzer (VNA). However, VNAs are typically expensive and complex. Furthermore, the scattering parameters (s-parameters) obtained by VNA measurements are generally considered increasingly unreliable at high frequencies—especially when used in statistical simulations of high-speed serial links.

[0054] However, the examples of this disclosure can use the tolerance tester 102 to test passive or active interconnects comprising one or more cable and / or PCB segments to quickly evaluate actual tolerance differences across numerous channels and components. These tests can easily identify the worst-case scenario and risk level of the interconnect. In this way, the tolerance tester 102 can include a “VNA” mode to test active or passive interconnects.

[0055] If a single-port tolerance tester is used, then a single-port transmitter is connected to one side of the interconnect under test and a single-port receiver is connected to the other side of the interconnect. Tolerance tests in a non-protocol PRBS can then be run to test the interconnect under test. However, the examples in this disclosure are not limited to testing the interconnect under test with a single tolerance tester 102. Instead, the test can also be run using a transmitter of one tolerance tester 102 connected to the interconnect under test and a receiver of another tolerance tester 102 connected to the other end of the interconnect under test.

[0056] Additionally or alternatively, the multi-port tolerance tester 102 can be used to measure the tolerance of the interconnect under test in a valid protocol state after training. In such a setup, the interconnect under test can be connected to one port of the multi-port tolerance tester 102, and the other side of the interconnect under test can be connected to another different port of the multi-port tolerance tester 102. The interconnect under test can then be tested to measure its tolerance under the protocol in a valid protocol state after training. Alternatively, instead of the multi-port tolerance tester 102, a multi-tolerance tester can be used to run tolerance tests on the interconnect under test.

[0057] Figure 7 This is a lower-level block diagram of a tolerance tester 102 for testing the electrical tolerance of a multi-channel high-speed I / O link of a DUT in either the Tx or Rx direction, or in both directions, according to an example embodiment.

[0058] An FPGA 714 is shown operatively coupled to a support unit 710 (which may include Ethernet and other communication functions), a time base unit 708 for providing a system reference clock, a high-speed I / O (HSIO) output unit 702, and an HSIO input unit 704. The tolerance tester 102 may also be powered via an AC / DC power unit 716. The high-speed I / O (HSIO) output unit 702 and the HSIO input unit 704 are also operatively coupled to an I / O connector 706. The FPGA 714 is a semiconductor device based on a matrix of configurable logic blocks (CLBs) connected via a programmable interconnect. In various embodiments, the tolerance tester 102 may have fewer or more components than those shown, and some of the components or functions shown, while operatively communicating with the tolerance tester 102, may be located external to or separate from the tolerance tester 102, or located within or integrated into the FPGA 714.

[0059] FPGA 714 can be reprogrammed post-manufacturing to meet desired application or functional requirements in order to perform the functions of the tolerance tester 102 described herein. For example, the firmware on FPGA 714 can act as a standard PCI Express upstream port (also referred to as an endpoint (for testing motherboards, as in the embodiment of insert card tolerance tester 202)) or a standard PCI Express root port (also referred to as an upstream port or root complex (for testing insert cards, as in the embodiment of motherboard tolerance tester 302)), including some link-layer logic for tolerance tester 102 to infer when an error begins at the DUT receiver based on flow in the opposite direction and to rapidly reduce tolerance stress once an error occurs to prevent catastrophic link failure. In some embodiments, FPGA 714 can be implemented using a system-on-module (SoM) architecture or may additionally include a system-on-module (SoM) architecture, which may incorporate memory, interfaces, etc., within FPGA 714. The SoM can be implemented, for example, using an Advanced Reduced Instruction Set Computing (RISC) machine (originally the Acorn RISC machine (ARM) architecture).

[0060] The configuration application and / or script may be implemented via FPGA 714 or stored in an additional accessible memory device or other non-transitory computer-readable storage medium that allows the end user to easily configure the tolerance tester options of tolerance tester 102, including multiple runs with one or more of the following options. In some embodiments, the option for the bit error rate (BER) target may be for tolerance scan settings (a few milliseconds for E-6 type tolerance and a few minutes for E-12 type tolerance). For example, such a target may include, but is not limited to, targets involving: the number of times tolerance settings are performed, tolerance timing and / or voltage; fixing Tx equalization for the tolerance tester or DUT transmitter; and fixing Rx CTLE and DFE for the tolerance tester receiver. In some embodiments, optional applications and / or scripts are provided that remove data from the tolerance tester 102 and provide users with visualization tools to view large tolerance datasets across multiple products / samples and to view average, time-evolved run-to-run changes and trends, and to compare tolerances across multiple runs on the same DUT under different configuration options (fixed Tx equalization, etc.). In some embodiments, optional applications that can be implemented on a bootable driver for installation on the motherboard under test are provided that unlock additional options for motherboard testing, including, but not limited to: running in loopback mode instead of L0 and using a specific mode; using on-die tolerance features in the DUT silicon instead of voltage swing and Sj tolerance from the DUT transmitter; and running both modes and comparing the results.

[0061] Simulations for PCIe and higher-speed links are increasingly using statistical simulation tools, along with transmitter and receiver models, to predict eye diagrams for naturally closed links without requiring complex baseline transmitter and receiver equalization models. One of the most common formats for simulation models is IBIS-AMI.

[0062] Examples of this disclosure include generating simulation models, such as, but not limited to, IBIS-AMI models for the silicon and interconnects of the tolerance tester 102. Users can use the simulation model of the tolerance tester 102 and connect it to models for their DUT channels and / or silicon to simulate the expected tolerance results in either direction using statistical simulation tools.

[0063] In some embodiments, an optional plug-in model is provided, which, if a plug-in is provided for the DUT silicon, allows the tolerance tester to configure the application to also configure the RX equalization settings on that particular DUT silicon. In some embodiments, an optional IBIS-AMI (or similar) software model is provided for each individual tolerance test unit, which can be used by designers and system integrators to be included in their simulations to help establish test constraints / methods for specific customer settings. IBIS-AMI is a modeling standard for the physical layer (PHY) of serializer / deserializer (SerDes), which enables fast, accurate, and statistically significant simulation of multi-gigabit serial links. In some embodiments, the optional IBIS-AMI model is provided to the tolerance test unit along with a customer model (IBIS-AMI or scattering (S) parameters) and can also be utilized by subsequent efforts to include some level of system de-embedding for increased accuracy and repeatability. A general model for the tolerance tester 102 can be provided as a model for a specific tolerance tester 102 or a specifically tuned model (where tuning is performed as part of manufacturing testing) and can generate characterizations.

[0064] Figure 8 This is a block diagram of an example of a field-programmable gate array (FPGA) 714 configured according to an example embodiment. The FPGA 714 can be used in the controller 210 of a tolerance tester 102 for testing the electrical tolerance of a multi-channel high-speed I / O link of a DUT in either the Tx or Rx direction or in both directions.

[0065] In various embodiments, FPGA 714 may have fewer or more components than those shown, and the functionality of some and / or those components (which operatively communicate with FPGA 714) shown may be external to or decoupled from FPGA 714. A register interface 804 is shown, operatively coupled to a local area network (LAN) connection 802 that may include SerDes. Register interface 804 is also operatively coupled to a Link Training and State Machine (LTSSM) and an LTSSM Rx controller 806. One of the processes at the physical layer of the operation of the tolerance tester 102 is link initialization and training processing. In a PCI Express device, this processing establishes many important tasks such as link width negotiation, link data rate negotiation, bit locking per channel, symbol locking / block alignment per channel, etc. All these functions are performed by an LTSSM device that observes stimuli from remote link partners and the current state of the link, and responds accordingly. Register interface 804 is also operatively coupled to one or more additional LTSSM controller units, such as LTSSM Universal Serial Bus (USB) controller 808 and additional LTSSM Universal Serial Bus (USB) controller 810. In the example embodiment shown, LTSSM Rx controller 806 is operatively coupled to PCIe Physical Layer (PHY) 16x SerDes 812 and LTSSM Universal Serial Bus (USB) controller 808 is operatively coupled to USB / Thunderbolt / DisplayPort (USB / TBT / DP) PHY x4 unit 814.

[0066] When the tolerance tester 102 tests a specific protocol such as PCIe, it runs the complete protocol and can track the link state as a link training process for valid states via the LTSSM Rx controller 806, the LTSSM Universal Serial Bus (USB) controller 808, and an additional LTSSM Universal Serial Bus (USB) controller 810. The FPGA 714 of the tolerance tester 102 can repeatedly perform tolerance measurements as training progresses and capture a log of time-comparative electrical tolerances of the link training states in one or both directions.

[0067] The link training status compared to electrical tolerances can be displayed to the user by plotting time and LTSSM status on one axis and tolerances for each direction, channel, etc. on another axis. Figure 16A and Figure 16BThe diagrams can display the corresponding transmit line diagram 1600 and receive line diagram 1602 to the user. Line diagram 1600 illustrates the LTSSM status comparison with tolerance in the Tx direction, and line diagram 1602 illustrates the LTSSM status comparison with tolerance in the Rx direction. For example, the x-axis can show the link status, which is illustrated as L0 to L... n As shown in the figure, the y-axis can indicate the tolerance, which in some examples can be defined as the eye region.

[0068] However, users can configure this mode in many different ways, such as by setting the duration of the tolerance measurement, setting which DUT to send or receive the tolerance measurement for this mode, which DUT to use for the height, width, both height and width, or which two-dimensional eye to use for the tolerance measurement, continuous measurement or measurement change for each LTSSM state, and / or bilateral or unilateral DUTs for the height and / or width. Examples of this disclosure can generate data logs as link training is performed using the DUT and plot various values ​​for the user to visualize what is happening during testing.

[0069] The jitter control unit 816 is also present as part of or operatively coupled to the FPGA 714 for controlling the jitter insertion unit, so that the eye tolerance expected at the DUT receiver can be varied for a specific target of timing or voltage tolerance without the need for software running on the DUT.

[0070] The offset control unit 826 can also be part of or operatively coupled to the FPGA 714 for controlling programmable offsets. Previously, the only test instruments capable of generating varying channel-to-channel offsets across multiple channels were rather complex and expensive multi-channel BERTs. However, multi-channel BERTs cannot run a complete training protocol, including transmit equalization training for modern protocols like PCIe, as the tolerance tester disclosed herein. Thus, there was previously no way to perform lab testing with protocols and a variety of different offsets without a very expensive and complex test setup. However, the examples of this disclosure can use the offset control unit 826 to add transmit offsets per channel in many different ways.

[0071] For example, the offset control unit 826 may include a separate per-channel programmable-length first-in-first-out (FIFO) buffer to set the offset for each channel. Alternatively, the offset control unit 826 may be programmed for each channel in a per-channel variable-length transmit FIFO within the FPGA 714 architecture. Alternatively, the offset control unit 826 may include a soft controller that can modify controller logic to have a variable-length programmable per-channel transmit FIFO that feeds to each physical layer transmitter.

[0072] Figure 9 This is a block diagram of example output drive options for an FPGA (such as FPGA 714) according to an example embodiment, which can be used in the controller (such as controller 210) of a tolerance tester for testing the electrical tolerance of a multi-channel high-speed I / O link of a DUT in either the Tx or Rx direction or in both directions.

[0073] The first output drive option is FPGA direct drive option 818, which is unbuffered and does not include any variable capacitor delay injection or jitter injection. The second output drive option is buffered drive option 820, which includes a linear buffer or limiting amplifier with a differential output voltage (Vod), and does not include any variable capacitor delay injection or jitter injection. The third output drive option is variable capacitor delay injection option 822, which includes a linear buffer and a variable capacitor component 828, causing inter-symbol interference (ISI) plus a delay, which may be, for example, approximately 3-5 ps. The fourth output drive option is jitter injection option 824, which in one embodiment may include a linear buffer (which may or may not be included) and a delay application-specific integrated circuit (ASIC) 830 (approximately 100 ps at 32 GBd), also available from ADSANTEC. In some embodiments, a linear buffer is not included. For example, in such embodiments where a linear buffer is not included, jitter injection can be performed via differential noise injection.

[0074] In various embodiments, the tolerance tester 102 can use different types of pressure to identify various corresponding failure modes, including but not limited to failure modes related to: assembly; interconnects (surface mount technology (SMT), packages, connectors, vias, etc.); defects; impacts series resistance; failure modes causing ISI and baseline drift; eye closure impact; failure modes causing failure modes other than width closure; functional test escape; operator configuration errors; incoming materials; processing changes; receiver bandwidth, which is similar to interconnect changes; power supply rejection ratio (PSRR); vertical / horizontal eye closure; PLL stability; design; changes between channels. A variable capacitor-based approach for jitter insertion may be more effective in exacerbating assembly-related defects.

[0075] Figure 10 This is a flowchart of an example method 1000 for tolerance testing of a DUT according to an example embodiment.

[0076] At position 1002, tolerance tester 102 establishes a multi-channel high-speed I / O link for the device under test (DUT).

[0077] At 1004, the tolerance tester 102 evaluates the electrical tolerance for each high-speed input / output (I / O) channel of the multi-channel high-speed I / O link in either the transmit (Tx) or receive (Rx) direction, or in both directions. For example, evaluating electrical tolerance may include injecting adjustable pressure onto the tolerance test transmitter of the multi-channel high-speed I / O link. The adjustable pressure may include the injection of jitter applied simultaneously to all channels of the multi-channel high-speed I / O link, as well as the application of voltage swing. Evaluating electrical tolerance may also include simultaneously evaluating the electrical tolerance for each high-speed input / output (I / O) channel of the multi-channel high-speed I / O link in both the transmit (Tx) and receive (Rx) directions.

[0078] Figure 11 This is a flowchart of an example method 1000 for identifying potential DUT assembly or manufacturing problems based on tolerance testing of the electrical tolerance of the multi-channel high-speed I / O links of the DUT in either the Tx or Rx directions, or in both directions, according to an example embodiment.

[0079] At 1102, the tolerance tester 102 evaluates the timing eye width tolerance for each high-speed input / output (I / O) channel of the multi-channel high-speed I / O link of the DUT for each of the multiple DUTs in either the Tx direction or the receive Rx direction, or both directions.

[0080] At 1104, the tolerance tester 102 evaluates the timing eye width tolerance measurement for each of the multiple DUTs based on the following: the timing eye width tolerance measurement is always below a predetermined threshold for the same channel across the multiple DUTs.

[0081] At 1106, the tolerance tester 102 identifies potential DUT design problems based on detecting a timing eye width tolerance measurement for each of the plurality of DUTs that is consistently below a predetermined threshold for the same channel across the plurality of DUTs. The detection may also, or alternatively, include detecting, based on evaluation, timing eye width tolerance measurements for multiple of the plurality of DUTs that are each below a predetermined threshold for different channels across the plurality of DUTs.

[0082] Figure 12 This is a flowchart of an example method 1200 for initiating an electrical tolerance assessment performed by a tolerance tester 102 based on a user-selectable option, according to an example embodiment.

[0083] At 1202, the tolerance tester 102 provides user-selectable options for establishing a multi-channel high-speed input / output (I / O) link of the device under test (DUT) and evaluating the electrical tolerance of the multi-channel high-speed I / O link in either the transmit (Tx) or receive (Rx) direction, or in both directions. User-selectable options may include customization for evaluating the electrical tolerance of the multi-channel high-speed I / O link.

[0084] At 1204, the tolerance tester 102 receives an instruction to select one or more user-selectable options for the tolerance tester 102.

[0085] At 1206, the tolerance tester 102 initiates an assessment of the electrical tolerance of a multi-channel high-speed I / O link based on an instruction to select one or more user-selectable options for the tolerance tester 102. The user-selectable options may include, but are not limited to, one or more of the following: selecting one or more different high-speed I / O protocols for performing tolerance testing of the DUT-based multi-channel high-speed I / O link; simultaneously testing multiple ports of the DUT using a hybrid protocol; outputting tolerance changes on any number of tolerance test runs on the multi-channel high-speed I / O link; and implementing a fixed Tx equalization (EQ) on the DUT to test how much tolerance change is due to Tx. Due to EQ training variations; using a fixed CTLE in the receiver of the tolerance tester to test the impact of receiver equalization on the tolerance of the DUT's multi-channel high-speed I / O link; using decision feedback equalization (DFE) in the receiver of the tolerance tester to test the impact of receiver equalization on the tolerance of the DUT's multi-channel high-speed I / O link; calculating the expected tolerance for the tolerance tester based on the target channel; automatically generating commissioning information when low tolerance is detected as a result of evaluating the electrical tolerance of the multi-channel high-speed I / O link; switching the tolerance tester to use a variable inter-symbol interference (ISI) source to find out how much ISI causes channel failure of the multi-channel high-speed I / O link; testing each channel individually to identify the amount of tolerance loss due to crosstalk in the DUT's multi-channel high-speed I / O link; disabling the DFE in the receiver of the tolerance tester to evaluate the tolerance with and without DFE, as well as the nonlinear discontinuities associated with the multi-channel high-speed I / O link in each channel; characterization data for the tolerance tester is shown on the base The system includes: Expected tolerances for quasi-receiver and typical channel conditions, allowing for marking of below-expected tolerances even when all channels of a multi-channel high-speed I / O link across one or more DUTs are consistently below expected tolerances; selection from multiple speeds of the multi-channel high-speed I / O link for which electrical tolerance assessment is performed; the tolerance tester uses protocol-specific knowledge to infer when an error occurs at the receiver of the DUT based on the flow traveling in opposite directions on the multi-channel high-speed I / O link, enabling the tolerance tester to perform tolerance testing on the production line without software on the DUT; automatic capture of time-domain reflectometer readings (TDR) of low-tolerance channels detected as a result of assessing the electrical tolerance of the multi-channel high-speed I / O link; automatic connection to an oscilloscope to automatically capture digitized waveforms when low tolerance is detected as a result of assessing the electrical tolerance of the multi-channel high-speed I / O link; and configuration of one or more user-selectable options for the DUT by configuring the DUT silicon to implement one or more user-selectable options.

[0086] Figure 13 This is a flowchart of an example method 1300 for providing a calibration tolerance tester according to an example embodiment.

[0087] At 1302, the tolerance tester 102 may provide options for performing or being able to perform calibration of the tolerance tester 102, enabling the user to receive a set of expected tolerances using a series of reference channels.

[0088] At 1304, a calibrated tolerance tester is provided, configured to measure the electrical eye tolerance of the Device Under Test (DUT) in either the transmit (Tx) or receive (Rx) direction, or in both directions, without a special test mode, under the condition of a fully operational link of the DUT, and to capture full load and crosstalk effects. Individually calibrated models for the tolerance tester can also be provided, enabling the calculation of expected tolerances using one or more of the following: individualized system channel, receiver model, and transmitter model. Additionally, features in the DUT silicon are provided that allow the tolerance tester to use vendor-defined messages or other protocol mechanisms to indicate that tolerance testing is to be performed by the tolerance tester, causing the DUT silicon to disable logic that might degrade link width or link speed due to errors during the tolerance test duration.

[0089] Software applications for a tolerance tester are also provided, enabling the tolerance tester to perform tests on the channel component under test (e.g., a bare printed circuit board (PCB) or cable) in a test configuration where the tolerance tester is used on either side or both sides of the channel component under test. In some embodiments, the hardware of the tolerance tester is provided to a company that manufactures the printed circuit board (PCB) and data associated with the use of the tolerance tester is provided to a silicon company that provides silicon used in the production of the PCB.

[0090] Figure 14 This is a flowchart of an example method 1400 for configuring a DUT for running tolerance tests, according to an example embodiment.

[0091] At 1402, the tolerance tester 102 receives the configuration settings of the device under test (DUT).

[0092] At 1404, the tolerance tester 102 configures the DUT for running tolerance tests under different conditions on the silicon of the DUT. The tolerance tester 102 may receive software plug-ins that enable configurations and DUT silicon parameters for running tolerance tests under different conditions on the silicon of the DUT. The DUT silicon parameters may include, but are not limited to, one or more of the following: parameters related to the receiver continuous time CTLE and parameters related to the DFE.

[0093] Figure 15 The illustration shows an example of a self-calibrating tolerance tester 102. Calibration of the tolerance tester 102 can be performed by electrically connecting the transmitter to the receiver. This can be done, for example, by electrically connecting the transmitter to the receiver within the same tolerance tester 102 via a switch within the tolerance tester 102. This eliminates the need for external testing equipment.

[0094] Figure 15 Similar to Figure 7 A lower-level block diagram. Similar to... Figure 7 , Figure 15 This is a lower-level block diagram of a tolerance tester 102 for testing the electrical tolerance of a multi-channel high-speed I / O link of a DUT in either the Tx or Rx direction, or in both directions, and featuring self-calibration. To perform self-calibration, one or more switches 1500 can be provided to connect each transmitter in the high-speed I / O (HSIO) output unit 702 to each receiver in the HSIO input unit 704. The transmitters can output signals, and the receivers can receive signals and determine whether the tolerance tester 102 is within the expected range. For ease of explanation... Figure 15 A single switch 1500 is shown, but those skilled in the art will understand that multiple switches 1500 can be provided to connect the transmitter to the receiver. Instead of switch 1500, a calibration device or fixture can be provided at I / O connector 706 to cause the transmitter to loop back to the receiver to perform self-calibration.

[0095] Different operating modes can be provided for performing calibration of the tolerance tester 102. For example, self-calibration can be performed only at the factory using a special loopback fixture that connects the transmitter to the receiver via one or more I / O connectors 706.

[0096] Another possible operating mode is to allow the end user to perform a self-test on the tolerance tester 102. This can be done by activating switch 1500 or by inserting a fixture that routes the transmitter to the receiver of the tolerance tester 102. During the self-test, the tolerance tester 102 can output whether the result is outside a specified range to the front panel indicator 712.

[0097] In some examples, calibration can be performed in protocol mode, PRBS mode, non-protocol mode, or both. However, in protocol mode, I / O connector 706 may not be able to function as both a host and a test device simultaneously. If tolerance tester 102 has two sets of I / O connectors 706, then tolerance tester 102 may have to connect two different sets of I / O connectors 706 or may have to connect a second tolerance tester.

[0098] Internal calibration can provide faster and potentially cheaper factory calibration for the tolerance tester 102 compared to traditional instruments. Internal calibration may also enable end users to perform their own calibration tests.

[0099] The benefits, advantages, and improvements of the disclosed embodiments include, but are not limited to, the following features. Some embodiments can be implemented almost entirely using off-the-shelf components including standard FPGAs and sinusoidal dithering injection chips or delay lines, and have a very low cost compared to conventional BERTs and oscilloscopes. Example embodiments can operate on the entire multi-channel link in normal operating condition without special software and capture any effects caused by simultaneous operation of all channels. Another advantage is that the embodiments of this disclosure can be tested in either or both directions (Tx and Rx) in a single independent unit. Various embodiments can also be run in production environments (e.g., in motherboard production test environments) without requiring any software or modifications to the DUT. Protocol-variable specific test logic can be provided in the tolerance tester 102 silicon / firmware to very quickly identify when an error occurs at the DUT receiver based on data sent back to the tolerance tester by the device under test. Some example embodiments include features implemented in the DUT silicon to identify the state in which tolerance testing is to be performed via PCIExpress vendor-specific messages or other standard protocol features, ensuring that the DUT silicon is in a state where it will not typically degrade link width and / or speed due to errors. This helps ensure that tolerance setting processing for the DUT receiver, using noise injection or voltage swing regulation, will occur without the risk of link width or speed degradation through normal protocol mechanisms. This is an alternative to specialized logic for quickly inferring when errors begin and reducing stress before link or speed degradation may occur.

[0100] Another improvement provided by the example embodiments described herein is that each of the multiple tolerance tester units is individually calibrated and characterized, so that the user knows the expected tolerance value for each particular unit and can flag even the smallest deviation from the expected value across its pre-production and production units. As part of this individual characterization and calibration, a model such as the IBIS-AMI model can be provided for each individual tolerance tester 102, which allows the end user to calculate the expected tolerance for their specific channel model based on simulated or measured S-parameters.

[0101] This disclosure describes a cleverly designed tolerance tester that is very fast and very simple to use. Convenient and efficient configuration software is provided for length tolerance measurements and a variety of user-configurable options. Once configured, the tolerance tester 102 takes the link as any standard device and then automatically performs measurements on the working link. Testing occurs simultaneously on all channels, and for rapid electrical tolerance scanning, it can occur within milliseconds. This enables batch testing, including full testing of all high-speed I / O ports and channels. Various embodiments provide different tolerance test modes to enable a degree of problem characterization without the need for conventional instrumentation, including, but not limited to: repeat counting and analysis of run-to-run variability on tolerances, and selection of Tx equalization (for both the DUT and the tolerance tester) and Rx equalization (for the tolerance test receiver), and the possibility of training problems in the DUT under the tested Tx or Rx training algorithm; fixing the transmitter equalization in either direction and observing its effect on the tolerance; fixing the receiver equalization (CTLE) and the number of DFE taps (including zero) in the tolerance tester receiver and observing its effect on the tolerance value. For example, if the DFE can be turned off, a significant change in tolerance indicates a significant discontinuity in a particular channel.

[0102] Another advantage provided by the various embodiments of the tolerance tester 102 is the ability to test every high-speed I / O port and channel of a particular DUT against electrical tolerances across all pre-production units and in actual production, creating an unprecedented ability to flag problems and potential issues before they cause problems in any way that could affect production or customers. The various embodiments also enable tolerance analysis before and after various link events such as power state transitions (in some cases, using software on the DUT).

[0103] Previous solutions employ highly generic and eigenspecific methods for jitter and noise insertion. The various embodiments of this disclosure offer advantages over previous solutions by significantly simplifying, but not eliminating, the jitter / amplitude pressure required to accomplish the desired task. This simplification translates to lower operating costs, faster results, and increased product confidence (through large datasets) compared to using existing methods.

[0104] Various aspects of this disclosure can operate on specially created hardware, firmware, digital signal processors, or specially programmed general-purpose computers including processors that operate according to programmed instructions. As used herein, the term controller or processor is intended to include one or more microprocessors, microcomputers, application-specific integrated circuits (ASICs), and dedicated hardware controllers that operate independently or in combination with each other. One or more aspects of this disclosure can be embodied in computer-usable data and computer-executable instructions, such as those embodied in one or more program modules, executed by one or more computers (including monitoring modules and controllers) or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc., which perform a specific task or implement a specific abstract data type when executed by a processor in a computer or other device. Computer-executable instructions can be stored on a non-transitory computer-readable storage medium, such as a hard disk, optical disk, removable storage medium, solid-state memory, DDR memory, random access memory (RAM), etc. As those skilled in the art will appreciate, the functionality of program modules can be combined or desiredly distributed across various aspects. Furthermore, functionality can be wholly or partially embodied in firmware or hardware equivalents (such as integrated circuits, FPGAs, etc.). Specific data structures can be used to more efficiently implement one or more aspects of this disclosure, and such data structures are conceivable to be within the scope of the computer-executable instructions and computer-usable data described herein.

[0105] In some cases, the disclosed aspects may be implemented in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried on or stored on one or more non-transitory computer-readable media, which may be read and executed by one or more processors. Such instructions may be referred to as a computer program product. As discussed herein, a computer-readable medium means any medium that can be accessed by a computing device. By way of example, and not limitation, a computer-readable medium may include computer storage media and communication media.

[0106] Computer storage media means any medium that can be used to store computer-readable information. By way of example, and not limitation, computer storage media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, optical disc read-only memory (CD-ROM), digital video disc (DVD) or other optical disc storage, magnetic tape cassettes, magnetic tape, disk storage or other magnetic storage devices, and any other volatile or non-volatile, removable or non-removable media implemented in any technology. Computer storage media excludes signals themselves and transient forms of signal transmission.

[0107] Communication medium means any medium that can be used for communication of computer-readable information. By way of example, and not limitation, communication medium can include coaxial cable, fiber optic cable, air, or any other medium suitable for communication of electrical, optical, radio frequency (RF), infrared, acoustic, or other types of signals.

[0108] Additionally, this written description refers to specific features. It should be understood that the disclosure in this specification includes all possible combinations of these specific features. For example, where a specific feature is disclosed in the context of a particular aspect, that feature may also be used, to the extent possible, in the context of other aspects.

[0109] Furthermore, when a method having two or more defined steps or operations is mentioned in this application, the defined steps or operations may be performed in any order or simultaneously, unless the context precludes those possibilities.

[0110] While specific aspects of this disclosure have been illustrated and described for illustrative purposes, it will be understood that various modifications may be made without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be limited except by the appended claims.

Claims

1. A testing device, comprising: At least one interface is configured to connect to the device under test (DUT); One or more channels connected to the interface; as well as A controller, coupled to at least one interface via one or more channels, is configured to establish a single-channel or multi-channel high-speed input / output (I / O) link with the DUT and cause the test equipment to evaluate the electrical tolerance of the single-channel or multi-channel high-speed I / O link in either the transmit (Tx) direction or the receive (Rx) direction, or in both directions. The controller is configured to evaluate the electrical tolerance of a single-channel or multi-channel high-speed I / O link by being configured at least to vary the offset of each channel.

2. The test apparatus of claim 1, wherein the at least one interface comprises at least one channel configured to be connected to the DUT to evaluate the electrical tolerance of a single-channel or multi-channel high-speed I / O link with the DUT in either the Tx direction or the Rx direction, or in both directions.

3. The test apparatus of claim 2, wherein the at least one channel comprises a plurality of channels, and wherein the controller is configured to support a plurality of different protocols for the test apparatus to test each of the plurality of different devices operating according to the different protocols, and provides options to configure the plurality of channels for different device roles and the plurality of different protocols.

4. The test apparatus of claim 3, wherein the plurality of channels are configured to be connected to at least one test fixture to evaluate the electrical tolerance of a multi-channel high-speed I / O link.

5. The test equipment according to claim 1, wherein the single-channel or multi-channel high-speed I / O link with the DUT is a fully operational link without any special test modes.

6. The test apparatus of claim 1, further comprising a printed circuit board (PCB) of an insert card and the DUT being a motherboard, the insert card being configured to be plugged into a connector on the motherboard to implement the physical layer and link logic layer for each channel of a single-channel or multi-channel high-speed I / O link.

7. The test apparatus of claim 1, wherein the controller is configured to evaluate the electrical tolerance of a single-channel or multi-channel high-speed I / O link by being configured at least to inject adjustable pressure onto a tolerance test transmitter.

8. The test apparatus of claim 1, wherein the controller is further configured to output a trigger signal when an event is detected during an electrical tolerance assessment.

9. The test apparatus of claim 1, wherein the controller is further configured to cause the test apparatus to evaluate electrical tolerances upon receiving a trigger signal.

10. The test apparatus of claim 1, wherein the controller is further configured to capture a log of the link training state versus the electrical tolerance during an electrical tolerance assessment.

11. The test apparatus of claim 1, wherein each of the one or more channels includes a transmitter and a receiver, and the controller is further configured to perform calibration by coupling each transmitter to a corresponding receiver.

12. The test apparatus of claim 1, wherein the DUT is an interconnect under test, and the controller is further configured to activate a vector network analyzer mode to test the interconnect under test.

13. The test apparatus of claim 12, wherein the interconnect under test is coupled between at least one transmitter and at least one receiver in one or more channels.

14. A method for performing electrical tolerance testing on a device under test (DUT), the method comprising: Couple the DUT to multiple channels of the tolerance tester; A multi-channel high-speed I / O link with the DUT is established through the aforementioned multiple channels; as well as The tolerance tester evaluates the electrical tolerance of each high-speed input / output (I / O) channel of a multi-channel high-speed I / O link in either the transmit (Tx) or receive (Rx) direction, or in both directions, by varying the offset of each channel.

15. The method of claim 14, wherein a trigger signal is generated when an event is detected during an electrical tolerance assessment.

16. The method of claim 14, further comprising receiving a trigger signal and evaluating electrical tolerance when the trigger signal is received.

17. The method of claim 14, further comprising capturing a log of the link training state compared to the electrical tolerance during electrical tolerance assessment.

18. The method of claim 14, wherein each channel includes a transmitter and a receiver, and the method further includes calibrating the test equipment by coupling the transmitter and the receiver and performing calibration.

19. The method of claim 14, wherein the DUT is an interconnect under test, and the method further includes activating a vector network analyzer mode to test the interconnect under test.

20. The method of claim 19, wherein the interconnect under test is coupled between at least one transmitter and at least one receiver of the plurality of channels.

21. A tolerance tester, comprising: One or more channels are configured to be coupled to the device under test (DUT); as well as One or more controllers are configured as follows: Establish a single-channel or multi-channel high-speed input / output (I / O) link with the DUT through one or more channels; and The electrical tolerance of a single-channel or multi-channel high-speed I / O link is evaluated in either the transmit (Tx) or receive (Rx) direction, or in both directions, by varying the offset of each channel.

22. The tolerance tester of claim 21, wherein the one or more controllers are further configured to establish a single-channel or multi-channel high-speed I / O link with the DUT when the tolerance tester acts as a root complex.

23. The tolerance tester of claim 21, wherein the one or more controllers are further configured to establish a single-channel or multi-channel high-speed I / O link with the DUT when the tolerance tester acts as an endpoint.

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