Voltage regulating circuit and method for operating a voltage regulating circuit

Abstract

The invention provides a voltage regulating circuit (300, 500). The voltage regulating circuit (300, 500) has a conversion circuit (106) which is designed to convert a voltage pulse sequence into a filtered analog voltage, wherein the voltage pulse sequence represents a predefined operating limit voltage, and a regulator (102) which is designed to receive the filtered analog voltage as a regulating variable and to regulate an output voltage (VDD) of the voltage regulating circuit (300, 500) to a predefined desired voltage.

Description

Technical Field

[0001] This invention relates to a voltage regulation circuit and a method for operating the voltage regulation circuit. Background Technology

[0002] A so-called low-dropout regulator is a linear regulator used to provide a stable output voltage. The low-dropout regulator may optionally be without (external) capacitors and is then also referred to as "capacitorless".

[0003] The challenge in designing such an integrated low-dropout regulator (LDO) without external capacitors is to achieve rapid regulation while ensuring (voltage) stability over a wide range of operating conditions.

[0004] Typically, stability requirements limit the regulation power to a level where voltage integrity can no longer be guaranteed solely by the regulation loop.

[0005] Additional measures may be required to prevent excessively low or high output voltage (VDD) under the stated conditions.

[0006] For example, a drain (also known as a shunt) may be provided to limit the output voltage if the output voltage VDD exceeds the upper voltage limit (Vclip; also known as the upper voltage threshold, upper limit, upper threshold, upper limit voltage, or trigger upper threshold), and / or a stopper may be provided to stop the clock signal generator (clock, or in this system clock) if the output voltage VDD drops below the lower voltage limit (Vdrop; also known as the lower voltage threshold, lower limit, lower threshold, lower limit voltage, or trigger lower threshold), which causes a reduction in load.

[0007] All of the aforementioned limit values ​​typically exhibit the following local fluctuations: within the actual voltage value, a specified action is actually triggered at the preset limit value (e.g., connecting to a shunt or stopping the clock signal generator).

[0008] The improvement in the fluctuations is limited by the current consumption of the comparator used and the performance requirements.

[0009] exist Figure 1 The left-hand diagram illustrates the range within which the output voltage VDD can vary in a voltage regulation circuit according to the prior art.

[0010] The total width of the range of possible values ​​of VDD is derived from the sum of the ranges of individual values ​​and lies between the minimum voltage (minimum output voltage) VDDmin and the maximum voltage (maximum output voltage) VDDmax.

[0011] In the case under consideration, fluctuations exist in the voltage value generated by the regulator itself (illustrated as the nominal output voltage VDDnom) and in the two supporting circuit blocks that implement the lower limit voltage Vdrop or the upper limit voltage Vclip.

[0012] VDDnom must be spaced far from Vdrop or Vclip so that they do not overlap in the distribution (here, for example, each with a width of 4σ), because otherwise measures to be implemented by the supporting circuit blocks may begin to be carried out while the voltage set by the regulator is still within the allowable voltage range, for example, within ±4σ around VDDnom.

[0013] In technologies with structural dimensions significantly smaller than one micrometer, the maximum output voltage VDDmax is reduced due to more stringent reliability requirements.

[0014] On the other hand, the limiting voltage of MOS transistors remains more or less the same, so that the minimum output voltage VDDmin also remains more or less the same in order to limit channel leakage (Kanal-Leckage).

[0015] Because voltage control must operate within the preset voltage range (VDDmin-VDDmax) that is thus limited and reduced, the fluctuation range around each preset value (Vnom, Vdrop, Vclip) must be reduced in order to prevent the fluctuation range from accumulating. Summary of the Invention

[0016] In different embodiments, a voltage regulation circuit is provided in which the regulation variable (also called the regulation target) for the low-dropout regulator is not derived from the output voltage VDD, but from the duty cycle (also called the duty ratio or duty factor) for overvoltage protection.

[0017] In different embodiments, the permissible voltage fluctuation range of the circuit elements in the voltage regulation circuit is increased and / or the voltage range (VDDmax-VDDmin) to be followed by the output voltage is decreased, without significantly reducing the permissible voltage fluctuation range of each circuit element, in order to reduce the number of limit values ​​used for voltage regulation or voltage limiting from three to two.

[0018] In different embodiments, limit values ​​for the upper or lower voltage limits can be used to derive the adjustment variable. This eliminates the need for a preset target voltage value, which in the prior art is based on a feedback signal generated by means of a resistor as the adjustment variable. Attached Figure Description

[0019] Embodiments of the present invention are shown in the accompanying drawings and described in detail below.

[0020] The attached diagram shows:

[0021] Figure 1 The left side shows a diagram illustrating possible values ​​for the output voltage provided by the voltage regulation circuit, based on existing technology, and the right side shows diagrams illustrating different embodiments.

[0022] Figure 2 A circuit diagram of a voltage regulation circuit according to the prior art is shown;

[0023] Figure 3 Circuit diagrams of voltage regulation circuits according to different embodiments are shown;

[0024] Figure 4 Circuit diagrams of voltage regulation circuits according to different embodiments are shown;

[0025] Figure 5 Circuit diagrams of voltage regulation circuits according to different embodiments are shown; and

[0026] Figure 6 A flowchart illustrating a method for operating a voltage regulation circuit according to different embodiments is shown. Detailed Implementation

[0027] The following detailed description refers to the accompanying drawings, which form part of the description and illustrate specific embodiments in which the invention can be practiced for illustrative purposes. In this regard, directional terms such as “above,” “below,” “front,” “rear,” “front,” “back,” etc., are used with respect to the orientation of the described figures(s). Because components of the embodiments can be positioned in a number of different orientations, the directional terms are used for illustrative purposes and are by no means limiting. It should be understood that other embodiments can be used, and structural or logical changes can be made without departing from the scope of the invention. It should be understood that features of the different exemplary embodiments described herein can be combined with each other unless otherwise specifically stated. Therefore, the detailed description below should not be construed in a limiting sense, and the scope of the invention is defined by the appended claims.

[0028] Within the scope of this specification, the terms "connection," "linkage," and "coupling" are used to describe direct and indirect connections, direct or indirect links, and direct or indirect couplings. In the accompanying drawings, identical or similar elements are given the same reference numerals, provided that it is appropriate.

[0029] exist Figure 1 The diagram on the right illustrates possible values ​​for the output voltage provided by the voltage regulation circuit according to different embodiments.

[0030] As described above, in different embodiments, the permissible voltage fluctuation range of the circuit elements in the voltage regulation circuit can be increased.

[0031] Alternatively or additionally, in different embodiments, the voltage range (VDDmax-VDDmin) to be followed by the output voltage can be reduced without significantly reducing the permissible voltage fluctuation range of the individual circuit elements.

[0032] By reducing the number of limits used for voltage regulation or voltage limiting from three to two, both can be achieved independently or together.

[0033] This is Figure 1 Explanation with Chinese diagrams.

[0034] exist Figure 1 The left half shows three limit values, which are typically used in voltage regulation circuits according to the prior art, such as voltage regulation circuit 200, to regulate the output voltage VDD, as the voltage regulation circuit is used in... Figure 2 The circuit diagram is explained in detail.

[0035] In the voltage regulation circuit 200 according to the prior art, the regulator 102 can be configured to regulate the output voltage VDD of the voltage regulation circuit 200 to a preset desired voltage. For this purpose, the output voltage VDD can be fed back to the regulator 102 via a voltage divider 106 with a preset voltage reference value Vref. The regulated output of the regulator 102 can be coupled to and controlled by a circuit element 112 (e.g., a so-called passive device) to achieve the desired output voltage VDD. If VDD is higher than the upper limit voltage Vclip, the current trap 108 can be activated (e.g., by means of a switchable channel element 110) to reduce the output voltage VDD.

[0036] The three limiting values ​​are the nominal output voltage VDDnom, the upper limit voltage Vclip, and the lower limit voltage Vdrop, which are the target variables. Figure 2 (Not illustrated in the diagram). As described above, each of the limiting values ​​has a fluctuation range, wherein the maximum possible upper limit voltage should be at most within the maximum output voltage VDDmax, and the minimum possible lower limit voltage should not be lower than the minimum output voltage VDDmin, so that the operation of the voltage regulation circuit and / or the circuit supplied with voltage by it can be realized or ensured.

[0037] The sum of the fluctuation widths yields the (minimum) width of the range of values ​​that VDD can take (VDDmax - VDDmin).

[0038] like Figure 1As illustrated in the embodiment shown on the right, omitting the explicit preset of the nominal output voltage allows for a narrowing of the range of possible VDD values ​​compared to the prior art, although the fluctuation widths of the remaining two extreme values, Vclip and Vdrop, remain the same. As shown in the illustrated embodiment, maintaining the maximum output voltage VDDmax means that the minimum output voltage VDDmin can be increased, which could translate to improved performance of the voltage regulation circuit 300 supplied by the output voltage.

[0039] Conversely, while maintaining the minimum output voltage VDDmin, the maximum output voltage VDDmax can be reduced.

[0040] Alternatively, the fluctuation widths of the remaining two limit values, Vclip and Vdrop (not shown), can be increased, which can achieve lower requirements on the corresponding circuit components.

[0041] In another alternative embodiment, the above embodiments can be combined to not only narrow the value range but also increase the fluctuation width.

[0042] More generally, in different embodiments, the reduced range of values ​​achievable by VDD can be determined by defining the position and actual width of the range relative to the voltage values ​​VDDmax and VDDmin, wherein the output voltage VDD should not exceed the voltage value VDDmax or should not be lower than the voltage value VDDmin, and the voltage values ​​VDDmax and VDDmin can be determined by the maximum reliability requirements of the voltage regulation circuit (e.g., VDDmax as overvoltage protection).

[0043] Vclip can be implemented, for example, by means of a shunt, and Vdrop can be implemented by means of a stopper that stops the clock signal generator when the output voltage VDD drops below the lower voltage limit Vdrop.

[0044] In different implementations, VDDnom is not required. Instead, VDD can be kept within a target range between VDDmin and VDDmax based on Vclip or Vdrop.

[0045] In different embodiments that use Vclip to keep VDD between VDDmin and VDDmax, VDD can typically be closer to Vclip (and thus closer to VDDmax, especially closer to VDDmax than closer to VDDmin) compared to being closer to Vdrop. Intuitively, in this case, the upper value of the fluctuation width around the (indirectly preset) nominal output voltage VDDnom can coincide with the upper value of the fluctuation width of the upper voltage limit value Vclip, i.e., coincide with VDDmax.

[0046] In different embodiments where Vdrop is used to keep VDD between VDDmin and VDDmax, VDD can typically be closer to Vdrop (and thus closer to VDDmin, especially closer to VDDmin than closer to VDDmax) compared to being closer to Vclip. Intuitively, in this case, the lower part of the fluctuation width around the (indirectly preset) nominal output voltage VDDnom can coincide with the lower part of the fluctuation width of the voltage lower limit Vdrop, i.e., coincide with VDDmin.

[0047] Figure 3 and Figure 4 Each figure in the diagram shows a circuit diagram of a voltage regulation circuit 300 according to a different embodiment, wherein Vclip is used to regulate the output voltage VDD.

[0048] The voltage regulation circuit 300 may include a conversion circuit 106 (e.g., a low-pass filter) configured to convert a voltage pulse sequence into a filtered analog voltage. Therefore, the conversion circuit 106 can function as a D / A converter.

[0049] Here, the voltage pulse sequence—and correspondingly the filtered analog voltage—can represent the preset operating limit voltage Vclip, even if, as in Figure 3 and Figure 4 In the illustrated embodiment, the voltage pulse sequence is inverted by means of inverter 330 before conversion.

[0050] The voltage regulation circuit 300 may also have a regulator 102, such as a regulating amplifier, which may be configured to receive a filtered analog voltage as a regulation variable and regulate the output voltage of the voltage regulation circuit 300 to a preset desired voltage.

[0051] In the voltage regulation circuit 300 according to a different embodiment (compared to the voltage regulation circuit 200 according to the prior art), the regulation variable may no longer be truncated at the output voltage VDD, but may be derived from the upper voltage limit Vclip by supplying a duty cycle representing Vclip as a digital signal to a low-pass filter 106, which converts the duty cycle into an analog voltage, which is then supplied to the regulator 102 as the regulation variable (by means of feedback 220).

[0052] The comparison value for regulator 102 can be provided by means of the output voltage VDD supplied to voltage divider 332, and the comparison value can form an analog corresponding quantity of the target duty cycle.

[0053] The preset desired voltage can be between the upper limit voltage Vclip and the lower limit voltage Vdrop, wherein the preset desired voltage can be closer to the upper limit voltage Vclip than to the lower limit voltage Vdrop.

[0054] The regulated output of regulator 102 can be coupled to and controlled by a circuit element (passive device, such as a MOSFET) 112 to generate a desired output voltage VDD, which is connected to an external voltage VDDP.

[0055] In different embodiments, the output signal of the regulator 102 can be averaged by means of capacitor 114.

[0056] In different embodiments, the output signal can also be fed to the gate of MOSFET 112 in order to control the current through circuit element 112.

[0057] In different embodiments, the voltage regulation circuit 300 also has overvoltage protection circuits 104, 110, and 108, which are configured to compare the output voltage VDD with the upper limit voltage Vclip (in comparator 104) and use the output voltage pulse sequence as the comparison result (in the form of duty cycle).

[0058] The duty cycle can correspond to the ratio of the upper limit voltage Vclip and the output voltage VDD relative to each other. When the upper limit voltage Vclip is exceeded, a voltage pulse sequence (duty cycle signal) can be used to connect the output voltage VDD to the current trap 108.

[0059] Therefore, in different embodiments, for example, the current sink 108 can be activated by means of a switchable channel element 110 (e.g., a MOSFET) to reduce the output voltage VDD.

[0060] The upper limit voltage Vclip (and, if necessary, the external supply voltage VDDP) can be set such that, on average, during a preset percentage of the operating duration of the voltage regulation circuit 300, the output voltage VDD is connected to the current sink 108, the preset percentage being greater than 0% and less than 100%, for example, between 1% and 90%, for example, between 10% and 80%, for example, between 20% and 50%.

[0061] Figure 3 The working principle of the voltage regulation circuit 300 is basically explained in a rough manner, and Figure 4 The illustrations provide a more detailed explanation of the embodiments.

[0062] In different embodiments, circuit element 112 (passive device) may be a high-voltage NMOS transistor, such as an N-channel transistor, one terminal of the circuit element (e.g., drain D) may be coupled to an external voltage supply VDDP, and the output voltage VDD may be provided at another terminal (e.g., source S) of the circuit element.

[0063] The adjustment variable is formed by the duty cycle of the clip-signal. In other words, the duty cycle, or the value derived from it, is fed to the regulator 102 as the adjustment variable.

[0064] The duty cycle indicator (transmitted as an analog signal to regulator 102) indicates a VDD value higher than a reference value Vref, which should not be exceeded by the output voltage VDD. The upper limit voltage Vclip of the output voltage VDD is limited by a current through a voltage trap (shunt) 108, which dissipates the limited current when clipping is activated. The dissipated current can be constant or varied depending on different operating points and / or conditions.

[0065] The embodiment also shows a low bias current, denoted by Iclipschwach, which is dissipated when VDD is higher than Vref.

[0066] To release load current, a weak clipping can activate an additional strong shunt to prevent overvoltage.

[0067] In different embodiments, the current trap 110 can be formed as a current mirror. This is exemplarily shown in... Figure 4 As shown in [the image]. Figure 4 In this context, m represents the number of fingers on the regulating transistor. Assuming the current mirror has only one finger, this allows us to consider the sum of the number of fingers in both current paths, and thus also the sum of the number of fingers in the two current paths, as in the case of... Figure 4 The Iclipschwach description of the current ratio yields the ratio 1 / m.

[0068] In the balanced state, the fast Vclip comparator 104 provides a high-frequency digital Vclip signal. This signal can be filtered by a low-pass filter 106 to produce an analog representation of the duty cycle of the clipped signal.

[0069] The analog signal is used as a regulating variable. Therefore, the duty cycle of the clipping signal in the equilibrium state is limited by a regulating loop or by a regulating loop.

[0070] As an additional component, Figure 4In one embodiment, a charge pump 440 is provided, indicated as “UP” (for “upward”) and “DN” (for “downward”), which controls the direction based on the difference between the current clipping duty cycle and the desired clipping duty cycle.

[0071] Figure 5 A circuit diagram of a voltage regulation circuit 500 according to a different embodiment is shown, wherein Vdrop is used to regulate the output voltage VDD.

[0072] As described in the overview section above, the basic function of voltage regulation circuit 500 is similar to that of voltage regulation circuit 300, and many circuit elements and functions are similar to or the same as those described for voltage regulation circuit 300, so much of the repetition is omitted here.

[0073] The difference between voltage regulation circuit 500 and voltage regulation circuit 300 is that the reference voltage Vref provided to comparator 104 for comparison with VDD corresponds to the lower limit voltage Vdrop and does not correspond to the upper limit voltage Vclip.

[0074] In different embodiments, the voltage regulation circuit 500 also has undervoltage protection circuits 104 and 108, which are configured to compare the output voltage VDD with the lower limit voltage Vdrop (in comparator 104) and use the output voltage pulse sequence as the comparison result (in the form of duty cycle).

[0075] The duty cycle can correspond to the ratio of the lower limit voltage Vdrop to the output voltage VDD relative to each other. When the voltage is below the lower limit voltage Vdrop, a voltage pulse sequence (duty cycle signal) can be used to increase the output voltage VDD again.

[0076] To achieve this, in different embodiments, a clock signal generator (clock) 550 can be provided as part of the voltage regulation circuit 500, which regularly connects the output voltage VDD to the current sink 108. If it is determined in comparator 104 that VDD is below the lower limit voltage Vdrop, the output signal of comparator 104 can be sent to an interrupt (or delay) 554, which can be configured to stop or at least delay the clock signal generator 550. Thus, the output voltage VDD is less frequently or completely decoupled from the current sink 108 and can rise again.

[0077] Figure 5 The current sink 108 in the diagram is a model representation of the current consumption of a clock circuit, whose current consumption is critically related to the clock (e.g., CPU).

[0078] The lower limit voltage Vdrop (and, if necessary, the supply voltage VDDP supplied externally) can be set to, on average, during a preset percentage of the operating duration of the voltage regulation circuit 500, connect the output voltage VDD to the current sink 108, the preset percentage being greater than 0% and less than 100%, for example, between 1% and 90%, for example, between 10% and 80%, for example, between 20% and 50%.

[0079] Similar to the voltage regulation circuit 300, in the voltage regulation circuit 500, the duty cycle can be supplied to the regulator 102 as an adjustment variable. Here, before being supplied to the regulator 102, the duty cycle can also be converted into an analog signal (voltage) by means of a D / A converter, thus eliminating the need for inversion.

[0080] The adjustment variable can be processed in essentially the same way as described above for voltage regulation circuit 300, i.e., by feeding the output signal of regulator 102 to circuit element 112 (e.g., a so-called passive device) and controlling said circuit element to form the desired output voltage VDD.

[0081] Figure 6 A flowchart 600 illustrates a method for operating a voltage regulation circuit according to different embodiments.

[0082] The method comprises: converting a voltage pulse sequence into a filtered analog voltage, wherein the voltage pulse sequence represents a preset operating limit voltage (at 610); receiving the filtered analog voltage as an adjustment variable in a regulator (at 620); and adjusting the output voltage of the voltage regulation circuit to a preset desired voltage (630).

[0083] The following is a summary of some examples.

[0084] Example 1 is a voltage regulation circuit. The voltage regulation circuit includes: a conversion circuit configured to convert a voltage pulse sequence into a filtered analog voltage, wherein the voltage pulse sequence represents a preset operating limit voltage; and a regulator configured to receive the filtered analog voltage as an adjustment variable and adjust the output voltage of the voltage regulation circuit to a preset desired voltage.

[0085] Example 2 is a voltage regulation circuit according to Example 1, wherein the conversion circuit has a low-pass filter.

[0086] Example 3 is a voltage regulation circuit based on Example 1 or 2, wherein the preset operating limit voltage is the upper limit voltage.

[0087] Example 4 is a voltage regulation circuit according to Example 3, wherein the conversion circuit has an inverter.

[0088] Example 5 is a voltage regulation circuit based on Example 4, wherein the voltage regulation circuit further includes an overvoltage protection circuit, which is configured to compare the output voltage with the upper limit voltage and use the output voltage pulse sequence as the comparison result.

[0089] Example 6 is a voltage regulation circuit according to Example 5, wherein the voltage pulse sequence corresponds to a duty cycle, which corresponds to the ratio of the upper limit voltage and the output voltage relative to each other.

[0090] Example 7 is a voltage regulation circuit according to Example 5 or 6, wherein the voltage regulation circuit is further configured to connect the output voltage to the current trap by means of a voltage pulse sequence when the upper limit voltage is exceeded.

[0091] Example 8 is a voltage regulation circuit according to Example 7, wherein the upper limit voltage is set such that the output voltage is connected to the current sink during the average operating duration of the voltage regulation circuit for a preset percentage greater than 0% and less than 100%.

[0092] Example 9 is a voltage regulation circuit according to one of Examples 3 to 8, wherein the preset desired voltage is between the upper limit voltage and the lower limit voltage.

[0093] Example 10 is a voltage regulation circuit according to Example 9, wherein the preset desired voltage is closer to the upper limit voltage than the lower limit voltage.

[0094] Example 11 is a voltage regulation circuit according to Example 1 or 2, wherein the preset limit voltage is the lower limit voltage.

[0095] Example 12 is a voltage regulation circuit according to Example 11, wherein the voltage regulation circuit further includes an undervoltage protection circuit, which is configured to compare the output voltage with a lower limit voltage and use the output voltage pulse sequence as the comparison result.

[0096] Example 13 is a voltage regulation circuit according to Example 5, wherein the voltage pulse sequence corresponds to the duty cycle, which corresponds to the ratio of the lower limit voltage and the output voltage relative to each other.

[0097] Example 14 is a voltage regulation circuit according to Example 12 or 13, wherein the voltage regulation circuit further includes a clock signal generator and a current sink, wherein the clock signal generator is configured to provide a clock signal for connecting the output voltage and the current sink in a clock-controlled manner.

[0098] Example 15 is a voltage regulation circuit according to Example 14, wherein the voltage regulation circuit is further configured to stop the clock signal generator by means of a voltage pulse sequence when the voltage is below the lower limit voltage, so as to prevent the output voltage from connecting to the current trap.

[0099] Example 16 is a voltage regulation circuit according to one of Examples 11 to 15, wherein the preset desired voltage is between the lower limit voltage and the upper limit voltage.

[0100] Example 17 is a voltage regulation circuit according to Example 16, wherein the preset desired voltage is closer to the lower limit voltage than the upper limit voltage.

[0101] Example 18 is a voltage regulation circuit according to one of Examples 1 to 17, the voltage regulation circuit further comprising a current mirror configured to output an output voltage.

[0102] Example 19 is a voltage regulation circuit according to Example 7, the voltage regulation circuit further having a current trap, the current trap being configured to reduce the current according to the current load current of the voltage regulation circuit.

[0103] Example 20 is a voltage regulation circuit according to Example 19, wherein the current trap is formed by means of a current mirror.

[0104] Example 21 is a method for operating a voltage regulation circuit. The method includes: converting a voltage pulse sequence into a filtered analog voltage, wherein the voltage pulse sequence represents a preset operating limit voltage; receiving the filtered analog voltage as an adjustment variable in a regulator; and adjusting the output voltage of the voltage regulation circuit to a preset desired voltage.

[0105] Example 22 is the method according to Example 21, wherein the conversion has a low-pass filter.

[0106] Example 23 is based on the method of Example 21 or 22, wherein the preset operating limit voltage is the upper limit voltage.

[0107] Example 24 is the method according to Example 23, wherein the conversion includes: inversion.

[0108] Example 25 is a method according to Example 23 or 24, the method further comprising comparing the output voltage with the upper limit voltage and using the output voltage pulse sequence as the comparison result.

[0109] Example 26 is the method according to Example 25, wherein the voltage pulse sequence corresponds to a duty cycle, which corresponds to the ratio of the upper limit voltage and the output voltage relative to each other.

[0110] Example 27 is a method according to Example 25 or 26, the method further comprising connecting the output voltage to a current sink when the upper limit voltage is exceeded.

[0111] Example 28 is based on the method of Example 27, wherein the upper limit voltage is set such that the output voltage is connected to the current sink during the average operating duration of the voltage regulation circuit for a preset percentage greater than 0% and less than 100%.

[0112] Example 29 is a method according to one of Examples 23 to 28, wherein the preset desired voltage is between an upper limit voltage and a lower limit voltage.

[0113] Example 30 is based on the method of Example 29, wherein the preset desired voltage is closer to the upper limit voltage than the lower limit voltage.

[0114] Example 31 is based on the method of Example 21 or 22, wherein the preset limit voltage is the lower limit voltage.

[0115] Example 32 is based on the method of Example 31, the method further comprising: comparing the output voltage with the lower limit voltage and using the output voltage pulse sequence as the comparison result.

[0116] Example 33 is the method according to Example 32, wherein the voltage pulse sequence corresponds to a duty cycle, which corresponds to the ratio of the lower limit voltage and the output voltage relative to each other.

[0117] Example 34 is a method according to Example 32 or 33, the method further comprising: providing a clock signal and connecting the output voltage to the current sink in a clock-controlled manner.

[0118] Example 35 is based on the method of Example 34, in which the clock signal generator is stopped when the voltage is below the lower limit to prevent the output voltage from connecting to the current sink.

[0119] Example 36 is a method according to one of Examples 31 to 35, wherein the preset desired voltage is between the lower limit voltage and the upper limit voltage.

[0120] Example 37 is based on the method of Example 36, wherein the preset desired voltage is closer to the lower limit voltage than the upper limit voltage.

[0121] Other advantageous design options for the equipment are derived from the description of the method, and vice versa.

Claims

1. A voltage regulation circuit (300, 500), comprising: A conversion circuit (106) is configured to convert a voltage pulse sequence into a filtered analog voltage, wherein the voltage pulse sequence represents a preset operating limit voltage. Regulator (102), configured to adjust the output voltage (VDD) of the voltage regulation circuit (300, 500) to a preset desired voltage by comparing the filtered analog voltage as an adjustment variable with the output voltage of the voltage regulation circuit. The preset desired voltage is between the upper limit voltage (Vclip) and the lower limit voltage; The voltage pulse sequence therein corresponds to a duty cycle, which in turn corresponds to the ratio of the upper limit voltage (Vclip) to the output voltage (VDD). An overvoltage or undervoltage protection circuit is configured to compare the output voltage (VDD) with the upper limit voltage (Vclip) or the lower limit voltage (Vdrop) and output the voltage pulse sequence as the comparison result. The conversion circuit is connected to the output of the overvoltage or undervoltage protection circuit.

2. The voltage regulation circuit (300, 500) according to claim 1. The conversion circuit (106) mentioned therein has a low-pass filter.

3. The voltage regulation circuit (300, 500) according to claim 1. The conversion circuit (106) mentioned therein has an inverter (552).

4. The voltage regulation circuit (300, 500) according to claim 1 or 2. The voltage regulation circuit is further configured to connect the output voltage (VDD) to the current trap (108) by means of the voltage pulse sequence when the upper limit voltage (Vclip) is exceeded.

5. The voltage regulation circuit (300, 500) according to claim 4. The upper limit voltage (Vclip) is set such that the output voltage (VDD) is connected to the current trap (108) during the average operating duration of the voltage regulation circuit (300, 500) for a preset percentage greater than 0% and less than 100%.

6. The voltage regulation circuit (300, 500) according to claim 1. The preset expected voltage is closer to the upper limit voltage (Vclip) than the lower limit voltage.

7. The voltage regulation circuit (300, 500) according to any one of claims 1 to 3 further comprises: A current mirror (440) is configured to output the output voltage (VDD).

8. The voltage regulation circuit (300, 500) according to claim 4. The current sink (108) is configured to reduce the current based on the current load current of the voltage regulation circuit (300, 500).

9. The voltage regulation circuit (300, 500) according to claim 8, wherein the current trap (108) is formed by means of a current mirror (440).

10. A method for operating a voltage regulation circuit, the method comprising: The overvoltage or undervoltage protection circuit compares the output voltage of the voltage regulation circuit with the upper or lower limit voltage, and uses the output voltage pulse sequence as the comparison result. The voltage pulse sequence represents the preset operating limit voltage. The voltage pulse sequence corresponds to a duty cycle, which in turn corresponds to the ratio of the upper limit voltage to the output voltage. A conversion circuit connected to the output of the overvoltage or undervoltage protection circuit converts the voltage pulse sequence into a filtered analog voltage. The filtered analog voltage is received as the regulation variable in the regulator; as well as The output voltage is adjusted to a preset desired voltage by comparing the filtered analog voltage with the output voltage of the voltage regulation circuit, wherein the preset desired voltage is between the upper limit voltage and the lower limit voltage.

11. The method according to claim 10, The conversion described therein has a low-pass filter.

12. The method according to claim 10, The aforementioned conversion has the following characteristics: phase reversal.

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