Memory devices, methods of operating the devices, and non-volatile machine-readable media

Abstract

Memory devices, methods of operating the devices, and non-transitory machine- readable media configured to intentionally degrade NAND performance when a value of a NAND health metric indicates that it can be likely that a user will not replace or back up their device before data loss occurs are disclosed in some examples. For example, the system can track a NAND health metric, and when the metric reaches a predetermined threshold or state, the system can intentionally degrade performance. This performance degradation can be more effective than a warning to implement device backup or replacement.

Description

[0001] Information related to divisional application

[0002] This case is a divisional application. The parent application of this divisional application is the invention patent application filed on October 31, 2018, with application number 201811290586.4 and entitled "Memory device, method of operating the device and non-volatile machine-readable medium". Technical Field

[0003] This invention generally relates to memory devices, and more specifically to EOL performance throttling for preventing data loss. Background Technology

[0004] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory.

[0005] Volatile memory requires power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM).

[0006] Non-volatile memory can retain stored data when no power is supplied and includes flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), static RAM (SRAM), erasable programmable ROM (EPROM), and resistive variable memory, such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), or 3D XPoint. TM Memory, etc.

[0007] Flash memory is used as a non-volatile memory for a variety of electronic applications. Flash memory devices typically contain one or more sets of single-transistor, floating-gate, or charge-well memory cells, which allow for high memory density, high reliability, and low power consumption.

[0008] Two common types of flash memory array architectures include NAND and NOR architectures, named after the logical form of the basic memory cell configuration in which each is arranged. The memory cells of a memory array are typically arranged in a matrix. In one example, the gate of each floating-gate memory cell in a row of the array is coupled to an access line (e.g., a word line). In a NOR architecture, the drain of each memory cell in a column of the array is coupled to a data line (e.g., a bit line). In a NAND architecture, the drain of each memory cell in a string of the array is coupled together in series between the source line and the bit line in a source-to-drain manner.

[0009] Both NOR and NAND architecture semiconductor memory arrays are accessed via a decoder that activates a specific memory cell by selecting a word line coupled to its gate. In a NOR architecture semiconductor memory array, once activated, the selected memory cell places its data value on the bit line, resulting in different current flows depending on the programmed state of the particular cell. In a NAND architecture semiconductor memory array, a high bias voltage is applied to the drain-side selected gate (SGD) line. Word lines coupled to the gates of unselected memory cells in each group are driven with a specified pass-through voltage (e.g., Vpass) to operate each group of unselected memory cells as pass transistors (e.g., passing current regardless of the data value they store). Current then flows from the source line to the bit line through each series-coupled group, limited only by the selected memory cell in each group, thereby placing the currently encoded data value of the selected memory cell on the bit line.

[0010] Each flash memory cell in a NOR or NAND architecture semiconductor memory array can be programmed individually or collectively to one or more programming states. For example, a single-level cell (SLC) can represent one of two programming states (e.g., 1 or 0) to represent a single bit of data.

[0011] However, flash memory cells can also represent one of more than two programmed states, allowing for the manufacture of higher-density memory without increasing the number of memory cells, since each cell can represent more than one binary digit (e.g., more than one bit). Such cells can be called multi-state memory cells, multi-bit cells, or multi-level cells (MLCs). In some instances, an MLC can refer to a memory cell that can store two bits of data per cell (e.g., one of four programmed states), a three-level cell (TLC) can refer to a memory cell that can store three bits of data per cell (e.g., one of eight programmed states), and a four-level cell (QLC) can store four bits of data per cell. MLC is used in its broader context here to refer to any memory cell that can store more than one bit of data per cell (i.e., can represent more than two programmed states).

[0012] Traditional memory arrays are two-dimensional (2D) structures arranged on the surface of a semiconductor substrate. To increase storage capacity in a given area and reduce cost, the size of individual memory cells has been reduced. However, there are technological limitations to further reducing the size of individual memory cells and thus the memory density of 2D memory arrays. In response, three-dimensional (3D) memory structures, such as 3D NAND architecture semiconductor memory devices, are being developed to further increase memory density and reduce memory costs.

[0013] Such 3D NAND devices typically include strings of memory cells (e.g., drain-to-source) coupled in series between one or more source-side selected gates (SGS) near the source, and one or more drain-side selected gates (SGDs) near the bit lines. In one example, the SGS or SGD may comprise one or more field-effect transistor (FET) or metal-oxide-semiconductor (MOS) structure devices, etc. In some examples, the strings will extend vertically through multiple vertically spaced layers containing corresponding word lines. Semiconductor structures (e.g., polysilicon structures) may extend near a string of memory cells to form channels for the memory cells of the string. In examples of vertical strings, the polysilicon structure may be in the form of vertically extending pillars. In some examples, the strings may be “folded” and thus arranged relative to U-shaped pillars. In other examples, multiple vertical structures may be stacked on top of each other to form a stacked array of memory cell strings.

[0014] Memory arrays or devices can be combined to form the storage volume of a memory system, such as solid-state drives (SSDs) and universal flash memory (UFS). TM Multimedia Card (MMC) solid-state storage device, embedded MMC device (eMMC) TM SSDs can be used as the main storage device for computers, offering advantages over traditional hard drives with moving parts in terms of performance, size, weight, robustness, operating temperature range, and power consumption. For example, SSDs can have reduced seek time, latency, or other latency associated with disk drives (e.g., electromechanical). SSDs use non-volatile memory cells (such as flash memory cells) to eliminate the need for an internal battery supply, allowing for more versatile and compact drives.

[0015] An SSD may contain multiple memory devices, multiple dies or logical units (e.g., a number of logical units or LUNs), and may contain one or more processors or other controllers that perform the logical functions required to operate the memory devices or interface with external systems. Such an SSD may contain one or more flash memory dies with multiple memory arrays and peripheral circuitry on them. Flash memory arrays may contain multiple blocks of memory cells organized into multiple physical pages. In many instances, the SSD will also contain DRAM or SRAM (or other forms of memory dies or other memory structures). The SSD may receive commands from the host in association with memory operations, such as read or write operations transferring data (e.g., user data and associated integrity data, such as error data and address data) between the memory devices and the host, or erase operations erasing data from the memory devices. Summary of the Invention

[0016] According to an embodiment of the present invention, a NAND memory device includes: a NAND memory array including a first memory pool; and a controller that executes instructions to cause the controller to perform operations including: monitoring a NAND device health metric; determining that the NAND device health metric conforms to a degradation criterion indicating that a NAND device degradation has occurred; and, in response to determining that the NAND device health metric conforms to the degradation criterion, intentionally slowing down the processing of subsequent read operations or subsequent write operations on the NAND memory device by an amount calculated by the controller based on the health metric of the NAND device to degrade the performance of subsequent read operations or subsequent write operations that read data from the NAND cells of the NAND memory array of the NAND memory device or write data to the NAND cells of the NAND memory array of the NAND memory device.

[0017] According to another embodiment of the present invention, a method for operating a NAND memory device includes: at a controller of the NAND memory device, the NAND memory device including a NAND memory array: monitoring a NAND device health metric of the NAND memory device; determining that the NAND device health metric conforms to a degradation criterion indicating that a NAND device degradation has occurred; and in response to determining that the NAND device health metric conforms to the degradation criterion, degrading the performance of subsequent read operations or subsequent write operations on the NAND memory device by intentionally slowing down the processing of subsequent read operations or subsequent write operations on the NAND memory device by an amount calculated by the controller based on the health metric of the NAND device.

[0018] According to another embodiment of the present invention, a non-volatile machine-readable medium includes instructions that, when executed by a controller of a NAND memory device including a NAND memory array, cause the controller to perform operations including: monitoring a NAND device health metric; determining that the NAND device health metric conforms to a degradation criterion indicating that a NAND device degradation has occurred; and, in response to determining that the NAND device health metric conforms to the degradation criterion, intentionally slowing down the processing of subsequent read operations or subsequent write operations on the NAND memory device by an amount calculated by the controller based on the health metric of the NAND device, thereby degrading the performance of subsequent read operations or subsequent write operations that read data from or write data to NAND cells of the NAND memory array of the NAND memory device. Attached Figure Description

[0019] In accompanying drawings that are not necessarily drawn to scale, the same reference numerals can describe similar components in different views. The same reference numerals with different letter suffixes can represent different instances of similar components. The accompanying drawings illustrate various embodiments discussed in this document by way of example and not limitation.

[0020] Figure 1 An example of an environment containing a memory device is shown.

[0021] Figure 2-3 A schematic diagram illustrating an example of a 3D NAND architecture semiconductor memory array is shown.

[0022] Figure 4 Illustrate an example block diagram of a memory module.

[0023] Figure 5 A flowchart illustrating a method for end-of-life performance throttling of user data according to some embodiments of the present invention is provided.

[0024] Figure 6 A flowchart illustrating a method for incorporating host commands for end-of-life performance throttling to preserve user data, according to some embodiments of the present invention.

[0025] Figure 7 A schematic diagram of a memory controller according to some embodiments of the present invention is shown.

[0026] Figure 8 It is a block diagram illustrating an example of a machine on which one or more embodiments may be implemented. Detailed Implementation

[0027] In some instances, methods, systems, memory devices, and machine-readable media are disclosed that are configured to intentionally degrade NAND performance when a NAND health metric indicates a potential inability to prompt a user to replace or back up their device before data loss occurs. For example, the system may track NAND health metrics, and when the metric reaches a predetermined threshold or state, the system may intentionally degrade performance. This performance degradation may achieve device backup or replacement more effectively than a warning.

[0028] Electronic devices, such as mobile electronic devices (e.g., smartphones, tablets, etc.), electronic devices for automotive applications (e.g., automotive sensors, control units, driver assistance systems, passenger safety or comfort systems, etc.), and Internet-connected appliances or devices (e.g., Internet of Things (IoT) devices, etc.), have different storage requirements depending on the type of electronic device, the environment in which it is used, performance expectations, etc.

[0029] Electronic devices can be broken down into several main components: a processor (e.g., a central processing unit (CPU) or other main processor); memory (e.g., one or more volatile or non-volatile random access memory (RAM) devices, such as dynamic RAM (DRAM), mobile or low-power dual data rate synchronous DRAM (DDR SDRAM), etc.); and storage devices (e.g., non-volatile memory (NVM) devices, such as flash memory, read-only memory (ROM), SSD, MMC, or other memory card structures or combinations, etc.). In some instances, electronic devices may include a user interface (e.g., a display, touchscreen, keyboard, one or more buttons, etc.), a graphics processing unit (GPU), power management circuitry, a baseband processor, or one or more transceiver circuits, etc.

[0030] Figure 1 An example of environment 100 is shown, which includes a host device 105 and a memory device 110 configured to communicate via a communication interface. The host device 105 or the memory device 110 may be included in various products 150, such as Internet of Things (IoT) devices (e.g., refrigerators or other appliances, sensors, motors or actuators, mobile communication devices, automobiles, drones, etc.) to support the processing, communication, or control of product 150.

[0031] Memory device 110 includes a memory controller 115 and a memory array 120, which includes, for example, multiple individual memory dies (e.g., a stack of three-dimensional (3D) NAND dies). In 3D architecture semiconductor memory technology, vertical structures are stacked, thereby increasing the number of layers, physical pages, and thus increasing the density of memory devices (e.g., storage devices). In one example, memory device 110 may be a discrete memory or storage device component of host device 105. In other examples, memory device 110 may be part of an integrated circuit (e.g., a system-on-a-chip (SoC) or the like), which is stacked or otherwise included in one or more other components of host device 105.

[0032] One or more communication interfaces may be used to transfer data between the memory device 110 and one or more other components of the host device 105, such as a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Fast (PCIe) interface, a Universal Serial Bus (USB) interface, a Universal Flash Memory (UFS) interface, and an eMMC interface. TM An interface or one or more other connectors or interfaces. Host device 105 may include a host system, electronic devices, a processor, a memory card reader, or one or more other electronic devices external to memory device 110. In some instances, host 105 may be a device with a reference... Figure 8 The machine 800 is a component of the machine that is discussed, either a part or all of it.

[0033] Memory controller 115 may receive instructions from host 105 and may communicate with the memory array, for example, to transfer data to (e.g., write or erase) or from (e.g., read) one or more memory cells, planes, sub-blocks, blocks, or pages of the memory array. Memory controller 115 may, in particular, include circuitry or firmware, comprising one or more components or integrated circuits. For example, memory controller 115 may include one or more memory control units, circuitry, or components configured to control access across memory array 120 and provide a translation layer between host 105 and memory device 110. Memory controller 115 may include one or more input / output (I / O) circuitry, lines, or interfaces to transfer data to or from memory array 120. Memory controller 115 may include memory manager 125 and array controller 135.

[0034] The memory manager 125 may include, in particular, circuitry or firmware, such as multiple components or integrated circuits associated with various memory management functions. For the purposes of this description, example memory operation and management functions will be described in the context of NAND memory. Those skilled in the art will recognize that other forms of non-volatile memory may have similar memory operation or management functions. Such NAND management functions include wear leveling (e.g., garbage collection or recycling), error detection or correction, block exit, or one or more other memory management functions. The memory manager 125 may parse or format host commands (e.g., commands received from a host) into device commands (e.g., commands associated with the operation of the memory array, etc.), or generate device commands (e.g., to implement various memory management functions) for one or more other components of the array controller 135 or memory device 110.

[0035] Memory manager 125 may include a set of management tables 130 configured to maintain various information associated with one or more components of memory device 110 (e.g., various information associated with a memory array or one or more memory cells coupled to memory controller 115). For example, management table 130 may contain information about block age, block erase count, error history, or one or more error counts (e.g., write operation error count, read bit error count, read operation error count, erase error count, etc.) of one or more blocks of memory cells coupled to memory controller 115. In some instances, a bit error may be termed an uncorrectable bit error if the number of detected errors in one or more error counts exceeds a threshold. Management table 130 may maintain counts of correctable or uncorrectable bit errors, etc.

[0036] The array controller 135 may in particular include circuitry or components configured to control memory operations associated with writing data to, reading data from, or erasing data from one or more memory cells of the memory device 110 coupled to the memory controller 115. Memory operations may be based on host commands (e.g., associated with wear leveling, error detection, or correction) received, for example, from the host 105 or generated internally by the memory manager 125.

[0037] Array controller 135 may include an error correction code (ECC) component 140, which may include an ECC engine or other circuitry configured to detect or correct errors associated with writing data to or reading data from one or more memory cells of memory device 110 coupled to memory controller 115. Memory controller 115 may be configured to proactively detect and recover from errors associated with various operations or data storage (e.g., bit errors, operational errors, etc.), while maintaining the integrity of data transferred between host 105 and memory device 110, or maintaining the integrity of stored data (e.g., using redundant RAID storage, etc.), and may remove (e.g., eject) failed memory resources (e.g., memory cells, memory arrays, pages, blocks, etc.) to prevent future errors.

[0038] Memory array 120 may contain a number of memory cells arranged, for example, in multiple devices, planes, sub-blocks, blocks, or pages. As an example, a 48GB TLC NAND memory device may contain 18,592 bytes (B) of data per page (16,384 + 2208 bytes), 1536 pages per block, 548 blocks per plane, and 4 or more planes per device. As another example, a 32GB MLC memory device (storing two bits of data per cell (i.e., 4 programmable states)) may contain 18,592 bytes (B) of data per page (16,384 + 2208 bytes), 1024 pages per block, 548 blocks per plane, and 4 planes per device, but requires only half the write time and twice the program / erase (P / E) cycles compared to the corresponding TLC memory device. Other examples may contain other numbers or arrangements. In some instances, the memory device or a portion thereof may be selectively operated in SLC mode or in a desired MLC mode (e.g., TLC, QLC, etc.).

[0039] During operation, data is typically written to or read from NAND memory device 110 in pages and erased in blocks. However, as needed, one or more memory operations (e.g., read, write, erase, etc.) can be performed on larger or smaller groups of memory cells. The data transfer size of NAND memory device 110 is typically referred to as a page, while the data transfer size of the host is typically referred to as a sector.

[0040] Although a single page of data can contain multiple bytes of user data (e.g., a data payload comprising multiple data sectors) and its corresponding metadata, the page size typically refers only to the number of bytes used to store the user data. As an example, a 4KB data page can contain 4KB of user data (e.g., 8 sectors assuming a sector size of 512B) and several bytes (e.g., 32B, 54B, 224B, etc.) of metadata corresponding to the user data, such as integrity data (e.g., error detection or correction code data), address data (e.g., logical address data, etc.), or other metadata associated with the user.

[0041] Different types of memory cells or memory arrays 120 can provide different page sizes, or may require different amounts of metadata associated with them. For example, different memory device types may have different bit error rates, which can result in different amounts of metadata required to ensure the integrity of data pages (e.g., a memory device with a higher bit error rate may require more bytes of error correction code data than a memory device with a lower bit error rate). As an example, a multi-level cell (MLC) NAND flash device can have a higher bit error rate than a corresponding single-level cell (SLC) NAND flash device. Therefore, an MLC device may require more metadata bytes for error data than a corresponding SLC device.

[0042] Figure 2 A schematic diagram of an example of a 3D NAND architecture semiconductor memory array 200 is shown, which includes multiple memory cell strings (e.g., first to third A0 memory strings 205A0-207A0 ... n Memory String 205A n -207A n The first to third B0 memory strings 205B0-207B0, the first to third B n Memory String 205B n -207B n etc., in blocks (e.g., block A201A, block B 201B, etc.) and sub-blocks (e.g., sub-block A0 201A0, sub-block A...). n 201A n Sub-block B0 201B0, Sub-block B n 201B n (etc.) organization. Memory array 200 represents a portion of a larger number of similar structures typically found in blocks, devices, or other cells of a memory device.

[0043] Each memory cell string contains a source line (SRC) 235 or a source-side selected gate (SGS) (e.g., first to third A0 SGS 231A0-233A0 ...n SGS 231A n -233A n First to third B0 SGS 231B0-233B0, first to third B n SGS 231B n -233B n (etc.) and drain-side selected gate (SGD) (e.g., first to third A0SGD 226A0-228A0, first to third A n SGD 226A n -228A n First to third B0 SGD 226B0-228B0, first to third B n SGD 226B n -228B n Multilayer charge storage transistors (e.g., floating gate transistors, charge trapping structures, etc.) are stacked in the Z direction from source to drain. Each string of memory cells in the 3D memory array can be arranged as a data line (e.g., bit line (BL) BL0-BL2 220-222) in the X direction and as a physical page in the Y direction.

[0044] Within a physical page, each layer represents a row of memory cells, and each string of memory cells represents a column. A sub-block may contain one or more physical pages. A block may contain multiple sub-blocks (or physical pages) (e.g., 128, 256, 384, etc.). Although shown here with two blocks, each with two sub-blocks, each sub-block with a single physical page, each physical page with three strings of memory cells, and each string with eight layers of memory cells, in other instances, the memory array 200 may contain more or fewer blocks, sub-blocks, physical pages, strings of memory cells, memory cells, or layers. For example, each string of memory cells may contain more or fewer layers (e.g., 16, 32, 64, 128, etc.), and one or more additional layers of semiconductor material (e.g., select gate, data line, etc.) above or below the charge storage transistors as needed. For example, a 48GB TLC NAND memory device may contain 18,592 bytes (B) of data per page (16,384+2208 bytes), 1536 pages per block, 548 blocks per plane, and 4 or more planes per device.

[0045] Each memory cell in the memory array 200 includes a control gate (CG) coupled to (e.g., electrically connected or otherwise operably connected to) an access line (e.g., word lines (WL) WL00-WL70 210A-217A, WL01-WL71 210B-217B, etc.), which, as needed, co-couples the control gates (CG) onto a specific layer or a portion of a layer. Specific layers in the 3D memory array, and specific memory cells in a corresponding string, can be accessed or controlled using appropriate access lines. Multiple sets of select gates can be accessed using various select lines. For example, the first to third A0 SGD 226A0-228A0 can be accessed using the A0 SGD line SGDA0225A0, and A... n SGD line SGDA n 225A n Accessing the first to third SGD 226A n -228A n You can use B0 SGD line SGDB0 225B0 to access the first to third B0 SGD lines 226B0-228B0, and you can use B n SGD line SGDB n 225B n Accessing the first to third B n SGD 226B n -228B n The first to third A0 gates, SGS 231A0-233A0, and the first to third A0 gates can be accessed using the gate select lines SGS0 230A and SGS 231A0-233A0. n SGS 231A n -233A n Furthermore, the first to third B0 SGS 231B0-233B0 and the first to third B0 can be accessed using the gate select lines SGS1 230B. n SGS 231B n -233B n .

[0046] In one example, memory array 200 may comprise multiple layers of semiconductor material (e.g., polysilicon, etc.) configured to couple a control gate (CG) or select gate (or a portion of a CG or select gate) to each memory cell of a corresponding layer of the array. A particular string of memory cells in the array can be accessed, selected, or controlled using a combination of bit lines (BLs) and select gates, and a particular memory cell in one or more layers of a particular string can be accessed, selected, or controlled using one or more access lines (e.g., word lines).

[0047] Figure 3This is an example schematic diagram illustrating a portion of a NAND architecture semiconductor memory array 300, which includes a plurality of memory cells 302 arranged in strings (e.g., first to third strings 305-307) and layers (e.g., illustrated as corresponding word lines (WL) WL0-WL7 310-317, drain-side selected gate (SGD) line 325, source-side selected gate (SGS) line 330, etc.) in a two-dimensional array, and a sense amplifier or device 360. For example, the memory array 300 may illustrate an example schematic diagram of a portion of a physical page of a memory cell in a 3D NAND architecture semiconductor memory device, for example... Figure 2 As shown in the image.

[0048] Each memory cell string is coupled to a source line (SRC) using a corresponding source-side select gate (SGS) (e.g., first to third SGS 331-333) and to a corresponding data line (e.g., first to third bit lines (BL) BL0-BL2 320-322) using a corresponding drain-side select gate (SGD) (e.g., first to third SGD 326-328). Although in Figure 3 The example is shown with 8 layers (e.g., using word lines (WL) WL0-WL7 310-317) and three data lines (BL0-BL2 326-328), but other examples may contain strings of memory cells with more or fewer layers or data lines as needed.

[0049] In a NAND architecture semiconductor memory array (e.g., instance memory array 300), the state of a selected memory cell 302 can be accessed by sensing current or voltage changes associated with a specific data line containing the selected memory cell. The memory array 300 can be accessed using one or more drivers (e.g., via control circuitry, one or more processors, digital logic, etc.). In an instance, one or more drivers can activate a specific memory cell or set of memory cells by driving a specific potential to one or more data lines (e.g., bit lines BL0-BL2), access lines (e.g., word lines WL0-WL7), or a selected gate, depending on the type of operation desired to be performed on the specific memory cell or set of memory cells.

[0050] To program or write data to a memory cell, a programming voltage (Vpgm) (e.g., one or more programming pulses, etc.) is applied to a selected word line (e.g., WL4), and thus to the control gate of each memory cell coupled to the selected word line (e.g., the first to third control gates (CG) 341-343 of the memory cell coupled to WL4). The programming pulse may begin, for example, at or near 15V, and in some instances, the magnitude may be increased during each programming pulse application. When the programming voltage is applied to the selected word line, a potential such as ground (e.g., Vss) may be applied to the data line (e.g., bit line) and substrate (and thus, the channel between the source and drain) of the target memory cell, resulting in a charge transfer from the channel to the floating gate of the target memory cell (e.g., direct injection or Fowler-Nordheim (FN) tunneling, etc.).

[0051] In contrast, a pass-through voltage (Vpass) can be applied to one or more word lines having memory cells not intended for programming, or a disable voltage (e.g., Vcc) can be applied to data lines (e.g., bit lines) having memory cells not intended for programming, to, for example, prevent charge transfer from the channel to the floating gate of these non-target memory cells. The pass-through voltage can be variable, depending on, for example, the proximity of the applied pass-through voltage to the word line intended for programming. The disable voltage may comprise a supply voltage (Vcc) relative to a ground potential (e.g., Vss), such as a voltage from an external source or power supply (e.g., a battery, AC-DC converter, etc.).

[0052] As an example, if a programming voltage (e.g., 15V or higher) is applied to a specific word line, such as WL4, a 10V pass-through voltage can be applied to one or more other word lines, such as WL3, WL5, etc., to prevent programming of non-target memory cells or to preserve values ​​stored on these memory cells that are not intended for programming. As the distance between the applied programming voltage and the non-target memory cells increases, the pass-through voltage required to prevent programming of the non-target memory cells can decrease. For example, with a 15V programming voltage applied to WL4, a 10V pass-through voltage can be applied to WL3 and WL5, an 8V pass-through voltage can be applied to WL2 and WL6, a 7V pass-through voltage can be applied to WL1 and WL7, and so on. In other examples, the pass-through voltage or the number of word lines can be higher or lower, more or fewer.

[0053] The sensing amplifier 360 coupled to one or more data lines (e.g., first, second, or third bit lines (BL0-BL2) 320-322) can detect the state of each memory cell in the corresponding data line by sensing the voltage or current on the specific data line.

[0054] Between the application of one or more programming pulses (e.g., Vpgm), a verification operation can be performed to determine whether the selected memory cell has reached its intended programming state. If the selected memory cell has reached its intended programming state, further programming can be prevented. If the selected memory cell has not yet reached its intended programming state, additional programming pulses can be applied. If, after a certain number of programming pulses (e.g., a maximum number), the selected memory cell, or the string, block, or page associated with such selected memory cell, has not reached its intended programming state, the selected memory cell can be marked as defective.

[0055] To erase a memory cell or a group of memory cells (e.g., erasure is typically performed in a block or sub-block), an erase voltage (Vers) (e.g., typically Vpgm) can be applied to the substrate of the memory cell targeted for erasure (and therefore the channel between the source and drain) (e.g., using one or more bit lines, select gates, etc.), while the word line of the target memory cell is held at a potential such as ground (e.g., Vss), resulting in a charge transfer from the floating gate of the target memory cell to the channel (e.g., direct injection or Fowler-Nordheim (FN) tunneling, etc.).

[0056] Figure 4 This diagram illustrates an example block diagram of a memory device 400 including a memory array 402 having a plurality of memory cells 404, and one or more circuits or components to provide communication with the memory array 402 or to perform one or more memory operations on the memory array 402. The memory device 400 may include a row decoder 412, a column decoder 414, a sense amplifier 420, a page buffer 422, a selector 424, input / output (I / O) circuitry 426, and a memory control unit 430.

[0057] The memory cells 404 of the memory array 402 can be arranged in blocks, such as first and second blocks 402A and 402B. Each block can contain sub-blocks. For example, the first block 402A can contain first and second sub-blocks 402A0 and 402A0. n The second block 402B may include the first and second sub-blocks 402B0 and 402B. n Each subblock may contain multiple physical pages, and each page contains multiple memory cells 404. Although shown here as having two blocks, each with two subblocks, and each subblock with multiple memory cells 404, in other instances, the memory array 402 may contain more or fewer blocks, subblocks, memory cells, etc. In other instances, the memory cells 404 may be arranged in multiple rows, columns, pages, subblocks, blocks, etc., and accessed using, for example, access lines 406, first data lines 410, or one or more select gates, source lines, etc.

[0058] The memory control unit 430 can control the memory operation of the memory device 400 based on one or more signals or instructions received on the control line 432, including one or more clock signals or control signals indicating the desired operation (e.g., write, read, erase, etc.), or address signals (A0-AX) received on one or more address lines 416. One or more devices external to the memory device 400 can control the values ​​of the control signals on the control line 432 or the address signals on the address lines 416. Examples of devices external to the memory device 400 may include, but are not limited to, a host, a memory controller, a processor, or other devices not connected to the memory device 400. Figure 4 One or more circuits or components are shown in the diagram.

[0059] The memory device 400 may use access lines 406 and first data lines 410 to transfer data to (e.g., write or erase) or to (e.g., read) one or more memory cells 404. Row decoder 412 and column decoder 414 may receive and decode address signals (A0-AX) from address lines 416, determine which memory cell 404 to access, and provide signals to access lines 406 (e.g., one or more of a plurality of word lines (WL0-WLm)) or first data lines 410 (e.g., one or more of a plurality of bit lines (BL0-BLn)) as described above.

[0060] The memory device 400 may include sensing circuitry, such as a sense amplifier 420, configured to determine the value of data on the memory cell 404 (e.g., read) or the value of data to be written to the memory cell 404 using a first data line 410. For example, in a selected string of memory cells 404, one or more sense amplifiers 420 may read the logic level in the selected memory cell 404 in response to a read current flowing through the selected string to the data line 410 in the memory array 402.

[0061] One or more devices external to memory device 400 may communicate with memory device 400 using I / O lines (DQ0-DQN) 408, address lines 416 (A0-AX) or control lines 432. Input / output (I / O) circuitry 426 may, for example, use I / O lines 408 to transfer data values ​​to or from memory device 400, for example, within or outside page buffer 422 or memory array 402, based on control lines 432 and address lines 416. Page buffer 422 may store data received from one or more devices external to memory device 400 before data is programmed into a relevant portion of memory array 402, or data read from memory array 402 before data is transmitted to one or more devices external to memory device 402.

[0062] Column decoder 414 can receive address signals (A0-AX) and decode them into one or more column select signals (CSEL1-CSELn). Selector 424 (e.g., selector circuitry) can receive column select signals (CSEL1-CSELn) and select data in page buffer 422 representing data values ​​to be read from or programmed into memory cell 404. The selected data can be transferred between page buffer 422 and I / O circuitry 426 using a second data line 418.

[0063] The memory control unit 430 may receive positive and negative power supply signals from an external source or power supply (e.g., an internal or external battery, an AC-DC converter, etc.), such as a supply voltage (Vcc) 434 and a negative power supply (Vss) 436 (e.g., ground potential). In some instances, the memory control unit 430 may include a regulator 428 to provide positive or negative power supply signals internally.

[0064] Blocks in a NAND memory device eventually fail after repeated program and erase cycles. Once these blocks fail, they are removed from the pool of available blocks and are no longer used. Typical NAND memory devices are over-produced—that is, more blocks are used to manufacture the device than are required to store the advertised capacity. These blocks are "spare" blocks used after other blocks wear out, or as extra space needed for garbage collection and other operations.

[0065] NAND memory cells have a limited number of write and erase cycles before they begin to wear out. To account for this, NAND devices are over-provisioned—having more memory cells than advertised. Even with this over-provisioning, NAND will no longer be written to once the memory cells have worn out sufficiently. If the NAND is used as the boot driver for the host device's operating system (O / S), then the O / S will not boot because it cannot write data to the NAND required during boot. For embedded NAND (e.g., NAND in mobile phones), recovering data on the NAND becomes impractical if the O / S cannot boot.

[0066] Through over-provisioning and other technologies, most users will never encounter NAND failure issues. Nevertheless, a small number of users may still have high usage rates and may experience NAND device failures. For example, some mobile phone applications have high NAND usage and can run continuously in the background. Other users may stream video or audio all day and thus continuously write low levels of data to the NAND. Various schemes have been tried to alert users to pending NAND failures involving messages and warnings. These schemes are generally ineffective.

[0067] In some instances, methods, systems, memory devices, and machine-readable media are disclosed that intentionally degrade NAND performance before data loss occurs, when NAND health metrics indicate a potential failure, to prompt users to replace or back up their devices. For example, the system may track NAND health metrics, and when the metrics reach predetermined thresholds or states, the system may intentionally degrade performance. Performance degradation may take the form of slower request processing. This may incentivize users to replace or at least back up their devices before any user data loss, and may be more effective than a warning.

[0068] In some instances, NAND health metrics can be the number of bad blocks currently observed in the NAND, an over-provisioning metric indicating the extent to which over-provisioned blocks are still available; a read error rate, write error rate, or both, measuring the number of read or write errors; a combination of the foregoing; and so on. In some instances, read performance may degrade, write performance may degrade, or both read and write performance may degrade. In some instances, certain usage profiles may indicate user backup attempts—if said usage profile is detected, the system can process those requests at full speed as a reward for users migrating their data from the failed NAND.

[0069] In some instances, degradation criteria indicate that a NAND device has undergone degradation (e.g., bad blocks, errors, etc.). Instance degradation criteria can be a threshold number of bad blocks, a minimum percentage or amount of over-provisioning, a read error rate threshold, a write error rate threshold, and so on.

[0070] In some instances, the severity of degradation can increase as NAND health metrics continue to indicate deteriorating NAND health. For example, a system might reduce the clock speed of the microprocessor executing the controller by 50% when the NAND detects that a health metric meets a first degradation criterion, and by 75% when the NAND detects that a health metric now meets a second NAND degradation criterion—where the second degradation criterion indicates a worse NAND health than the first. In some instances, instead of increasing the severity of degradation in response to deteriorating health metrics, or otherwise, the NAND device may modify the degradation operation. For example, a system might begin by degrading write performance, but also begin degrading read performance as NAND health deteriorates.

[0071] In some instances, to degrade NAND performance, NAND can introduce intentional latency, for example, by using timers, no-operation instructions, loops, etc., in the code that servicing read, write, or read and write requests. In other instances, NAND can reduce the bus frequency of the NAND microprocessor, causing the code handling read or write requests to run more slowly.

[0072] Turn now Figure 5 The diagram illustrates a flowchart of a method 500 for end-of-life performance throttling of user data storage according to some embodiments of the present invention. At operation 510, the NAND controller may monitor one or more health metrics indicating the normal state of the NAND. For example, the number of bad blocks, over-provisioning metrics, read error rate, etc.

[0073] At operation 520, the controller can determine whether health metrics meet one or more degradation criteria, and thus indicate a degradation status. Degradation criteria can be predetermined by the NAND designer and installed into the controller's firmware. In other instances, degradation criteria refer to those that can be changed or programmed by the host via a host interface (e.g., UFS). Instance degradation criteria include threshold numbers of bad blocks, minimum number or percentage of functional spare blocks (e.g., over-provisioning), read error rate thresholds, write error rate thresholds, and so on.

[0074] For example, a health metric could be the number of bad blocks. NAND can compare the current number of bad blocks with a degradation criterion (i.e., a predetermined threshold number of bad blocks) to determine if the current number of bad blocks exceeds the threshold. If the current number of bad blocks exceeds the threshold, then the health metric meets the degradation criterion. At operation 530, if the health metric meets the degradation criterion, the controller can degrade the performance of the NAND memory device. For example, this could be done by slowing down the clock speed of the NAND device's microprocessor, etc., by setting a deceleration flag that is checked before a read or write request is made by the NAND service.

[0075] Turn now Figure 6 A flowchart illustrating a method 600 for processing host commands for end-of-life performance throttling of user data according to some embodiments of the present invention is shown. At operation 610, the controller receives host commands. Examples of host commands include read commands, write commands, erase commands, etc. Host commands can be received from the host via a host interface. In some instances, host commands are queued, and operation 610 includes removing host commands from the queue.

[0076] At operation 620, the controller can check a deceleration flag. The flag can be set in the controller's working memory, stored in the NAND flash memory, stored in both working memory and the NAND flash memory, etc. If the flag is not set, the controller can process commands normally at operation 650. If the flag is set, the controller can determine whether the currently observed host activity resembles a profile of exempted NAND activity. Exempted NAND activity is activity exempt from performance degradation. For example, backup activity can be processed at full speed. The profile can be one or more of certain observed host request characteristics, such as command volume, command type, etc. For example, the profile of backup activity could contain a large number (e.g., greater than a predetermined threshold) of pending read requests in the host request queue. If the currently observed activity matches a profile of degrade-exempt activity, the system can process requests normally at operation 650. If the currently observed activity at operation 630 does not resemble a degrade-exempt profile, commands can be decelerated at operation 640.

[0077] As mentioned, in some instances, the controller may reduce the clock speed of the microprocessor on which it executes instead of having a flag (e.g., in...). Figure 5 (At operation 530), this can reduce the speed without checking the flag at operation 620. The controller can then check at operation 630 to determine if the observed activity matches the exempted activity profile, and at operation 650 increase the clock speed back to normal until the activity no longer matches the exempted activity profile. For example, at operation 640, the clock speed can be reduced again.

[0078] Figure 7 A schematic diagram of a memory controller 715 according to some embodiments of the present invention is shown. The memory controller 715 is an example of a memory controller 115, the memory manager 725 is an example of a memory manager 125, and the management table 730 may be an example of a management table 130. The controller 735 and the ECC 740 may be... Figure 1 Instances of controller 135 and ECC 140. Controller 735 includes a monitoring component 760 that monitors health metrics of the NAND. Monitoring component 760 can determine whether the health metric meets one or more degradation criteria. If the health metric meets one or more degradation criteria, monitoring component 760 can instruct read component 750 or write component to degrade performance. Queuing component 755 may include a host queue for queuing host commands. Read component 750 can service one or more read commands submitted to the queue by the host. Read component 750 can also degrade the performance of read operations in response to commands from monitoring component 760. Write component 745 can service one or more write commands submitted to the queue by the host. Write component 745 can also degrade the performance of write operations in response to commands from monitoring component 760.

[0079] Figure 8 A block diagram of an exemplary machine 800 is shown, on which any one or more of the techniques (e.g., methods) discussed herein can be executed. In alternative embodiments, machine 800 may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, machine 800 may operate as a server machine, a client machine, or both in a server-client network environment. In an example, machine 800 may act as a peer-to-peer (P2P) (or other distributed) network environment. Machine 800 may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, network device, IoT device, automotive system, or any machine capable of executing instructions (sequentially or otherwise) specifying the actions to be taken by said machine. Furthermore, although only a single machine is shown, the term "machine" should also be considered as any collection of machines that individually or jointly execute a set (or more) of instructions to perform any one or more methods discussed herein (such as cloud computing, Software as a Service (SaaS), other computer cluster configurations).

[0080] As described herein, an instance may comprise, or be operated by, logic, components, devices, packages, or mechanisms. A circuit is a collection (e.g., a group) of circuits implemented in a tangible entity, comprising hardware (e.g., simple circuits, gates, logic, etc.). Circuit membership may become flexible over time and form the basis of hardware variability. A circuit contains members that can perform specific tasks when operated, individually or in combination. In an instance, the hardware of a circuit may be immutably designed to perform a specific operation (e.g., hardwired). In an instance, the hardware of a circuit may comprise physically connected components (e.g., execution units, transistors, simple circuits, etc.) and computer-readable media containing physically modified (e.g., magnetic, electrical, placement of movable, invariant aggregated particles, etc.) instructions to encode specific operations. When connecting physical components, the underlying electrical properties of the hardware components, for example, change from insulators to conductors and vice versa. The instructions enable participating hardware (e.g., execution units or loading mechanisms) to create members of the circuit in the hardware through variable connections to perform a specific task when operated. Therefore, when the device is operating, it can be communicatively coupled to other components of the circuit via computer-readable media. In this example, any physical component can be used in more than one member of more than one circuit. For instance, during operation, an execution unit can be used in a first circuit of a first circuit at one point in time and reused by a second circuit in the first circuit, or reused by a third circuit in the second circuit at a different time.

[0081] Machine (e.g., computer system) 800 (e.g., host device 105, memory device 110, etc.) may include a hardware processor 802 (e.g., a central processing unit (CPU), graphics processing unit (GPU), hardware processor core, or any combination thereof, such as memory controller 115, etc.), main memory 804, and static memory 806, some or all of which may communicate with each other via interconnect links (e.g., bus 808). Machine 800 may also include a display unit 810, an alphanumeric input device 812 (e.g., keyboard), and a user interface (UI) navigation device 814 (e.g., mouse). In an example, display unit 810, input device 812, and UI navigation device 814 may be a touch screen display. Machine 800 may additionally include a storage device (e.g., drive unit) 816, a signal generation device 818 (e.g., speaker), a network interface device 820, and one or more sensors 816, such as a global positioning system (GPS) sensor, compass, accelerometer, or other sensors. Machine 800 may include an output controller 828, for example, a serial (e.g., Universal Serial Bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC) etc.) connection to communicate with or control one or more peripheral devices (e.g., printer, card reader, etc.).

[0082] Storage device 816 may include machine-readable medium 822 storing one or more data structures or instruction sets 824 (e.g., software) that embody or are used by any one or more of the technologies or functions described herein. Instructions 824 may also reside wholly or at least partially within main memory 804, static memory 806, or hardware processor 802 during execution by machine 800. In an example, one or any combination of hardware processor 802, main memory 804, static memory 806, or storage device 816 may constitute machine-readable medium 822.

[0083] Although machine-readable media 822 is shown as a single medium, the term "machine-readable media" may include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) configured to store the one or more instructions 824.

[0084] The term "machine-readable media" can include any medium capable of storing, encoding, or carrying instructions for execution by machine 800 and causing machine 800 to perform any one or more of the technologies disclosed herein, or any medium capable of storing, encoding, or carrying data structures used by or associated with such instructions. Non-limiting examples of machine-readable media can include solid-state memory as well as optical and magnetic media. In examples, a collection of machine-readable media includes machine-readable media having a plurality of particles having invariant (e.g., rest) masses. Therefore, the collection of machine-readable media is not a transient propagation signal. Specific examples of a collection of machine-readable media can include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0085] Instructions 824 (e.g., software, programs, operating system (OS), etc.) or other data stored on storage device 821 can be accessed by memory 804 for use by processor 802. Memory 804 (e.g., DRAM) is typically fast but volatile, and is therefore a different type of storage device from storage device 821 (e.g., SSD), suitable for long-term storage, including when in a "shutdown" state. Instructions 824 or data used by user or machine 800 are typically loaded into memory 804 for use by processor 802. When memory 804 is full, virtual space from storage device 821 can be allocated to supplement memory 804. However, because storage device 821 is typically slower than memory 804, and write speeds are typically at least twice as fast as read speeds, using virtual memory can significantly reduce user experience due to storage device latency (compared to memory 804, e.g., DRAM). Furthermore, using storage device 821 for virtual memory can significantly reduce the available lifespan of storage device 821.

[0086] In contrast to virtual memory, virtual memory compression (e.g., The kernel feature “ZRAM” uses a portion of memory as compressed blocks to avoid paging of storage device 821. Paging occurs within the compressed blocks until it is necessary to write such data to storage device 821. Virtual memory compression increases the available size of memory 804 while reducing wear on storage device 821.

[0087] Storage devices optimized for mobile electronic devices or mobile storage traditionally include MMC solid-state storage devices (e.g., microSD cards). TM) (e.g., cards). MMC devices contain multiple parallel interfaces (e.g., 8-bit parallel interfaces) and a host device, and are typically removable and separate from the host device. In contrast, eMMC... TM The device is connected to the circuit board and is considered a component of the host device; its read speed is comparable to that based on Serial ATA. TM Comparable to SSDs using Serial ATA (Advanced Technology) accessories or SATA. However, the demand for mobile device performance continues to increase, such as fully enabling virtual or augmented reality devices and taking advantage of increased network speeds. In response to this demand, storage devices have shifted from parallel communication interfaces to serial communication interfaces. Universal Flash Memory (UFS) devices (including the controller and firmware) communicate with the host device using a Low Voltage Differential Signaling (LVDS) serial interface with dedicated read / write paths, thereby further improving read / write speeds.

[0088] Instruction 824 can also be transmitted or received via network interface device 820 on a communication network 826 using a transmission medium, utilizing any of a variety of transport protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.). Example communication networks may include local area networks (LANs), wide area networks (WANs), packet data networks (e.g., the Internet), mobile phone networks (e.g., cellular networks), conventional telephone (POTS) networks, and wireless data networks (e.g., the Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard series, which is known as…). The IEEE 802.16 standard series is known as... This includes standards such as the IEEE 802.15.4 series and peer-to-peer (P2P) networks. In an example, network interface device 820 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas to connect to communication network 826. In an example, network interface device 820 may include multiple antennas to perform wireless communication using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technologies. The term "transmission medium" should be considered as any intangible medium capable of storing, encoding, or carrying instructions executable by machine 800, and includes digital or analog communication signals or other intangible media to facilitate communication of such software.

[0089] The above detailed description includes reference to the accompanying drawings, which form part of the detailed description. The drawings illustrate specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as "examples". These examples may include elements other than those shown or described. However, the inventors also contemplate examples where only those elements shown or described are provided. Furthermore, the inventors also contemplate examples using any combination or substitution of those elements (or aspects thereof) shown or described with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0090] In this document, the term "a / an" is common in patent literature and includes one or more, independent of any other instances or uses of "at least one" or "one or more". In this document, the term "or" is used to indicate non-exclusivity, such that "A or B" may include "A but not B", "B but not A", and "A and B" unless otherwise stated. In the appended claims, the terms "comprising" and "wherein" are used as their common English equivalents. Furthermore, in the following claims, the terms "comprising" and "including" are open-ended, meaning that a system, apparatus, article, or process that includes elements other than those listed after such terms in the claims is still considered to be within the scope of the claims. Additionally, in the following claims, the terms "first", "second", and "third", etc., are used merely as designations and are not intended to impose numerical requirements on their objects.

[0091] In various instances, the components, controllers, processors, units, engines, or tables described herein may include physical circuitry or firmware stored on a physical device. As used herein, "processor" means any type of computing circuitry, such as, but not limited to, a microprocessor, microcontroller, graphics processor, digital signal processor (DSP), or any other type of processor or processing circuitry, comprising a set of processors or a multi-core device.

[0092] As used herein, the term "horizontal" is defined as a plane parallel to a conventional plane or surface of the substrate, such as the plane beneath a wafer or die, regardless of the actual orientation of the substrate at any point in time. The term "vertical" refers to a direction perpendicular to the horizontal plane as defined above. Prepositions such as "on," "above," and "below" are defined relative to a conventional plane or surface located on top of or exposed on the substrate, regardless of the substrate's orientation. "On" is intended to indicate direct contact between one structure and another structure situated thereon (unless explicitly indicated otherwise); the terms "above" and "below" are explicitly intended to identify the relative placement of structures (or layers, features, etc.) that explicitly include, but are not limited to, direct contact between the identified structures, unless explicitly stated otherwise. Similarly, the terms "above" and "below" are not limited to horizontal orientation, because if a structure is the outermost part of the construction under discussion at a certain point in time, then said structure may be "above" a reference structure, even if such a structure extends vertically rather than horizontally relative to the reference structure.

[0093] The terms “wafer” and “substrate” as used herein generally refer to any structure on which an integrated circuit is formed, and also to such structures during the various stages of integrated circuit manufacturing. Therefore, the following detailed description should not be considered limiting, and the scope of the various embodiments is defined only by the appended claims and the full scope of their equivalents.

[0094] Various embodiments of the present invention, and described herein, include memories utilizing vertical structures of memory cells (e.g., NAND strings of memory cells). As used herein, directional adjectives will be relative to the surface of the substrate on which the memory cells are formed (i.e., the vertical structure will be considered as extending away from the substrate surface, the bottom end of the vertical structure will be considered as the end closest to the substrate surface, and the top end of the vertical structure will be considered as the end farthest from the substrate surface).

[0095] As used herein, unless otherwise stated, directional adjectives such as horizontal, vertical, normal, parallel, perpendicular, etc., may refer to relative orientation and are not intended to require strict adherence to specific geometric properties. For example, as used herein, a vertical structure does not need to be strictly perpendicular to the surface of the substrate, but may instead generally be perpendicular to the surface of the substrate and may form an acute angle with the surface of the substrate (e.g., between 60 and 120 degrees, etc.).

[0096] In some embodiments described herein, different doping configurations can be applied to the source-side selected gate (SGS), control gate (CG), and drain-side selected gate (SGD), each of which in this example may be formed of or at least contain polysilicon, resulting in these layers (e.g., polysilicon, etc.) having different etch rates when exposed to an etch solution. For example, during the formation of monolithic pillars in a 3D semiconductor device, SGS and CG can form grooves, while SGD can retain fewer or no grooves. Therefore, these doping configurations can be selectively etched into different layers (e.g., SGS, CG, and SGD) in a 3D semiconductor device using an etch solution (e.g., tetramethylammonium hydroxide (TMCH)).

[0097] As used herein, operating a memory cell includes reading from a memory cell, writing to a memory cell, or erasing a memory cell. The operation of placing a memory cell in a desired state is referred to herein as “programming” and may include writing to or erasing from a memory cell (e.g., a memory cell may be programmed to an erase state).

[0098] According to one or more embodiments of this disclosure, a memory controller (e.g., processor, controller, firmware, etc.) located inside or outside the memory device can determine (e.g., select, set, adjust, calculate, change, clear, communicate, adjust, derive, define, utilize, modify, apply, etc.) a certain number of wear cycles or wear states (e.g., record wear cycles, calculate the operation of the memory device while the memory device is operating, track the operation of the memory device that it initiates, evaluate the characteristics of the memory device corresponding to the wear state, etc.).

[0099] According to one or more embodiments of this disclosure, a memory access device can be configured to provide wear cycle information to a memory device for each memory operation. Memory device control circuitry (e.g., control logic) can be programmed to compensate for memory device performance variations corresponding to the wear cycle information. The memory device can receive the wear cycle information and determine one or more operating parameters (e.g., values, characteristics) in response to the wear cycle information.

[0100] It should be understood that when a component is referred to as "on another component," "connected to another component," or "coupled to another component," it can be directly on, connected to, or coupled to another component, or an intermediate component may exist. Conversely, when a component is referred to as "directly on another component," "directly connected to another component," or "directly coupled to another component," no intermediate component or layer exists. If two components are shown in the accompanying drawings as connected by a line, then unless otherwise stated, the two components may be coupled or directly coupled.

[0101] The methods described herein may be implemented, at least in part, by a machine or computer. Some examples may include computer-readable or machine-readable media encoded with instructions operable to configure an electronic device to perform the methods described in the examples above. Implementations of these methods may include code, such as microcode, assembly language code, higher-level language code, etc. Such code may contain computer-readable instructions for performing various methods. The code may form part of a computer program product. Furthermore, the code may be tangibly stored on one or more volatile or non-volatile tangible computer-readable media, for example, during execution or at other times. Examples of such tangible computer-readable media may include, but are not limited to, hard disks, removable disks, removable optical discs (e.g., optical discs and digital video discs), magnetic tapes, memory cards or sticks, random access memory (RAM), read-only memory (ROM), solid-state drives (SSDs), universal flash memory (UFS) devices, embedded MMC (eMMC) devices, etc.

[0102] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used by those skilled in the art after reading the above description. It is understood at the time of filing that it is not intended to interpret or limit the scope or meaning of the claims. Moreover, in the above detailed description, various features may be combined together to simplify this disclosure. This should not be construed as an intention that any unclaimed features of the disclosure are essential to any claim. Rather, the subject matter of the invention may lie in fewer than all features of a particular disclosed embodiment. Therefore, the following claims are incorporated herein by reference, wherein each claim is itself an individual embodiment, and these embodiments are contemplated to be combined with each other in various combinations or substitutions. The scope of the invention should be determined by reference to the appended claims and the full scope of the equivalents conferred by those claims.

Claims

1. A memory device comprising: A memory array, which comprises multiple memory cells; A memory controller configured to perform operations including the following: Monitor the operational metrics of the memory device; Determine whether the operational metric meets a specified condition, which indicates that memory device degradation has occurred; In response to determining that the operating metric conforms to the specified condition, the memory controller reduces the performance of the memory device; Receive host requests; Determine whether the host request corresponds to a backup operation; as well as In response to determining that the host request corresponds to the backup operation, the performance of the memory device is avoided by the memory controller when serving the host request.

2. The memory device of claim 1, wherein the operation of reducing the performance of the memory device by the memory controller includes reducing the operating frequency of the memory controller.

3. The memory device of claim 1, wherein the operation of reducing the performance of the memory device by the memory controller includes introducing an intentional delay when servicing at least one of a read request and a write request.

4. The memory device of claim 1, wherein the operation of determining whether the host request corresponds to the backup operation includes comparing the number of pending read requests with a defined threshold; and The operation of determining that the host request corresponds to the backup operation includes determining that the number of pending read requests exceeds the defined threshold.

5. The memory device of claim 1, wherein the operational metric includes the number of defective blocks.

6. The memory device of claim 1, wherein the operational metric includes an over-provisioning metric indicating the extent to which over-provisioned blocks are still available.

7. The memory device of claim 1, wherein the operation metric includes a read error metric.

8. The memory device of claim 1, wherein the operational metric includes a write error metric.

9. The memory device of claim 1, wherein the operational metric includes at least two of the following: the number of bad blocks, an over-provisioning metric indicating the extent to which over-provisioned blocks are still available, a read error metric, or a write metric.

10. A method for controlling a memory device, the method comprising: Monitor the operational metrics of the memory device; Determine whether the operational metric meets a specified condition, which indicates that memory device degradation has occurred; as well as In response to determining that the operating metric conforms to the specified condition, the performance of the memory device is reduced via the memory controller; Receive host requests; Determine whether the host request corresponds to a backup operation; as well as In response to determining that the host request corresponds to the backup operation, the performance of the memory device is avoided by the memory controller when serving the host request.

11. The method of claim 10, wherein reducing the performance of the memory device by the memory controller includes reducing the operating frequency of the memory controller.

12. The method of claim 10, wherein reducing the performance of the memory device by the memory controller includes introducing an intentional delay when servicing at least one of a read request and a write request.

13. The method of claim 10, wherein determining whether the host request corresponds to the backup operation comprises comparing the number of pending read requests with a defined threshold; and Determining that the host request corresponds to the backup operation includes determining that the number of pending read requests exceeds the defined threshold.

14. The method of claim 10, wherein the operational metric includes the number of defective blocks.

15. The method of claim 10, wherein the operational metric includes an over-provisioning metric indicating the extent to which over-provisioned blocks are still available.

16. The method of claim 10, wherein the operational metric includes a read error metric.

17. The method of claim 10, wherein the operational metric includes a write error metric.

18. The method of claim 10, wherein the operational metric comprises at least two of the following: the number of bad blocks, an over-provisioning metric indicating the extent to which over-provisioned blocks are still available, a read error metric, or a write metric.

Images