Multilayer ceramic capacitor

Abstract

The present disclosure provides a multilayer ceramic capacitor. The multilayer ceramic capacitor includes a ceramic main body including dielectric layers, a first internal electrode, and a second internal electrode disposed opposite each other with the dielectric layers interposed therebetween, and a first external electrode and a second external electrode. The ceramic main body further includes a first edge portion and a second edge portion, and a first cover portion and a second cover portion disposed on upper and lower surfaces of a capacitance forming portion and upper and lower surfaces of the first and second edge portions, respectively. The first and second cover portions each include a first cover layer adjacent to an internal electrode disposed on an outermost side among the first and second internal electrodes, a second cover layer disposed on the first cover layer, and an interface at which the first and second cover layers contact each other.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2020-0149551, filed on November 10, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a multilayer ceramic capacitor. Background Technology

[0003] Typically, electronic components using ceramic materials (such as capacitors, inductors, piezoelectric elements, varistors, thermistors, etc.) may include a ceramic body made of ceramic material, an internal electrode formed in the ceramic body, and an external electrode mounted on the surface of the ceramic body to connect to the internal electrode.

[0004] Recently, as electronic products have become smaller and more multifunctional, chip assemblies have also been miniaturized and made more functional. Therefore, there is a need to reduce the size of multilayer ceramic capacitors and increase their capacitance.

[0005] Typically, the area of ​​the dielectric layer is formed to be larger than the area of ​​the inner electrode, and an edge region is formed in the peripheral portion of the inner electrode, except for the portion where the inner electrode connects to the outer electrode. However, in this case, when tens to hundreds of dielectric layers are stacked, the dielectric layers are stretched to fill the step difference portion, and the inner electrode is also bent. When the inner electrode is bent, there may be a problem that the breakdown voltage (BDV) will decrease in the corresponding portion.

[0006] To address this issue, a method for separately preparing and attaching sheet-like edges has recently been used. However, when forming edges by attaching separately manufactured sheets, the following problem arises: delamination occurs between the edge and the ceramic body. Summary of the Invention

[0007] One aspect of this disclosure is to provide a multilayer ceramic capacitor with improved moisture resistance reliability.

[0008] Another aspect of this disclosure is to provide a multilayer ceramic capacitor with improved mechanical strength.

[0009] According to one aspect of this disclosure, a multilayer ceramic capacitor includes: a ceramic body including a dielectric layer and a first inner electrode and a second inner electrode, the first inner electrode and the second inner electrode being disposed opposite each other and the dielectric layer being disposed therebetween, and the ceramic body including a first surface and a second surface opposite each other in a first direction, a third surface and a fourth surface opposite each other in a second direction, and a fifth surface and a sixth surface opposite each other in a third direction; a first outer electrode disposed on the first surface of the ceramic body and connected to the first inner electrode; and a second outer electrode disposed on the second surface of the ceramic body and connected to the second inner electrode. The ceramic body further includes: a capacitor forming portion including the first inner electrode and the second inner electrode stacked in the third direction, and the dielectric layer being disposed between the first inner electrode and the second inner electrode to form a capacitor; a first edge portion and a second edge portion respectively disposed on the two surfaces of the capacitor forming portion in the second direction; and a first cover portion and a second cover portion respectively disposed on the two surfaces of the capacitor forming portion in the third direction, the first edge portion on the two surfaces of the third direction, and the second edge portion on the two surfaces of the third direction. Both the first cover portion and the second cover portion include a first cover layer adjacent to the outermost inner electrode of the first inner electrode and the second inner electrode, a second cover layer disposed on the first cover layer, and an interface in which the first cover layer and the second cover layer contact each other.

[0010] According to another aspect of this disclosure, a multilayer ceramic capacitor includes: a ceramic body including a dielectric layer, a first inner electrode and a second inner electrode, the first inner electrode and the second inner electrode being disposed opposite each other and the dielectric layer being disposed therebetween; and a first outer electrode and a second outer electrode disposed on two opposing surfaces of the ceramic body in a first direction and respectively connected to the first inner electrode and the second inner electrode. The ceramic body further includes: a capacitor forming portion including the first inner electrode and the second inner electrode stacked in a third direction with the dielectric layer disposed between the first inner electrode and the second inner electrode; a first edge portion and a second edge portion respectively disposed on two surfaces of the capacitor forming portion in a second direction, the second direction being orthogonal to the first direction and the third direction; and a first cover portion and a second cover portion respectively disposed on the two surfaces of the capacitor forming portion in the third direction, the first edge portion on the two surfaces of the third direction, and the second edge portion on the two surfaces of the third direction. Both the first cover portion and the second cover portion include two or more cover layers stacked in the third direction and have interfaces between adjacent layers of the two or more cover layers. Attached Figure Description

[0011] The above and other aspects, features and advantages of this disclosure will be more clearly understood by taking into account the accompanying drawings and the following detailed description, in which:

[0012] Figure 1 This is a perspective view schematically illustrating a multilayer ceramic capacitor according to an embodiment of the present disclosure.

[0013] Figure 2 It is shown schematically. Figure 1 A three-dimensional view of the ceramic body.

[0014] Figure 3 It is intercepted along line I-I' Figure 1 Cross-sectional view.

[0015] Figure 4 It is taken along line II-II' Figure 1 Cross-sectional view.

[0016] Figure 5 It is shown Figure 4 A cross-sectional view of a modified embodiment.

[0017] Figure 6 This is a schematic perspective view of a multilayer ceramic capacitor according to another embodiment of the present disclosure.

[0018] Figure 7 It is shown schematically. Figure 6 A three-dimensional view of the ceramic body.

[0019] Figure 8 It is intercepted along line I-I' Figure 6 Cross-sectional view.

[0020] Figure 9 It is taken along line II-II' Figure 6 Cross-sectional view.

[0021] Figure 10 It is shown Figure 9 A cross-sectional view of a modified embodiment.

[0022] Figure 11 This is a photograph of the covering portion where layering occurs within a conventional structure. Detailed Implementation

[0023] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, the present disclosure may be exemplified in many different forms and should not be construed as being limited to the specific embodiments set forth herein. Furthermore, embodiments of the present disclosure may be provided to describe the present disclosure more completely to those skilled in the art. Therefore, for clarity of description, the shape and size of the elements in the drawings may be exaggerated, and elements indicated by the same reference numerals in the drawings may be the same elements.

[0024] For clarity of this disclosure, parts irrelevant to the description have been omitted, and thicknesses have been enlarged to clearly indicate layers and regions. Throughout the specification, similar parts having the same function within the same area are indicated by similar reference numerals.

[0025] In this specification, expressions such as “having,” “may have,” “including,” “comprise,” “may include,” or “may contain” may refer to the presence of a corresponding feature (e.g., an element such as a number, function, action, or component) and do not exclude the presence of additional features.

[0026] In this specification, expressions such as “A and / or B”, “at least one of A and B”, or “one or more of A and B” may include all possible combinations of the items listed together. For example, “A and / or B”, “at least one of A and B”, or “one or more of A and B” may mean (1) including at least one A, (2) including at least one B, or (3) including all of at least one A and at least one B.

[0027] In the accompanying drawings, the X direction can be defined as a first direction, the L direction, or the length direction; the Y direction can be defined as a second direction, the W direction, or the width direction; and the Z direction can be defined as a third direction, the T direction, or the thickness direction.

[0028] This disclosure relates to a multilayer ceramic capacitor. Figures 1 to 5 This is a schematic diagram illustrating a multilayer ceramic capacitor according to an embodiment of the present disclosure. (Refer to...) Figures 1 to 5 According to an embodiment of the present disclosure, a multilayer ceramic capacitor 100 may include: a ceramic body 110, including a dielectric layer 111 and a first inner electrode 121 and a second inner electrode 122, wherein the first inner electrode 121 and the second inner electrode 122 are disposed opposite to each other and the dielectric layer 111 is disposed therebetween, and the ceramic body 110 includes a first surface S1 and a second surface S2 opposite to each other in a first direction (X direction), a third surface S3 and a fourth surface S4 opposite to each other in a second direction (Y direction), and a fifth surface S5 and a sixth surface S6 opposite to each other in a third direction (Z direction); a first outer electrode 131 disposed on the first surface S1 of the ceramic body 110 and connected to the first inner electrode 121; and a second outer electrode 132 disposed on the second surface S2 of the ceramic body 110 and connected to the second inner electrode 122.

[0029] In this configuration, the ceramic body 110 may further include: a capacitor forming portion comprising a first inner electrode 121 and a second inner electrode 122 stacked in a third direction (Z direction), with a dielectric layer 111 between the first inner electrode 121 and the second inner electrode 122 to form a capacitor; a first edge portion 114 and a second edge portion 115 respectively disposed on two surfaces of the capacitor forming portion in a second direction (Y direction); and a first cover portion 112 and a second cover portion 113 respectively disposed on two surfaces of the capacitor forming portion in a third direction (Z direction) and on two surfaces of the first edge portion 114 in a third direction (Z direction). The first cover portion 112 and the second cover portion 113 may each include a first cover layer 112a and 113a adjacent to the outermost inner electrode of the first inner electrode 121 and the second inner electrode 122, and a second cover layer 112b and 113b respectively disposed on the first cover layer 112a and 113a. The first cover portion 112 and the second cover portion 113 may each include an interface between the first cover layer 112a and the second cover layer 112b and an interface between the first cover layer 113a and the second cover layer 113b.

[0030] In the ceramic body 110 of this embodiment, the arrangement of the first covering portion 112 and the second covering portion 113 on the two surfaces of the capacitor forming portion in the third direction (Z direction), the first edge portion 114 on the two surfaces of the third direction (Z direction), and the second edge portion 115 on the two surfaces of the third direction (Z direction) means that the first edge portion 114 and the second edge portion 115 are first attached to the two surfaces of the capacitor forming portion in the second direction (Y direction), and then the first covering portion 112 and the second covering portion 113 are attached to the capacitor forming portion.

[0031] Figure 11 This is a photograph of the XY plane of a conventional multilayer ceramic capacitor. A traditional multilayer ceramic capacitor may have the following structure: a cover portion is attached above and below the capacitor forming portion, and then an edge portion is attached to cover the two side surfaces of the capacitor forming portion and the two side surfaces of the cover portion. In this case, the edge portion may widen during its manufacturing process. Figure 11 A multilayer ceramic capacitor with widened edges, as described above, is shown. Referring to the accompanying drawings, when delamination occurs in the edges, the inner electrodes can be directly exposed to external moisture, etc.

[0032] This disclosure may have the following structure: an edge portion is first attached to a capacitor forming portion, and then a cover portion is attached to it. The structure where the first cover portion 112 and the second cover portion 113 are attached to the two surfaces of the capacitor forming portion in the third direction (Z direction) where the first edge portion 114 and the second edge portion 115 are first attached can refer to a structure where the first cover portion 112 and the second cover portion 113 are arranged to cover the two surfaces of the capacitor forming portion in the third direction (Z direction), the two surfaces of the first edge portion 114 in the third direction (Z direction), and the two surfaces of the second edge portion 115 in the third direction (Z direction). In the structure of the cover portion being attached later as described above, even if delamination occurs in the attachment portion, the inner electrode cannot be immediately exposed to the outside because the cover portion may be separated first. For example, compared to conventional structures, this embodiment can greatly improve moisture resistance reliability.

[0033] In this embodiment, the first cover portion 112 and the second cover portion 113 of the ceramic body 110 may respectively include the interface between the first cover layer 112a and the second cover layer 112b and the interface between the first cover layer 113a and the second cover layer 113b. In this specification, the term "interface" may refer to a surface where two layers in contact with each other are configured to be distinguishable from each other. The term "distinguishable" may refer to a state where the properties of two layers differ from each other due to physical and / or chemical differences. For example, the first cover layers 112a and 113a and the second cover layers 112b and 113b may have different physical and / or chemical properties. The multilayer ceramic capacitor according to this disclosure may include first cover layers 112a and 113a and second cover layers 112b and 113b with different properties to prevent delamination and improve the mechanical reliability of the product. The interface can be visually confirmed by scanning electron microscopy (SEM) or the like, but is not limited thereto. When it is difficult to visually confirm the interface, the interface can be verified by analyzing the physical properties of the first and second cover layers.

[0034] In embodiments of this disclosure, the ceramic body 110 may include a capacitor forming portion, a first covering portion 112, a second covering portion 113, a first edge portion 114, and a second edge portion 115.

[0035] While there are no particular limitations on the specific shape of the ceramic body 110, as shown in the figure, the ceramic body 110 may have a hexahedral shape or a similar shape. Due to the shrinkage of the ceramic powder particles contained in the ceramic body 110 during the sintering process, the ceramic body 110 may not have a perfectly parallelepiped shape, but may have a generally hexahedral shape. If necessary, the ceramic body 110 may be rounded so that the corners are not angled. Rounding may be performed, for example, by tumbling, but is not limited to this.

[0036] In the capacitor forming section of the multilayer ceramic capacitor according to the present disclosure, dielectric layer 111, first internal electrode 121, and second internal electrode 122 may be stacked alternately. Dielectric layer 111, first internal electrode 121, and second internal electrode 122 may be stacked in a third direction (Z direction). The plurality of dielectric layers 111 used to form the capacitor forming section may be in a sintered state, and the boundaries between adjacent dielectric layers 111 may be integrated with each other such that the boundaries between them are not obvious without the use of a scanning electron microscope (SEM).

[0037] According to embodiments of this disclosure, the raw materials used to form the dielectric layer 111 are not limited, as long as sufficient capacitance can be obtained. For example, barium titanate-based materials, lead-based perovskite composite materials, strontium titanate-based materials, etc., can be used.

[0038] Furthermore, for the purposes of this disclosure, various ceramic additives, organic solvents, plasticizers, binders, dispersants, etc., as by-products can be added to powder particles such as barium titanate (BaTiO3) as the main component.

[0039] The dielectric layer 111 can be formed by adding additives as needed to a slurry comprising the main and secondary components described above, coating the slurry onto a carrier film, and drying the slurry to prepare multiple ceramic sheets. The ceramic sheets can be formed by using a doctor blade to fabricate the slurry into sheets with a thickness of several micrometers, but are not limited thereto.

[0040] The first inner electrode 121 and the second inner electrode 122 may be stacked such that their cross-sections are exposed from opposite ends of the ceramic body 110. Specifically, the first inner electrode 121 and the second inner electrode 122 may be exposed from two surfaces of the ceramic body 110 in a first direction (X direction), and the first inner electrode 121 may be exposed from the first surface S1 of the ceramic body 110, and the second inner electrode 122 may be exposed from the second surface S2 of the ceramic body 110.

[0041] The materials used to form the first internal electrode 121 and the second internal electrode 122 are not particularly limited. For example, conductive paste containing at least one of silver (Ag), palladium (Pd), gold (Au), platinum (Pt), nickel (Ni), copper (Cu), tin (Sn), tungsten (W), titanium (Ti) and alloys thereof can be used to form them.

[0042] The ceramic body 110 can be formed by alternately stacking ceramic green sheets on which a first internal electrode 121 is printed and ceramic green sheets on which a second internal electrode 122 is printed in the third direction (Z direction). Screen printing, gravure printing, and other printing methods can be used for the first and second internal electrodes, but are not limited to these methods.

[0043] In the multilayer ceramic capacitor 100 according to an embodiment of the present disclosure, a first external electrode 131 and a second external electrode 132 may be disposed on the outer surface of the ceramic body 110. The first external electrode 131 may be connected to a first internal electrode 121, and the second external electrode 132 may be connected to a second internal electrode 122.

[0044] The first external electrode 131 and the second external electrode 132 may also contain a conductive metal. The conductive metal may be at least one of copper (Cu), nickel (Ni), tin (Sn), palladium (Pd), platinum (Pt), gold (Au), silver (Ag), tungsten (W), titanium (Ti), lead (Pb), and alloys thereof, but is not limited thereto.

[0045] The multilayer ceramic capacitor 100 according to embodiments of the present disclosure may include a first cover portion 112 and a second cover portion 113, which are respectively disposed on two surfaces of the capacitor forming portion in the third direction (Z direction), two surfaces of the first edge portion 114 in the third direction (Z direction), and two surfaces of the second edge portion 115 in the third direction (Z direction). The first cover portion 112 and the second cover portion 113 may each include a first cover layer 112a and 113a adjacent to the outermost inner electrode of the first inner electrode 121 and the second inner electrode 122, and second cover layers 112b and 113b respectively disposed on the first cover layers 112a and 113a. The two surfaces of the capacitor forming portion in the third direction may be disposed on planes substantially the same as the two surfaces of the first edge portion and the two surfaces of the second edge portion in the third direction. Those skilled in the art will understand that the expression "substantially the same" means identical (located on the same plane) by allowing for process errors, positional deviations, and / or measurement errors that may occur during the manufacturing process.

[0046] According to embodiments of this disclosure, the maximum value of the width of the first covering portion 112 in the second direction (Y direction) or the maximum value of the width of the second covering portion 113 in the second direction (Y direction) may be substantially equal to the maximum value of the width of the ceramic body 110 in the second direction. Those skilled in the art will understand that the expression "substantially equal" means identical by allowing for process errors, positional deviations, and / or measurement errors that may occur in the manufacturing process.

[0047] The first capping layers 112a and 113a and the second capping layers 112b and 113b may include ceramic materials (e.g., barium titanate (BaTiO3) based ceramic materials).

[0048] The first capping layers 112a and 113a, as well as the second capping layers 112b and 113b, can all be formed by stacking a single dielectric layer or two or more dielectric layers in the vertical direction (e.g., the Z direction), and can substantially prevent damage to the inner electrode caused by physical or chemical stress.

[0049] According to embodiments of this disclosure, the average density of the second cover layers 112b and 113b included in the multilayer ceramic capacitor of this disclosure may be greater than the average density of the first cover layers 112a and 113a. In this specification, "average density" may refer to the average density of a sample taken from five (5) different locations, for example, it may be a value measured using a densitometer such as the Excellence D6 manufactured by METTLER TOLEDO. The second cover layers 112b and 113b of the multilayer ceramic capacitor 100 according to this disclosure may use materials with an average density greater than the average density of the first cover layers 112a and 113a to prevent cracks and other defects that may occur due to sintering mismatch during the sintering process, thereby improving reliability. Furthermore, the average density of the second cover layers 112b and 113b may be controlled to be greater than the average density of the first cover layers 112a and 113a to give the exposed portion of the cover layer higher strength, thereby improving moisture resistance reliability.

[0050] In one example, the thickness of an element may refer to the dimension of the element in a direction perpendicular to the flat surface of the element. Unless contradicting another explicitly described definition, the thickness of an element may be any of the average thickness, maximum thickness, minimum thickness, and the thickness of the element measured in a predetermined area. In one example, the thickness of an element may be determined by measuring the thickness of each of the points at equal (or alternatively, unequal) intervals to the left and to the right of a predetermined number (e.g., 5) points defined at equal intervals (or alternatively, unequal intervals) from a reference center point of the element, and obtaining an average value therefrom. Optionally, the thickness may be the maximum or minimum thickness measured multiple times. Optionally, the thickness may be the thickness at a reference center point in the measurement area. In one instance, an optical microscope or a scanning electron microscope (SEM) may be used in the measurement, but this disclosure is not limited thereto. Other measurement methods and / or tools understood by those skilled in the art may be used even if not described in this disclosure.

[0051] In embodiments of this disclosure, the maximum thickness of the second covering layer 112b or 113b included in the first covering portion 112 or the second covering portion 113 of this disclosure (e.g., Figure 4t2 in the figure can be 20% to 70% of the maximum thickness (e.g., t1+t2) of the first cover 112 or the second cover 113. The maximum thickness of the second cover 112b or 113b can be 70% or less, 65% or less, 60% or less, 55% or less, or 50% or less of the maximum thickness of the first cover 112 or the second cover 113. Since the density (e.g., average density) of the second cover 112b and 113b is greater than the density (e.g., average density) of the first cover 112a and 113a, thicknesses within the above range can be used to ensure sufficient moisture resistance reliability. When the maximum thickness of the second cover 112b or 113b is too thin, it may be difficult to ensure the desired moisture resistance reliability, and when the maximum thickness of the second cover 112b or 113b is too thick, it may be difficult to correct mismatches in the sintering process.

[0052] According to embodiments of this disclosure, the average grain size of the dielectric grains included in the second capping layer 112b or 113b may be greater than the average grain size of the dielectric grains included in the first capping layer 112a or 113a. In this specification, the “average grain size” of the dielectric grains may refer to the average length in the X-axis direction obtained by taking images at five (5) random locations on the XZ plane of the multilayer ceramic capacitor using a scanning electron microscope (SEM, Jeol's JSM-7400F), and then calculating the obtained images using an image analysis program (Mediacybernetics' ImagePro Plus ver 4.5).

[0053] During the sintering process, grain growth and densification can occur simultaneously in the dielectric. Therefore, as grain density increases, grain growth can also increase, leading to an increase in grain size. Conversely, when grain density decreases, grain growth can be suppressed to reduce grain size. Thus, the average grain size of the dielectric grains included in the second capping layer 112b or 113b, which has a relatively high dielectric density, can be greater than the average grain size of the dielectric grains included in the first capping layer 112a or 113a. This results in improved sintering mismatch and moisture resistance reliability.

[0054] In embodiments of this disclosure, the first cover layers 112a and 113a and the second cover layers 112b and 113b of the multilayer ceramic capacitor 100 according to this disclosure may include a ceramic composition having a composition similar to that of the dielectric layer 111 of the capacitor forming portion as a main component. In this specification, "main component" may refer to a component that occupies a relatively large weight percentage compared to other components, and may refer to a component that, based on the weight of the entire composition or the entire dielectric layer, can be 50% by weight or more. Additionally, "secondary component" may refer to a component that occupies a relatively small weight percentage compared to other components, and may refer to a component that, based on the weight of the entire composition or the entire dielectric layer, can be less than 50% by weight.

[0055] The principal component can be composed of (Ba 1-x Ca x (Ti) 1-y (Zr,Sn,Hf) y The main component is represented by BaTiO3 (where 0 ≤ x ≤ 1, 0 ≤ y ≤ 0.5). The main component can be, for example, a compound in which Ca, Zr, Sn, and / or Hf are partially dissolved in BaTiO3. In this formula, x is greater than or equal to 0 and less than or equal to 1, and y is greater than or equal to 0 and less than or equal to 0.5, but is not limited thereto. For example, when x is 0 and y is 0, the main component can be BaTiO3.

[0056] In an example, the first cover portion 112 and the second cover portion 113 of the multilayer ceramic capacitor 100 according to this disclosure may include one or more of the group consisting of sodium (Na), lithium (Li), and boron (B) as secondary components. In this case, in the first cover portion 112 and the second cover portion 113, the amount of Na, Li, and / or B contained in the second cover layer 112b or 113b may be greater than the amount of Na, Li, and / or B contained in the first cover layer 112a or 113a. The first cover portion 112 and the second cover portion 113 may be adjusted such that the amount of Na, Li, and / or B contained in the second cover layer 112b or 113b is greater than the amount of Na, Li, and / or B contained in the first cover layer 112a or 113a, thereby increasing the density of the second cover layers 112b and 113b of the first cover portion 112 and the second cover portion 113, thereby improving moisture resistance.

[0057] In another embodiment of this disclosure, the first cover portion 112 and the second cover portion 113 of the multilayer ceramic capacitor 100 according to this disclosure may include magnesium (Mg) as a secondary component. In this case, the amount of magnesium (Mg) contained in the first cover layer 112a or 113a of the first cover portion 112 and the second cover portion 113 may be greater than the amount of magnesium (Mg) contained in the second cover layer 112b or 113b. The first cover portion 112 and the second cover portion 113 may be adjusted such that the amount of magnesium (Mg) contained in the first cover layer 112a or 113a is greater than the amount of magnesium (Mg) contained in the second cover layer 112b or 113b, so as to increase the density of the second cover layers 112b and 113b of the first cover portion 112 and the second cover portion 113 compared with the first cover layers 112a and 113a, thereby improving moisture resistance.

[0058] According to a modified embodiment of the present disclosure, the first edge portion 114 and the second edge portion 115 included in the multilayer ceramic capacitor 100 of the present disclosure may respectively include first edge layers 114a and 115a adjacent to the first inner electrode 121 and / or the second inner electrode 122, and second edge layers 114b and 115b respectively disposed on the first edge layers 114a and 115a. The first edge portion 114 and the second edge portion 115 may respectively include the interface between the first edge layer 114a and the second edge layer 114b and the interface between the first edge layer 115a and the second edge layer 115b.

[0059] According to embodiments of the present disclosure, the average density of the second edge layer 114b or 115b included in the multilayer ceramic capacitor 100 of the present disclosure may be greater than the average density of the first edge layer 114a or 115a included in the multilayer ceramic capacitor 100.

[0060] In embodiments of this disclosure, the thickness of the second edge layer 114b or 115b included in the first edge portion 114 and the second edge portion 115 of this disclosure (e.g., Figure 5 d2) can be 20% to 70% of the maximum thickness (e.g., d, d1+d2) of the first edge portion 114 and the second edge portion 115, preferably 30% to 70%.

[0061] According to embodiments of this disclosure, the average grain size of the dielectric grains included in the second edge layer 114b or 115b may be larger than the average grain size of the dielectric grains included in the first edge layer 114a or 115a. The descriptions of the interfaces, average densities, thicknesses, average grain sizes, main components, and secondary components between the first edge layers 114a and 115a and the second edge layers 114b and 115b are the same as those for the interfaces, average densities, thicknesses, average grain sizes, main components, and secondary components between the first capping layers 112a and 113a and the second capping layers 112b and 113b, and therefore will be omitted.

[0062] In another embodiment of this disclosure, the multilayer ceramic capacitor 200 according to this disclosure may further include third cover layers 212c and 213c respectively disposed on the second cover layers 212b and 213b. Figures 6 to 10 This is a schematic diagram illustrating a multilayer ceramic capacitor according to this embodiment. (Refer to...) Figures 6 to 10 According to this embodiment, the multilayer ceramic capacitor 200 may include: a ceramic body 210, including a dielectric layer 211 and a first inner electrode 221 and a second inner electrode 222, wherein the first inner electrode 221 and the second inner electrode 222 are disposed opposite to each other and the dielectric layer 211 is disposed therebetween, and the ceramic body 210 includes a first surface S1 and a second surface S2 opposite to each other in a first direction (X direction), a third surface S3 and a fourth surface S4 opposite to each other in a second direction (Y direction), and a fifth surface S5 and a sixth surface S6 opposite to each other in a third direction (Z direction); a first outer electrode 231 disposed on the first surface S1 of the ceramic body 210 and connected to the first inner electrode 221; and a second outer electrode 232 disposed on the second surface S2 of the ceramic body 210 and connected to the second inner electrode 222.

[0063] In addition, the ceramic body 210 may also include: a capacitor forming portion, including a first inner electrode 221 and a second inner electrode 222 stacked in a third direction (Z direction), and a dielectric layer 211 between the first inner electrode 221 and the second inner electrode 222 to form a capacitor; a first edge portion 214 and a second edge portion 215 disposed on two surfaces of the capacitor forming portion in a second direction (Y direction); and a first covering portion 212 and a second covering portion 213 disposed on two surfaces of the capacitor forming portion in a third direction (Z direction), the first edge portion 214 on two surfaces of the first edge portion in a third direction (Z direction), and the second edge portion 215 on two surfaces of the second edge portion in a third direction (Z direction), respectively. The first covering portion 212 and the second covering portion 213 may respectively include a first covering layer 212a and 213a adjacent to the outermost inner electrode of the first inner electrode 221 and the second inner electrode 222, a second covering layer 212b and 213b respectively disposed on the first covering layer 212a and 213a, and a third covering layer 212c and 213c disposed on the second covering layer 212b and 213b. The first covering portion 212 may include the interface between the first covering layer 212a and the second covering layer 212b and the interface between the second covering layer 212b and the third covering layer 212c. The second covering portion 213 may include the interface between the first covering layer 213a and the second covering layer 213b and the interface between the second covering layer 213b and the third covering layer 213c.

[0064] According to embodiments of this disclosure, among the first capping layer 212a or 213a, the second capping layer 212b or 213b, and the third capping layer 212c or 213c included in the multilayer ceramic capacitor 200 of this disclosure, the third capping layer 212c or 213c may have the largest average density. For example, the average density of the third capping layer 212c or 213c may be greater than the average density of the second capping layer 212b or 213b. The average density of the third capping layer 212c or 213c can be adjusted by the amount of the aforementioned secondary components, and the amount of secondary components in the third capping layer 212c or 213c can be relatively determined according to the magnitude of the average density.

[0065] In embodiments of this disclosure, the maximum thickness of the third covering layer 212c or 213c included in the first covering portion 212 and the second covering portion 213 of this disclosure (e.g., Figure 9 t3 in the figure can be 20% to 70% of the maximum thickness of the first cover 112 or the second cover 113 (e.g., t1+t2+t3). The maximum thickness of the third cover 212c or 213c can be 70% or less, 65% or less, 60% or less, 55% or less, or 50% or less of the maximum thickness of the first cover 112 or the second cover 113.

[0066] According to embodiments of this disclosure, in the first capping layer 212a or 213a, the second capping layer 212b or 213b, and the third capping layer 212c or 213c included in the multilayer ceramic capacitor 200 of this disclosure, the average grain size of the dielectric grains included in the third capping layer 212c or 213c can be the largest. For example, the average grain size of the dielectric grains included in the third capping layer 212c or 213c can be larger than the average grain size of the dielectric grains included in the second capping layer 212b or 213b. The descriptions of the interface, average density, thickness, average grain size, main component, and secondary component of the third capping layer 212c or 213c are the same as the descriptions of the interface, average density, thickness, average grain size, main component, and secondary component described above, and therefore will be omitted.

[0067] According to another embodiment of this disclosure, the average density of the second cover layers 112b and 113b included in the multilayer ceramic capacitor 100 of this disclosure may be lower than the average density of the first cover layers 112a and 113a. The second cover layers 112b and 113b of the multilayer ceramic capacitor 100 of this disclosure may use materials with an average density lower than the average density of the first cover layers 112a and 113a to prevent the occurrence of cracks or other defects caused by sintering mismatch that may occur during the sintering process, thereby improving reliability. Furthermore, the average density of the second cover layers 112b and 113b may be controlled to be lower than the average density of the first cover layers 112a and 113a, so that the portion of the cover disposed inside has higher strength, thereby improving the mechanical strength of the multilayer ceramic capacitor 100.

[0068] In embodiments of this disclosure, the maximum thickness of the second covering layer 112b or 113b included in the first covering portion 112 or the second covering portion 113 can be 20% to 70% of the maximum thickness of the first covering portion 112 or the second covering portion 113. The maximum thickness of the second covering layer 112b or 113b can be 70% or less, 65% or less, 60% or less, 55% or less, or 50% or less of the maximum thickness of the first covering portion 112 or the second covering portion 113. The density of the second covering layers 112b and 113b is less than the density of the first covering layers 112a and 113a. Therefore, when the second covering layers 112b and 113b have a thickness within the above range, they can absorb external forces even when applied.

[0069] According to embodiments of this disclosure, the average grain size of the dielectric grains included in the second capping layer 112b or 113b may be smaller than the average grain size of the dielectric grains included in the first capping layer 112a or 113a.

[0070] In an example, the first cover portion 112 and the second cover portion 113 of the multilayer ceramic capacitor 100 according to this disclosure may include one or more of the group consisting of sodium (Na), lithium (Li), and boron (B) as secondary components. In this case, the amount of Na, Li, and / or B included in the second cover layer 112b or 113b in the first cover portion 112 and the second cover portion 113 may be less than the amount of Na, Li, and / or B included in the first cover layer 112a or 113a. The first cover portion 112 and the second cover portion 113 may be adjusted such that the amount of Na, Li, and / or B included in the second cover layer 112b or 113b is less than the amount of Na, Li, and / or B included in the first cover layer 112a or 113a, thereby increasing the density of the first cover layers 112a and 113a of the first cover portion 112 and the second cover portion 113, thereby improving mechanical strength.

[0071] In another example of this disclosure, the first cover portion 112 and the second cover portion 113 of the multilayer ceramic capacitor 100 according to this disclosure may include magnesium (Mg) as a secondary component. In this case, the amount of magnesium (Mg) contained in the first cover layer 112a or 113a of the first cover portion 112 and the second cover portion 113 may be less than the amount of magnesium (Mg) contained in the second cover layer 112b or 113b. The first cover portion 112 and the second cover portion 113 may be adjusted such that the amount of magnesium (Mg) contained in the first cover layer 112a or 113a is less than the amount of magnesium (Mg) contained in the second cover layer 112b or 113b, so as to increase the density of the first cover layers 112a and 113a of the first cover portion 112 and the second cover layer 113 compared with the second cover layers 112b and 113b, thereby improving mechanical strength.

[0072] According to a modified embodiment of the present disclosure, the first edge portion 114 and the second edge portion 115 included in the multilayer ceramic capacitor 100 of the present disclosure may respectively include first edge layers 114a and 115a adjacent to the first inner electrode 121 and / or the second inner electrode 122, and second edge layers 114b and 115b respectively disposed on the first edge layers 114a and 115a. The first edge portion 114 and the second edge portion 115 may respectively include the interface between the first edge layer 114a and the second edge layer 114b and the interface between the first edge layer 115a and the second edge layer 115b.

[0073] According to embodiments of the present disclosure, the average density of the second edge layer 114b or 115b included in the multilayer ceramic capacitor 100 of the present disclosure may be lower than the average density of the first edge layer 114a or 115a included in the multilayer ceramic capacitor 100.

[0074] In embodiments of this disclosure, the thickness of the second edge layer 114b or 115b included in the first edge portion 114 and the second edge portion 115 may be 20% to 70% of the maximum thickness of the first edge portion 114 and the second edge portion 115.

[0075] According to embodiments of this disclosure, the average grain size of the dielectric grains included in the second edge layer 114b or 115b may be smaller than the average grain size of the dielectric grains included in the first edge layer 114a or 115a. The descriptions of the interfaces, average density, thickness, average grain size, main components, secondary components, etc., of the first edge layers 114a and 115a and the second edge layers 114b and 115b are the same as those of the first capping layers 112a and 113a and the second capping layers 112b and 113b, and therefore will be omitted.

[0076] In another embodiment of this disclosure, the multilayer ceramic capacitor 200 according to this disclosure may further include third cover layers 212c and 213c respectively disposed on the second cover layers 212b and 213b. Figures 6 to 10 This is a schematic diagram illustrating a multilayer ceramic capacitor according to this embodiment. (Refer to...) Figures 6 to 10 According to this embodiment, the multilayer ceramic capacitor 200 may include: a ceramic body 210, including a dielectric layer 211 and a first inner electrode 221 and a second inner electrode 222, wherein the first inner electrode 221 and the second inner electrode 222 are disposed opposite to each other and the dielectric layer 211 is disposed therebetween, and the ceramic body 210 includes a first surface S1 and a second surface S2 opposite to each other in a first direction (X direction), a third surface S3 and a fourth surface S4 opposite to each other in a second direction (Y direction), and a fifth surface S5 and a sixth surface S6 opposite to each other in a third direction (Z direction); a first outer electrode 231 disposed on the first surface S1 of the ceramic body 210 and connected to the first inner electrode 221; and a second outer electrode 232 disposed on the second surface S2 of the ceramic body 210 and connected to the second inner electrode 222.

[0077] Furthermore, the ceramic body 210 may also include: a capacitor forming portion, comprising a first inner electrode 221 and a second inner electrode 222 stacked in a third direction (Z direction), with a dielectric layer 211 between the first inner electrode 221 and the second inner electrode 222 to form a capacitor; a first edge portion 214 and a second edge portion 215 disposed on two surfaces of the capacitor forming portion in a second direction (Y direction); and a first cover portion 212 and a second cover portion 213 disposed on two surfaces of the capacitor forming portion in a third direction (Z direction), the first edge portion 214 on two surfaces of the first edge portion 214 on two surfaces of the first edge portion 214 on two surfaces of the first edge portion 215 on two surfaces of the second edge portion 215 in a third direction (Z direction), wherein the first cover portion 212 and the second cover portion 213... The first cover portion 212 may include first cover layers 212a and 213a adjacent to the outermost inner electrodes of the first inner electrode 221 and the second inner electrode 222, second cover layers 212b and 213b respectively disposed on the first cover layers 212a and 213a, and third cover layers 212c and 213c respectively disposed on the second cover layers 212b and 213b. The first cover portion 212 may include the interface between the first cover layer 212a and the second cover layer 212b and the interface between the second cover layer 212b and the third cover layer 212c. The second cover portion 213 may include the interface between the first cover layer 213a and the second cover layer 213b and the interface between the second cover layer 213b and the third cover layer 213c.

[0078] According to embodiments of this disclosure, among the first capping layer 212a or 213a, the second capping layer 212b or 213b, and the third capping layer 212c or 213c included in the multilayer ceramic capacitor 200 of this disclosure, the third capping layer 212c or 213c may have the lowest average density. For example, the average density of the third capping layer 212c or 213c may be lower than the average density of the second capping layer 212b or 213b. The average density of the third capping layer 212c or 213c can be adjusted by the amount of the aforementioned secondary components, and the amount of the secondary components of the third capping layer 212c or 213c can be relatively determined according to the magnitude of the average density.

[0079] In embodiments of this disclosure, the maximum thickness of the third covering layer 212c or 213c included in the first covering portion 212 and the second covering portion 213 may be 20% to 70% of the maximum thickness of the first covering portion 112 or the second covering portion 113. The maximum thickness of the third covering layer 212c or 213c may be 70% or less, 65% or less, 60% or less, 55% or less, or 50% or less of the maximum thickness of the first covering portion 112 or the second covering portion 113.

[0080] According to embodiments of this disclosure, in the first capping layer 212a or 213a, the second capping layer 212b or 213b, and the third capping layer 212c or 213c included in the multilayer ceramic capacitor 200 of this disclosure, the average grain size of the dielectric grains included in the third capping layer 212c or 213c can be the smallest. For example, the average grain size of the dielectric grains included in the third capping layer 212c or 213c can be smaller than the average grain size of the dielectric grains included in the second capping layer 212b or 213b. The descriptions of the interface, average density, thickness, average grain size, main component, and secondary component of the third capping layer 212c or 213c are the same as the descriptions of the interface, average density, thickness, average grain size, main component, and secondary component described above, and therefore will be omitted.

[0081] According to a modified embodiment of the present disclosure, the first edge portion 214 and the second edge portion 215 included in the multilayer ceramic capacitor 200 of the present disclosure may respectively include first edge layers 214a and 215a adjacent to the first inner electrode 221 and / or the second inner electrode 222, and second edge layers 214b and 215b respectively disposed on the first edge layers 214a and 215a. The first edge portion 214 and the second edge portion 215 may respectively include the interface between the first edge layer 214a and the second edge layer 214b and the interface between the first edge layer 215a and the second edge layer 215b.

[0082] According to embodiments of the present disclosure, the average density of the second edge layer 214b or 215b included in the multilayer ceramic capacitor 200 of the present disclosure may be less than the average density of the first edge layer 214a or 215a included in the multilayer ceramic capacitor 200.

[0083] In embodiments of this disclosure, the thickness of the second edge layer 214b or 215b included in the first edge portion 214 and the second edge portion 215 may be 20% to 70% of the maximum thickness of the first edge portion 214 and the second edge portion 215.

[0084] According to embodiments of this disclosure, the average grain size of the dielectric grains included in the second edge layer 214b or 215b may be smaller than the average grain size of the dielectric grains included in the first edge layer 214a or 215a. The descriptions of the interfaces, average density, thickness, average grain size, principal components, and secondary components of the first edge layers 214a and 215a and the second edge layers 214b and 215b are the same as those for the first edge layers 114a and 115a and the second edge layers 114b and 114b described above, and therefore will be omitted.

[0085] One of the effects of this disclosure is improved moisture resistance reliability of multilayer ceramic capacitors.

[0086] One of the effects of this disclosure is improved mechanical strength of multilayer ceramic capacitors.

[0087] However, the various advantages and effects of this disclosure are not limited to those described above, and will be more readily understood in the process of describing specific embodiments of this disclosure.

[0088] While exemplary embodiments have been shown and described above, it will be readily understood by those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A multilayer ceramic capacitor, comprising: A ceramic body includes a dielectric layer and a first inner electrode and a second inner electrode, the first inner electrode and the second inner electrode being disposed opposite each other and the dielectric layer being disposed therebetween, and the ceramic body includes a first surface and a second surface opposite each other in a first direction, a third surface and a fourth surface opposite each other in a second direction, and a fifth surface and a sixth surface opposite each other in a third direction. as well as A first external electrode and a second external electrode are disposed on the first surface of the ceramic body and connected to the first internal electrode, and the second external electrode is disposed on the second surface of the ceramic body and connected to the second internal electrode. The ceramic body further includes: A capacitor forming section includes a first inner electrode and a second inner electrode stacked upwards on the third side, with the dielectric layer between the first inner electrode and the second inner electrode to form a capacitor. A first edge portion and a second edge portion are respectively disposed on two surfaces of the capacitor forming portion in the second direction; and The first covering portion and the second covering portion are respectively disposed on the two surfaces of the capacitor forming portion in the third direction, the first edge portion on the two surfaces of the first edge portion in the third direction, and the second edge portion on the two surfaces of the second edge portion in the third direction. The first covering portion and the second covering portion each include a first covering layer adjacent to the outermost inner electrode of the first inner electrode and the second inner electrode, a second covering layer disposed on the first covering layer, and an interface in contact between the first covering layer and the second covering layer. The average density of the second cover layer is greater than the average density of the first cover layer. Wherein, both the first and second cover layers contain magnesium, and The amount of magnesium in the first capping layer is greater than the amount of magnesium in the second capping layer.

2. The multilayer ceramic capacitor as described in claim 1, wherein, The first covering portion and the second covering portion are configured to cover the two surfaces of the capacitor forming portion in the third direction, the two surfaces of the first edge portion in the third direction, and the two surfaces of the second edge portion in the third direction, respectively.

3. The multilayer ceramic capacitor as described in claim 1, wherein, The capacitor forming portion is disposed on the same plane as the two surfaces of the first edge portion and the second edge portion in the third direction.

4. The multilayer ceramic capacitor as described in claim 1, wherein, The maximum value of the width of the first covering portion in the second direction or the maximum value of the width of the second covering portion in the second direction is substantially equal to the maximum value of the width of the ceramic body in the second direction.

5. The multilayer ceramic capacitor as described in claim 1, wherein, The first cover layer is spaced apart from the first inner electrode and the second inner electrode in the third direction.

6. The multilayer ceramic capacitor as described in claim 5, wherein, The first capping layer and the second capping layer comprise dielectric grains, and The average particle size of the dielectric grains included in the second capping layer is greater than the average particle size of the dielectric grains included in the first capping layer.

7. The multilayer ceramic capacitor as described in claim 5, wherein, Both the first and second capping layers contain at least one selected from the group consisting of sodium, lithium, and boron, and The first and second covering layers contain the same elements from the group consisting of sodium, lithium, and boron, and the amount of at least one of sodium, lithium, and boron contained in the second covering layer is greater than the amount of at least one of sodium, lithium, and boron contained in the first covering layer.

8. The multilayer ceramic capacitor as claimed in claim 1, wherein, Each of the first covering portion and the second covering portion further includes a third covering layer disposed on the second covering layer.

9. The multilayer ceramic capacitor as claimed in claim 8, wherein, The third cover layer, of the first cover layer, the second cover layer, and the third cover layer, has the largest or smallest average density.

10. The multilayer ceramic capacitor as claimed in claim 8, wherein, The third capping layer includes dielectric grains, and The dielectric grains included in the third cover layer among the first cover layer, the second cover layer, and the third cover layer have the largest or smallest average grain size.

11. The multilayer ceramic capacitor as claimed in claim 10, wherein, The average density of the third cover layer is greater than the average density of the second cover layer.

12. The multilayer ceramic capacitor as claimed in claim 11, wherein, The maximum thickness of the third covering layer is 20% to 70% of the maximum thickness of the first covering portion or the second covering portion.

13. The multilayer ceramic capacitor of claim 10, wherein the average grain size of the dielectric grains included in the second capping layer is greater than the average grain size of the dielectric grains included in the first capping layer, and the average grain size of the dielectric grains included in the third capping layer is greater than the average grain size of the dielectric grains included in the second capping layer.

14. The multilayer ceramic capacitor according to claim 1, wherein, Both the first edge portion and the second edge portion include a first edge layer adjacent to the first inner electrode and / or the second inner electrode, a second edge layer disposed on the first edge layer, and an interface in contact between the first edge layer and the second edge layer.

15. The multilayer ceramic capacitor according to claim 1, wherein, The maximum thickness of the second covering layer is 20% to 70% of the maximum thickness of the first covering portion or the maximum thickness of the second covering portion.

16. The multilayer ceramic capacitor as claimed in claim 14, wherein, The maximum thickness of the second edge layer is 30% to 70% of the maximum thickness of the first edge portion or the maximum thickness of the second edge portion.

17. A multilayer ceramic capacitor, comprising: A ceramic body includes a dielectric layer and a first inner electrode and a second inner electrode, wherein the first inner electrode and the second inner electrode are arranged opposite to each other and the dielectric layer is therebetween. as well as A first external electrode and a second external electrode are disposed on two opposing surfaces of the ceramic body in a first direction and are respectively connected to the first internal electrode and the second internal electrode. The ceramic body further includes: A capacitor forming section includes a first inner electrode and a second inner electrode stacked upwards on a third-party side, with a dielectric layer between the first inner electrode and the second inner electrode to form a capacitor. A first edge portion and a second edge portion are respectively disposed on two surfaces of the capacitor forming portion in a second direction, wherein the second direction is orthogonal to the first direction and the third direction; and The first covering portion and the second covering portion are respectively disposed on the two surfaces of the capacitor forming portion in the third direction, the first edge portion on the two surfaces of the first edge portion in the third direction, and the second edge portion on the two surfaces of the second edge portion in the third direction. Both the first covering portion and the second covering portion include two or more covering layers stacked upwards on the third party, and have interfaces between adjacent layers of the two or more covering layers. Among the two or more cover layers, the closer to the capacitor forming portion, the lower the average density of the corresponding cover layer, and Each of the two or more capping layers contains magnesium, with the amount of magnesium in the capping layer increasing the closer it is to the capacitor forming portion.

18. The multilayer ceramic capacitor as claimed in claim 17, wherein, The capacitor forming portion is disposed on the same plane as the two surfaces of the first edge portion and the second edge portion in the third direction.

19. The multilayer ceramic capacitor as claimed in claim 17, wherein, The maximum value of the width of the first covering portion in the second direction or the maximum value of the width of the second covering portion in the second direction is substantially equal to the maximum value of the width of the ceramic body in the second direction.

20. The multilayer ceramic capacitor as claimed in claim 17, wherein, Both the first covering portion and the second covering portion include a first covering layer and a second covering layer. The first covering layer is adjacent to the outermost inner electrode of the first inner electrode and the second inner electrode, and the second covering layer is disposed on the first covering layer.

21. The multilayer ceramic capacitor as claimed in claim 20, wherein, The first cover layer is spaced apart from the first inner electrode and the second inner electrode in the third direction.

22. The multilayer ceramic capacitor as claimed in claim 20, wherein, The first capping layer and the second capping layer comprise dielectric grains, and The average particle size of the dielectric grains included in the second capping layer is greater than the average particle size of the dielectric grains included in the first capping layer.

23. The multilayer ceramic capacitor as claimed in claim 20, wherein, Each of the first covering portion and the second covering portion further includes a third covering layer disposed on the second covering layer.

24. The multilayer ceramic capacitor as claimed in claim 23, wherein, The third capping layer includes dielectric grains, and Among them, the dielectric grains included in the third cover layer of the first cover layer, the second cover layer and the third cover layer have the largest average grain size.

25. The multilayer ceramic capacitor as claimed in claim 24, wherein, The maximum thickness of the third covering layer is 20% to 70% of the maximum thickness of the first covering portion or the second covering portion.

26. The multilayer ceramic capacitor as claimed in claim 17, wherein, Both the first edge portion and the second edge portion include a first edge layer adjacent to the first inner electrode and / or the second inner electrode, a second edge layer disposed on the first edge layer, and an interface between the first edge layer and the second edge layer.

27. The multilayer ceramic capacitor as claimed in claim 20, wherein, The maximum thickness of the second covering layer is 20% to 70% of the maximum thickness of the first covering portion or the maximum thickness of the second covering portion.

28. The multilayer ceramic capacitor as claimed in claim 26, wherein, The maximum thickness of the second edge layer is 30% to 70% of the maximum thickness of the first edge portion or the maximum thickness of the second edge portion.

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