Semiconductor structure and method of forming the same

Abstract

Embodiments of the invention relate to semiconductor structures and methods of forming the same. The method includes depositing a gate dielectric layer; depositing a work function (WF) metal layer over the gate dielectric layer; and etching the WF metal layer through an etch mask, thereby removing a first portion of the WF metal layer while leaving a second portion of the WF metal layer exposed with sidewalls of the second portion of the WF metal layer exposed. The method further includes forming a first barrier on the sidewalls of the second portion of the WF metal layer and depositing a gate metal layer. A first portion of the gate metal layer is deposited over the gate dielectric layer and a second portion of the gate metal layer is deposited over the first barrier and the second portion of the WF metal layer. The first barrier is disposed between the first portion of the gate metal layer and the second portion of the WF metal layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor structures and methods for forming the same. Background Technology

[0002] The electronics industry has experienced a growing demand for smaller and faster electronic devices capable of supporting a greater number of increasingly complex and sophisticated functions. To meet these demands, the integrated circuit (IC) industry has consistently trended towards manufacturing low-cost, high-performance, and low-power ICs. To date, these goals have been largely achieved by reducing IC size (e.g., minimizing IC component size), thereby increasing production efficiency and lowering associated costs. However, this scaling also increases the complexity of IC manufacturing processes. Therefore, continued advancements in IC devices and their performance require similar progress in IC manufacturing processes and technologies.

[0003] One area of ​​progress is providing CMOS devices with appropriate threshold voltages (Vt) for NMOS and PMOS transistors to improve performance while reducing power consumption. In particular, Vt engineering has been challenging as devices continue to scale down to multi-gate devices such as FinFETs, gate-all-around (GAA) devices (including nanowire and nanosheet devices), and other types of multi-gate devices. Improvements are needed in the metal gates that isolate adjacent multi-gate devices. Summary of the Invention

[0004] Embodiments of the present invention provide a method for forming a semiconductor structure, comprising: depositing a gate dielectric layer over a semiconductor channel layer; depositing a power function (WF) metal layer over the gate dielectric layer; forming an etch mask that covers a second portion of the WF metal layer and has an opening over a first portion of the WF metal layer; etching the WF metal layer through the etch mask to remove the first portion of the WF metal layer while retaining the second portion of the WF metal layer, wherein, after the etching, the sidewalls of the second portion of the WF metal layer are exposed; forming a first barrier on the sidewalls of the second portion of the WF metal layer; and depositing a gate metal layer, wherein the first portion of the gate metal layer is deposited over the gate dielectric layer and at the same level as the first barrier, the second portion of the gate metal layer is deposited over the first barrier and the second portion of the WF metal layer, and the first barrier is disposed between the first portion of the gate metal layer and the second portion of the WF metal layer.

[0005] Another embodiment of the present invention provides a method for forming a semiconductor structure, comprising: depositing a gate dielectric layer over a substrate; depositing a power function (WF) metal layer over the gate dielectric layer, wherein the gate dielectric layer and the power function metal layer are deposited over regions defining the substrate for first and second devices having different threshold voltages; forming an etch mask covering the power function metal layer for the second device; etching the power function metal layer through the etch mask to remove a first portion of the power function metal layer while retaining a second portion of the power function metal layer, wherein, after the etching, sidewalls of the second portion of the power function metal layer are exposed; removing the etch mask to expose a top surface of the second portion of the power function metal layer; and forming a first barrier on the sidewalls of the second portion of the power function metal layer and forming a second barrier on the top surface of the second portion of the power function metal layer.

[0006] Another embodiment of the present invention provides a semiconductor structure comprising: a first transistor adjacent to a second transistor, wherein the first transistor includes a first gate metal layer above a gate dielectric layer, and the second transistor includes a second gate metal layer above the gate dielectric layer, wherein the first gate metal layer and the second gate metal layer comprise different materials; and a first barrier laterally disposed between the first gate metal layer and the second gate metal layer, wherein one of the first gate metal layer and the second gate metal layer comprises aluminum, and the first barrier has a low dielectric constant for aluminum. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1A This is a partial top view of a portion of the semiconductor device according to the present invention. Figure 1B , Figure 1C and Figure 1D According to the present invention, respectively along Figure 1A The "BB", "CC" and "DD" lines Figure 1A A schematic cross-sectional view of a portion of the semiconductor device.

[0009] Figure 2 This is a flowchart of a method for manufacturing a semiconductor device according to various aspects of the present invention.

[0010] Figure 3A-1 and Figure 3A-2 According to embodiments of the present invention, during the manufacturing stage (such as with) Figure 2 The methods associated with those in the middle) are respectively along Figure 1A The "BB" and "CC" lines Figure 1A A schematic cross-sectional view of a portion of the semiconductor device.

[0011] Figure 3A-3 , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H , Figure 3I and Figure 3J This is according to embodiments of the invention at various manufacturing stages (such as with) Figure 2 Those methods associated with the middle) along Figure 1A The "DD" line in Figure 1A A schematic cross-sectional view of a portion of the semiconductor device.

[0012] Figure 4 This is a flowchart of a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0013] Figure 5A and Figure 5B This is according to embodiments of the invention at various manufacturing stages (such as with) Figure 4 Those methods associated with the middle) along Figure 1A The "DD" line in Figure 1A A schematic cross-sectional view of a portion of the semiconductor device.

[0014] Figure 6 This is a flowchart of a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0015] Figure 7A and Figure 7B This is according to embodiments of the invention at various manufacturing stages (such as with) Figure 6 Those methods associated with the middle) along Figure 1A The "DD" line in Figure 1A A schematic cross-sectional view of a portion of the semiconductor device.

[0016] Figure 8 Another embodiment of the invention is shown. Figure 1A A schematic cross-sectional view of a portion of the semiconductor device. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the individual embodiments and / or configurations discussed.

[0018] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. Further, unless otherwise stated, based on the knowledge of those skilled in the art in light of the specific techniques disclosed herein, when describing numerical values ​​or ranges using terms such as “about,” “approximately,” etc., the term covers values ​​within a specific variation (such as + / - 10% or other variations) of the described value. For example, the term “about 5 nm” may cover a size range from 4.5 nm to 5.5 nm, from 4.0 nm to 5.0 nm, etc.

[0019] This invention generally relates to semiconductor structures and manufacturing processes, and more specifically to providing diffusion barriers (or isolation) between different metal gates (MGs) and / or between different metal layers within the same metal gate. With ongoing technology scaling and pitch constraints, multi-threshold voltage (or multi-Vt) devices can be formed by using dipole engineering and / or patterning different work function metal (WFM) layers. However, metals (such as Al and La) from the high-k metal gate (HKMG) of one device can diffuse into the HKMG of adjacent devices. This diffusion can lead to Vt inhomogeneity in the IC. For example, transistors that should have the same Vt (e.g., standard Vt) by design may exhibit significant variations in their Vt due to such diffusion during the manufacturing process or throughout the IC's operational lifetime. This invention relates to preventing (or mitigating) the diffusion and mixing of metal elements in the HKMG.

[0020] Figure 1A A partial top view of a portion of a semiconductor device 200 according to the present invention is shown. (Reference) Figure 1ADevice 200 includes active regions 204 (two shown) generally longitudinally oriented along the "x" direction and gate regions 206 (four shown) generally longitudinally oriented along the "y" direction perpendicular to the "x" direction. Transistors such as field-effect transistors (FETs) can be formed with gate regions 206 and active regions 204. For illustrative purposes, Figure 1A Two FETs, 200A and 200B, in device 200 are shown. Semiconductor device 200 may be an intermediate device manufactured during the processing of an IC or a portion thereof. The intermediate device may include static random access memory (SRAM) and / or logic circuitry, passive components (such as resistors, capacitors, and inductors), and active components (such as p-type field-effect transistors (PFETs), n-type FETs (NFETs), multi-gate FETs (such as FinFETs and all-around gate devices), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, other memory cells, and combinations thereof).

[0021] Figure 1B , Figure 1C and Figure 1D According to the present invention, respectively along Figure 1A A schematic cross-sectional view of a portion of semiconductor device 200 with the “BB”, “CC” and “DD” lines in the diagram. Figure 1B , Figure 1C and Figure 1D The embodiments of FETs 200A and 200B shown are FinFETs, wherein their channel layer is in the shape of one or more semiconductor fins 215. In various embodiments, FETs 200A and 200B may have other configurations. For example, one or both of FETs 200A and 200B may be FinFETs, nanowire FETs, nanosheet FETs, or planar FETs.

[0022] Common Reference Figures 1B to 1D Device 200 includes a substrate (e.g., a wafer) 202. In the depicted embodiment, substrate 202 includes silicon. Optionally or additionally, substrate 202 includes another semiconductor, such as germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Optionally, substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate.

[0023] Each of FETs 200A and 200B includes a pair of source / drain components 260. For an n-type FET (or NFET), the source / drain components 260 are n-type. For a p-type FET (or PFET), the source / drain components 260 are p-type. In the depicted embodiment, the source / drain components 260 are positioned above the semiconductor channel layer (fin 215) in the same FET to apply stress to the semiconductor channel layer. The source / drain components 260 can be formed by epitaxially growing a semiconductor material (e.g., Si or SiGe) to fill the trenches in device 200, for example using CVD deposition techniques (e.g., vapor phase epitaxy), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The source / drain components 260 are doped with suitable n-type and / or p-type dopants. For example, for an NFET, the source / drain component 260 may comprise silicon and be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof; and for a PFET, the source / drain component 260 may comprise silicon, silicon germanium, or germanium and be doped with boron, other p-type dopants, or combinations thereof. In some embodiments, one of FETs 200A and 200B is an NFET and the other is a PFET, and they together form a CMOSFET. In some embodiments, FETs 200A and 200B are both NFETs or both are PFETs. In some embodiments, the gate electrodes of FETs 200A and 200B share some common metal layer, as will be discussed further.

[0024] Each of FETs 200A and 200B also includes one or more semiconductor fins (or simply fins) 215 extending from the substrate 202 and through the isolation member 230. The fins 215 connect to a pair of source / drain members 260 and serve as the transistor channel for the respective FET. Figures 1B to 1D In the embodiments depicted, each FET 200A and 200B includes a single fin 215. In alternative embodiments, each FET 200A and 200B may include a single fin 215 or multiple fins 215. For example, a fin 215 may have a height of about 40 nm to about 70 nm (along the “z” direction) and a width of about 4 nm to about 8 nm (along the “y” direction).

[0025] Fin 215 may comprise crystalline silicon, germanium, silicon-germanium, or other suitable semiconductor materials; and may be formed using any suitable method, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over substrate 202, and the sacrificial layer is patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used as masking elements for patterning fin 215. For example, the masking elements can be used to etch grooves in a semiconductor layer over or in substrate 202, leaving fin 215 on substrate 202. Etching processes may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.

[0026] Device 200 also includes isolation components 230 to isolate various regions, such as various active regions 204. Isolation components 230 include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., including silicon, oxygen, nitrogen, carbon, or other suitable isolation components) or combinations thereof. In embodiments, isolation component 230 is formed by etching trenches in or over substrate 202 (e.g., as part of a process forming fin 215), filling the trenches with an insulating material, and performing a chemical mechanical planarization (CMP) process and / or an etch-back process on the insulating material, leaving the remaining insulating material as isolation component 230. Isolation component 230 may include different structures, such as shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, and / or localized oxidation of silicon (LOCOS) structures. Isolation component 230 may include multiple layers of insulating material.

[0027] like Figures 1B to 1D As shown, FET 200A includes a gate stack 240A that bonds to fin 215, and FET 200B includes a gate stack 240B that bonds to another fin 215. Gate stacks 240A and 240B are provided in gate region 206. Gate stack 240A includes an interface layer 280, a gate dielectric layer (such as a high-k gate dielectric layer) 282, a work function metal (WFM) layer 284A, a diffusion barrier 304, another WFM layer 284B, and a body metal layer 286. Gate stack 240B includes an interface layer 280, a gate dielectric layer 282, a WFM layer 284B, and a body metal layer 286.

[0028] In embodiments, the interface layer 280 comprises a dielectric material such as silicon oxide (SiO2) or silicon oxynitride (SiON) and can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. In embodiments, the gate dielectric layer 282 may comprise SiO2. The gate dielectric layer 282 may comprise HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, or HfAlO. x ZrO2, ZrSiO2, AlSiO, Al2O3, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, STiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3N4, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, or combinations thereof. High-k dielectric materials generally refer to dielectric materials with a high dielectric constant, such as greater than that of silicon oxide (k≈3.9). The gate dielectric layer 282 can be formed by ALD and / or other suitable methods.

[0029] In this embodiment, FETs 200A and 200B have different threshold voltages, which are provided at least in part by the different WFM layers 284A and 284B therein. Each of the WFM layers 284A and 284B may include one or more layers of metallic material. Each of the WFM layers 284A and 284B may include an n-type work function metal or a p-type work function metal. Examples of n-type work function metals include Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TaAl, TaAlC, TaSiAlC, TiAlN, other n-type work function materials, or combinations thereof. Examples of p-type work function metals include TiN, TaN, TaSN, Ru, Mo, Al, WN, WCN, ZrSi2, MoSi2, TaSi2, NiSi2, other p-type work function materials, or combinations thereof. The WFM layers 284A and 284B may be deposited by ALD, CVD, PVD, and / or other suitable processes.

[0030] refer to Figure 1DThe WFM layer 284B of FET 200B and the WFM layer 284A of FET 200A are disposed at the same stack level. For example, in the depicted embodiment, both are disposed directly on the gate dielectric layer 282. Device 200 also includes a diffusion barrier 302 laterally disposed between the WFM layer 284B of FET 200B and the WFM layer 284A of FET 200A. The diffusion barrier 302 prevents the mixing of metal elements in the WFM layers 284A and 284B of the two FETs. In FET 200A, a diffusion barrier 304 is disposed between the WFM layers 284A and 284B and prevents the mixing of metal elements in the WFM layers 284A and 284B of the same FET. In this embodiment, the diffusion barrier 304 is conductive. Therefore, layers 284A, 304, 284B, and 286 in the gate stack 240A collectively serve as the gate electrode. In embodiments, the diffusion barrier 302 may be conductive or insulating. The formation of diffusion barrier elements 302 and 304 will be discussed in detail later.

[0031] The diffusion barriers 302 and 304 advantageously maintain the threshold voltage of FETs 200A and 200B during the manufacturing process and throughout the operational lifetime of device 200. It also improves the uniformity of threshold voltages for FETs of the same type within device 200, according to design specifications. For example, device 200 can provide FETs with various threshold voltages (Vt), such as ultra-low Vt, low Vt, standard Vt, high Vt, etc. Different threshold voltages can be provided using different WFM layers in different FETs or by incorporating different dipole materials in the gate stacks of different FETs. Without diffusion barriers (such as 302 and 304), different WFM layers or different dipole materials can diffuse and mix between different FETs, undesirably causing variations in the FET threshold voltage beyond design specifications. For example, aluminum (a common metal used in work function engineering) is known to diffuse through a variety of materials. Without diffusion barriers (such as 302 and 304), aluminum in the WFM layer of a gate stack can diffuse into adjacent WFM layers of the same gate stack or another gate stack. This diffusion of aluminum alters the expected work function of the gate stack, thus changing the expected Vt of the FET. The diffusion barriers 302 and 304 address this issue.

[0032] The bulk metal layer 286 may include metals such as aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), and / or other suitable materials; and may be deposited using plating, CVD, PVD, or other suitable processes. Figure 1DIn the illustrated embodiments, gate stacks 240A and 240B share some common metal layers, such as WFM layer 284B and body metal layer 286, and these common metal layers are electrically connected to gate stacks 240A and 240B. In various embodiments, gate stacks 240A and 240B may share at least one common metal layer or may not share any common metal layers (i.e., they are not electrically connected through common metal layers).

[0033] refer to Figures 1B to 1C The device 200 also includes a gate spacer 247 located above the sidewalls of the gate stacks 240A and 240B. The gate spacer 247 may comprise silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbonitride (SiCN), silicon carbonitride (SiOC), silicon carbonitride (SiOCN)). In some embodiments, the gate spacer 247 comprises a multilayer structure, such as a first dielectric layer comprising silicon nitride and a second dielectric layer comprising silicon oxide. The gate spacer 247 may be formed by deposition (e.g., CVD, PVD, ALD, etc.) and etching processes (e.g., dry etching).

[0034] Device 200 also includes a contact etch stop layer (CESL) 268 disposed over the isolation component 230, the source / drain component 260, and the gate spacer 247. CESL 268 comprises silicon and nitrogen, such as silicon nitride or silicon oxynitride. CESL 268 can be formed by a deposition process such as CVD or other suitable methods. Device 200 also includes an interlayer dielectric (ILD) layer 270 located above CESL 268. ILD layer 270 comprises a dielectric material, including, for example, silicon oxide, silicon nitride, silicon oxynitride, oxides formed from TEOS, PSG, BPSG, low-k dielectric materials, other suitable dielectric materials, or combinations thereof. ILD layer 270 can be formed by a deposition process such as CVD, flowable CVD (FCVD), or other suitable methods.

[0035] Figure 2 This is a flowchart of a method 100 for manufacturing device 200 according to various aspects of the present invention. The invention considers additional processing. Additional steps may be provided before, during, and after method 100, and for additional embodiments of method 100, some of the described steps may be moved, replaced, or eliminated. The following is in conjunction with… Figures 3A-1 to 3J Description method 100. Figure 3A-1 , Figure 3A-2 and Figure 3A-3 They are along Figure 1A A schematic cross-sectional view of part of device 200 with lines “BB”, “CC” and “DD”. Figures 3B to 3J In the context of Figure 2Method 100 is associated with each manufacturing stage along Figure 1A A cross-sectional view of part of device 200 with the “DD” line in the diagram.

[0036] At operation 102, method 100 ( Figure 2 Provides the initial structure (or workpiece) of device 200, such as Figure 3A-1 , Figure 3A-2 and Figure 3A-3 As shown. As discussed above, device 200 includes substrate 202, fin 215, source / drain components 260, gate spacer 247, CESL 268, and ILD 270. Fin 215 is exposed in gate trench 275, which is located from gate region 206 ( Figure 1A This is generated by removing the dummy gate.

[0037] At operation 104, method 100 ( Figure 2 An interface gate dielectric layer (or simply interface layer) 280 is formed above fin 215, and a gate dielectric layer (such as a high-k (or HK) gate dielectric layer) 282 is formed above interface layer 280, such as... Figure 3B As shown. Go to Figure 3B In the depicted embodiments, the interface layer 280 is disposed on the surface of the fin 215 but not on the isolation member 230. For example, the interface layer 280 can be formed by oxidizing the semiconductor material in the fin 215, which does not create the interface layer 280 on the isolation member 230. In some embodiments, the interface layer 280 is also disposed on the isolation member 230, for example, by atomic layer deposition (ALD) of a dielectric material as the interface layer 280. The interface layer 280 includes a dielectric material such as SiO2, HfSiO, SiON, other silicon-containing dielectric materials, other suitable dielectric materials, or combinations thereof. The interface layer 280 is formed by any of the processes described herein, such as thermal oxidation, chemical oxidation, ALD, CVD, other suitable processes, or combinations thereof. For example, the interface layer 280 may have a thickness of about 0.5 nm to about 1.5 nm. In alternative embodiments, the interface layer 280 may be omitted in FETs 200A and 200B.

[0038] A gate dielectric layer 282 is disposed above the interface layer 280 and the isolation member 230. In one embodiment, the gate dielectric layer 282 comprises HfO2. In another embodiment, the gate dielectric layer 282 comprises another hafnium-containing high-k dielectric material, such as HfSiO4, HfSiON (hafnium nitride silicate), lanthanum hafnium oxide (such as Hf2La2O7), HfTaO, HfTiO, HfZrO, hafnium aluminum oxide (i.e., HfAlOx), or hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy. In another embodiment, the gate dielectric layer 282 comprises another high-k dielectric material, such as ZrO2, ZrSiO4, Al2SiO5, Al2O3, TiO2, La2O3, La4Si3O 12 The gate dielectric layer 282 may be formed by any of the processes described herein, such as ALD, CVD, PVD, oxidation-based deposition processes, other suitable processes, or combinations thereof. For example, the gate dielectric layer 282 may have a thickness of about 0.2 nm to about 1.5 nm.

[0039] At operation 106, method 100 ( Figure 2 A square power functional metal (WFM) layer 284A is placed on the gate dielectric layer 282, such as... Figure 3C As shown. In an embodiment, WFM layer 284A comprises TiN. In some embodiments, WFM layer 284A comprises another nitride-based metallic material, such as TaN, WN, TiCN, TaCN, WCN, TiAlN, or TaAlN. In some embodiments, WFM layer 284A may comprise TiAlC, TiAlSiC, TaC, TaAl, TaAlC, TaSiAlC, or other suitable work function metals. In some examples, WFM layer 284A has a thickness of about 1 nm to about 2.5 nm, such as about 1 nm to about 1.5 nm. WFM layer 284A is formed by any of the processes described herein, such as ALD, CVD, PVD, other suitable processes, or combinations thereof. WFM layer 284A may comprise a single layer of material or multiple layers of material.

[0040] At operation 108, method 100 ( Figure 2 An etching mask 290 is formed, which covers the area of ​​FET 200A and exposes the area of ​​FET 200B, such as... Figure 3DAs shown. Mask 290 comprises a material different from that of WFM layer 284A and gate dielectric layer 282 to achieve etch selectivity during etching of WFM layer 284A and removal of etch mask 290. For example, mask 290 may comprise a photoresist material (and thus may be referred to as a patterned resist layer and / or a patterned photoresist layer). In some embodiments, mask 290 has a multilayer structure, such as a photoresist layer disposed over an antireflective coating (ARC) layer. Other materials for mask 290 are contemplated in the present invention, as long as the aforementioned etch selectivity is achieved. In some embodiments, operation 108 includes a photolithography process comprising forming a photoresist layer over device 200 (e.g., by spin coating), performing a pre-exposure baking process, performing an exposure process using the photomask, performing a post-exposure baking process, and developing the exposed photoresist layer in a developer. After development, the patterned photoresist layer (e.g., patterned mask 290) comprises a photoresist pattern corresponding to the photomask. Alternatively, the exposure process can be implemented or replaced by other methods, such as maskless lithography, electron beam writing, ion beam writing, or a combination thereof.

[0041] At operation 110, with the etching mask 290 in the proper position, method 100 ( Figure 2 Etch WFM layer 284A and remove WFM layer 284A from transistor 200B, such as Figure 3E As shown. After etching is complete, the sidewalls 284A' of the gate dielectric layer 282 and the WFM layer 284A in transistor 200B are exposed. The etching process can be a dry etching process, a wet etching process, or a reactive ion etching process, which has high etch selectivity for the WFM layer 284A relative to the gate dielectric layer 282. Therefore, the gate dielectric layer 282 is not etched or significantly etched by operation 110. In some embodiments, the etching process also has etch selectivity for the WFM layer 284A relative to the mask 290. In some embodiments, the etching process partially etches the mask 290.

[0042] At operation 112, while the etch mask 290 or at least a portion thereof remains in place, method 100 ( Figure 2 A diffusion barrier (or simply barrier) 302 is formed on the exposed sidewall 284A' of the WFM layer 284A, such as Figure 3FAs shown. Barrier 302 is not formed on the gate dielectric layer 282 of FET 200B. Barrier 302 is formed to prevent or substantially block the diffusion of chemical elements (such as Al) into the WFM layer 284A in FET 200A. In other words, barrier 302 has a low dielectric constant for aluminum and / or other chemical elements that may adversely affect the WFM layer 284A in FET 200A. Three methods of forming barrier 302 are discussed below. Alternative methods of forming barrier 302 are also contemplated.

[0043] In a first embodiment, operation 112 forms a barrier 302 by applying an oxidant to the sidewall 284A'. The oxidant reacts with the elements in the sidewall 284A' and forms an oxide as the barrier 302. For example, the oxidant may include H2O2 or ozonated DIW (deionized water). The composition of the barrier 302 depends on the material of the WFM layer 284A. In some embodiments, the barrier 302 may include TiO, TiON, TiAlO, WO, WCO, WCNO, RuO, WON, TaO, TaCO, TaAlO, TaTiO, TiOH, WOH, AlOH, TaOH, or combinations thereof. The oxidant does not react with the gate dielectric layer 282. Therefore, the barrier 302 is not formed on the gate dielectric layer 282. In some cases, the oxidant helps improve the quality of the gate dielectric layer 282 by re-oxidizing the gate dielectric layer 282 or by reducing the O vacancies in the gate dielectric layer 282. For example, oxygen from the oxidant can diffuse into the gate dielectric layer 282 and repair dangling bonds therein. In some embodiments, the barrier 302 has a thickness of about 0.5 nm to about 10 nm. If the barrier 302 is too thin (e.g., less than 0.5 nm), it may not effectively prevent aluminum or other elements from diffusing into the WFM layer 284A. If the barrier 302 is too thick (e.g., greater than 10 nm), it may take up too much space and leave too little space for the WFM layer 284A of FET 200A and the WFM layer 284B of FET 200B (see [link to documentation]). Figure 3I This would violate the size reduction of device 200.

[0044] In a second embodiment, operation 112 forms the barrier 302 by selectively depositing a tungsten-containing layer as a barrier 302 on the sidewall 284A'. The tungsten-containing layer is not deposited on the gate dielectric layer 282. Therefore, the deposition is selective. For example, operation 112 can use a precursor having WCl5 and H2 and B2H6 as a reducing agent to form the tungsten-containing layer. Alternatively, operation 112 can use a precursor having WCl5 and H2 and SiH4 as a reducing agent to form the tungsten-containing layer. Alternatively, operation 112 can use a gas mixture of WF6 and SiH4 to form the tungsten-containing layer. Alternatively, operation 112 can use a gas mixture of WF6 and H2 to form the tungsten-containing layer. In another embodiment, operation 112 can use a precursor having bis(dimethylamide-W) to form the tungsten-containing layer. Deposition can be performed at a temperature ranging from about 150°C to about 450°C and a pressure ranging from about 10 Torr to 350 Torr. In this embodiment, the blocking element 302 may include W, WC, WCN, WCl, WF, WB, WS, or combinations thereof; and may have a thickness in the range of about 0.5 nm to about 10 nm. The importance of this thickness has been discussed with reference to the first embodiment above.

[0045] In the third embodiment, operation 112 forms a barrier 302 by selectively treating the sidewalls 284A' of the WFM layer 284A with fluorine (F) radicals. For example, fluorine radicals can be generated from F2, CF4, NF3, other fluorine-containing gases, or combinations thereof. The fluorine radicals react with the sidewalls 284A' (or the thin outer layer of the WFM layer 284A) to produce the fluorinated barrier 302. In this embodiment, the barrier 302 comprises the material of the WFM layer 284A and fluorine. Aluminum has been shown to have a strong affinity for fluorine. Therefore, the fluorine in the barrier 302 can bind with aluminum elements that may originate from other layers (such as the WFM layer 284B) and prevent aluminum from diffusing into the WFM layer 284A. In this embodiment, the barrier 302 can have a thickness ranging from about 0.5 nm to about 10 nm. The importance of this thickness has been discussed with reference to the first embodiment above.

[0046] At operation 114, method 100 ( Figure 2 For example, the etch mask 290 can be removed via photoresist stripping or other suitable processes. Figure 3G As shown, after removing the etch mask 290, the outer surface (including the top surface) 284A” of the WFM layer 284A is exposed.

[0047] At operation 116, method 100 ( Figure 2 A diffusion barrier (or simply barrier) 304 is selectively formed on the exposed outer surface 284A” of the WFM layer 284A, such as Figure 3HAs shown in the diagram, barrier 304 is not formed on the gate dielectric layer 282 of FET 200B. Barrier 304 is formed to prevent or substantially block the diffusion of chemical elements (such as Al) into the WFM layer 284A in FET 200A. In other words, barrier 304 has a low dielectric constant for aluminum and / or other chemical elements that may adversely affect the WFM layer 284A in FET 200A. Furthermore, barrier 304 is conductive, making it part of the gate electrode of FET 200A. Two methods of forming barrier 304 are discussed below. Alternative methods of forming barrier 304 are also contemplated.

[0048] In the first embodiment, operation 116 forms the barrier 304 by selectively depositing a tungsten-containing layer as a barrier 304 on the outer surface 284A”. The tungsten-containing layer is not deposited on the gate dielectric layer 282. Therefore, the deposition is selective. This embodiment of operation 116 can be the same as the second embodiment of operation 112. For example, operation 116 can use a precursor having WCl5 and H2 with B2H6 or SiH4 as a reducing agent, a precursor having WF6 and H2, a precursor having WF6 and SiH4, or a precursor having bis(dimethylamide-W) to form the tungsten-containing layer. Deposition can The operation is performed at a temperature ranging from about 150°C to about 450°C and a pressure ranging from about 10 Torr to 350 Torr. In this embodiment, the stop 304 may include W, WC, WCN, WCl, WF, WB, WS, or combinations thereof; and may have a thickness ranging from about 0.5 nm to about 10 nm. The importance of this thickness has been discussed with reference to the first embodiment of operation 112 above. In the embodiment, the stop 302 and the stop 304 are formed to have different thicknesses. In an alternative embodiment, the stop 302 and the stop 304 are formed to have the same thickness.

[0049] In the second embodiment, operation 116 forms the barrier 304 by selectively treating the outer surface 284A” with fluorine (F) radicals. This embodiment of operation 116 can be the same as the third embodiment of operation 112. For example, the fluorine radicals can be generated from F2, CF4, NF3, other fluorine-containing gases, or combinations thereof. The fluorine radicals react with the outer surface 284A” (or the thin outer layer of the WFM layer 284A) to produce the fluorinated barrier 304. In this embodiment, the barrier 304 comprises the material of the WFM layer 284A and fluorine. In this embodiment, the barrier 304 can have a thickness in the range of about 0.5 nm to about 10 nm. The importance of this thickness has been discussed above.

[0050] In some embodiments, barriers 302 and 304 comprise different materials. For example, barrier 302 can be formed using the first embodiment of operation 112 (therefore, barrier 302 comprises an oxide), and barrier 304 comprises a tungsten-containing layer or a fluorine-containing layer as described above with reference to operation 116. As another example, barrier 302 comprises a tungsten-containing layer, and barrier 304 comprises a fluorine-containing layer. As yet another example, barrier 302 comprises a fluorine-containing layer, and barrier 304 comprises a tungsten-containing layer. In some embodiments, barriers 302 and 304 comprise the same material, although they are formed separately. For example, both may comprise a tungsten-containing layer or a fluorine-containing layer.

[0051] At operation 118, method 100 ( Figure 2 Another work function metal (WFM) layer 284B is formed above the gate dielectric layer 282 in FET 200B and above the barrier 304 in FET 200A, such as Figure 3I As shown in the diagram, WFM layer 284B is also deposited over barrier 302. Barrier 302 is laterally disposed between a portion of WFM layer 284B of FET 200B and a portion of WFM layer 284A of FET 200A. In an embodiment, barrier 302 is in direct contact with a portion of WFM layer 284B of FET 200B and a portion of WFM layer 284A of FET 200A. Barrier 304 is sandwiched between a portion of WFM layer 284B of FET 200A and a portion of WFM layer 284A of FET 200A. In an embodiment, barrier 304 is in direct contact with a portion of WFM layer 284B of FET 200A and a portion of WFM layer 284A of FET 200A. Barriers 302 and 304 separate WFM layer 284A from WFM layer 284B (but may not be insulating). WFM layers 284A and 284B comprise different materials. In this embodiment, WFM layer 284B comprises aluminum. For example, WFM layer 284B may comprise TiAlN, TaAlN, TiAl, TiAlC, TiAlSiC, TaAl, TaAlC, or TaSiAlC. Barriers 302 and 304 prevent aluminum in WFM layer 284B from diffusing into WFM layer 284A. In alternative embodiments, WFM layer 284B may include other elements. In some examples, WFM layer 284B has a thickness of about 1 nm to about 2.5 nm, such as about 1 nm to about 1.5 nm. WFM layer 284B is formed by any of the processes described herein, such as ALD, CVD, PVD, other suitable processes, or combinations thereof. WFM layer 284B may comprise a single layer of material or multiple layers of material.

[0052] At operation 120, method 100 ( Figure 2A bulk metal layer 286 is formed above the WMF layer 284B in FETs 200A and 200B, such as... Figure 3J As shown. For example, a CVD or PVD process deposits a bulk metal layer 286 such that it fills any remaining portion of the gate trench 275 (see...). Figure 3A-1 , Figure 3A-2 and Figure 3A-3 The body metal layer 286 comprises a suitable conductive material, such as Al, W, and / or Cu. The body metal layer 286 may additionally or collectively comprise other metals, metal oxides, metal nitrides, other suitable materials, or combinations thereof. In some embodiments, one or more WFM layers (not shown) are formed (e.g., via ALD) over WFM layers 284A and 284B prior to the formation of the body metal layer 286. In some embodiments, a stop layer (not shown) (e.g., via ALD) is formed over WFM layers 284A and 284B prior to the formation of the body metal layer 286, such that the body metal layer 286 is disposed on the stop layer. After depositing the body metal layer 286, a planarization process can then be performed to remove excess gate material from the device 200. For example, a CMP process is performed until the top surface of the ILD layer 270 is reached (exposed).

[0053] At operation 122, method 100 ( Figure 2 Further manufacturing processes are performed, such as forming contacts electrically connected to the source / drain components 260, forming gate vias electrically connected to the body metal layer 286, and forming multilayer interconnects that connect transistors 200A and 200B to various portions of the device 200 to form a complete IC.

[0054] Figure 4 This is a flowchart of another embodiment of method 100. In this embodiment, method 100 ( Figure 4 Skip (or omit) operation 112 and proceed from operation 110 to operation 114. At operation 114, method 100 ( Figure 4 Remove the etch mask 290, as discussed above. The resulting structure is shown in... Figure 5A In the middle, the sidewall surface 284A' and other outer surfaces 284A” are exposed. Then, method 100 ( Figure 4 Operation 116A is performed to simultaneously form blocking elements 302 and 304 on surfaces 284A' and 284A'". The resulting structure is shown in Figure 5B In the middle. A stopper 302 is formed on the sidewall 284A', and a stopper 304 is formed on other outer surfaces 284A'". Operation 116A and reference. Figure 2The operation discussed is the same as operation 116, except that it processes more surfaces than operation 116. For example, in a first embodiment, operation 116A forms barriers 302 and 304 by selectively depositing a tungsten-containing layer on the exposed surfaces 284A' and 284A" of the WFM layer 284A, which is similar to the first embodiment of operation 116. In a second embodiment, operation 116A forms barriers 302 and 304 by selectively treating the exposed surfaces 284A' and 284A" of the WFM layer 284A with fluorine (F) radicals, which is similar to the second embodiment of operation 116. In this embodiment of method 100, barriers 302 and 304 comprise the same material. For example, depending on which embodiment of operation 116A is used, both may comprise a tungsten-containing layer or a fluorine-containing layer. After completing operation 116A, method 100 ( Figure 4 Proceed to operation 118, as per reference. Figure 2 The subject of discussion.

[0055] Figure 6 This is a flowchart of another embodiment of method 100. In this embodiment, method 100 ( Figure 6 Skip (or omit) operation 116 and proceed from operation 114 (see...) Figure 3G The process proceeds to operation 118. Therefore, in this embodiment, no blocking element 304 is formed. At operation 118, method 100 ( Figure 6 A WFM layer 284B is formed above the gate dielectric layer 282 in FET 200B, above the barrier 302, and above the WFM layer 284A in FET 200A, such as Figure 7A As shown in the diagram. WFM layer 284B can directly contact WFM layer 284A in FET 200A. Then, method 100 ( Figure 6 The process proceeds to operation 120 to form a bulk metal layer 286 over the WMF layer 284B in FETs 200A and 200B, such as... Figure 7B As shown. In this embodiment of method 100, only the blocking member 302 is formed.

[0056] Figure 8Another embodiment of the device 200 according to the present invention is shown. Device 200 includes FETs 200A, 200B, and 200C arranged side-by-side. FETs 200A, 200B, and 200C each include gate stacks 240A, 240B, and 240C, and the three gate stacks 240A-C have different work functions. Gate stack 240A includes WFM layers 284A, 284B, and 284C, wherein WFM layer 284A is disposed above gate dielectric layer 282, WFM layer 284B is disposed above WFM layer 284A, and WFM layer 284C is disposed above WFM layer 284B. Gate stack 240B includes a WFM layer 284B disposed above gate dielectric layer 282 and a WFM layer 284C disposed above WFM layer 284B. Gate stack 240C includes a WFM layer 284C disposed above gate dielectric layer 282. In one embodiment, WFM layer 284C includes an element that readily diffuses outward (such as aluminum). Therefore, diffusion barriers 302 and 304 (which may include the same or different materials discussed above) are formed between WFM layer 284C and WFM layer 284B to prevent the element in WFM layer 284C from diffusing into WFM layer 284B. In various embodiments, the gate stack in device 200 may include any suitable number of WFM layers, and barriers 302 and 304 may be formed over any WFM layer.

[0057] While not intended to be limiting, one or more embodiments of the present invention provide numerous benefits for semiconductor devices and their fabrication. For example, embodiments of the present invention provide a method for forming a diffusion barrier on a function metal layer. The diffusion barrier can effectively prevent elements (such as aluminum) in adjacent structures from diffusing into the function metal layer, thereby improving the uniformity of the threshold voltage of transistors on an IC. In other words, the present invention can provide uniform threshold voltages for transistors of the same type in an IC. The diffusion barrier also reduces defects associated with the metal gate during the manufacturing process and throughout the IC's operational lifetime. This embodiment can be readily integrated into existing CMOS manufacturing processes.

[0058] In one example aspect, the invention relates to a method comprising depositing a gate dielectric layer over a semiconductor channel layer; depositing a work function (WF) metal layer over the gate dielectric layer; forming an etch mask that covers a second portion of the WF metal layer and has an opening over a first portion of the WF metal layer; and etching the WF metal layer through the etch mask to remove the first portion of the WF metal layer while retaining the second portion of the WF metal layer, wherein after etching, the sidewalls of the second portion of the WF metal layer are exposed. The method further includes forming a first barrier on the sidewalls of the second portion of the WF metal layer and depositing a gate metal layer, wherein the first portion of the gate metal layer is deposited over the gate dielectric layer and at the same level as the first barrier, the second portion of the gate metal layer is deposited over the first barrier and the second portion of the WF metal layer, and the first barrier is disposed between the first portion of the gate metal layer and the second portion of the WF metal layer.

[0059] In one embodiment of the method, the gate metal layer comprises aluminum, and the first barrier has a low dielectric constant for aluminum. In another embodiment, the formation of the first barrier includes applying an oxidant to the sidewall of a second portion of the WF metal layer. In yet another embodiment, the oxidant comprises H₂O₂ or ozonated deionized water.

[0060] In one embodiment of the method, forming the first barrier includes selectively depositing a tungsten-containing layer as the first barrier, wherein the tungsten-containing layer is deposited on the sidewall of a second portion of the WF metal layer, but not on the gate dielectric layer. In another embodiment, forming the first barrier includes applying a precursor having WCl5 and H2 and B2H6 or SiH4, WF6 and SiH4, WF6 and H2, or bis(dimethylamide-W) as a reducing agent.

[0061] In one embodiment, the formation of the first barrier includes selectively treating the sidewalls of a second portion of the WF metal layer with fluorine radicals.

[0062] In another embodiment, after the formation of the first barrier and before the deposition of the gate metal layer, the method further includes removing the etch mask to expose the top surface of the second portion of the WF metal layer and forming a second barrier on the top surface of the second portion of the WF metal layer. In a further embodiment, forming the second barrier includes selectively depositing another tungsten-containing layer as the second barrier, wherein the other tungsten-containing layer is deposited on the top surface of the second portion of the WF metal layer but not on the gate dielectric layer. In another embodiment, forming the second barrier includes selectively treating the top surface of the second portion of the WF metal layer with fluorine radicals.

[0063] In another example aspect, the invention relates to a method comprising depositing a gate dielectric layer over a substrate and depositing a power function (WF) metal layer over the gate dielectric layer, wherein the gate dielectric layer and the WF metal layer are deposited over regions defining first and second devices having different threshold voltages. The method further comprises forming an etch mask covering the WF metal layer for the second device and etching the WF metal layer through the etch mask to remove a first portion of the WF metal layer while retaining a second portion of the WF metal layer, wherein sidewalls of the second portion of the WF metal layer are exposed after etching. The method further comprises removing the etch mask to expose a top surface of the second portion of the WF metal layer; and forming a first barrier on the sidewalls of the second portion of the WF metal layer and a second barrier on the top surface of the second portion of the WF metal layer.

[0064] In one embodiment, the method further includes depositing a gate metal layer, wherein a first portion of the gate metal layer is deposited at the same layer level as the first barrier, and a second portion of the gate metal layer is deposited over the first and second barriers. In a further embodiment, the gate metal layer comprises aluminum, and the first and second barriers have a low dielectric constant relative to aluminum.

[0065] In one embodiment, both the first and second blocking elements comprise tungsten. In another embodiment, both the first and second blocking elements comprise fluorine.

[0066] In yet another example aspect, the present invention relates to a semiconductor structure including a first transistor adjacent to a second transistor. The first transistor includes a first gate metal layer located above a gate dielectric layer, and the second transistor includes a second gate metal layer located above a gate dielectric layer, wherein the first and second gate metal layers comprise different materials. The semiconductor structure also includes a first barrier laterally disposed between the first and second gate metal layers, wherein one of the first and second gate metal layers comprises aluminum, and the first barrier has a low dielectric constant for aluminum.

[0067] In one embodiment, the first gate metal layer also extends over the first barrier and the second gate metal layer. In yet another embodiment, the semiconductor structure further includes a second barrier perpendicularly disposed between the first gate metal layer and the second gate metal layer.

[0068] In one embodiment, the first barrier comprises oxygen and a material included in the second gate metal layer. In another embodiment, the first barrier comprises tungsten or fluorine.

[0069] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a base to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the invention.

Claims

1. A method for forming a semiconductor structure, comprising: Deposit a gate dielectric layer above the semiconductor channel layer; A work function (WF) metal layer is deposited above the gate dielectric layer; An etching mask is formed, which covers a second portion of the power function metal layer and has an opening over a first portion of the power function metal layer; The power function metal layer is etched through the etching mask to remove the first portion of the power function metal layer while retaining the second portion of the power function metal layer, wherein, after the etching, the sidewalls of the second portion of the power function metal layer are exposed; A first blocking element is formed on the sidewall of the second portion of the functional metal layer; and A gate metal layer is deposited, wherein a first portion of the gate metal layer is deposited above the gate dielectric layer and at the same level as the first barrier, a second portion of the gate metal layer is deposited above the first barrier and the second portion of the power function metal layer, and the first barrier is disposed between the first portion of the gate metal layer and the second portion of the power function metal layer.

2. The method according to claim 1, wherein, The gate metal layer comprises aluminum, and the first barrier has a low dielectric constant for aluminum.

3. The method according to claim 1, wherein, The formation of the first barrier includes applying an oxidant to the sidewall of the second portion of the functional metal layer.

4. The method according to claim 3, wherein, The oxidant includes H2O2 or ozonated deionized water.

5. The method according to claim 1, wherein, The formation of the first barrier includes selectively depositing a tungsten-containing layer as the first barrier, wherein the tungsten-containing layer is deposited on the sidewall of the second portion of the power function metal layer, but not on the gate dielectric layer.

6. The method according to claim 5, wherein, The formation of the first barrier includes applying a precursor having WCl5 and H2 and B2H6 or SiH4 as a reducing agent; WF6 and SiH4; WF6 and H2; or bis(dimethylamide-W).

7. The method according to claim 1, wherein, The formation of the first barrier includes selectively treating the sidewall of the second portion of the work function metal layer with fluorine radicals.

8. The method of claim 1, further comprising, after the formation of the first barrier and before the deposition of the gate metal layer: Remove the etching mask to expose the top surface of the second portion of the power functional metal layer; as well as A second blocking element is formed on the top surface of the second portion of the functional metal layer.

9. The method according to claim 8, wherein, The formation of the second barrier includes selectively depositing another tungsten-containing layer as the second barrier, wherein the other tungsten-containing layer is deposited on the top surface of the second portion of the power function metal layer, but not on the gate dielectric layer.

10. The method according to claim 8, wherein, The formation of the second barrier includes selectively treating the top surface of the second portion of the work function metal layer with fluorine radicals.

11. A method for forming a semiconductor structure, comprising: Deposit a gate dielectric layer over the substrate; A power function (WF) metal layer is deposited over the gate dielectric layer, wherein the gate dielectric layer and the power function metal layer are deposited over a region defining a first device and a second device having different threshold voltages; An etching mask is formed, the etching mask covering the work function metal layer used for the second device; The power function metal layer is etched through the etching mask to remove a first portion of the power function metal layer while retaining a second portion of the power function metal layer, wherein, after the etching, the sidewalls of the second portion of the power function metal layer are exposed; Remove the etching mask to expose the top surface of the second portion of the power functional metal layer; and A first blocking member is formed on the sidewall of the second portion of the power functional metal layer, and a second blocking member is formed on the top surface of the second portion of the power functional metal layer.

12. The method of claim 11, further comprising: A gate metal layer is deposited, wherein a first portion of the gate metal layer is deposited at the same level as the first barrier, and a second portion of the gate metal layer is deposited above the first barrier and the second barrier.

13. The method according to claim 12, wherein, The gate metal layer comprises aluminum, and the first and second blocking elements have low dielectric constants relative to aluminum.

14. The method according to claim 11, wherein, Both the first and second blocking elements comprise tungsten.

15. The method according to claim 11, wherein, Both the first and second blocking elements contain fluorine.

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