Semiconductor device and method of manufacturing a semiconductor device

Abstract

Embodiments of the present disclosure relate to semiconductor devices and methods of manufacturing semiconductor devices. A semiconductor device and a method of manufacturing the same can include a stack including conductive layers and insulating layers alternately stacked; a separation insulating structure passing through the stack and including a line pattern, a first protrusion pattern protruding from the line pattern to one side, and a second protrusion pattern protruding from the line pattern to another side; first passage structures passing through the stack at the one side of the separation insulating structure, respectively, and enclosing the first protrusion pattern; and second passage structures passing through the stack at the another side of the separation insulating structure, respectively, and enclosing the second protrusion pattern.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0148739, filed on November 9, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to electronic devices, and more specifically, to semiconductor devices and methods of manufacturing semiconductor devices. Background Technology

[0004] Recently, as the integration density of two-dimensional memory devices, which form memory cells in a single layer on a substrate, has reached its limit, three-dimensional memory devices have been proposed, in which memory cells are vertically stacked on the substrate. Furthermore, various structures and manufacturing methods are being developed to improve the operational reliability of memory devices with three-dimensional structures. Summary of the Invention

[0005] Embodiments of this disclosure provide semiconductor devices with stable structures and improved properties, and methods for manufacturing semiconductor devices.

[0006] According to embodiments of the present disclosure, a semiconductor device may include: a stack, which may include alternately stacked conductive layers and insulating layers; a separation insulating structure passing through the stack, and may include: a line pattern, a first protruding pattern protruding from the line pattern to one side, and a second protruding pattern protruding from the line pattern to the other side; a first channel structure passing through the stack and surrounding the first protruding pattern at one side of the separation insulating structure; and a second channel structure passing through the stack and surrounding the second protruding pattern at the other side of the separation insulating structure.

[0007] According to embodiments of the present disclosure, a semiconductor device may include: a first channel structure passing through a stack; a second channel structure passing through the stack; and a separation insulating structure passing through the stack, and may include a line pattern positioned between the first channel structure and the second channel structure, a first protruding pattern protruding from the line pattern into the first channel structure, and a second protruding pattern protruding from the line pattern into the second channel structure.

[0008] According to embodiments of the present disclosure, a method of manufacturing a semiconductor device may include: forming a stack comprising alternating stacked first and second material layers; forming a channel structure through the stack; forming a trench through the stack, and may include: forming line portions extending between the channel structures and protrusions extending from the line portions into the channel structures; and forming a separation insulating structure in the trench.

[0009] Semiconductor devices with stable structures and improved reliability can be provided. Furthermore, the manufacturing process for semiconductor devices can be simplified and costs reduced. Attached Figure Description

[0010] Figures 1A to 1D This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 2A and 2B This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 3A and 3B This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figures 4A to 7A Figures 4B to 7B are illustrations of a method for manufacturing a semiconductor device according to embodiments of the present disclosure.

[0014] Figure 8 This is a block diagram illustrating a memory system according to an embodiment of the present disclosure.

[0015] Figure 9 This is a block diagram illustrating a memory system according to an embodiment of the present disclosure.

[0016] Figure 10 This is a block diagram illustrating a memory system according to an embodiment of the present disclosure.

[0017] Figure 11 This is a block diagram illustrating a memory system according to an embodiment of the present disclosure.

[0018] Figure 12 This is a block diagram illustrating a memory system according to an embodiment of the present disclosure. Detailed Implementation

[0019] The specific structural or functional descriptions of embodiments based on the concepts disclosed in this specification or application are merely illustrative to describe embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and are not limited to the embodiments described in this specification or application.

[0020] Figures 1A to 1D This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. Figure 1A and 1B It's a floor plan. Figure 1C It is along Figure 1A The cross-sectional view taken by line A-A', and Figure 1D yes Figure 1A A magnified view of region B.

[0021] refer to Figures 1A to 1D Semiconductor devices may include stacked ST, discrete insulating structure IS, first channel structure CH1 and second channel structure CH2.

[0022] The stacked ST may include alternately stacked conductive layers 11 and insulating layers 12. The conductive layers 11 may be gate electrodes of memory cells, select transistors, etc. As an example, at least one uppermost conductive layer 11 and at least one lowermost conductive layer 11 may be a lower select line, while the remaining conductive layers 11 may be word lines. The conductive layers 11 may include conductive materials such as polysilicon, tungsten, molybdenum, or another metal. The insulating layers 12 are used to insulate the stacked conductive layers 11 from each other. The insulating layers 12 may include insulating materials such as oxides or nitrides.

[0023] The first channel structure CH1 and the second channel structure CH2 can pass through the stack ST. Each of the first channel structures CH1 and CH2 can be arranged in a first direction I. The first channel structure CH1 can be arranged relative to the second channel structure CH2 in a second direction II that intersects the first direction I. The first channel structure CH1 and the second channel structure CH2 can pass through the stack ST in a third direction III. The third direction III can be a direction protruding from the plane defined by the first direction I and the second direction II. The third direction III can be the stacking direction of the conductive layer 11 and the insulating layer 12. The first channel structure CH1 can be arranged symmetrically with the second channel structure CH2.

[0024] Each first channel structure in the first channel structure CH1 may include a first channel layer 16A, and may also include a first memory layer M1 or a first insulating core 17A, or a combination thereof. The first channel layer 16A may be a region in which a channel for a memory cell or selection transistor is formed. The first channel layer 16A may include a semiconductor material, such as silicon (Si) or germanium (Ge). The first memory layer M1 may include a barrier layer 13A, a data storage layer 14A, or a tunnel insulating layer 15A, or a combination thereof. The data storage layer 14A may include a floating gate, a charge trapping material, polysilicon, a nitride, or a variable resistance material, or a combination thereof. The first insulating core 17A may include an insulating material, such as an oxide, a nitride, and an air gap.

[0025] Each second channel structure in the second channel structure CH2 may include a second channel layer 16B, and may also include a second memory layer M2 or a second insulating core 17B, or a combination thereof. The second channel layer 16B may be a region in which a memory cell or a channel of a selection transistor is formed. The second channel layer 16B may include a semiconductor material, such as silicon (Si) or germanium (Ge). The second memory layer M2 may include a barrier layer 13B, a data storage layer 14B, or a tunnel insulating layer 15B, or a combination thereof. The data storage layer 14B may include a floating gate, a charge trapping material, polysilicon, a nitride, or a variable resistance material, or a combination thereof. The second insulating core 17B may include an insulating material, such as an oxide, a nitride, and an air gap.

[0026] The separation insulation structure IS can be positioned between the first channel structure CH1 and the second channel structure CH2, can pass through the stack ST in the third direction III, and can have a depth that passes through at least one uppermost conductive layer 11. Compared to channel structures CH1 to CH4, the separation insulation structure IS can pass through the stack ST at a shallower depth. As an example, the separation insulation structure IS can have a depth that passes through the select line but not through the word line.

[0027] The separated insulation structure IS may include a line pattern LP and protruding patterns PP1 and PP2 extending from the line pattern LP. The line pattern LP may be positioned between the first channel structure CH1 and the second channel structure CH2, and may extend in a first direction I. The protruding patterns PP1 and PP2 may protrude in a second direction II.

[0028] The separated insulation structure IS may include a line pattern LP, a first protruding pattern PP1, and a second protruding pattern PP2. The first protruding pattern PP1 may be arranged symmetrically with the second protruding pattern PP2.

[0029] As an example, the first protruding pattern PP1 can protrude from the line pattern LP to one side. The first channel structure CH1 can be positioned on one side of the line pattern LP. The first protruding pattern PP1 can be positioned corresponding to the first channel structure CH1. In the plane defined by the first direction I and the second direction II, the first channel structure CH1 can respectively surround the first protruding pattern PP1, and the first protruding pattern PP1 can respectively protrude into the first channel structure CH1.

[0030] According to the hierarchy, the first channel structure CH1 may include a first portion P1 and a second portion P2. In each first channel structure of the first channel structure CH1, the first portion P1 may contact the first protruding pattern PP1, and the second portion P2 may be spaced apart from the first protruding pattern PP1. In a plane, the second portion P2 may have a circular, elliptical, square, or other shapes. The first portion P1 may be similar to the second portion P2 and may have a shape that is partially cut off by the first protruding pattern PP1. In a plane, the first portion P1 may have an area narrower than that of the second portion P2.

[0031] As an example, the second protruding pattern PP2 can protrude from the line pattern LP to the other side. The second channel structure CH2 can be positioned on the other side of the line pattern LP. The second protruding pattern PP2 can be positioned corresponding to the second channel structure CH2. In the plane, the second channel structure CH2 can respectively surround the second protruding pattern PP2. The second protruding pattern PP2 can respectively protrude into the second channel structure CH2.

[0032] Depending on the hierarchy, the second channel structure CH2 may include a first portion P1 and a second portion P2. In each second channel structure of the second channel structure CH2, the first portion P1 may contact the second protruding pattern PP2, and the second portion P2 may be spaced apart from the second protruding pattern PP2. In a plane, the second portion P2 may have a shape such as a full circle, an ellipse, or a square. The first portion P1 may be similar to the second portion P2 and may have a shape partially cut off by the first protruding pattern PP1. In a plane, the first portion P1 may have an area narrower than that of the second portion P2.

[0033] The semiconductor device may further include a third channel structure CH3 and a fourth channel structure CH4. The third channel structure CH3 may extend through the stacked ST on one side of the separate insulating structure IS and may be spaced apart from the first protruding pattern PP1. The fourth channel structure CH4 may extend through the stacked ST on the other side of the separate insulating structure IS and may be spaced apart from the second protruding pattern PP2. The third channel structure CH3 and the fourth channel structure CH4 may be arranged symmetrically. Each of the third channel structure CH3 and the fourth channel structure CH4 may include a channel layer, and may also include a memory layer or an insulating core, or a combination thereof.

[0034] The semiconductor device may also include contact plugs CT or wires M11 to M14, or may include combinations thereof, wherein the contact plugs CT may be respectively connected to channel structures CH1 to CH4. Channel structures CH1 to CH4 and wires M11 to M14 may be electrically connected via the contact plugs CT. Wires M11 to M14 may extend in a second direction II and may be commonly connected to channel structures symmetrically positioned among a first channel structure CH1 and a third channel structure CH3 located on one side of a separating insulating structure IS, and a second channel structure CH2 and a fourth channel structure CH4 located on the other side of the separating insulating structure IS. As an example, the first wire M11 may be electrically connected to the first channel structure CH1 and the second channel structure CH2. For reference, it should be noted that only a portion of the contact plugs CT or wires M11 to M14 are in... Figure 1B It is shown in the middle.

[0035] According to the structure described above, memory cells or select transistors can be positioned at the intersection of channel structures CH1 to CH4 and conductive layer 11. The memory cell or select transistor corresponding to the second portion P2 of the first channel structure CH1 and the second channel structure CH2 has a gate-all-around (GAA) structure, wherein the gate electrode completely surrounds the sidewalls of the channel layer. The memory cell or select transistor corresponding to the second portion P2 of the first channel structure CH1 and the second channel structure CH2 can have a shape partially cut by the separating insulating structure IS, and can be operated as a real memory cell or a real select transistor, rather than a dummy transistor.

[0036] Figure 2A and 2B This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0037] refer to Figure 2A The semiconductor device may include a conductive layer 11, a channel structure CH', and a separation insulating structure IS'. The channel structure CH' may include a memory layer M', a channel layer 16', and an insulating core 17'. The memory layer M' may include a barrier layer 13', a data storage layer 14', or a tunnel insulating layer 15', or a combination thereof.

[0038] The separation insulating structure IS' does not include a protruding pattern and has a linear shape extending in one direction, such that the channel structure CH' is cut into a linear shape, and the channel layer 16' positioned near the center of the channel structure CH' is cut relatively less. In this case, since the C region of the channel layer 16' is not covered by the conductive layer 11, the bias voltage applied to the conductive layer 11 may not be sufficiently transferred to the C region during erase or programming operations, which may degrade operating characteristics, such as slower operating speed.

[0039] refer to Figure 2B The semiconductor device may include a conductive layer 11, a channel structure CH, and a separation insulating structure IS. The channel structure CH may include a memory layer M, a channel layer 16, and an insulating core 17. The memory layer M may include a barrier layer 13, a data storage layer 14, or a tunnel insulating layer 15, or a combination thereof. The separation insulating structure IS may include a line pattern LP and a protruding pattern PP, such that the channel layer 16 can also be cut by the protruding pattern PP. (Comparison) Figure 2A and 2B Region C of the channel structure CH' can be cut open by the protruding pattern PP so that the channel layer 16 can be completely covered by the conductive layer 11. In addition, during erase or programming operations, the bias voltage applied to the conductive layer 11 can be sufficiently transferred to the channel layer 16.

[0040] Figure 3A and 3B This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. Figure 3B It can be along Figure 3A The cross-sectional view taken by line B-B'. In the following text, content repeated from the previous description is omitted.

[0041] refer to Figure 3A and 3B The semiconductor device may include a stacked ST, a discrete insulating structure IS, a first channel structure CH1, and a second channel structure CH2. The semiconductor device may also include a third channel structure CH3 or a fourth channel structure CH4, or a combination thereof.

[0042] The stacked ST may include alternately stacked conductive layers 31 and insulating layers 32. Each first channel structure in the first channel structure CH1 may include a first channel layer 36A, and may also include a first memory layer M1 or a first insulating core 37A, or a combination thereof. The first memory layer M1 may include a barrier layer 33A, a data storage layer 34A, or a tunnel insulating layer 35A, or a combination thereof. Each second channel structure in the second channel structure CH2 may include a second channel layer 36B, and may also include a second memory layer M2 or a second insulating core 37B, or a combination thereof. The second memory layer M2 may include a barrier layer 33B, a data storage layer 34B, or a tunnel insulating layer 35B, or a combination thereof.

[0043] The separate insulation structure IS can be positioned between the first channel structure CH1 and the second channel structure CH2. The first channel structure CH1 can be positioned on one side of the separate insulation structure IS, and the second channel structure CH2 can be positioned on the other side of the separate insulation structure IS. Based on the separate insulation structure IS, the first channel structure CH1 and the second channel structure CH2 can be arranged asymmetrically.

[0044] The separated insulation structure IS may include a line pattern LP, a first protruding pattern PP1 and a second protruding pattern PP2 protruding from the line pattern LP. The first protruding pattern PP1 and the second protruding pattern PP2 may be arranged asymmetrically. A first channel structure CH1 may surround the first protruding pattern PP1, and the first protruding pattern PP1 may protrude into the first channel structure CH1. A second channel structure CH2 may surround the second protruding pattern PP2, and the second protruding pattern PP2 may protrude into the second channel structure CH2.

[0045] The third channel structure CH3 can be spaced apart from the first protruding pattern PP1 and can be positioned on one side of the separate insulation structure IS. The fourth channel structure CH4 can be spaced apart from the second protruding pattern PP2 and can be positioned on the other side of the separate insulation structure IS. The third channel structure CH3 and the fourth channel structure CH4 can be arranged asymmetrically.

[0046] Based on the structure described above, even if the memory cell or select transistor has a shape partially cut by the isolated insulating structure IS, the memory cell or select transistor can still be used as a real memory cell or an actual select transistor instead of a dummy one. Furthermore, by asymmetrically arranging the first to fourth channel structures CH1 to CH4, the integration density of the semiconductor device can be improved.

[0047] Figures 4A to 7A Figures 4B to 7B are illustrations of a method of manufacturing a semiconductor device according to embodiments of the present disclosure. Each figure B is a cross-sectional view taken along line C-C' of Figure A.

[0048] refer to Figure 4A and 4B A stack ST is formed, wherein the stack ST may include an alternately stacked first material layer 41 and a second material layer 42. The first material layer 41 may include a material having high etch selectivity relative to the second material layer 42. For example, the first material layer 41 may include a sacrificial material, such as a nitride, and the second material layer 42 may include an insulating material, such as an oxide. As another example, the first material layer 41 may include a conductive material, such as polysilicon, tungsten, and molybdenum, and the second material layer 42 may include an insulating material, such as an oxide.

[0049] Subsequently, a channel structure CH is formed through the stack ST. After forming an opening through the stack, the channel structure CH can be formed in the opening. As an example, a memory layer M can be formed in the opening, and a channel layer 46 can be formed in the memory layer M. The memory layer M may include a barrier layer 43, a data storage layer 44, or a tunnel insulating layer 45, or a combination thereof. The opening can be completely filled with the channel layer 46, or an insulating core 47 can be formed in the channel layer 46.

[0050] refer to Figures 5A to 6B The trench T is formed through the stacked ST. Using mask pattern 48, the trench T can be formed by an etching process.

[0051] First, refer to Figure 5A and 5B A mask pattern 48 is formed on the stacked ST. The mask pattern 48 may include a material with high etch selectivity relative to the first material layer 41 and the second material layer 42.

[0052] The mask pattern 48 may include an opening OP, which includes a first portion OP_P1 and a second portion OP_P2. The first portion OP_P1 may have a linear shape extending in a first direction I, may be positioned between adjacent channel structures CH in a second direction II, and may expose the stack ST. The channel structures CH positioned on both sides of the first portion OP_P1 may be partially exposed by the first portion OP_P1. The first portion OP_P1 may partially overlap with the channel structures CH on both sides in the second direction II.

[0053] The second part OP_P2 may protrude from the first part OP_P1 in the second direction II and may be positioned to correspond to the channel structure CH respectively. Each second part in the second part OP_P2 may expose a portion of each channel structure in the channel structure CH. The channel layer 46 may be exposed by the second part OP_P2. The insulating core 47 or the memory layer M may also be exposed by the second part OP_P2.

[0054] Subsequently, reference Figure 6A and 6B A trench T is formed. The trench T can be formed by etching the stacked ST and channel structure CH using a mask pattern 48 as an etch stop layer. The trench T can be formed to a depth penetrating at least one uppermost first material layer 41. As an example, the trench T can be formed to a depth penetrating the first material layer 41 corresponding to the select line within the first material layers 41 but not penetrating the first material layer 41 corresponding to the word line.

[0055] The trench T may have a shape corresponding to the opening OP and may include a line portion T_LP and a protruding portion T_PP. The line portion T_LP may have a linear shape extending in a first direction I and may extend between adjacent channel structures CH in a second direction II. The protruding portion T_PP may protrude from the line portion T_LP in the second direction II and may protrude into the channel structure CH respectively. The area of ​​the channel layer 46 not surrounded by the first material layer 41 may be cut by the protruding portion T_PP.

[0056] refer to Figure 7A and 7B A separate insulating structure IS is formed. After the insulating layer is formed to fill the trench T, the separate insulating structure IS can be formed by planarizing the insulating layer, wherein the separate insulating structure IS may include an insulating material such as an oxide or nitride.

[0057] The separated insulation structure IS may include a line pattern LP and a protruding pattern PP. The line pattern LP may extend between the channel structures CH and may extend in a first direction I. The protruding pattern PP may protrude from the line pattern LP and may protrude into the channel structure CH.

[0058] For reference, although not shown in this figure, the process of replacing the first material layer 41 with a third material layer can be additionally performed. When the first material layer 41 comprises a sacrificial material and the second material layer 42 comprises an insulating material, the first material layer 41 can be replaced with a conductive layer. As another example, when the first material layer 41 comprises a conductive material and the second material layer 42 comprises an insulating material, the first material layer 41 can be siliconized. The process of replacing the first material layer 41 with a third material layer can be performed before or after the formation of the separated insulating structure IS.

[0059] According to the manufacturing method described above, using mask pattern 48, the stacked ST and channel structure CH can be etched. Therefore, the line portion T_LP and the protrusion portion T_PP can be formed simultaneously in a single etching process. While patterning the first material layer 41 through the line portion T_LP, the areas in the channel layer 46 not surrounded by the first material layer 41 can be removed.

[0060] Figure 8 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0061] refer to Figure 8 The memory system 1000 may include a memory device 1200 for storing data and a controller 1100 for communicating between the memory device 1200 and the host 2000.

[0062] The host 2000 can be a device or system that stores data in or retrieves data from the memory system 1000. The host 2000 can generate requests for various operations and can output these requests to the memory system 1000. Requests may include programming requests for programming operations, read requests for read operations, erase requests for erase operations, etc. The host 2000 can communicate with the memory system 1000 through various interfaces, such as Peripheral Component Interconnect Fast (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), Non-Volatile Memory Fast (NVMe), Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE)).

[0063] The host 2000 may include at least one of a computer, portable digital device, tablet computer, digital camera, digital audio player, television, wireless communication device or cellular phone, but the embodiments disclosed herein are not limited thereto.

[0064] The controller 1100 generally controls the operation of the memory system 1000, and can control the memory device 1200 according to requests from the host 2000. The controller 1100 can control the memory device 1200 so that programming, reading, erasing, and other operations can be performed according to requests from the host 2000. Alternatively, even if no request is received from the host 2000, the controller 1100 can perform background operations to improve the performance of the memory system 1000.

[0065] To control the operation of memory device 1200, controller 1100 can send control signals and data signals to memory device 1200. Control signals and data signals can be sent to memory device 1200 via different input / output lines. Data signals can include commands, addresses, or data. Control signals can be used to segment the data signals into input sections.

[0066] Under the control of controller 1100, memory device 1200 can perform programming operations, reading operations, erasing operations, etc. Memory device 1200 can be implemented using a volatile memory device whose stored data is corrupted when power is cut off, or a non-volatile memory device whose stored data is retained even when power is cut off. Memory device 1200 can be [referenced above]. Figures 1A to 3B The semiconductor device described herein. The memory device 1200 can be as described in the above reference. Figures 4A to 7BThe semiconductor device manufactured by the described manufacturing method. As an embodiment, the semiconductor memory device may include: a stack including alternately stacked conductive layers and insulating layers; a separation insulating structure passing through the stack and including a line pattern, a first protruding pattern protruding from the line pattern to one side, and a second protruding pattern protruding from the line pattern to the other side; a first channel structure passing through the stack and surrounding the first protruding pattern at one side of the separation insulating structure; and a second channel structure passing through the stack and surrounding the second protruding pattern at the other side of the separation insulating structure.

[0067] Figure 9 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0068] refer to Figure 9 The memory system 30000 can be implemented as a cellular phone, smartphone, tablet computer, personal computer (PC), personal digital assistant (PDA), or wireless communication device. The memory system 30000 may include a memory device 2200 and a memory controller 2100 capable of controlling the operation of the memory device 2200.

[0069] The memory controller 2100 can control the data access operations of the memory device 2200, such as programming operations, erasing operations, and reading operations, under the control of the processor 3100.

[0070] Under the control of the memory controller 2100, the data programmed in the memory device 2200 can be output through the display 3200.

[0071] The radio transceiver 3300 can transmit and receive radio signals via the antenna ANT. For example, the radio transceiver 3300 can convert the radio signals received via the antenna ANT into signals that can be processed by the processor 3100. Therefore, the processor 3100 can process the signals output from the radio transceiver 3300 and send the processed signals to the memory controller 2100 or the display 3200. The memory controller 2100 can send the signals processed by the processor 3100 to the memory device 2200. Alternatively, the radio transceiver 3300 can convert the signals output from the processor 3100 into radio signals and output the converted radio signals to an external device via the antenna ANT. The input device 3400 can be a device capable of inputting control signals for controlling the operation of the processor 3100 or data to be processed by the processor 3100. The input device 3400 can be implemented as a pointing device, such as a touchpad or computer mouse, keypad, or keyboard. The processor 3100 can control the operation of the display 3200 so that data output from the memory controller 2100, data output from the radio transceiver 3300, or data output from the input device 3400 can be output through the display 3200.

[0072] According to an embodiment, the memory controller 2100, which is capable of controlling the operation of the memory device 2200, can be implemented as part of the processor 3100, or it can be implemented as a chip separate from the processor 3100.

[0073] Figure 10 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0074] refer to Figure 10 The memory system 40000 can be implemented as a personal computer (PC), tablet computer, netbook, e-reader, personal digital assistant (PDA), portable multimedia player (PMP), MP3 player or MP4 player.

[0075] The memory system 40000 may include a memory device 2200 and a memory controller 2100 capable of controlling the data processing operations of the memory device 2200.

[0076] Based on the data input via input device 4200, processor 4100 can output the data stored in memory device 2200 via display 4300. For example, input device 4200 can be implemented as a pointing device, such as a touchpad or computer mouse, keypad or keyboard.

[0077] The processor 4100 can control the overall operation of the memory system 40000 and control the operation of the memory controller 2100. According to an embodiment, the memory controller 2100, which is capable of controlling the operation of the memory device 2200, can be implemented as part of the processor 4100 or can be implemented as a chip separate from the processor 4100.

[0078] Figure 11 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0079] refer to Figure 11 The memory system 50000 can be implemented as an image processing device, such as a digital camera, a portable phone equipped with a digital camera, a smartphone equipped with a digital camera, or a tablet computer equipped with a digital camera.

[0080] The memory system 50000 may include a memory device 2200 and a memory controller 2100, which is capable of controlling data processing operations of the memory device 2200, such as programming operations, erasing operations, or reading operations.

[0081] The image sensor 5200 of the memory system 50000 can convert optical images into digital signals. The converted digital signals can be sent to the processor 5100 or the memory controller 2100. Under the control of the processor 5100, the converted digital signals can be output through the display 5300 or stored in the memory device 2200 through the memory controller 2100. Furthermore, under the control of the processor 5100 or the memory controller 2100, the data stored in the memory device 2200 can be output through the display 5300.

[0082] According to an embodiment, the memory controller 2100, which is capable of controlling the operation of the memory device 2200, may be implemented as part of the processor 5100 or as a chip separate from the processor 5100.

[0083] Figure 12 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0084] refer to Figure 12 The memory system 70000 can be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 2200, a memory controller 2100, and a card interface 7100.

[0085] The memory controller 2100 can control the data exchange between the memory device 2200 and the card interface 7100. According to an embodiment, the card interface 7100 may be a Secure Digital (SD) card interface or a Multimedia Card (MMC) interface, but is not limited thereto.

[0086] Card interface 7100 can interface for data exchange between host 60000 and memory controller 2100 according to the protocol of host 60000. According to an embodiment, card interface 7100 can support Universal Serial Bus (USB) protocol and IC-USB protocol. Here, card interface 7100 can refer to hardware capable of supporting protocols used by host 60000, software installed in the hardware, or signal transmission methods.

[0087] When the memory system 70000 is connected to the host interface 6200 of the host 60000 (such as a PC, tablet computer, digital camera, digital audio player, mobile phone, console video game hardware, or digital set-top box), the host interface 6200 can perform data communication with the memory device 2200 through the card interface 7100 and the memory controller 2100 under the control of the microprocessor 6100.

Claims

1. A semiconductor device, comprising: Stacking, including alternating stacked conductive and insulating layers; A separate insulating structure extends through the stack and includes: a line pattern, a first protruding pattern protruding from the line pattern to one side, and a second protruding pattern protruding from the line pattern to the other side; A first channel structure passes through the stack and surrounds the first protruding pattern at one side of the separated insulating structure; and The second channel structure passes through the stack and surrounds the second protruding pattern at the other side of the separated insulating structure. The separation insulation structure passes through a portion of the first channel structure adjacent to the separation insulation structure in the first channel structure, and a portion of the second channel structure adjacent to the separation insulation structure in the second channel structure.

2. The semiconductor device of claim 1, wherein the first protruding pattern and the second protruding pattern are arranged symmetrically.

3. The semiconductor device of claim 1, wherein the first protruding pattern and the second protruding pattern are arranged asymmetrically.

4. The semiconductor device according to claim 1, wherein the first channel structure and the second channel structure are arranged symmetrically.

5. The semiconductor device according to claim 1, wherein the first channel structure and the second channel structure are arranged asymmetrically.

6. The semiconductor device of claim 1, wherein the line pattern extends in a first direction, and the first protruding pattern and the second protruding pattern protrude in a second direction intersecting the first direction.

7. The semiconductor device of claim 1, wherein the separation insulating structure penetrates the stack at a shallower depth compared to the first channel structure.

8. The semiconductor device according to claim 1, further comprising: A third channel structure passes through the stack on one side and is spaced apart from the first protruding pattern.

9. The semiconductor device according to claim 8, further comprising: A fourth channel structure passes through the stack on the other side and is spaced apart from the second protruding pattern.

10. The semiconductor device of claim 9, wherein the third channel structure and the fourth channel structure are arranged symmetrically.

11. The semiconductor device of claim 9, wherein the third channel structure and the fourth channel structure are arranged asymmetrically.

12. A semiconductor device, comprising: The first channel structure passes through the stack; A second channel structure passes through the stack; as well as A separate insulating structure extends through the stack and includes: a line pattern positioned between the first channel structure and the second channel structure; a first protruding pattern protruding from the line pattern into the first channel structure; and a second protruding pattern protruding from the line pattern into the second channel structure. The separation insulation structure passes through a portion of the first channel structure adjacent to the separation insulation structure in the first channel structure, and a portion of the second channel structure adjacent to the separation insulation structure in the second channel structure.

13. The semiconductor device of claim 12, wherein the first protruding pattern and the second protruding pattern are arranged symmetrically.

14. The semiconductor device of claim 12, wherein the first protruding pattern and the second protruding pattern are arranged asymmetrically.

15. The semiconductor device of claim 12, wherein the first channel structure and the second channel structure are arranged symmetrically.

16. The semiconductor device of claim 12, wherein the first channel structure and the second channel structure are arranged asymmetrically.

17. A method for manufacturing a semiconductor device, the method comprising: Forming a stack comprising alternating layers of first and second materials; Forming a channel structure through the stack; A groove is formed that passes through the stack and includes a line portion extending between the channel structures and a protruding portion protruding from both sides of the line portion into the interior of the channel structure; as well as A separate insulating structure is formed in the trench.

18. The method of claim 17, wherein forming the trench comprises: A mask pattern is formed, the mask pattern including an opening, the opening including a first portion extending in one direction and a second portion protruding from the first portion on the stack and exposing the channel structure; as well as The trench is formed by etching the stack and the channel structure using the mask pattern as an etch barrier layer.

19. The method of claim 17, wherein the separating insulation structure comprises a line pattern extending between the channel structures and a protruding pattern extending from the line pattern into the channel structure.

20. The method of claim 17, wherein forming the channel structure comprises: Forming an opening through the stack; A memory layer is formed in the opening; as well as A channel layer is formed in the memory layer.

21. The method of claim 20, wherein forming the trench includes removing the area of ​​the channel layer not covered by the first material layer.

Images