Image sensor, method of manufacturing the same, and semiconductor device

Abstract

An image sensor includes a pixel and an isolation structure. The pixel includes a photosensitive region and a circuit region proximate to the photosensitive region. The isolation structure is positioned over the pixel, wherein the isolation structure includes a conductive grid and a dielectric structure covering sidewalls of the conductive grid, and the isolation structure includes an opening or recess that overlaps the photosensitive region. The isolation structure surrounds a peripheral region of the photosensitive region. Embodiments of the present application also relate to methods of manufacturing an image sensor and a semiconductor device.

Description

Technical Field

[0001] Embodiments of this application relate to image sensors, methods of manufacturing the same, and semiconductor devices. Background Technology

[0002] Semiconductor image sensors are used to sense radiation, such as light. Complementary metal-oxide-semiconductor (CMOS) image sensors and charge-coupled device (CCD) sensors are widely used in a variety of applications, such as digital cameras or mobile phone cameras. These sensors utilize pixel arrays in a substrate, including photodiodes and transistors, which can absorb radiation projected onto the substrate and convert the sensed radiation into electrical signals.

[0003] With technological advancements, CMOS image sensors (CIS) have become more popular than CCDs due to certain inherent advantages. Specifically, CMOS image sensors can offer high image acquisition rates, lower operating voltages, lower power consumption, and higher noise immunity, while also allowing for random access. Furthermore, CMOS image sensors can be manufactured on the same high-volume wafer processing lines as logic and memory devices. Summary of the Invention

[0004] Some embodiments of this application provide an image sensor, including: a pixel including a photosensitive region and a circuit region adjacent to the photosensitive region; and an isolation structure surrounding a peripheral region of the photosensitive region, wherein the isolation structure includes: a conductive grid; and a dielectric structure covering the sidewalls of the conductive grid.

[0005] Other embodiments of this application provide a semiconductor device comprising: a substrate having a first side and a second side opposite to the first side; an interconnect located on the first side; a photodiode array disposed in an active region of the substrate and electrically connected to the interconnect; an isolation structure extending from the second side of the substrate to a location in the active region of the substrate, wherein the photodiode array is surrounded by and spaced apart from the isolation structure, and the isolation structure includes a conductive grid; and a plurality of conductive structures disposed in a peripheral region of the substrate and electrically connected to the interconnect, wherein the conductive grid is electrically connected to the interconnect through the conductive structures and electrically isolated from the photodiode array.

[0006] Some embodiments of this application provide a method for manufacturing an image sensor, comprising: forming a pixel in a substrate at a first side of the substrate, the pixel including a photosensitive region and a circuit region adjacent to the photosensitive region; recessing the substrate at a second side of the substrate opposite to the first side to form a grid cavity surrounding the photosensitive region above the circuit region; disposing a first dielectric structure within the grid cavity; forming a conductive grid on the first dielectric structure in the grid cavity to form an isolation structure including the first dielectric structure and the conductive grid; recessing the substrate at the second side of the substrate to form a plurality of openings on a side adjacent to the grid cavity; disposing a second dielectric structure in the openings; and forming a plurality of conductive structures on the second dielectric structure in the openings, wherein the conductive structures are electrically connected to the conductive grid of the isolation structure, and the isolation structure is electrically isolated from the pixel. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figure 1 This is a block diagram of a semiconductor structure according to some embodiments of the present invention, the semiconductor structure having an image sensor having a pixel column connected to a circuit in a (semiconductor) image sensor die.

[0009] Figures 2 to 3 This is a schematic diagram illustrating an image sensor comprising a column of pixels connected to a circuit in a (semiconductor) image sensor die according to some embodiments of the present invention.

[0010] Figure 4 , Figure 6 , Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 19 , Figure 21 , Figure 23 and Figure 24 This is a schematic vertical (or cross-sectional) view illustrating a method of manufacturing an image sensor in a (semiconductor) image sensor die according to some embodiments of the present invention.

[0011] Figure 5 , Figure 8 , Figure 10 , Figure 12 , Figure 14 , Figure 16 , Figure 18 , Figure 20 and Figure 22 It is shown that it includes Figure 4 , Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 19 and Figure 21 A schematic horizontal (or planar) view of the relative positions of components in an image sensor as depicted in the image.

[0012] Figure 25 This is a schematic vertical (or cross-sectional) view of an image sensor in a (semiconductor) image sensor die according to some alternative embodiments of the present invention.

[0013] Figure 26 and Figure 27 These are schematic vertical (or cross-sectional) and horizontal (or planar) views of an image sensor in a (semiconductor) image sensor die according to some alternative embodiments of the present invention.

[0014] Figure 28 This is a schematic vertical (or cross-sectional) view of an image sensor in a (semiconductor) image sensor die according to some alternative embodiments of the present invention.

[0015] Figure 29 , Figure 31 , Figure 33 , Figure 35 , Figure 37 and Figure 38 This is a schematic vertical (or cross-sectional) view illustrating a method of manufacturing an image sensor in a (semiconductor) image sensor die according to some embodiments of the present invention.

[0016] Figure 30 , Figure 32 , Figure 34 and Figure 36 It is shown that it includes Figure 29 , Figure 31 , Figure 33 and Figure 35 A schematic horizontal (or planar) diagram depicting the relative positions of components in an image sensor.

[0017] Figure 39 This is a schematic vertical (or cross-sectional) view of an image sensor in a (semiconductor) image sensor die according to some alternative embodiments of the present invention.

[0018] Figure 40 and Figure 41These are schematic vertical (or cross-sectional) and horizontal (or planar) views of an image sensor in a (semiconductor) image sensor die according to some alternative embodiments of the present invention.

[0019] Figure 42 This is a schematic vertical (or cross-sectional) view of an image sensor in a (semiconductor) image sensor die according to some alternative embodiments of the present invention.

[0020] Figure 43 , Figure 45 , Figure 47 and Figure 49 This is a schematic vertical (or cross-sectional) view illustrating a method of manufacturing an image sensor in a (semiconductor) image sensor die according to some embodiments of the present invention.

[0021] Figure 44 , Figure 46 , Figure 48 and Figure 50 It is shown that it includes Figure 43 , Figure 45 , Figure 47 and Figure 49 The diagram depicts a schematic horizontal (or planar) view of the relative positions of components in an image sensor.

[0022] Figure 51 This is a schematic vertical (or cross-sectional) view of an image sensor in a (semiconductor) image sensor die according to some alternative embodiments of the present invention.

[0023] Figure 52 and Figure 53 These are schematic vertical (or cross-sectional) and horizontal (or planar) views of an image sensor in a (semiconductor) image sensor die according to some alternative embodiments of the present invention.

[0024] Figure 54 This is a schematic vertical (or cross-sectional) view of an image sensor in a (semiconductor) image sensor die according to some alternative embodiments of the present invention.

[0025] Figures 55 to 58 This is a schematic vertical (or cross-sectional) view illustrating various embodiments of an image sensor in a (semiconductor) image sensor die according to some embodiments of the present invention.

[0026] Figures 59 to 62 It is shown Figure 49 , Figure 51 , Figure 52 , Figure 54 and Figures 55 to 58Schematic enlarged and schematic vertical (or cross-sectional) views of various embodiments of the bonding between the conductive structures in the dashed regions C, D, E, and F outlined in the image sensor and the doped regions of the image sensor.

[0027] Figure 63 , Figure 65 , Figure 67 , Figure 69 , Figure 71 , Figure 73 and Figure 75 This is a schematic vertical (or cross-sectional) view illustrating a method of manufacturing an image sensor in a (semiconductor) image sensor die according to some embodiments of the present invention.

[0028] Figure 64 , Figure 66 , Figure 68A , Figure 68B , Figure 70A , Figure 70B , Figure 72A , Figure 72B and Figure 74 It is shown that it includes Figure 63 , Figure 65 , Figure 67 , Figure 69 , Figure 71 and Figure 73 A schematic horizontal (or planar) view of the relative positions of components in an image sensor as depicted in the image.

[0029] Figure 76 This is a schematic vertical (or cross-sectional) view of an image sensor in a (semiconductor) image sensor die according to some alternative embodiments of the present invention.

[0030] Figures 77 to 79 Flowcharts are provided illustrating various manufacturing methods of an image sensor in a (semiconductor) image sensor die according to some embodiments of the present invention. Detailed Implementation

[0031] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc., are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. Other components, values, operations, materials, arrangements, etc., may be considered. For example, in the following description, forming a first component on or above a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0032] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0033] Furthermore, for ease of description, this document may use terms such as “first,” “second,” and “third” to describe similar or different elements or components as shown in the figures, and these terms may be used interchangeably depending on the order of their existence or the context of the description.

[0034] A CMOS image sensor comprises an array of photosensitive image elements (pixels), each of which may include a transistor, a capacitor, and a photosensitive element. The CMOS image sensor utilizes photosensitive CMOS circuitry to convert photons into electrons. This photosensitive CMOS circuitry includes photodiodes formed in a substrate. When a photodiode is exposed to light, a charge is induced in it. When light from a subject scene is incident on a pixel, each pixel can generate electrons based on the amount of light falling on it. Furthermore, the electrons are converted into a voltage signal within the pixel and further converted into a digital signal by an A / D converter. Multiple peripheral circuits can receive and process these digital signals to display an image of the subject scene. Therefore, a CMOS image sensor device (e.g., a semiconductor chip or die equipped with a CMOS image sensor) may include an image sensor and any necessary logic components, such as amplifiers, A / D converters, etc.

[0035] CMOS image sensors may include multiple additional layers formed on top of a substrate, such as dielectric layers and interconnect metal layers, where the interconnect layers are used to couple photodiodes to peripheral circuitry. The side with the additional layers of the CMOS image sensor is generally referred to as the front side, while the side with the substrate is called the back side. Based on the different optical paths, CMOS image sensors can be further divided into two main categories: front-illuminated (FSI) image sensors and back-illuminated (BSI) image sensors.

[0036] In view of the foregoing, an image sensor and a method of manufacturing the same are provided according to various exemplary embodiments. Before specifically describing the illustrated embodiments, certain advantageous features and aspects of the embodiments of the invention will be summarized. The image sensor is equipped with an isolation structure having a conductive grid, which can be used to improve quantum efficiency (QE) and suppress crosstalk (Xtalk) to improve the performance of the image sensor. The following describes an image sensor having an integrated circuit having a semiconductor substrate and interconnects thereon, a photodiode therein, and an isolation structure having a conductive grid located on the substrate and surrounding the photodiode, wherein the conductive grid and interconnects are disposed on two opposite sides of the semiconductor substrate and electrically connected to each other. Furthermore, a color filter and a microlens are disposed above the conductive grid and overlap the photodiode. The conductive grid is capable of reflecting light to ensure that incident light entering a pixel is not affected by other pixels adjacent to it, thereby providing isolation between adjacent pixels, which suppresses potential crosstalk between them. Furthermore, due to the high reflectivity of the conductive grid, when light is incident on a pixel, the amount of light falling on the pixel can be enhanced by reflecting the light (which strikes the conductive grid) back to the pixel, which increases the quantum efficiency of the pixel. Such a conductive grid improves the performance of the image sensor. Intermediate stages in forming an image sensor with a conductive grid are shown according to some embodiments. Variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, the same reference numerals are used to denote the same elements.

[0037] Figure 1 This is a block diagram of a semiconductor structure (such as a (semiconductor) image sensor device, die, or chip) according to some embodiments of the present invention, the semiconductor structure having an image sensor having a pixel column connected to a circuit in the (semiconductor) image sensor die.

[0038] refer to Figure 1In some embodiments, exemplary functionality of an image sensor die including an image sensor 10 and an integrated circuit 20 is shown. In some embodiments, the image sensor 10 includes a grid or array of pixels 11. The pixels 11 can be arranged in a matrix form, such as an N×N or N×M array (N, M>0, N may be equal to or may not be equal to M). The array size for the pixels 11 can be specified and selected based on needs and is not limited to this invention. For example, the pixels 11 are arranged as follows: Figure 1 The 5×5 array is depicted in the diagram. In this invention, pixel 11 may be referred to as a sensor element. Each column of pixels 11 in the image sensor 10 may share an interconnect or metal line 13 electrically connected to the integrated circuit 20 to transmit pixel output to the integrated circuit 20. For example, the image sensor 10 generates a voltage signal in each pixel 11, which is further converted into a digital signal for processing by the integrated circuit 20.

[0039] In some embodiments, integrated circuit 20 includes a readout circuit component 21, a signal processing circuit component 22, and an output circuit component 23. The signal output from the 11-pixel array is read by the readout circuit component 21. The readout signal from the readout circuit component 21 is processed by the signal processing circuit component 22. The processed signal from the signal processing circuit component 22 generates an output for image sensor applications, which is performed by the output circuit component 23. Depending on requirements and layout design, integrated circuit 20 may include additional or fewer circuit components, and the invention is not limited thereto.

[0040] In some embodiments, other circuitry, such as access circuitry 12, is also formed on the image sensor 10 to enable pixels during operation. For example, access circuitry 12 includes a rolling shutter circuit or a global shutter circuit. In alternative embodiments, access circuitry 12 may be integrated into each of the pixels 11.

[0041] Figures 2 to 3 This is a schematic diagram illustrating an image sensor comprising a column of pixels connected to a circuit in a (semiconductor) image sensor die according to some embodiments of the present invention. Figure 2 and Figure 3 For simplicity, only one of the pixels 11 included in the image sensor 10 is shown for representation. (Reference) Figure 2 In some embodiments, pixel 11 includes a photosensitive device PD, a first transmission gate transistor TG1, a memory device SD, and a driving circuit DC, and is electrically connected to a shutter gate transistor SHG included in access circuit 12.

[0042] In some embodiments, the photosensitive device PD is formed by a PN structure through a first doped region 102a and a second doped region 104a. In some embodiments, the first doped region 102a is doped with an n-type dopant, while the second doped region 104a is doped with a p-type dopant. However, this does not constitute a limitation of the invention. Depending on the conductivity type of the semiconductor substrate used to construct the image sensor 10, the dopants in the first doped region 102a and the second doped region 104a can be interchanged. When irradiated by incident light, the photosensitive device PD is capable of accumulating image charge in response to the incident light. For example, the photosensitive device PD includes a photodiode. It should be noted that the photodiode is only used as an exemplary illustration of the photosensitive device PD, and the invention is not limited thereto. Other suitable photosensitive devices can be used, as long as such devices are capable of accumulating image charge when irradiated by incident light. For example, the photosensitive device PD may include a memory device with charge storage.

[0043] In some embodiments, the shutter gate transistor SHG is coupled to the photosensitive device PD. For example, the source or drain of the shutter gate transistor SHG is coupled to a voltage V. aa The image charge accumulated in the photosensitive device PD is selectively depleted. In some embodiments, a first transfer gate transistor TG1 is located between the photosensitive device PD and the storage device SD. In some embodiments, the first transfer gate transistor TG1 is capable of controlling the transfer of image charge accumulated in the photosensitive device PD to the storage device SD. For example, during operation of the image sensor 10, the first transfer gate transistor TG1 is capable of receiving a transfer signal and implementing the transfer of image charge accumulated in the photosensitive device PD to the storage device SD based on the transfer signal.

[0044] In some embodiments, a storage device SD is coupled to a first transmission gate transistor TG1 and a photosensitive device PD to receive image charge accumulated in the photosensitive device PD and store the received image charge in a depletion region. Figure 2 As shown, the memory device SD can be adjacent to the photosensitive device PD. In some embodiments, the memory device SD includes a first doped region 102b, a second doped region 104b, and a memory gate electrode SG. In some embodiments, image charge is stored in a semiconductor substrate (e.g., below the first doped region 102b, the second doped region 104b, and the second doped region 104b) Figures 4 to 24In the semiconductor substrate 100a / 100 shown, the first doped region 102b of the memory device SD and the first doped region 102a of the photosensitive device PD can be formed simultaneously using the same steps. Similarly, the second doped region 104b of the memory device SD and the second doped region 104a of the photosensitive device PD can also be formed simultaneously using the same steps. However, the invention is not limited thereto. In some alternative embodiments, the first doped regions 102a, 102b and the second doped regions 104a, 104b can be formed separately using different steps. This will be discussed later. Figures 4 to 24 The structure of the photosensitive device (PD) will be discussed in more detail.

[0045] In some embodiments, the driving circuit DC is configured to be adjacent to the memory device SD. The driving circuit DC includes a second transfer gate transistor TG2, a floating diffusion FD, a reset transistor RST, a source follower transistor SF, and a row select transistor RS. In some embodiments, the second transfer gate transistor TG2 is coupled to the output of the memory device SD. Similar to the first transfer gate transistor TG1, the second transfer gate transistor TG2 also provides the function of selectively transferring image charge accumulated in the memory device SD to the floating diffusion FD. In some embodiments, the second transfer gate transistor TG2 and the memory gate electrode SG can work together to transfer image charge stored in the memory device SD to the floating diffusion FD. For example, a bias voltage can be applied to the gate of the memory gate electrode SG and the gate of the second transfer gate transistor TG2 to generate an electric field, thereby creating a channel for charge movement. In some embodiments, due to the generated electric field, charge stored in the semiconductor substrate below the first doped region 102b, the second doped region 104b, and the second doped region 104b is pulled out from the first doped region 102b and the second doped region 104b to enter the channel of the second transfer gate transistor TG2 adjacent to the memory device SD. Subsequently, these charges can pass through the channel of the second transfer gate transistor TG2 to reach the floating diffusion FD. In some embodiments, the drain of the second transfer gate transistor TG2 can be used as the drain of the memory device SD.

[0046] In some embodiments, the floating diffused FD is referred to as a readout node. The floating diffused FD is, for example, a lightly doped n-type region at least partially formed within a p-well. In some embodiments, the floating diffused FD can be used as a capacitor for storing image charge.

[0047] like Figure 2 As shown, in some embodiments, the reset transistor RST is coupled to the floating diffuser FD and the voltage V. pixThe image charge in the floating diffuse FD is selectively reset. For example, the reset transistor RST can discharge or charge the floating diffuse FD to a preset voltage in response to a reset signal. In some embodiments, the source follower transistor SF is coupled to the floating diffuse FD and the voltage V. aa For example, the source follower transistor SF can provide a high-impedance output. The source follower transistor SF can be an amplifying transistor that amplifies the signal of the floating diffuse FD for readout operations. In some embodiments, the row select transistor RS is coupled to the source follower transistor SF. In some embodiments, the other end of the row select transistor RS is coupled to a readout column line (e.g., an interconnect or intermetallic line 13) to selectively output image data Pixout.

[0048] In some embodiments, because the drive circuit DC performs the readout function, the drive circuit DC is referred to as the readout circuit, in addition to the readout circuit component 21 included in the integrated circuit 20. Furthermore, Figure 2 The schematic diagram (or figure) of the image sensor 10 shown is merely an example, and the invention is not limited thereto. In some alternative embodiments, the image sensor 10 may have different circuit designs. For example, the first transmission gate transistor TG1 may be omitted. In some alternative embodiments, the layout of the components in the drive circuit DC may be changed according to circuit requirements. For example, the drive circuit DC in Figure 2 It is depicted as a four-transistor (4T) circuit. However, in some alternative embodiments, the drive circuit DC can be a 3T circuit, a 5T circuit, or any other suitable circuit.

[0049] However, the present invention is not limited thereto. In a further alternative embodiment, the first transfer gate transistor TG1 is incorporated into the photosensitive device PD, and the second transfer gate transistor TG2 is incorporated into the memory device SD, such that the drive circuit DC is a three-transistor (3T) circuit including a reset transistor RST, a source follower transistor SF, and a row select transistor RS.

[0050] The operation of the image sensor 10 will be briefly described below. To prevent the signal to be received from mixing with previously received signals, a reset process is first performed. During the reset process, the reference voltage V... cc Applying voltage V to reset transistor RST to turn on reset transistor RST and turn on reset transistor RST. pix Change to reference voltage V cc In some embodiments, the reference voltage V cc It can be 3.3V. Afterwards, the potential of the floating diffuser FD is determined by the reset transistor RST and the voltage V. pix Pulled to reference voltage V cc Simultaneously, the storage gate electrode SG and the second transfer gate transistor TG2 are turned on, thereby enabling the high reference voltage V...cc It can deplete the charge previously stored in the storage device SD, thereby resetting the storage device SD. In some embodiments, the photosensitive device PD is depleted along with the storage device SD. For example, voltage V aa It can be set as a reference voltage V cc Furthermore, the shutter gate transistor SHG can be turned on to deplete the charge previously accumulated in the photosensitive device PD. It should be noted that during this phase, the first transfer gate transistor TG1 is turned off. After ensuring that the memory device SD is reset and the photosensitive device PD is depleted, the shutter gate transistor SHG, the first transfer gate transistor TG1, and the second transfer gate transistor TG2 are turned off. Upon incident light illumination, image charge is captured in the photosensitive device PD. To access the image charge accumulated in the photosensitive device PD, the first transfer gate transistor TG1 and the storage gate electrode SG are turned on, thereby transferring the image charge accumulated in the photosensitive device PD to the memory device SD. To access the image charge stored in the memory device SD, the storage gate electrode SG and the second transfer gate transistor TG2 are turned on to transfer the image charge from the depletion region of the memory device SD to the floating diffusion FD. Subsequently, the source follower transistor SF is turned on to amplify the signal of the floating diffusion FD for readout operations, and the row selection transistor RS is turned on to selectively output image data Pixout.

[0051] In some embodiments, such as Figure 3 As shown, for illustrative purposes, emphasis is placed on Figure 1 and Figure 2 The image depicts the arrangement of certain components within a pixel 11 of the image sensor 10. For example, for ease of illustration, the locations (or areas) of the photosensitive device PD, the memory device SD, and the driving circuit DC are shown in... Figure 3 As shown in the diagram. For example, the photosensitive device PD is located in the photosensitive region 11A, the memory device SD is located in the memory device region 11B, and the driving circuit DC is located in the circuit region 11C, as shown in the diagram. Figure 3 As shown in the diagram. In some embodiments, the memory device SD and the driving circuit DC are arranged adjacent to each other along direction Y to facilitate electrical coupling between the memory device SD and the driving circuit DC, and the memory device SD and the driving circuit DC are arranged adjacent to the photosensitive device PD along direction X to facilitate electrical coupling between the memory device SD and the photosensitive device PD, wherein direction X is different from direction Y. Direction X may be perpendicular to direction Y. However, the invention is not limited thereto. Other suitable arrangements may be adopted, as long as the above electrical couplings can be achieved with acceptable image charge loss during image charge transfer. For example, the components of the photosensitive device PD, the memory device SD, and the driving circuit DC may be formed on and / or in a semiconductor substrate without clearly defined locations (or regions).

[0052] Figures 4 to 24 These are schematic vertical and horizontal views illustrating methods for manufacturing an image sensor comprising a semiconductor structure (e.g., a (semiconductor) image sensor device 1000a) according to some embodiments of the present invention, wherein Figure 4 , Figure 6 , Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 19 , Figure 21 , Figure 23 and Figure 24 It is along Figure 5 , Figure 8 , Figure 10 , Figure 12 , Figure 14 , Figure 16 , Figure 18 , Figure 20 and Figure 22 The cross-sectional views of lines AA and BB depicted herein. In the embodiments, the manufacturing method is part of a wafer-level process. It should be noted that the process steps described herein cover a portion of the manufacturing process for fabricating semiconductor structures, including image sensors equipped with an isolation structure having a conductive grid. Such semiconductor structures may be referred to as (semiconductor) image sensor dies or chips or (semiconductor) image sensor devices. The embodiments are intended to provide further explanation but are not intended to limit the scope of the invention. For example, some steps may occur in a different order and / or simultaneously with other steps or events besides those shown and / or described herein. Furthermore, not all steps shown require implementation of one or more aspects or embodiments described herein, and one or more of the steps depicted herein may be performed in one or more different steps and / or stages. In some embodiments, the (semiconductor) image sensor device 1000a is a BSI image sensor device, wherein the radiation of incident light (denoted as...) Figure 24 The “L” depicted in the image is projected onto the back side of the semiconductor substrate 100 into the photosensitive device PD.

[0053] Let's refer to each other. Figure 4 and Figure 5 In some embodiments, an initial integrated circuit structure ICS is provided, wherein the initial integrated circuit structure ICS includes a semiconductor substrate 100a, a device region (not shown), and interconnects 120. In some embodiments, the initial integrated circuit structure ICS includes an active region AR1 (e.g., for...). Figure 2 and Figure 3 The location of pixel 11 in the image) and the peripheral (or "peripheral") region PR (e.g., used for... Figure 1 (The location of the circuitry within). The initial integrated circuit structure (ICS) may include additional areas for housing other components of the image sensor device 1000a, if needed. Figure 5 As shown, for example, the peripheral region PR is located on the side of the active region AR. However, the invention is not limited thereto; the peripheral region PR may be located on one side, more than one side, or all sides of the active region AR.

[0054] exist Figure 4 In this embodiment, semiconductor substrate 100a is, for example, a silicon substrate doped with a p-type dopant such as boron, and is therefore a p-type substrate. Optionally, semiconductor substrate 100a can be another suitable semiconductor material. For example, semiconductor substrate 100a can be a silicon substrate doped with an n-type dopant such as phosphorus or arsenic, and is therefore an n-type substrate. Depending on design requirements (e.g., p-type well or n-type well), semiconductor substrate 100a may include various doped regions. In some embodiments, the doped regions are doped with p-type dopant (such as boron or BF2) and / or n-type dopant (such as phosphorus or arsenic). Furthermore, the doped regions can be formed directly on semiconductor substrate 100a in a P-well structure, an N-well structure, a double-well structure, or using a bump structure. In alternative embodiments, semiconductor substrate 100a can be made of some other suitable elemental semiconductor (such as diamond or germanium); suitable compound semiconductor (such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide); or suitable alloy semiconductor (such as silicon germanium carbide, gallium arsenide, or gallium indium phosphide). Furthermore, the semiconductor substrate 100a may include an epitaxial layer (epi layer) that can be strained for performance enhancement. Optionally, the semiconductor substrate 100a may be a semiconductor-on-insulator, such as silicon-on-insulator (SOI) or silicon-on-sapphire.

[0055] like Figure 4 As shown, for example, the semiconductor substrate 100a has a top surface S100t and a bottom surface S100b opposite to the top surface S100t along the Z direction. The Z direction can be perpendicular to the XY plane, for example, the X direction and the Y direction. In some embodiments, the thickness T100a of the semiconductor substrate 100a is approximately in the range of 500 μm to 900 μm.

[0056] In some embodiments, the semiconductor substrate 100a also includes a plurality of first isolators (not shown) in the active region AR and a plurality of second isolators 110 in the peripheral region PR, which are formed to isolate components of different devices, such as photosensitive devices PD, memory devices SD, transistors (such as RST, SF, RS, TG1 and / or TG2) and / or circuits (e.g., 12, 21, 22, 23) in the driving circuit DC. Each of the first and second isolators 110 may utilize isolation techniques, such as localized oxidation of silicon (LOCOS) or shallow trench isolation (STI), to electrically isolate the respective regions. If the first and second isolators 110 are made of STI, the STI may include silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof. In some instances, the filled trenches have a multilayer structure, such as a thermal oxide pad layer filled with silicon nitride or silicon oxide. In one embodiment, the first isolator is the same as the second isolator 110. In alternative embodiments, the first isolator is different from the second isolator 110. For example, as Figure 4 As shown, the second isolator 110 is an STI embedded inside the semiconductor substrate 100a, wherein the top surface S110t of each of the second isolators 110 is substantially coplanar with the top surface S100t of the semiconductor substrate 100a, and the bottom surface S110b of each of the second isolators 110 is covered by the bottom surface S100b of the semiconductor substrate 100a (e.g., inaccessibly exposed).

[0057] Return to Figure 4 In some embodiments, a first doped region 102a and a second doped region 104a are formed in a semiconductor substrate 100a within an active region AR to form a photodiode 106. For example, a photodiode 106 and the interface region (e.g., the first doped region 102a) between the photodiode 106 and the surrounding semiconductor substrate 100a / 100a constitute a photosensitive device PD. It should be noted that the configuration of the photodiode 106 shown in this invention is merely illustrative of the photosensitive device PD, and the invention is not limited thereto. Optionally, the photosensitive device PD may be a photodiode comprising only the first doped region 102a (configured to be close to the top surface S100t of the semiconductor substrate 100a) and the interface region between the photodiode 106 and the surrounding semiconductor substrate 100a. Figure 4 As shown, the photodiode 106 has a top surface (unmarked) and a bottom surface (unmarked) opposite it along direction Z. For example, the top surface is substantially coplanar with the top surface S110t of the semiconductor substrate 100a, and the bottom surface is covered by the bottom surface S110b of the semiconductor substrate 100a. In an alternative embodiment, the top surface of the photodiode 106 is close to the top surface S110t of the semiconductor substrate 100a, but not coplanar with it.

[0058] The first doped region 102a can be formed by doping the semiconductor substrate 100a with a first type of dopant, and the second doped region 104a can be formed by doping the semiconductor substrate 100a above the first doped region 102a with a second type of dopant. In some embodiments, the first type of dopant and the second type of dopant are different. For example, when the semiconductor substrate 100a is a p-type substrate, the first doped region 102a can be doped with an n-type dopant (such as phosphorus or arsenic), and the second doped region 104a can be doped with a p-type dopant (such as boron or BF2) to form a PN junction between the first doped region 102a and the second doped region 104a. That is, the semiconductor substrate 100a and the second doped region 104a have the same conductivity type (e.g., the second type) that is different from the conductivity type (e.g., the first type) of the first doped region 102a.

[0059] Optionally, when the semiconductor substrate 100a is an n-type substrate, the first doped region 102a may be doped with a p-type dopant, and the second doped region 104a may be doped with an n-type dopant to form a PN junction between them. In some embodiments, the dopant can be doped into the first doped region 102a and the second doped region 104a by an ion implantation process.

[0060] As described above, the first doped region 102b and the second doped region 104b of the memory device SD can be formed in a manner similar to that of the first doped region 102a and the second doped region 104a. Therefore, although not shown, it should be understood that the memory device SD is located within the semiconductor substrate 100a.

[0061] In some embodiments, the device region is arranged along the top surface S100t of the semiconductor substrate 100a and extends into the semiconductor substrate 100a. The device region includes a plurality of devices such as a photosensitive device PD (including a photodiode 106), a memory device SD (including a first doped region 102b and a second doped region 104b), and a driving circuit DC (including transistors RST, SF, RS, TG1, or TG2) corresponding to each pixel 11; a logic device (such as a transistor SHG) corresponding to the access circuit 12 for enabling the pixel 11; and active and passive devices corresponding to the readout circuit assembly 21, the signal processing circuit assembly 22, and the output circuit assembly 23 for readout of the photosensitive device PD. The photosensitive devices PD are arranged in rows and columns within the semiconductor substrate 100a and configured to accumulate charge from photons incident on the photodiode 106. Furthermore, the photodiodes 106 are optically isolated from each other by a first isolator (not shown, such as STI or LOCOS) in the semiconductor substrate 100a, thereby reducing crosstalk between adjacent pixels 11.

[0062] In some embodiments, the device region is formed in a front-end process (FEOL) process. Devices in the device region include integrated circuit devices. Devices are, for example, transistors, capacitors, resistors, diodes, photodiodes, fuse devices, or other similar devices. In embodiments, the device region includes a gate structure as well as source and drain regions. Various N-type metal-oxide-semiconductor (NMOS) and / or P-type metal-oxide-semiconductor (PMOS) devices, such as transistors or memories, can be formed and interconnected in the device region to implement one or more functions. The functions of the devices may include memory, processors, sensors, amplifiers, power distribution, input / output circuitry, etc.

[0063] continue Figure 4 In some embodiments, interconnect 120 is formed on semiconductor substrate 100a along the top surface S100t of semiconductor substrate 100a. In some embodiments, interconnect 120 is formed in a back-end process (BEOL) process. Interconnect 120 is located on top of a device region and electrically connected to devices in the device region for providing wiring functionality to the device region. In some embodiments, interconnect 120 includes at least one patterned dielectric layer and at least one conductive layer, which provide interconnections (e.g., wiring) between inputs / outputs of various doped components, circuits, and device regions formed on and / or in semiconductor substrate 100a. For example, interconnect 120 is considered a redistributed circuit structure or interconnect structure of the device region.

[0064] For example, interconnect 120 includes a multilayer interconnect (MLI) structure, wherein the MLI structure includes a dielectric layer (or a dielectric structure having multiple dielectric layers) 122, multiple conductors 124, and multiple vias / contacts 126. For illustrative purposes, it should be understood that... Figure 4 The dielectric layer 122, conductor 124, and via / contact 126 shown are merely exemplary, and the actual location, number of layers, and configuration of the dielectric layer 122, conductor 124, and via / contact 126 may vary depending on design requirements and manufacturing issues.

[0065] The dielectric layer 122 may be polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), nitrides (such as silicon nitride), oxides (such as silicon oxide), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), combinations thereof, etc., which may be patterned using photolithography and / or etching processes. In some embodiments, the dielectric layer 122 is formed using suitable fabrication techniques, such as spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc.

[0066] The conductor 124 and the via / contact 126 can be made of a conductive material formed by electroplating or deposition, such as copper, copper alloys, aluminum, aluminum alloys, or combinations thereof, which can be patterned using photolithography and etching processes. In some embodiments, the conductor 124 can be a metal line, a metal pad, a metal trace, etc. For example, the via / contact 126 can be a metal via, etc. For example, the conductor 124 and the via / contact 126 are patterned copper layers / vias. In some embodiments, the conductor 124 and the via / contact 126 are formed by a dual damascene process. That is, the conductor 124 and the via / contact 126 can be formed simultaneously. Throughout this specification, the term "copper" is intended to include substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing trace amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum, or zirconium.

[0067] In some embodiments, the wire 124 and the via / contact 126 together are referred to as a metallization layer. The interconnect 120 may be referred to as a BEOL metallization stack. Figure 4 As shown, for example, the topmost layer (e.g., 124) of the metallization layer of interconnect 120 is exposed by the top surface S122t of dielectric layer 122. In other words, the top surface S124t of the topmost layer (e.g., 124) of the metallization layer of interconnect 120 is substantially coplanar with the top surface S122t of dielectric layer 122. In some embodiments, the top surface S122t of dielectric layer 122 and the top surface S124t exposed by the top surface S122t of dielectric layer 122 are collectively referred to as the top surface S120t of interconnect 120, as shown. Figure 4 As shown in the image.

[0068] In some embodiments, after the device region is formed and before the interconnect 120 is formed, an etch stop layer (not shown) is conformally formed over the device region to cover its devices, and an interlayer dielectric (ILD) layer (not shown) is formed over the etch stop layer until a top surface with high planarity and flatness is obtained, which is beneficial for subsequently formed layers / elements (e.g., interconnect 120). For example, the bottom layer (e.g., 126) of the metallization layer of interconnect 120 penetrates the ILD layer and the etch stop layer to electrically connect to the devices in the device region. In some embodiments, the etch stop layer provides protection for the device region during the establishment of an electrical connection between the device region and interconnect 120. The etch stop layer may be referred to as a contact etch stop layer (CESL).

[0069] The etch stop layer may comprise silicon nitride, carbon-doped silicon nitride, or a combination thereof, which may be deposited using processes such as CVD (e.g., high-density plasma CVD, subatmospheric pressure CVD (SACVD)), molecular layer deposition (MLD), or other suitable methods. In some embodiments, a buffer layer (not shown) is further formed over the semiconductor substrate 100a and on the device region prior to the formation of the etch stop layer. In embodiments, the buffer layer is an oxide, such as silicon oxide; however, the invention is not limited thereto, and other components may be utilized. In some embodiments, the buffer layer is deposited using processes such as CVD (e.g., HDPCVD, SACVD), MLD, or other suitable methods.

[0070] The ILD layer may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, spin-coated glass (SOG), PSG, BPSG, FSG, carbon-doped silicon oxide (e.g., SiOC(-H)), polyimide, and / or combinations thereof. In some alternative embodiments, the ILD layer may comprise a low-k dielectric material. Examples of low-k dielectric materials include xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB, silsesquioxane (HSQ), or fluorinated silicon oxide (SiOF) and / or combinations thereof. It should be understood that the ILD layer may comprise one or more dielectric materials. In some embodiments, the ILD layer is formed to a suitable thickness by CVD (e.g., flowable chemical vapor deposition (FCVD), HDPCVD, SACVD), spin coating, sputtering, or other suitable methods.

[0071] refer to Figure 6 In some embodiments, the initial integrated circuit structure ICS is placed on the carrier 50 via a release layer 52. For example, the top surface S120t of the interconnect 120 contacts the release layer 52, which is located between the carrier 50 and the initial integrated circuit structure ICS. The material of the carrier 50 may include glass, metal, ceramic, silicon, plastic, combinations thereof, multilayers thereof, or other suitable materials that can provide structural support for the initial integrated circuit structure ICS in subsequent processing. In some embodiments, the carrier 50 is made of glass, and the release layer 52 is used to bond the initial integrated circuit structure ICS to the carrier 50. The material of the release layer 52 may be any material suitable for bonding and peeling the carrier 50 from layers above it (e.g., interconnect 120) or any wafer disposed thereon (e.g., the initial integrated circuit structure ICS). In some embodiments, the release layer 50 may include a release layer (such as a photothermal conversion (“LTHC”) layer) or an adhesive layer (such as a UV-curable adhesive or a thermosetting adhesive). Other suitable temporary adhesives may be used for the release layer 50.

[0072] Subsequently, in some embodiments, a planarization process is performed on the bottom surface S100b of the semiconductor substrate 100a to form a (thinned) semiconductor substrate 100. In some embodiments, the thickness T100 of the semiconductor substrate 100 is approximately in the range of 1.5 μm to 21 μm. For example, the thickness T100 of the thinned semiconductor substrate 100 is less than the thickness T100a of the semiconductor substrate 100a. In other words, the planarization process is applied to the bottom surface S100b of the semiconductor substrate 100a until a thinned semiconductor substrate 100 with a desired thickness is achieved. This thinned semiconductor substrate 100 reduces the gap (or distance) between the bottom surface of the photodiode 106 and the bottom surface S100b of the semiconductor substrate 100, which allows light to pass through the semiconductor substrate 100 and strike the photodiode 106 of the photosensitive device PD embedded in the semiconductor substrate 100 without being absorbed by the semiconductor substrate 100. For example, as Figure 6 As shown, the photosensitive device PD, the first isolator, and the second isolator 110 are not accessiblely exposed by the bottom surface S100b of the semiconductor substrate 100.

[0073] In some embodiments, the planarization process may include a grinding process, a chemical mechanical polishing (CMP) process, an etching process, or a combination thereof. The etching process may include anisotropic etching or isotropic etching. Optionally, a cleaning process may be performed after planarization, for example, to clean and remove residues generated during the planarization process. However, the invention is not limited thereto, and the planarization process may be implemented by any other suitable method.

[0074] refer to Figure 7 and Figure 8 In some embodiments, a patterning process PE1 is performed to form a plurality of trenches OP1 in the semiconductor substrate 100. The trenches OP1 may include partially deep trenches (PDTs). Figure 8 As shown, for example, trench OP1 is located within the active region AR, wherein trench OP1 surrounds the photodiode 106 of the photosensitive device PD of each pixel 11. In other words, trenches OP1 are spatially connected to each other and extend continuously around the photosensitive device PD. Figure 6 and Figure 7 As shown, for example, the photosensitive device PD is positioned in a plurality of regions 166 defined by the trench OP1. In some embodiments, such as Figure 8 As shown, in the vertical projection along direction Z on the semiconductor substrate 100, the trench OP1 does not overlap with the photosensitive device PD. For example, the trench OP1 can be a continuous trench and can be configured in a grid shape (e.g., in the form of a grid). That is, the trenches OP1 can be collectively referred to as a grid (mesh) cavity formed in the semiconductor substrate 100. In some embodiments, at least some of the trenches OP1 further extend to the peripheral region PR, such as... Figure 8As shown in the diagram. For example, the height T1 of trench OP1 is approximately in the range of 0.3 μm to 20 μm. In one embodiment, the height T1 of trench OP1 is less than the thickness T100 of semiconductor substrate 100, wherein the portion of semiconductor substrate 100 located below trench OP1 has sufficient thickness to allow other devices such as memory devices SD and drive circuitry DC to be formed below trench OP1. For example, the width D1 of trench OP1 is approximately in the range of 0.01 μm to 5 μm, wherein the width D1 is measured along a direction perpendicular to the extension direction of trench OP1, as shown in the diagram. Figure 7 and Figure 8 As shown in the image.

[0075] However, the present invention is not limited thereto; optionally, the height T1 of the trench OP1 can be substantially equal to the thickness T100 of the semiconductor substrate 100, wherein the trench OP1 does not overlap with the memory device SD and the driving circuit DC. In an embodiment where the height T1 of the trench OP1 is substantially equal to the thickness T100 of the semiconductor substrate 100, the photosensitive device PD and the trench OP1 comprise a full-depth trench (FDT), wherein the memory device SD and the driving circuit DC are located adjacent to the trench OP1.

[0076] The patterning process PE1 may include photolithography and etching processes. For example, a patterned mask layer (not shown) is formed on the bottom surface S100b of the semiconductor substrate 100. The patterned mask layer may include photoresist and / or one or more hard mask layers. The patterned mask layer has openings (not shown) that expose the portion of the semiconductor substrate 100 that does not have a photosensitive device PD and cover the portion of the semiconductor substrate 100 that has a photosensitive device PD. Subsequently, an etching process is performed using the patterned mask layer as an etching mask to at least remove the portion of the semiconductor substrate 100 exposed by the patterned mask layer to form the trench OP1. For illustrative purposes, Figure 8 The number of grooves OP1 shown does not limit the invention and can be specified and selected based on requirements and layout design (e.g., the position of pixel 11).

[0077] refer to Figure 9 and Figure 10In some embodiments, dielectric layers 150, 152, 154, and a conductive material 160m are formed over the semiconductor substrate 100 along the bottom surface S100b. In some embodiments, dielectric layer 150 is formed on the semiconductor substrate 100 and extends into trench OP1. Dielectric layer 150 is conformally formed over the bottom surface S100b of the semiconductor substrate 100 and further covers the sidewalls (not labeled) and bottom surface (not labeled) of trench OP1. Dielectric layer 150 may also be referred to as a dielectric pad (of trench OP1). Dielectric layer 150 may include a suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material. It should be noted that high-k dielectric materials may include dielectric materials having a dielectric constant greater than about 4 or even greater than about 10. High-k dielectric materials may include metal oxides. Examples of metal oxides used for high-k dielectric materials include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Ta, and / or combinations thereof. For example, dielectric layer 150 may include aluminum oxide (AlO), hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium aluminum oxide (HfAlO), or hafnium tantalum oxide (HfTaO). In some embodiments, the thickness T150 of dielectric layer 150 is approximately in the range of 5 Å to 1000 Å. Dielectric layer 150 can be formed using a suitable process with good gap-filling capability, such as atomic layer deposition (ALD). Here, when a layer is described as conformal or conformally formed, it means that the layer has substantially equal thicknesses extending along the region on which the layer is formed.

[0078] In one embodiment, dielectric layer 150 comprises a single-layer structure. In an alternative embodiment, dielectric layer 150 comprises a multilayer structure of two or more different materials. In a further alternative embodiment, dielectric layer 150 comprises a multilayer structure of the same material. The invention is not limited thereto.

[0079] Subsequently, in some embodiments, dielectric layer 152 is formed on dielectric layer 150 located on the bottom surface S100b of semiconductor substrate 100. For example... Figure 9As shown, for example, dielectric layer 152 does not extend into trench OP1. In other words, in some embodiments, dielectric layer 152 is a patterned dielectric layer having a plurality of holes (unmarked) corresponding to (e.g., exposed) trench OP1. Dielectric layer 152 may include a suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material as described above. Dielectric layer 152 may include a monolayer structure or a multilayer structure. In some embodiments, dielectric layer 152 may include a first dielectric layer and a second dielectric layer on the first dielectric layer. The first dielectric layer may include an oxide (such as silicon oxide), and the second dielectric layer may include a nitride (such as silicon nitride). In some embodiments, the thickness T152 of dielectric layer 152 is approximately in the range of 50 Å to 6000 Å. Dielectric layer 152 may be formed using a suitable process with poor gap-filling capability, such that dielectric layer 152 is not formed inside trench OP1. The deposition process may include CVD (such as PECVD), physical vapor deposition (PVD), thermal oxidation, UV-ozone oxidation, or combinations thereof. The top opening of trench OP1 may or may not be covered by dielectric layer 152. If the top opening of trench OP1 is covered by dielectric layer 152, an etching process is further employed to accessibly expose trench OP1 and the dielectric layer 150 formed therein. The etching process may be anisotropic etching. In one embodiment, the material of dielectric layer 150 is different from the material of dielectric layer 152, wherein an interface exists between dielectric layers 150 and 152. Alternatively, the material of dielectric layer 150 may be the same as the material of dielectric layer 152, wherein there is no apparent interface between dielectric layers 150 and 152.

[0080] Then, dielectric layer 154 is formed on dielectric layers 152 and 150 and extends further into trench OP1. Dielectric layer 154 is conformally formed over the bottom surface S100b of semiconductor substrate 100 and further covers dielectric layers 152 and 150. Dielectric layer 154 may also be referred to as a dielectric pad (of trench OP1). Dielectric layer 154 may include a suitable dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the thickness T154 of dielectric layer 154 is approximately in the range of 50 Å to 5000 Å. Dielectric layer 154 can be formed using a suitable process with good gap-filling capability, such as atomic layer deposition (ALD). Figure 9 As shown, for example, the thickness T150 of dielectric layer 150 and the thickness T154 of dielectric layer 154 are less than the thickness T152 of dielectric layer 152.

[0081] In some embodiments, after the dielectric layer 154 is formed, a conductive material 160m is formed over the semiconductor substrate 100 to cover the top surface S154 of the dielectric layer 154 upwards and fill the trench OP1 and the holes in the dielectric layer 152. In some embodiments, the material of the conductive material 160m includes a suitable conductive material, such as a metal and / or a metal alloy. For example, the conductive material 160m may be aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), copper alloy, or a combination thereof (e.g., AlCu) or a combination thereof. In some embodiments, the material of the conductive material 160m includes a suitable conductive material having a reflectivity of 80% or more, 95% or more, or 99% or more in the wavelength range of about 400 nm to about 5 μm. In other words, the material of the conductive material 160m is capable of reflecting 80% or more, 95% or more, or 99% or more of incident light in the wavelength range of about 400 nm to about 5 μm. For example, the conductive material 160m is Al, such as... Figure 9 As shown in the figure. In some embodiments, the formation of the conductive material 160m may include: deposition processes, such as CVD, PVD, etc.; plating processes or combinations thereof.

[0082] refer to Figure 11 and Figure 12 In some embodiments, a planarization process is performed on the conductive material 160m to form the conductive component 160 inside the trench OP1. In this invention, for example, the conductive component 160 is referred to as a conductive grid (or metal grid, metallized grid) 160, which is formed inside the grid cavity (composed of the trench OP1). Figure 11 As shown, for example, the top surface S160 of the conductive grid 160 is substantially coplanar and flush with the top surface S154 of the dielectric layer 154. For example, in this invention, the conductive grid 160, the dielectric layer 150 (serving as a dielectric pad) in the trench OP1, and the dielectric layer 154 (serving as a dielectric pad) in the trench OP1 are referred to as an isolation structure GS in the form of a grid. In some embodiments, the portions of the dielectric layer 150 located within the trench OP1 and the portions of the dielectric layer 154 located within the trench OP1 are collectively referred to as the dielectric structure DI1 of the isolation structure GS. An advantageous feature of having such an isolation structure GS is that the bias voltage (e.g., Figure 24 A negative bias voltage (Nb) is applied to the conductive grid 160, which generates hole accumulation along the sidewalls of the isolation structure GS and prevents electrons from being trapped near the isolation structure GS, thereby reducing leakage current and crosstalk between adjacent pixels 11 in the image sensor 10. This improves the performance of the image sensor 10. Figure 11 and Figure 12As shown, the isolation structure GS within the active region AR covers the driving circuit DC and memory device SD of pixel 11, as well as the photosensitive device PD located in region 166. Region 166 may be referred to as the opening 166 surrounding and exposing the photosensitive device PD of the isolation structure GS. In an alternative embodiment where the trench OP1 is an FDT, the isolation structure GS within the active region AR is located next to the driving circuit DC, memory device SD, and photosensitive device PD.

[0083] The planarization process may include polishing, CMP, etching, or combinations thereof. The dielectric layer 154 may also be planarized during the planarization process. After planarization, a cleaning process may optionally be performed, for example, to clean and remove residues generated during the planarization process. However, the invention is not limited thereto, and the planarization process may be implemented by any other suitable method.

[0084] refer to Figure 13 and Figure 14 In some embodiments, a patterning process PE2 is performed to form a plurality of openings OP2 in the semiconductor substrate 100. For example, the openings OP2 are located within a peripheral region PR, wherein the openings OP2 are formed at least on the sides of the conductive grid 160 and are spaced apart from each other. In other words, the openings OP2 are located away from the conductive grid 160. Optionally, the openings OP2 may be formed on one or more sides of the conductive grid 160, and the invention is not limited thereto. In some embodiments, in a vertical projection along the Z direction on the semiconductor substrate 100, the openings OP2 correspond to (e.g., overlap with) the second spacer 110. For example, the openings OP2 further extend into a portion of the second spacer 110 and may proximately expose the surface S110 of the second spacer 110. If the planar view of the openings OP2 is considered (e.g., the XY plane), the shape of the openings OP2 may include a circle. However, the invention is not limited thereto; in alternative embodiments, the shape of the openings OP2 in the planar view is, for example, a rectangle, an ellipse, an egg, a quadrilateral, an octagon, or any suitable polygon.

[0085] In some embodiments, the height of the opening OP2 is less than the thickness T100 of the semiconductor substrate 100. In some embodiments, the width D2 of the opening OP2 is approximately in the range of 0.1 μm to 15 μm, wherein the width D2 is measured along a direction perpendicular to the extension direction of the opening OP2, such as... Figure 13 As shown in the image. The patterning process PE2 can be used with... Figure 7 and Figure 8 The patterning process PE1 described herein is the same or identical, but applies to different patterning mask layers, and therefore will not be repeated here for the sake of simplicity. For illustrative purposes, Figure 14The number of openings OP2 shown is not limited to the present invention and can be specified and selected based on requirements and layout design.

[0086] refer to Figure 15 and Figure 16 In some embodiments, a dielectric layer 156 is formed on the dielectric layer 154 and the conductive gate 160, extending further into the opening OP2. The dielectric layer 156 is conformally formed over the bottom surface S100b of the semiconductor substrate 100 and covers the sidewalls (unlabeled) and bottom surface (unlabeled) of the opening OP2, the top surface S154 of the dielectric layer 154, and the top surface S160 of the conductive gate 160. The dielectric layer 156 may also be referred to as a dielectric pad (of the opening OP2). The dielectric layer 156 may comprise a suitable dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the thickness T156 of the dielectric layer 156 is approximately in the range of 50 Å to 5000 Å. The dielectric layer 156 can be formed using a suitable process with good gap-filling capabilities, such as atomic layer deposition (ALD). Figure 15 As shown, for example, the thickness T156 of dielectric layer 156 is less than the thickness T152 of dielectric layer 152.

[0087] refer to Figure 17 and Figure 18 In some embodiments, a patterning process PE3 is performed to form a plurality of openings OP3 and a plurality of openings OP4 within the peripheral region PR. The patterning process PE3 can be combined with... Figure 7 and Figure 8 The patterning process PE1 described herein is the same or identical, but applies to different patterned mask layers, and therefore will not be repeated here for the sake of simplicity.

[0088] In some embodiments, the opening OP3 is formed to penetrate the dielectric layer 156 to accessibly expose a portion of the conductive grid 160 located within the peripheral region PR. That is, for example, as... Figure 18 As shown, in a vertical projection along the Z direction on the semiconductor substrate 100, the opening OP3 overlaps with the conductive gate 160 and exposes the top surface S160 of the conductive gate 160. For example, the width D3 of the opening OP3 is approximately in the range of 0.01 μm to 5 μm. Optionally, the opening OP3 may not extend into the dielectric layer 154. In some embodiments, the width D3 of the opening OP3 is substantially equal to the width D1 of the trench OP1, such as... Figure 18 As shown in the diagram. Optionally, the width D3 of the opening OP3 can be greater than the width D1 of the trench OP1, or the width D3 of the opening OP3 can be less than the width D1 of the trench OP1; provided that the conductive grid 160 and the subsequently formed components are properly constructed (e.g., Figure 19 Electrical connection between 170 and / or 174).

[0089] On the other hand, opening OP4 is formed in opening OP2 to penetrate dielectric layer 156 (which is located above the bottom surface of opening OP2) and the remainder of the second isolator 110 to expose the metallization layer of interconnect 120 (e.g., the conductor 124 furthest from the top surface S120t). In other words, the surface S124 of conductor 124 is accessiblely exposed through opening OP4. One of openings OP2 is spatially connected to a corresponding one of openings OP4. For example, the width D4 of opening OP4 is approximately in the range of 0.08 μm to 14.8 μm, where the width D4 is measured along a direction perpendicular to the extension direction of opening OP4, such as... Figure 17 As shown in the image.

[0090] If we consider the plan view (e.g., the XY plane) of openings OP3 and OP4, the shape of opening OP3 may include a rectangular shape and the shape of opening OP4 may include a circular shape. However, the invention is not limited thereto; in alternative embodiments, the shapes of openings OP3 and OP4 in the plan view are, for example, circular, rectangular, elliptical, oval, quadrilateral, octagonal, or any suitable polygonal shape based on requirements and layout design. For illustrative purposes, Figure 17 The number of openings OP3 and OP4 shown does not limit the invention and can be specified and selected based on requirements and layout design. For example, the number of openings OP3 and OP4 can be one or more independently.

[0091] refer to Figure 19 and Figure 20 In some embodiments, conductive components including a plurality of conductive components 162, a plurality of conductive components 170, and a plurality of conductive components 174 are formed on the dielectric layer 156 within the peripheral region PR. In some embodiments, conductive components 162 are electrically connected to conductive components 170 via conductive components 174, wherein conductive components 162, 170, and 174 are integrally formed.

[0092] In some embodiments, the conductive member 162 is formed in the opening OP3 to contact the conductive grid 160, such that the conductive member 162 is electrically connected to the conductive grid 160. For example, as Figure 19 As shown, conductive member 162 fills opening OP3. For example, the top surface (not marked) of conductive member 162 is considered to be substantially coplanar with the top surface S156 of dielectric layer 156, and the bottom surface (not marked) of conductive member 162 is considered to be substantially coplanar with the top surface S160 of conductive grid 160. However, the invention is not limited thereto; alternatively, conductive member 162 may be formed in the form of a conductive pad with opening OP3.

[0093] In some embodiments, conductive member 170 is formed in openings O2 and OP4 to make layer contact with the exposed metallization layer of interconnect 120, such that conductive member 170 is electrically connected to interconnect 120. For example, as Figure 19 As shown, the conductive member 170 is formed as a conductive pad covering the inner sidewall S156i of the dielectric layer 156 located at the sidewall of the opening OP2, and further extends into the opening OP4 to cover the sidewall (unmarked) and bottom surface (unmarked) of the opening OP4. For example, the shown top surface (unmarked) of the conductive member 170 is considered to be a surface substantially coplanar with the top surface S156 of the dielectric layer 156. In some embodiments, each of the conductive members 170 includes a first portion 170a in the opening OP2 and a second portion 170b in the opening OP4. For example, as Figure 19 As shown, conductive component 170 is electrically connected to interconnect 120 via an exposed layer of the metallization layer of interconnect 120, physically and electrically connecting second portion 170b and interconnect 120, and electrically connected to conductive component 174 via a physical and electrical connection of first portion 170a and conductive component 174. Conductive component 170 may be referred to as conductive structure 170, wherein each first portion 170a may be referred to as a conductor and each second portion 170b may be referred to as a conductive via of a conductor. Figure 19 As shown, for example, each of the conductive structures 170 has a stepped shape (or profile), wherein the inner wall S170i and the outer wall S170o of the conductive structure 170 are curves (e.g., not straight lines) in the cross-sectional view.

[0094] In some embodiments, conductive member 174 is formed on the top surface S156 of dielectric layer 156 to contact conductive member 170 and conductive member 162, such that conductive member 174 is electrically connected to conductive members 162 and 170. In other words, conductive member 174 is a patterned conductive layer extending between conductive member 162 and conductive member 170 to provide a proper electrical connection between them. For example, the bottom surface (not marked) of conductive member 174 is considered to be a surface substantially coplanar with the top surface S156 of dielectric layer 156. Conductive member 174 may be referred to as conductive pattern 174.

[0095] The formation of the conductive components, including conductive components 162, 170, and 174, can be achieved by, but is not limited to, forming a conductive material layer (not shown) above the semiconductor substrate 100 along the bottom surface S100b to cover it. Figure 17 and Figure 18 The structure shown includes a conductive material layer extending into openings OP2, OP3, and OP4; and a patterning process PE4 applied to the conductive material layer to simultaneously form conductive components 162, 170, and 174. The patterning process PE4 can be combined with... Figure 7 and Figure 8 The patterning process described in [the document] is the same as or exactly the same as PE1, but uses a different patterning mask layer, and therefore will not be repeated here for the sake of simplicity. The conductive material layer can be [the same as / the same as / the patterning process described in the document]. Figure 9 and Figure 10 The conductive material layer 160m described herein is made of the same or similar material, and therefore will not be repeated here for the sake of simplicity. For example, the conductive grid 160 is made of Al, and the conductive parts 162, 170, and 174 are also made of Al. In another example, the conductive grid 160 is made of Al, and the conductive parts 162, 170, and 174 are made of W. Figure 19 As shown, for example, the conductive grid 160 is electrically connected to the interconnect 120 via the conductive component 162, the conductive structure 170, and the conductive pattern 174.

[0096] In this invention, although multiple conductive patterns 174 are used to electrically connect the conductive structures 170 and the conductive grid 160, a single conductive pattern 174 may span all conductive structures 170 and be electrically connected to all conductive structures 170 for electrically connecting the conductive structures 170 and the conductive grid 160. In other words, for example, a conductive pattern 174 may electrically connect one conductive structure 170 to the conductive grid 160 or connect two or more conductive structures 170 to the conductive grid 160. This invention does not limit the number of conductive patterns 174. In this invention, two or more conductive structures 170 may be connected to a conductor 124 on the top layer of the metallization layer of the interconnect 120, which is simultaneously exposed by corresponding two or more openings OP4. For example, every two conductive structures 170 may be connected together to a conductor 124 on the top layer of the metallization layer of the interconnect 120, wherein the conductor 124 is exposed by two openings OP4. However, the invention is not limited thereto; alternatively, each of the conductive structures 170 may be connected to a wire 124 exposed by a corresponding opening OP4 on the top layer of the metallization layer of the interconnect 120. In other words, the conductive structures 170 are connected to different wires 124 on the top layer of the metallization layer of the interconnect 120. Alternatively, two or more conductive structures 170 in a portion of the conductive structure 170 may be connected to a wire 124 on the top layer of the metallization layer of the interconnect 120, while each conductive structure 170 in the remaining portion of the conductive structure 170 may be connected to a wire 124 on the top layer of the metallization layer of the interconnect 120.

[0097] refer to Figure 21 and Figure 22 In some embodiments, in Figure 19 and Figure 20A dielectric layer 158 is formed on the structure depicted to cover the conductive pattern 174. The dielectric layer 158 may include a suitable dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the thickness T158 of the dielectric layer 158 is approximately in the range of 50 Å to 5000 Å. The dielectric layer 158 can be formed using suitable processes such as CVD, physical vapor deposition (PVD), thermal oxidation, UV-ozone oxidation, or combinations thereof. Figure 21 As shown, for example, the thickness T158 of dielectric layer 158 is greater than the thickness T156 of dielectric layer 156, the thickness T154 of dielectric layer 154, and the thickness T150 of dielectric layer 150. In some embodiments, the formation of dielectric layer 158 may further include a planarization process, such as a CMP process, such that dielectric layer 158 is formed to have a substantially flat top surface. In one embodiment, the material of dielectric layer 158 may be the same as the material of dielectric layer 156, wherein there is no obvious interface between dielectric layers 156 and 158. In an alternative embodiment, the material of dielectric layer 158 is different from the material of dielectric layer 156, wherein there is an interface between dielectric layers 156 and 158. Dielectric layer 158 may be referred to as a passivation layer with high planarity and flatness, which is beneficial for subsequently formed layers / elements (e.g., color filters, microlenses, etc.).

[0098] refer to Figure 23 In some embodiments, the filter layer 180 (including multiple color filters 182, 184, and 186) and the microlens 190 are disposed on the dielectric layer 158 and above the isolation structure GS within the active region AR. Figure 23 As shown, for example, each of color filters 182, 184, and 186 corresponds to a photosensitive device PD not covered by the isolation structure GS, wherein each of microlenses 190 corresponds to one of color filters 182, 184, and 186. However, the invention is not limited thereto; in an alternative embodiment, each of color filters 182, 184, and 186 corresponds to one or more photosensitive devices PD not covered by the isolation structure GS, wherein each of microlenses 190 corresponds to one of color filters 182, 184, and 186.

[0099] Color filters 182, 184, and 186 have an upper surface approximately flush with the top surface of dielectric layer 158. Color filters 182, 184, and 186 are assigned a corresponding color or wavelength of light and are configured to filter out all light except for the assigned color or wavelength. The color filter assignment alternates between red, green, and blue light, such that color filters 182, 184, and 186 include a red color filter 182, a green color filter 184, and a blue color filter 186. In some embodiments, the color filter assignment alternates between red, green, and blue light according to a Bayer color filter mosaic. Other combinations, such as cyan, yellow, and magenta, may also be used. The number of different colors in color filters 182, 184, and 186 may also vary. According to embodiments, filter layer 180 may include a colored or dyed material, such as acrylic. For example, polymethyl methacrylate (PMMA) or polyglycidyl methacrylate (PGMS) are suitable materials for which pigments or dyes can be added to form the filter layer 180. However, other materials may be used. The filter layer 180 may be formed by any suitable method known in the art.

[0100] For example, a microlens 190 is disposed above the filter layer 180 and configured to filter the incident light L ( Figure 24 The microlens 190 is focused onto the photosensitive device PD. The microlens 190 can be formed of any material that can be patterned and formed into a lens, such as a high-transmittance acrylic polymer. The microlens 190 can be formed by any suitable method known in the art. The microlens 190 is centered on the photosensitive device PD corresponding to pixel 11 and is symmetrical about a vertical axis centered on the photosensitive device PD, such as... Figure 23 As shown in the diagram. Furthermore, adjacent edges of the microlens 190 are adjacent to each other.

[0101] refer to Figure 24 In some embodiments, the carrier 50 is peeled off from the interconnect 120 to expose the top surface S120t. In some embodiments, the top surface S120t of the interconnect 120 is easily separated from the carrier 50 due to the release layer 52. In some embodiments, the carrier 50 is separated from the top surface S120t of the interconnect 120 by a peeling process, and the carrier 50 and the release layer 52 are removed. In some embodiments, the outermost layer (e.g., 124) of the metallization layer of the interconnect 120 may be readily exposed, such as... Figure 24 As shown in the figure. In one embodiment, the stripping process is a laser stripping process. Thus, the image sensor device 1000a is manufactured.

[0102] It should be understood that when the image sensor device 1000a is completed in the wafer-level process, a dicing (segmentation) process is performed to cut the multiple interconnected image sensor devices 1000a into individual and separated (semiconductor) image sensor devices 1000a. In one embodiment, the dicing (segmentation) process is a wafer dicing process including mechanical blade sawing or laser cutting, but the invention is not limited thereto. During the stripping step, prior to the stripping carrier 50 and the stripping layer 52, Figure 23 The structure depicted is flipped (inverted) and secured by a holding device (not shown). After the peeling and cutting (splitting) processes, the image sensor device 1000a is released from the holding device.

[0103] like Figure 24 As shown, for example, because the image sensor device 1000a includes a P-type semiconductor substrate 100, a negative bias Nb is applied to the interconnect 120. This negative bias Nb is transmitted to the conductive grid 160 via a conductive structure 170 formed in the peripheral region PR electrically connected to the interconnect 120. The high negative charge concentration in the isolation structure GS will generate hole accumulation (denoted as "HA") along the sidewalls of the isolation structure GS, and prevent electrons in the semiconductor substrate 100 from being trapped near the isolation structure GS, thereby reducing leakage current and crosstalk between adjacent pixels 11. However, the invention is not limited thereto; in an alternative embodiment (not shown) where the image sensor device 1000a includes an n-type semiconductor substrate 100, a positive bias is applied to the conductive grid 160 via a conductive structure 170 formed in the peripheral region PR electrically connected to the interconnect 120. The high positive charge concentration in the isolation structure GS will generate electron accumulation along the sidewalls of the isolation structure GS, and prevent electrons in the semiconductor substrate 100 from being trapped near the isolation structure GS, thereby reducing leakage current and crosstalk between adjacent pixels 11. By utilizing such an isolation structure GS, better isolation is provided for the photosensitive device PD, thereby improving the performance of the image sensor 10.

[0104] In an alternative embodiment, a portion of the dielectric layer 156 extending along the XY plane is removed. Figure 25 This is a schematic vertical view illustrating an image sensor included in a semiconductor structure (e.g., (semiconductor) image sensor device 1000b) according to some alternative embodiments of the invention. Elements similar to or substantially the same as those previously described will be used with the same reference numerals, and certain details or descriptions of the same elements will not be repeated herein. Figure 25 The image sensor device 1000b is similar to Figure 24 The image sensor device 1000a differs in that... Figure 25 In the image sensor device 1000b, dielectric layer 156 is replaced by dielectric layer 156A and conductive component 162 is omitted. For example, as Figure 25 As shown, dielectric layer 156A is only disposed on the sidewall of opening OP2.

[0105] In some embodiments, in a vertical projection along the Z direction on the semiconductor substrate 100, the dielectric layer 156A is located only within the opening OP2 and does not overlap with the conductive structure 170. The dielectric layer 156A is referred to as the dielectric pad of the opening OP2. The formation and material of the dielectric layer 156A are similar to... Figures 15 to 18 The process and materials used to form dielectric layer 156, as described herein, are used except for the use of etch masks with different patterns, and therefore will not be repeated here. Alternatively, dielectric layer 156A can also be formed by a blanket etching process, wherein no photomask is used as an etch mask during etching, and will be combined later. Figures 29 to 38 A more detailed discussion follows. Using this configuration, the overall thickness of the image sensor device (e.g., 1000b) is further reduced without compromising the isolation capability of the isolation structure GS. For example, the overall thickness of image sensor device 1000b (in the Z direction) is less than the overall thickness of image sensor device 1000a (in the Z direction).

[0106] Alternatively, each conductive structure may have a non-stepped shape (or profile), such as conductive structure 170A. Figure 26 and Figure 27 These are schematic vertical and horizontal views illustrating an image sensor included in a semiconductor structure (e.g., a (semiconductor) image sensor device 1000c) according to some alternative embodiments of the present invention. Figure 28 This is a schematic vertical view illustrating an image sensor included in a semiconductor structure (e.g., a (semiconductor) image sensor device 1000d) according to some alternative embodiments of the invention. Elements similar to or substantially the same as those previously described will be used with the same reference numerals, and certain details or descriptions of the same elements will not be repeated herein. Figure 26 and Figure 27 The image sensor device 1000c is similar to Figure 24 The image sensor device 1000a differs in that... Figure 26 and Figure 27 In the image sensor device 1000c, the conductive structure 170 is replaced by the conductive structure 170A. For example, as... Figure 26 As shown in the cross-sectional view, the inner wall S170Ai and the outer wall S170Ao of the conductive structure 170A are straight lines (e.g., not curves). In other words, there are no bends at the inner wall S170Ai and the outer wall S170Ao of the conductive structure 170A.

[0107] In some embodiments, such as Figure 26 and Figure 27As shown, instead of forming an opening OP4, a plurality of openings OP5 are formed to penetrate the second spacer 110, wherein the sidewalls of the openings OP5 are aligned with the inner sidewalls S156i of the dielectric layer 156. For example, the width D5 of the openings OP5 is approximately in the range of 0.08 μm to 14.8 μm, wherein the width D5 is measured along a direction perpendicular to the extension direction of the openings OP5, as shown. Figure 26 As shown in the diagram. In some embodiments, the size of opening OP5 (e.g., D5) is larger than the size of opening OP4 (e.g., D4). The formation and material of opening OP5 are similar to those shown in the diagram. Figures 17 to 18 The process and materials used to form the opening OP4, as described herein, are used except for the use of etch masks with different patterns, and therefore will not be repeated here. In some embodiments, the width of the dielectric layer 156 inside the conductive structure 170 is constant, as measured along a direction perpendicular to the Z direction (e.g., directions X and / or Y). Due to the conductive structure 170A, the contact area between the conductive structure 170A and the interconnect 120 is increased, which reduces the contact resistance between them; thereby enhancing the isolation capability of the isolation structure GS and further improving the performance of the image sensor 10.

[0108] Alternatively, similar to image sensor device 1000b, the dielectric layer 156 of image sensor device 1000c can be replaced by dielectric layer 156A, which omits the presence of conductive component 162, see [link to relevant documentation]. Figure 28 The image sensor device 1000d shown is an example.

[0109] Figures 29 to 38 These are schematic vertical and horizontal views illustrating methods for manufacturing an image sensor comprising a semiconductor structure (e.g., a (semiconductor) image sensor device 2000a) according to some embodiments of the present invention, wherein Figure 29 , Figure 31 , Figure 33 , Figure 35 and Figure 37 It is along Figure 30 , Figure 32 , Figure 34 , Figure 36 and Figure 38 The cross-sectional views are taken by lines AA and BB as depicted in the figure. Components similar to or substantially the same as those previously described will use the same reference numerals, and certain details or descriptions of the same components will not be repeated here.

[0110] refer to Figure 29 and Figure 30 In some embodiments, a dielectric layer 156B is formed on the dielectric layer 154 and the conductive grid 160, extending further into the opening OP2, following... Figure 13 and Figure 14 The process described herein. For example, such as... Figure 29As shown, dielectric layer 156B covers the sidewalls and bottom surface of opening OP2, the top surface S154 of dielectric layer 154, and the top surface S160 of conductive grid 160. In some embodiments, dielectric layer 156B has a first portion (unlabeled) extending outside opening OP2 along the XY plane, a plurality of second portions (unlabeled) extending inside opening OP2 along the Z direction, and a plurality of third portions (unlabeled) extending inside opening OP2 along the XY plane, wherein each of the third portions is connected to the first portion through the second portions. In some embodiments, each of the first and third portions of dielectric layer 156B has a thickness T156h, measured along the Z direction, in the range of approximately 50 Å to 5000 Å. In some embodiments, each of the second portions of dielectric layer 156B has a thickness T156v, measured along a direction perpendicular to the Z direction (e.g., X and / or Y), in the range of approximately 50 Å to 5000 Å. For example, thickness T156h is less than thickness T156v. Optionally, the thickness T156h can be approximately equal to the thickness T156v. For example... Figure 29 As shown, for example, the thickness T156h is constant, while the thickness T156v gradually increases from the top opening toward the bottom surface of the opening OP2. That is, the thickness T156v is non-constant. The formation and material of dielectric layer 156B are related to... Figure 15 and Figure 18 The dielectric layer 156 described herein is similar to or the same in terms of process and materials, and therefore will not be repeated here for the sake of brevity.

[0111] refer to Figure 31 and Figure 32 In some embodiments, for Figure 29 and Figure 30The structure depicted implements a patterning process BE1 to form a plurality of openings OP4. For example, openings OP4 are formed in openings OP2 to penetrate the dielectric layer 156B and the remainder of the second isolator 110 to expose a layer of the metallization layer of the interconnect 120 (e.g., the conductor 124 furthest from the top surface S120t). In other words, the surface S124 of the conductor 124 is accessiblely exposed by openings OP4. One of the openings OP2 is spatially connected to a corresponding one of the openings OP4. The patterning process BE1 is, for example, a blanket etching process that does not use a photomask during etching. In some embodiments, the blanket etching process BE1 is an anisotropic etching performed integrally on the bottom surface S100b of the semiconductor substrate 100 (e.g., the active region AR and the peripheral region PR) to simultaneously pattern a first portion, a second portion, and a third portion of the dielectric layer 156B, wherein the first and third portions of the dielectric layer 156B are completely removed, while some of each of the second portions remain as residues disposed at the sidewalls of the openings OP2. Dielectric layer 156B (e.g., the remaining second portion) can also be referred to as the dielectric pad (of opening OP2), which has a non-constant thickness T156v. For example, as Figure 31 and Figure 32 As shown, the top surface S156B of the second portion of dielectric layer 156B, the top surface S154 of dielectric layer 154, and the top surface S160 of conductive grid 160 are accessiblely exposed.

[0112] refer to Figure 33 and Figure 34 In some embodiments, conductive components including a plurality of conductive components 172 and a plurality of conductive components 174 are formed on dielectric layers 154 and 156B within the peripheral region PR. In some embodiments, conductive components 170 are electrically connected to conductive components 174 via direct contact. For example, conductive components 170 and 174 are integrally formed.

[0113] In some embodiments, conductive member 172 is formed in openings O2 and OP4 to make layer contact with the exposed metallization layer of interconnect 120, such that conductive member 172 is electrically connected to interconnect 120. For example, as Figure 33 As shown, the conductive member 172 is formed in the form of a conductive pillar that contacts the inner sidewall S156Bi of the dielectric layer 156B located at the sidewall of the opening OP2, and further extends into the opening OP4 to contact the sidewall (unmarked) and bottom surface (unmarked) of the opening OP4. For example, the shown top surface (unmarked) of the conductive member 172 is considered to be a surface substantially coplanar with the top surface S154 of the dielectric layer 154 and the top surface S156B of the dielectric layer 156B. In some embodiments, each of the conductive members 172 includes a first portion 172a in the opening OP2 and a second portion 172b in the opening OP4. For example, as Figure 33As shown, conductive component 172 is electrically connected to interconnect 120 via a physical and electrical connection between the second portion 172b and the exposed layer of the metallization layer of interconnect 120, and conductive component 172 is electrically connected to conductive component 174 via a physical and electrical connection between the first portion 172a and conductive component 174. Conductive component 172 may be referred to as conductive structure 172, wherein each first portion 172a may be referred to as a conductor, and each second portion 172b may be referred to as a conductive via of a conductor. Figure 33 As shown, for example, each of the conductive structures 172 has a stepped shape (or profile), wherein each of the sidewalls S172 of the conductive structure 172 is a curve (e.g., not a straight line) in the cross-sectional view.

[0114] In some embodiments, conductive member 174 is formed on the top surface S154 of dielectric layer 154 and the top surface S156B of dielectric layer 156B to contact conductive member 172 and conductive grid 160 of isolation structure GS, such that conductive member 174 is electrically connected to conductive member 172 and conductive grid 160 of isolation structure GS. In other words, conductive member 174 is a planar conductive layer extending between conductive grid 160 of isolation structure GS and conductive member 172 to provide a proper electrical connection between them. For example, the bottom surface (not marked) of conductive member 174 is considered to be a surface substantially coplanar with the top surface S154 of dielectric layer 154. Conductive member 174 may be referred to as conductive pattern 174.

[0115] The formation of the conductive components, including conductive components 172 and 174, can be achieved by, but is not limited to, forming a conductive material layer (not shown) above the semiconductor substrate 100 along the bottom surface S100b to cover it. Figure 31 The structure depicted herein includes a conductive material layer filling openings OP2 and OP4; and a patterning process PE5 applied to the conductive material layer to simultaneously form conductive components 172 and 174. The patterning process PE5 can be combined with... Figure 7 and Figure 8 The patterning process described in [the document] is the same as or exactly the same as PE1, but uses a different patterning mask layer, and therefore will not be repeated here for the sake of simplicity. The conductive material layer can be [the same as / the same as / the patterning process described in the document]. Figure 9 and Figure 10 The conductive material layer 160m described herein is made of the same or similar material, and therefore will not be repeated here for the sake of brevity. For example, the conductive grid 160 is made of Al, and the conductive parts 170 and 174 are also made of Al. In another example, the conductive grid 160 is made of Al, and the conductive parts 170 and 174 are made of W. Figure 33As shown, for example, the conductive grid 160 is electrically connected to the interconnect 120 via a conductive structure 172 and a conductive pattern 174. The presence of the conductive structure 172 ensures an electrical connection between the isolation structure GS and the interconnect 120.

[0116] In some embodiments, the formation of the conductive material layer may further include a planarization process, such as a CMP process, to form the conductive material layer with a substantially flat top surface. Furthermore, although multiple conductive patterns 174 are used to electrically connect the conductive structures 172 and the conductive grid 160, a single conductive pattern 174 may exist that spans over and is electrically connected to all conductive structures 172 for electrically connecting the conductive structures 172 and the conductive grid 160. For example, a conductive pattern 174 may electrically connect one conductive structure 172 to the conductive grid 160 or connect two or more conductive structures 172 to the conductive grid 160. The invention does not limit the number of conductive patterns 174.

[0117] refer to Figure 35 and Figure 36 In some embodiments, in Figure 33 and Figure 34 A dielectric layer 158 is formed on the structure depicted to cover the conductive pattern 174. The dielectric layer 158 can be described as a passivation layer with high planarity and flatness, which is beneficial for subsequently formed layers / devices (e.g., color filters, microlenses, etc.). Details of the dielectric layer 158 are already shown in [the original text]. Figure 21 and Figure 22 As described in [the text], and therefore will not be repeated here for simplicity. References Figure 37 In some embodiments, a filter layer 180 (including multiple color filters 182, 184, and 186) and a microlens 190 are disposed on the dielectric layer 158 and above the isolation structure GS within the active region AR. Details of the filter layer 180 and the microlens 190 have been described in detail below. Figure 23 As described in [the text], and therefore will not be repeated here for simplicity. References Figure 38 In some embodiments, it is possible to Figure 37 The structural implementation described in Figure 24 The manufacturing process described previously is used to obtain Figure 38 The image sensor device 2000a depicted herein utilizes an isolation structure GS to provide better isolation for the photosensitive device PD, thereby improving the performance of the image sensor 10. Furthermore, the overall thickness of the image sensor device 2000a (in the Z direction) is further reduced.

[0118] Figure 39This is a schematic vertical view illustrating an image sensor included in a semiconductor structure (e.g., a (semiconductor) image sensor device 2000b) according to some alternative embodiments of the invention. Elements similar to or substantially the same as those previously described will be used with the same reference numerals, and certain details or descriptions of the same elements will not be repeated herein. Figure 39 The image sensor device 2000b is similar to Figure 38 The image sensor device 2000a differs in that... Figure 38 In the image sensor device 2000b, the first portion of dielectric layer 156B is retained on the top surface S154 of dielectric layer 154. In other words, instead of as shown above... Figure 33 and Figure 34 The previously described manufacturing process uses patterning process BE1 (without a photomask), and another patterning process (with a photomask) to form the opening OP4. The other patterning process can be combined with... Figure 7 and Figure 8 The patterning process described in the text is the same or identical to PE1, but uses a different patterning mask layer, and therefore will not be repeated here for the sake of simplicity.

[0119] Figure 40 and Figure 41 These are schematic vertical and horizontal views illustrating an image sensor included in a semiconductor structure (e.g., a (semiconductor) image sensor device 2000c) according to some alternative embodiments of the invention. Figure 42 This is a schematic vertical view illustrating an image sensor included in a semiconductor structure (e.g., a (semiconductor) image sensor device 2000d) according to some alternative embodiments of the invention. Elements similar to or substantially the same as those previously described will be used with the same reference numerals, and certain details or descriptions of the same elements will not be repeated herein. Figure 40 and Figure 41 The image sensor device 2000c is similar to Figure 38 The image sensor device 2000a differs in that... Figure 40 and Figure 41 In the image sensor device 2000c, conductive structure 172 is replaced by conductive structure 172A. For example, as... Figure 40 As shown in the cross-sectional view, the sidewall S172A of the conductive structure 172A is a straight line (e.g., not a curve). In other words, there is no curvature at the sidewall S172A of the conductive structure 172A. That is, each of the conductive structures 172A has a non-stepped shape (or profile). The formation and material of the conductive structure 172A are similar to... Figure 26 and Figure 27 The process for forming the opening OP5 described in the document and Figure 33 and Figure 34The process and materials used to form the conductive structure 172 are described herein and will therefore not be repeated here for the sake of brevity. Due to the conductive structure 172A, the contact area between the conductive structure 170A and the interconnect 120 is increased, which reduces the contact resistance between them; thereby enhancing the isolation capability of the isolation structure GS and further improving the performance of the image sensor 10.

[0120] Alternatively, similar to image sensor device 2000b, the first portion of dielectric layer 156B of image sensor device 2000c may not be removed, see [link to image sensor device 2000c]. Figure 42 The image sensor device 2000d shown is illustrated.

[0121] In an alternative embodiment, instead of having a first isolator in the active region AR and / or a second isolator in the peripheral region PR, the first and second isolators can be independently formed as doped isolation components with a stacked structure of multiple doped regions. The dopants in the multiple doped regions can vary depending on the conductivity type of the semiconductor substrate used to construct the image sensor. In some embodiments, the multiple doped regions and the dopants in the semiconductor substrate in which the multiple doped regions are formed are of the same type.

[0122] Figures 43 to 50 These are schematic vertical and horizontal views illustrating methods for manufacturing an image sensor comprising a semiconductor structure (e.g., a (semiconductor) image sensor device 3000a) according to some embodiments of the present invention, wherein Figure 43 , Figure 45 , Figure 47 and Figure 49 It is along Figure 44 , Figure 46 , Figure 48 and Figure 50 The cross-sectional views are taken by lines AA and BB as depicted in the figure. Components similar to or substantially the same as those previously described will use the same reference numerals, and certain details or descriptions of the same components will not be repeated here.

[0123] refer to Figure 43 and Figure 44 In some embodiments, an initial integrated circuit structure ICS' is provided and placed on the carrier 50 via a stripping layer 52, and then through previously... Figure 6 The process described herein thins the initial integrated circuit structure ICS'. In some embodiments, such as Figure 43 As shown, the initial integrated circuit structure ICS' includes a semiconductor substrate 100A, a device region (not shown), and interconnects 120. Details of the carrier 50, release layer 52, device region, and interconnects 120 are already shown. Figure 4 and Figure 5As described herein, and therefore will not be repeated here for the sake of brevity. In this invention, Figure 43 The semiconductor substrate 100A is similar to Figure 6 The semiconductor substrate 100 differs in that, in Figure 43 In the semiconductor substrate 100A, the second isolation member 110 is replaced by a plurality of second isolation members 110A. In some embodiments, each of the second isolation members 110A includes a doped isolation member with a stacked structure having doped regions. The second isolation member 110A may be referred to as a doped isolation component 110A. For example, as Figure 43 As shown, each doped isolation component 110A includes a doped region 112, a doped region 114, and a doped region 116 stacked along the Z direction. In some embodiments, along the Z direction, the doped region 112 is located between the interconnect 120 and the doped region 114, and the doped region 114 is located between the doped region 112 and the doped region 116. In some embodiments, the thickness T110A of the doped isolation component 110A is approximately in the range of 0.01 μm to 10 μm, wherein the thickness T110A is measured along the stacking direction of the doped regions 112-116, as shown below. Figure 43 As shown in the image.

[0124] For example, the surface of the doped region 112 is substantially coplanar with the top surface S100t of the semiconductor substrate 100A, and the doped region 116 is not accessiblely exposed by the bottom surface of the semiconductor substrate 100A. In some embodiments, the doped isolation member 110A is electrically connected to the interconnect 120 through a layer of the metallization layer of the interconnect 120 (e.g., one or more vias 126 furthest from the top surface S120t). The configuration of the semiconductor substrate 100A is similar to... Figure 4 and Figure 5 The configuration of the semiconductor substrate 100 described herein will not be repeated here for the sake of brevity.

[0125] In some embodiments, the semiconductor substrate 100A and the doped regions 112, 14, and 116 have the same conductivity type. For example, the semiconductor substrate 100A is a p-type substrate, and the doped regions 112, 14, and 116 are doped with p-type dopants (such as boron or BF2). The doped regions 112, 114, and 116 can be formed by implanting a p-type dopant (such as boron) through the top surface S100t of the semiconductor substrate 100A before forming the interconnect 120, but not limited to this method. In some embodiments, the p-type doping concentration of the doped region 114 is greater than that of the doped region 112, and the p-type doping concentration of the doped region 116 is greater than that of the doped region 114. Furthermore, the p-type doping concentration of the doped region 116 is greater than that of the semiconductor substrate 100A. The doped region 112 may have approximately 10... 15 / cm 3To about 10 21 / cm 3 The doping concentration is within the range. Doped region 114 can have approximately 10... 15 / cm 3 To about 10 19 / cm 3 The doping concentration is within the range. Doped region 116 can have approximately 10... 13 / cm 3 To about 10 18 / cm 3 The doping concentration within the range. In some embodiments, for each doped isolation component 110A, the doped region 112 may be referred to as a p+ doped region or p+ well, the doped region 114 may be referred to as a heavily doped region or single-cell p-well (CPW), and the doped region 116 may be referred to as a heavily doped region or deep p-well (DPW).

[0126] On the other hand, if the semiconductor substrate 100A is an n-type substrate, then doped regions 112, 114, and 116 are doped with n-type dopants (such as phosphorus or arsenic). The formation of doped regions 112, 114, and 116 can be achieved by implanting n-type dopants through the top surface S100t of the semiconductor substrate 100A before forming the interconnect 120, but is not limited to this method. In some embodiments, the n-type doping concentration of doped region 114 is greater than that of doped region 112, and the n-type doping concentration of doped region 116 is greater than that of doped region 114. Furthermore, the n-type doping concentration of doped region 116 is greater than that of the semiconductor substrate 100A. Doped region 112 may have approximately 10n 15 / cm 3 To about 10 21 / cm 3 The doping concentration is within the range. Doped region 114 can have approximately 10... 15 / cm 3 To about 10 19 / cm 3 The doping concentration is within the range. Doped region 116 can have approximately 10... 13 / cm 3 To about 10 18 / cm 3 The doping concentration within the range. In some embodiments, for each doped isolation component 110A, the doped region 112 may be referred to as an n+ doped region or an n+ well, the doped region 114 may be referred to as a heavily doped region or a single-cell n-well (CNW), and the doped region 116 may be referred to as a heavily doped region or a deep n-well (DNW).

[0127] The first isolation element (not shown) may have the same structure as the doped isolation element 110A. Alternatively, the first isolation element may not have the same structure as the doped isolation element 110A. The invention is not limited thereto.

[0128] refer to Figure 45 and Figure 46 In some embodiments, a plurality of trenches OP1 are formed in the semiconductor substrate 100A, and an isolation structure GS having a conductive grid 160 is formed in the trenches OP1, wherein the trenches OP1 together constitute a grid cavity. Details of the trenches OP1 are already described in […]. Figure 7 and Figure 8 The manufacturing process described previously, as described in the previous description, details of the isolation structure GS are already described in, as in, Figure 9 and Figure 12 The manufacturing process described in the previous description is as follows, and therefore will not be repeated here for simplicity.

[0129] refer to Figure 47 and Figure 48 In some embodiments, a patterning process PE2 is performed to form a plurality of openings OP2 in the semiconductor substrate 100A to expose the doped isolation component 110A. For example, the surface S116 of the doped isolation component 110A is accessiblely exposed by the openings OP2 formed in the peripheral region PR. Details of the patterning process PE2 and the openings OP2 are described in [reference needed]. Figure 13 and Figure 14 The manufacturing process described previously is as follows, and therefore will not be repeated here for simplicity. In some embodiments, after forming the opening OP2 of the surface S116 of the exposed doped isolation member 110A, the surface can be... Figure 47 and Figure 48 The structure described above is implemented as follows. Figures 19 to 24 The previously described manufacturing process, as described in the document, is used to obtain... Figure 49 and Figure 50 The image sensor device 3000a is depicted in the figure. In the image sensor device 3000a, a plurality of conductive components (or conductive patterns) 174 electrically connect a plurality of conductive components (or conductive structures) 170A to a conductive grid 160 of an isolation structure GS, wherein the isolation structure GS is electrically connected to an interconnect structure 120 (e.g., via 126) through doped isolation components 110A, conductive structures 170A, and conductive patterns 174. Utilizing such an isolation structure GS provides better isolation for the photosensitive device PD, and thus improves the performance of the image sensor 10.

[0130] In an optional embodiment, the portion of dielectric layer 156 extending along the XY plane above dielectric layer 154 in image sensor device 3000a is removed, see... Figure 51The (semiconductor) image sensor device 3000b. The removal of such a portion of dielectric layer 156 can be achieved by... Figure 25 The process or previously described in Figures 33 to 36 The process is similar to or the same as the process previously described. With this configuration, the overall thickness of the image sensor device (e.g., 3000b) is further reduced without compromising the isolation capability of the isolation structure GS.

[0131] For example, such as Figure 49 Image sensor device 3000a and Figure 51 As shown in the image sensor device 3000b, each conductive structure 170A has a non-stepped shape (or profile). However, the invention is not limited thereto; alternatively, Figure 49 Image sensor device 3000a and Figure 51 The conductive structure 170A in the image sensor device 3000b can be replaced by each conductive structure 170 having a stepped shape (or contour), such as Figure 59 As shown in the image.

[0132] In a further optional embodiment, conductive structure 170A in image sensor device 3000a is replaced by conductive structure 172A, see [link to documentation]. Figure 52 and Figure 53 The (semiconductor) image sensor device 3000c. Due to the presence of the conductive structure 172A, an electrical connection between the isolation structure GS and the interconnect 120 is ensured. The formation of the conductive structure 172A can be achieved through... Figures 40 to 41 The process is similar to or the same as the previously described process. In a further embodiment, similar to image sensor device 3000b, the portion of dielectric layer 156 extending along the XY plane above dielectric layer 154 in image sensor device 3000c is removed, see [link to previous description]. Figure 54 The (semiconductor) image sensor device 3000d. With this configuration, the overall thickness of the image sensor device (e.g., 3000d) is further reduced without compromising the isolation capability of the isolation structure GS.

[0133] For example, such as Figure 52 Image sensor device 3000c and Figure 54 As shown in the image sensor device 3000d, each conductive structure 172A has a non-stepped shape (or profile). However, the invention is not limited thereto; alternatively, Figure 52 Image sensor device 3000c and Figure 54 The conductive structure 172A in the image sensor device 3000d can be replaced by each conductive structure 172 having a stepped shape (or contour), such as Figure 60 As shown in the image.

[0134] Figures 55 to 58 This is a schematic vertical (or cross-sectional) view illustrating various embodiments of an image sensor included in a semiconductor structure (e.g., a (semiconductor) image sensor device) according to some embodiments of the present invention. Elements similar to or substantially the same as those previously described will be used with the same reference numerals, and certain details or descriptions of the same elements will not be repeated herein.

[0135] For example, Figure 55 4000a (semiconductor) image sensor device and Figure 49 The image sensor device is similar to the 3000a; and the difference lies in that... Figure 55 In the image sensor device 4000a depicted herein, a plurality of second isolation elements (referred to as doped isolation elements) 110B are used instead of second isolation elements (referred to as doped isolation elements) 110A. Apart from the doped isolation elements 110B, the details and other components of the image sensor device 4000a are similar to those of the image sensor device 4000a. Figures 43 to 50 The details of the image sensor device 3000a and other components described herein will not be repeated here for the sake of simplicity.

[0136] In some embodiments, each of the doped isolation components 110B includes a doped region 112 and a doped region 114 stacked along the Z direction. In some embodiments, along the Z direction, the doped region 112 is located between the interconnect 120 and the doped region 114, wherein the doped region 114 is not accessiblely exposed by the bottom surface S100b of the semiconductor substrate 100B, and the surface of the doped region 112 is substantially coplanar with the top surface S100t of the semiconductor substrate 100B. In some embodiments, the thickness T110B of the doped isolation component 110B is approximately in the range of 0.01 μm to 9.5 μm, wherein the thickness T110B is measured along the stacking direction of the doped regions 112-114, such as... Figure 55 As shown in the diagram. For example, opening OP2 penetrates the semiconductor substrate 100B to expose (or proximately expose) the doped isolation component 110B (e.g., surface S114). In some embodiments, the doped isolation component 110B is electrically connected to the interconnect 120 through a layer of the metallization layer of the interconnect 120 (e.g., one or more vias 126 furthest from the top surface S120t). Figure 55 As shown, conductive pattern 174 electrically connects conductive structure 170A to conductive grid 160 of isolation structure GS, wherein isolation structure GS is electrically connected to interconnect structure 120 (e.g., via 126) through doped isolation component 110B, conductive structure 170A, and conductive pattern 174. Utilizing such isolation structure GS provides better isolation for photosensitive device PD, and thus improves the performance of image sensor 10.

[0137] In an optional embodiment, the portion of dielectric layer 156 extending along the XY plane above dielectric layer 154 in image sensor device 4000a is removed, see... Figure 56 The (semiconductor) image sensor device 4000b. The removal of such a portion of dielectric layer 156 can be achieved by... Figure 25 The process or previously described in Figures 33 to 36 The process is similar to or the same as the previously described process. Using this configuration, the overall thickness of the image sensor device (e.g., 4000b) is further reduced without compromising the isolation capability of the isolation structure GS. For example, as... Figure 55 Image sensor device 4000a neutral Figure 56 As shown in the image sensor device 4000b, each conductive structure 170A has a non-stepped shape (or profile). However, the invention is not limited thereto; alternatively, Figure 55 Image sensor device 4000a neutral Figure 56 The conductive structure 170A in the image sensor device 4000b can be replaced by each conductive structure 170 having a stepped shape (or contour), such as Figure 61 As shown in the image.

[0138] In a further optional embodiment, conductive structure 170A in image sensor device 4000A is replaced by conductive structure 172A, see [link to documentation]. Figure 57 The (semiconductor) image sensor device 4000c. Due to the presence of conductive structure 172A, an electrical connection between the isolation structure GS and the interconnect 120 is ensured. The formation of conductive structure 172A can be achieved by connecting it to previously... Figures 40 to 41 The process described herein is similar to or the same as the process described. In a further embodiment, similar to image sensor device 4000b, the portion of dielectric layer 156 extending along the XY plane above dielectric layer 154 in image sensor device 4000c is removed, see [link to documentation]. Figure 58 The (semiconductor) image sensor device 4000d. Using this configuration, the overall thickness of the image sensor device (e.g., 4000d) is further reduced without compromising the isolation capability of the isolation structure GS. For example, as... Figure 57 Image sensor device 4000c and Figure 58 As shown in the image sensor device 4000d, each conductive structure 172A has a non-stepped shape (or profile). However, the invention is not limited thereto; alternatively, Figure 57 Image sensor device 4000c and Figure 58 The conductive structure 172A in the image sensor device 4000d can be replaced by each conductive structure 172 having a stepped shape (or contour), such as Figure 62As shown in the image.

[0139] Figures 63 to 75 These are schematic vertical and horizontal views illustrating methods for manufacturing an image sensor comprising a semiconductor structure (e.g., a (semiconductor) image sensor device 2000a) according to some embodiments of the present invention, wherein Figure 63 , Figure 65 , Figure 67 , Figure 69 , Figure 71 and Figure 73 It is along Figure 64 , Figure 66 , Figure 68A , Figure 70A , Figure 72A and Figure 74 The cross-sectional view is taken from lines AA and BB. Figure 76 This is a schematic vertical view illustrating an image sensor in a (semiconductor) image sensor die according to some alternative embodiments of the present invention. Components similar to or substantially the same as those previously described will be referred to using the same reference numerals, and certain details or descriptions of the same components will not be repeated herein.

[0140] refer to Figure 63 and Figure 64 In some embodiments, an initial integrated circuit structure (ICS) is provided and placed on the carrier 50 via a peel layer 52, and then through previously... Figure 6 The process described in the document thins the initial integrated circuit structure (ICS). Figure 63 The initial integrated circuit structure "ICS" is similar to Figure 43 The initial integrated circuit structure ICS' described in [the original text] differs in that [the original text] is in [the original text]. Figure 63 In the initial integrated circuit structure "ICS", multiple second isolation elements (called doped isolation structures) 110C are used to replace the second isolation element (called doped isolation component) 110A. Apart from the doped isolation structures 110C, the details and other components of the initial integrated circuit structure "ICS" are similar to those of other components. Figures 43 to 44 The details of the initial integrated circuit structure ICS' and other components described herein are not repeated here for the sake of simplicity.

[0141] In some embodiments, each of the doped isolation structures 110C includes a doped region (referred to as a p+ doped region or p+ well) 112a, a doped region (referred to as a heavily doped region or cell p-well (CPW)) 114a, and a doped region (referred to as a heavily doped region or deep p-well (DPW)) 116a stacked along the Z direction. In some embodiments, along the Z direction, the doped region 112a is located between the interconnect 120 and the doped region 114a, and the doped region 114a is located between the doped region 112a and the doped region 116a. For example, as Figure 63As shown, doped region 116a is not accessiblely exposed by the bottom surface S100b of semiconductor substrate 100C, and the surface of doped region 112a is substantially coplanar with the top surface S100t of semiconductor substrate 100C, so as to be electrically connected to interconnect 120 through a layer of metallization layer of interconnect 120 (e.g., one or more vias 126 furthest from the top surface S120t). In some embodiments, the thickness T110C of doped isolation structure 110C is approximately in the range of 0.01 μm to 10 μm, wherein the thickness T110C is measured along the stacking direction of doped regions 112a-116a, as shown. Figure 63 As shown in the figure. The formation and material of doped regions 112a-116a are similar to those previously shown. Figures 43 to 44 The process and materials used to form the doped regions 112-116 described herein are the same or similar, and therefore will not be repeated here for simplicity.

[0142] refer to Figure 65 and Figure 66 In some embodiments, a patterning process PE6 is performed to form multiple trenches OP6 and multiple openings OP7. The patterning process PE6 can be combined with... Figure 7 and Figure 8 The patterning process PE1 described herein is the same or identical, but uses a different patterning mask layer, and therefore will not be repeated here for the sake of simplicity. Figure 65 and Figure 66 As shown, trench OP6 is formed in the active region AR and extends further into the peripheral region PR to spatially communicate with the opening OP7 formed only in the peripheral region PR. For example, trench OP6 can be a continuous trench and can be configured as a grid shape (e.g., a mesh) within the active region AR. That is, trench OP6 can collectively be referred to as a grid (mesh) cavity formed in the semiconductor substrate 100C within the active region AR. Figure 65 and Figure 66 As shown, for example, the photosensitive device PD is positioned in a plurality of regions 166 defined by trench OP6. In some embodiments, the top surface S116a of the doped isolation structure 110C is exposed by an opening OP7 (e.g., accessiblely exposed).

[0143] For example, the height T6 of trench OP6 is approximately in the range of 0.1 μm to 20 μm. In one embodiment, the height T6 of trench OP6 is less than the thickness T100 of semiconductor substrate 100C. In an alternative embodiment, the height T6 of trench OP6 is substantially equal to the thickness T100 of semiconductor substrate 100C. For example, the width D6 of trench OP6 is approximately in the range of 0.01 μm to 5 μm, where the width D6 is measured along a direction perpendicular to the extension direction of trench OP6, such as... Figure 65 and Figure 66As shown in the figure. For example, the height T7 of the opening OP7 is approximately in the range of 0.1 μm to 20.9 μm. In one embodiment, the height T7 of the opening OP7 is less than the thickness T100 of the semiconductor substrate 100C. In an alternative embodiment, the height T7 of the opening OP7 is substantially equal to the thickness T100 of the semiconductor substrate 100C. For example, the width D7 of the opening OP7 is approximately in the range of 0.013 μm to 25 μm, where the width D7 is measured along a direction perpendicular to the extension direction of the opening OP7, as shown in the figure. Figure 65 As shown in the figure. In some embodiments, the width D6 of the groove OP6 is smaller than the width D7 of the opening OP7. For example, the ratio of the width D6 of the groove OP6 to the width D7 of the opening OP7 is approximately in the range of 1:1.3 to 1:5.

[0144] refer to Figure 67 , Figure 68A and Figure 68B In some embodiments, dielectric layers 150, 154, 156m, and 158 are sequentially formed above the semiconductor substrate 100C along the bottom surface S100B. For example, dielectric layer 150 is conformally formed on the bottom surface S100b of the semiconductor substrate 100C and extends further into the sidewalls (unmarked) and bottom surface (unmarked) of trench OP6 and opening OP7; dielectric layer 152 is conformally formed on the top surface S150 of dielectric layer 150 and extends further into trench OP6 and opening OP7 to cover dielectric layer 150; and dielectric layer 154 is conformally formed on the top surface S152 of dielectric layer 152 and extends further into trench OP6 and opening OP7 to cover dielectric layer 152. Dielectric layers 150, 152, and 154 may also be individually referred to as dielectric pads (of trench OP6 and opening OP7). In some embodiments, dielectric layers 150, 152, and 154 are each formed using a suitable process with good gap-filling capability or a slow deposition rate, such as atomic layer deposition (ALD). The materials for dielectric layers 150, 152, and 154 have already been prepared. Figure 9 and Figure 10 As described herein, and therefore will not be repeated here for simplicity. In an alternative embodiment, dielectric layer 152 may be omitted.

[0145] After dielectric layer 154 is formed, dielectric layer 156m is formed on the top surface S154 of dielectric layer 154 without extending into trench OP6 and opening OP7. In some embodiments, dielectric layer 156m is formed by a deposition process with poor gap-filling capability or fast deposition rate, such as PECVD. Therefore, dielectric layer 156m can be formed as a non-conformal layer. In some embodiments, the thickness of dielectric layer 156m above the bottom surface S100b of semiconductor substrate 100C is much thicker than the thickness of dielectric layer 156m above trench OP6 and opening OP7. In some embodiments, dielectric layer 156m substantially does not fill trench OP6 and opening OP7. In some embodiments, due to the ratio between the width D6 of trench OP6 and the width D7 of opening OP7, the top of trench OP6 is covered by dielectric layer 156m, while the top of opening OP7 is not completely covered by dielectric layer 156m, such as... Figure 67 As shown. For example, as Figure 67 , Figure 68A and Figure 68B As shown, multiple openings OP8 formed in the dielectric layer 156m expose openings OP7 respectively. That is, in the vertical projection along the Z direction on the semiconductor substrate 100C, the positioning positions of openings OP8 and OP7 overlap, as shown below. Figure 68A and Figure 68B As shown in the figure. The material of the 156m dielectric layer is... Figure 15 and Figure 16 The material of dielectric layer 156 described herein is the same as or similar to that described herein, and therefore will not be repeated here for the sake of brevity.

[0146] refer to Figure 69 , Figure 70A and Figure 70B In some embodiments, a patterning process BE2 is performed on dielectric layer 156m to form dielectric layer 156 having multiple trenches OP9 and openings OP8, and further forming multiple openings OP10 that penetrate the dielectric layers 150, 152, and 154, are located on the bottom surface of opening OP7, and overlap with opening OP8. The patterning process BE2 can be combined with... Figure 31 and Figure 32 The patterning process described in BE1 is the same or identical, and therefore will not be repeated here for the sake of brevity.

[0147] In some embodiments, trench OP9 is formed above and within trench OP6, wherein trench OP9 is formed in the active region AR and further extends to the peripheral region PR to spatially communicate with the opening OP8 formed only in the peripheral region PR. For example, trench OP9 may be a continuous trench and may be configured as a grid shape (e.g., in the form of a grid) within the active region AR. That is, in the semiconductor substrate 100C within the active region AR, trench OP9 may also be collectively referred to as a grid (mesh) cavity formed inside trench OP6.

[0148] In some embodiments, in the peripheral region PR, opening OP10 is formed below and spatially communicates with openings OP8 and OP7. For example, as Figure 69 , Figure 70A and Figure 70B As shown, the top surface S116a of the doped isolation structure 110C is exposed by the opening OP10 (e.g., accessiblely exposed). In some embodiments, the size D10 of the opening OP10 is substantially equal to the size of the opening OP8 (not labeled).

[0149] When considering the plan view (e.g., the XY plane) of openings OP7, OP8, and / or OP10, the shapes of openings OP7, OP8, and / or OP10 may independently include circles. However, the invention is not limited thereto; in alternative embodiments, the shapes of openings OP7, OP8, and / or OP10 in the plan view are, for example, rectangles, ellipses, ovals, quadrilaterals, octagons, or any suitable polygons.

[0150] refer to Figure 71 , Figure 72A and Figure 72B In some embodiments, conductive components including a plurality of conductive components 168, conductive components 178, and a plurality of conductive components 176 are formed on the dielectric layer 156. In some embodiments, conductive components 168 are electrically connected to conductive components 176 via conductive components 178, wherein conductive components 168, 176, and 178 are integrally formed.

[0151] In some embodiments, conductive members 168 are formed in trenches OP6 and OP9. For example, conductive members 168 fill trenches OP6 and OP9. For example, as... Figure 71As shown, the top surface (not labeled) of the conductive component 168 is considered to be substantially coplanar with the top surface S156 of the dielectric layer 156. The conductive components 168 may be collectively referred to as the conductive grid 168. For example, in this invention, the conductive grid 168 in trenches OP6 and OP9, and the dielectric layers 150, 152, and 154 (serving as dielectric pads) in trench OP6, are collectively referred to as the isolation structure GS' in the form of a grid. In some embodiments, portions of dielectric layer 150, dielectric layer 152, and dielectric layer 154 located within trench OP6 are collectively referred to as the dielectric structure DI2 of the isolation structure GS'. An advantageous feature of having such an isolation structure GS' is that the bias (e.g., Figure 75 A negative bias voltage (Nb) is applied to the conductive grid 168, which generates hole accumulation along the sidewalls of the isolation structure GS' and prevents electrons from being trapped near the isolation structure GS', thereby reducing leakage current and crosstalk between adjacent pixels 11 in the image sensor 10. Therefore, the performance of the image sensor 10 is improved. Figure 71 , Figure 72A and Figure 72B As shown, the isolation structure GS' within the active region AR covers the driving circuit DC and memory device SD of pixel 11, as well as the photosensitive device PD located in region 166. Region 166 may be referred to as the opening 166 surrounding and exposing the photosensitive device PD of the isolation structure GS'. In an alternative embodiment where the trench OP1 is an FDT, the isolation structure GS' within the active region AR is located next to the driving circuit DC, memory device SD, and photosensitive device PD.

[0152] In some embodiments, conductive members 176 are formed in openings OP10, OP7, and OP8 to contact the surface S116a of the doped isolation structure 110C, such that conductive members 176 are electrically connected to the interconnect 120 through the doped isolation structure 110C. For example, conductive members 176 fill openings OP10, OP7, and OP8. For example, as... Figure 71 As shown, the top surface (not labeled) of the conductive member 176 is considered to be substantially coplanar with the top surface S156 of the dielectric layer 156. In some embodiments, each of the conductive members 176 includes a first portion 176a in openings OP8 and OP7 and a second portion 176b in opening OP10. For example, as Figure 71As shown, conductive component 176 is electrically connected to interconnect 120 by physically and electrically connecting the second portion 176b to the doped isolation structure 110C electrically connected to interconnect 120, and conductive component 176 is electrically connected to conductive component 178 by physically and electrically connecting the first portion 176a and conductive component 178. Conductive component 176 may be referred to as conductive structure 176, wherein each first portion 176a may be referred to as a conductor and each second portion 176b may be referred to as a conductive via of a conductor. Figure 71 As shown, for example, each of the conductive structures 176 has a stepped shape (or profile), wherein each of the sidewalls S176 of the conductive structure 176 in the cross-sectional view is curved (e.g., not straight, but with a bend). Alternatively, the conductive structure 176 may have a non-stepped shape (or profile), wherein each of the sidewalls S176 of the conductive structure 176 in the cross-sectional view is straight (e.g., without a bend).

[0153] In some embodiments, a conductive member 178 is formed on the top surface S156 of the dielectric layer 156 to contact the conductive grid 168 and the conductive structure 176, such that the conductive member 178 is electrically connected to the conductive grid 168 and the conductive structure 176. In other words, the conductive member 178 is a continuous conductive layer on the dielectric layer 156 extending between the conductive grid 168 and the conductive structure 176 to provide a proper electrical connection between them. For example, the bottom surface (not marked) of the conductive member 178 is considered to be a surface substantially coplanar with the top surface S156 of the dielectric layer 156. The conductive member 178 may be referred to as a conductive pattern 178.

[0154] The conductive components, including conductive components 168, 176, and 178, can be formed by, but not limited to, forming a conductive material layer (not shown) above the semiconductor substrate 100C along the bottom surface S100b to cover... Figure 69 and Figure 70A The structure depicted herein is used to form conductive components 168, 176, and 178, wherein a conductive material layer extends into trenches OP6 and OP9 and openings OP7, OP8, and OP10 to simultaneously form conductive components 168, 176, and 178. The conductive material layer can be combined with... Figure 9 and Figure 10 The conductive material layer 160µm described herein is made of the same or similar material, and therefore will not be repeated here for the sake of simplicity. For example, the conductive material layer is made of Al. Figure 71As shown, for example, conductive grid 168 is electrically connected to interconnect 120 via conductive structure 176 and conductive pattern 178. In some embodiments, the formation of the conductive components including conductive parts 168, 176, and 178 may further include a planarization process, such as a CMP process, such that conductive part 178 is formed to have a substantially flat top surface. After planarization, a cleaning process may optionally be performed, for example, to clean and remove residues generated by the planarization process. However, the invention is not limited thereto, and the planarization process may be implemented by any other suitable method.

[0155] In this invention, although the conductive components including conductive components 168, 176, and 178 are formed as non-conformal layers, such as Figure 71 As shown, however, the conductive components including conductive elements 168, 176, and 178 can be formed as a conformal layer, provided that the electrical connection between the doped isolation structure 110C and the conductive components including conductive elements 168, 176, and 178 is properly established. The invention is not limited thereto.

[0156] refer to Figure 73 and Figure 74 In some embodiments, in Figure 71 and Figure 72A A dielectric layer 158 is formed on the structure depicted to cover the conductive pattern 178. The dielectric layer 158 can be described as a passivation layer with high planarity and flatness, which is beneficial for subsequent layer / device formation (e.g., color filters, microlenses, etc.). Details of the dielectric layer 158 are already shown in [the original text]. Figure 21 and Figure 22 As described in [the text], and therefore will not be repeated here for simplicity. References Figure 75 In some embodiments, a filter layer 180 (including multiple color filters 182, 184, and 186) and a microlens 190 are disposed on the dielectric layer 158 and above the isolation structure GS' within the active region AR. Details of the filter layer 180 and the microlens 190 have been described in detail. Figure 23 As described above, and therefore will not be repeated here for simplicity. In some embodiments, implementation may be as described above. Figure 24 The manufacturing process described previously in the text obtains Figure 75 The (semiconductor) image sensor device 5000a is depicted in the figure. By utilizing the isolation structure GS', better isolation is provided for the photosensitive device PD, thus improving the performance of the image sensor 10. Furthermore, the overall thickness of the image sensor device 5000a (in the Z direction) is further reduced.

[0157] In some alternative embodiments, conductive pattern 178 may be omitted, see Figure 76The (semiconductor) image sensor device 5000b. Since trenches OP6, OP9 and openings OP7, OP8 are spatially connected to each other, conductive grid 168 and conductive structure 176 are connected by electrical and physical connections. Using this configuration, the overall thickness of the image sensor device (e.g., 5000b) is further reduced without compromising the isolation capability of the isolation structure GS'.

[0158] In the cross-sectional views of the above embodiments, although trenches OP1 and / or openings OP2, OP3, OP4, OP5, OP8, and OP10 are shown as having vertical and flat sidewalls, trenches OP1 and / or openings OP2, OP3, OP4, OP5, OP8, and OP10 may independently have inclined and flat sidewalls. On the other hand, in the cross-sectional views of the above embodiments, although trenches OP6, OP9, and / or openings OP7 are shown as having inclined and flat sidewalls, trenches OP6, OP9, and / or openings OP7 may independently have vertical and flat sidewalls. The invention is not limited thereto.

[0159] Figure 77 A flowchart of a method 6000 according to the present invention for forming an image sensor included in a semiconductor image sensor device is presented. Method 6000 begins at step 6002, providing a substrate having interconnects disposed on a first side of a substrate, a dielectric isolation member located in the substrate along the first side, and a pixel having a photosensitive device in the substrate along the first side. Figure 6 The cross-sectional view provides an example.

[0160] Step 6004 involves forming a plurality of trenches in the substrate along the second side of the substrate. Figure 7 The cross-sectional view provides an example.

[0161] Step 6006 is to form the first dielectric structure in the trench. Figure 9 The cross-sectional view provides an example.

[0162] Step 6008 involves forming a conductive grid in the trench to form an isolation structure having a first dielectric structure and a conductive grid. Figure 11 The cross-sectional view provides an example.

[0163] Step 6010 involves forming a plurality of openings in the substrate along the second side immediately adjacent to the trench and above the dielectric isolator. Figure 13 The cross-sectional view provides an example.

[0164] Step 6012 is to form a second dielectric structure in the opening. Figure 15 Cross-sectional view and Figure 29 The cross-sectional views provide various examples.

[0165] Step 6014 is to form a through-hole penetrating the second dielectric structure in the opening and dielectric isolation element. Figure 17 Cross-sectional view and Figure 31 The cross-sectional views provide various examples.

[0166] Step 6016 is to form a conductive structure in the opening and through hole to contact the interconnect. Figure 19 Cross-sectional view and Figure 33 The cross-sectional views provide various examples.

[0167] Step 6018 is to form a color filter on the substrate above the pixel. Figure 23 Cross-sectional view and Figure 38 The cross-sectional views provide various examples.

[0168] Step 6020 involves setting microlenses on the color filter. Figure 23 Cross-sectional view and Figure 38 The cross-sectional views provide various examples.

[0169] Figure 78 A flowchart of a method 7000 according to the present invention for forming an image sensor included in a semiconductor image sensor device is presented. Method 7000 begins at step 7002, providing a substrate having interconnects disposed on a first side of a substrate, doped isolation members located in the substrate along the first side, and pixels having photosensitive devices in the substrate along the first side. Figure 43 The cross-sectional view provides an example.

[0170] Step 7004 involves forming a plurality of trenches in the substrate along the second side of the substrate. Figure 45 The cross-sectional view provides an example.

[0171] Step 7006 is to form the first dielectric structure in the trench. Figure 45 The cross-sectional view provides an example.

[0172] Step 7008 is to form a conductive grid in the trench to form an isolation structure having a first dielectric structure and a conductive grid. Figure 45 The cross-sectional view provides an example.

[0173] Step 7010 involves forming a plurality of openings in the substrate along the second side immediately adjacent to the trench and above the doped isolation element. Figure 47 The cross-sectional view provides an example.

[0174] Step 7012 is to form a second dielectric structure in the opening. Figure 49 The cross-sectional view provides an example.

[0175] Step 7014 is to form a via in the opening that penetrates the second dielectric structure and exposes the doped spacer, wherein the doped spacer is in contact with the interconnect. Figure 49 The cross-sectional view provides an example.

[0176] Step 7016 involves forming conductive structures in the openings and vias to contact the doped isolation element. Figure 49 The cross-sectional view provides an example.

[0177] Step 7018 is to form a color filter on the substrate above the pixel. Figure 49 The cross-sectional view provides an example.

[0178] Step 7020 involves setting microlenses on the color filter. Figure 49 The cross-sectional view provides an example.

[0179] Figure 79 A flowchart of a method 8000 according to the present invention for forming an image sensor included in a semiconductor image sensor device is presented. Method 8000 begins at step 8002, providing a substrate having interconnects disposed on a first side of a substrate, doped isolation members located in the substrate along the first side, and pixels having photosensitive devices in the substrate along the first side. Figure 63 The cross-sectional view provides an example.

[0180] Step 8004 involves forming a plurality of trenches and a plurality of openings along the second side of the substrate, with the openings exposing the doped isolation elements. Figure 65 The cross-sectional view provides an example.

[0181] Step 8006 involves forming a first dielectric structure in the trench and a second dielectric structure in the opening. Figure 67 The cross-sectional view provides an example.

[0182] Step 8008 involves forming a plurality of vias in the opening that penetrate the second dielectric structure and expose the doped isolation elements, wherein the doped isolation elements are in contact with the interconnect elements. Figure 69 The cross-sectional view provides an example.

[0183] Step 8010 involves forming a conductive grid in the trench to form an isolation structure having a first dielectric structure and a conductive grid, and forming conductive structures in the openings and vias to contact the doped isolation element. Figure 71 The cross-sectional view provides an example.

[0184] Step 8012 is to form a color filter on the substrate above the pixel. Figure 75 The cross-sectional view provides an example.

[0185] Step 8014 involves setting microlenses on the color filter. Figure 75 The cross-sectional view provides an example.

[0186] Although Figures 77 to 79Methods 6000, 7000, and 8000 are shown and described herein as a series of steps or events; however, it should be understood that the order in which such steps or events are shown should not be construed as limiting. For example, some steps may occur in a different order and / or simultaneously with other steps or events in addition to those shown and / or described herein. Furthermore, it may not be necessary to implement all the steps shown to achieve one or more aspects or embodiments described herein, and one or more steps described herein may be performed in one or more separate steps and / or stages.

[0187] According to some embodiments, an image sensor includes pixels and an isolation structure. The pixel includes a photosensitive region and a circuit region adjacent to the photosensitive region. The isolation structure is located above the pixel, wherein the isolation structure includes a conductive grid and a dielectric structure covering the sidewalls of the conductive grid. The isolation structure surrounds a peripheral region of the photosensitive region.

[0188] According to some embodiments, a semiconductor device includes a substrate, interconnects, a photodiode array, an isolation structure, and a plurality of conductive structures. The substrate has a first side and a second side opposite to the first side. Interconnects are located on the first side. The photodiode array is disposed within an active region of the substrate and electrically connected to the interconnects. The isolation structure extends from the second side of the substrate to a location within the active region of the substrate, wherein the photodiode array is surrounded by and spaced apart from the isolation structure, and the isolation structure includes a conductive grid. A plurality of conductive structures are disposed within a peripheral region of the substrate and electrically connected to the interconnects, wherein the conductive grids are electrically connected to the interconnects through the conductive structures and electrically isolated from the photodiode array.

[0189] According to some embodiments, a method for manufacturing an image sensor includes the following steps: forming a pixel in a substrate at a first side of a substrate, the pixel including a photosensitive region and a circuit region adjacent to the photosensitive region; recessing the substrate at a second side of the substrate opposite to the first side to form a grid cavity surrounding the photosensitive region above the circuit region; disposing a first dielectric structure within the grid cavity; forming a conductive grid on the first dielectric structure in the grid cavity to form an isolation structure including the first dielectric structure and the conductive grid; recessing the substrate at a second side of the substrate to form a plurality of openings on a side adjacent to the grid cavity; disposing a second dielectric structure in the openings; and forming a plurality of conductive structures on the second dielectric structure in the openings, wherein the conductive structures are electrically connected to the conductive grid of the isolation structure, and the isolation structure is electrically isolated from the pixel.

[0190] Some embodiments of this application provide an image sensor, including: a pixel including a photosensitive region and a circuit region adjacent to the photosensitive region; and an isolation structure surrounding a peripheral region of the photosensitive region, wherein the isolation structure includes: a conductive grid; and a dielectric structure covering the sidewalls of the conductive grid.

[0191] In some embodiments, the isolation structure overlaps with the circuit region and is electrically isolated from the pixel. In some embodiments, the dielectric structure further covers the bottom surface of the conductive grid. In some embodiments, the conductive grid is made of a metal or a metal alloy. In some embodiments, the image sensor further includes: a substrate having an active region and a peripheral region adjacent to the active region, wherein the pixel and the isolation structure are located in the substrate within the active region; and a conductive structure located in the substrate within the peripheral region, wherein the conductive grid is electrically connected to the conductive structure. In some embodiments, the conductive grid is separated from the substrate by the dielectric structure. In some embodiments, the material of the conductive grid and the material of the conductive structure are identical. In some embodiments, the conductive grid and the conductive structure are integral. In some embodiments, the image sensor further includes: a conductive pattern located on the substrate within the peripheral region, wherein the conductive grid is electrically connected to the conductive structure through the conductive pattern. In some embodiments, the material of the conductive structure and the material of the conductive pattern are identical. In some embodiments, the material of the conductive grid and the material of the conductive structure are identical. In some embodiments, the conductive grid, the conductive pattern, and the conductive structure are integral. In some embodiments, the conductive grid is in the form of a conformal layer or a solid block.

[0192] Other embodiments of this application provide a semiconductor device comprising: a substrate having a first side and a second side opposite to the first side; an interconnect located on the first side; a photodiode array disposed in an active region of the substrate and electrically connected to the interconnect; an isolation structure extending from the second side of the substrate to a location in the active region of the substrate, wherein the photodiode array is surrounded by and spaced apart from the isolation structure, and the isolation structure includes a conductive grid; and a plurality of conductive structures disposed in a peripheral region of the substrate and electrically connected to the interconnect, wherein the conductive grid is electrically connected to the interconnect through the conductive structures and electrically isolated from the photodiode array.

[0193] In some embodiments, a portion of the isolation structure is located between two adjacent photodiodes of the photodiode array in the substrate within the active region, along a direction perpendicular to the stacking direction of the substrate and the interconnect. In some embodiments, the semiconductor device further includes: a plurality of first isolation members located in the substrate on the first side and electrically isolated from the interconnect, wherein the conductive structure penetrates the first isolation members to be electrically connected to the interconnect; or a plurality of second isolation members located in the substrate on the first side and electrically connected to the interconnect, wherein the conductive structure contacts the second isolation members to be electrically connected to the interconnect, wherein the second isolation members include doped regions.

[0194] Some embodiments of this application provide a method for manufacturing an image sensor, comprising: forming a pixel in a substrate at a first side of the substrate, the pixel including a photosensitive region and a circuit region adjacent to the photosensitive region; recessing the substrate at a second side of the substrate opposite to the first side to form a grid cavity surrounding the photosensitive region above the circuit region; disposing a first dielectric structure within the grid cavity; forming a conductive grid on the first dielectric structure in the grid cavity to form an isolation structure including the first dielectric structure and the conductive grid; recessing the substrate at the second side of the substrate to form a plurality of openings on a side adjacent to the grid cavity; disposing a second dielectric structure in the openings; and forming a plurality of conductive structures on the second dielectric structure in the openings, wherein the conductive structures are electrically connected to the conductive grid of the isolation structure, and the isolation structure is electrically isolated from the pixel.

[0195] In some embodiments, the grid cavity and the opening are formed simultaneously, and the grid cavity and the opening are spatially connected; the first dielectric structure and the second dielectric structure are formed simultaneously; and the conductive grid and the conductive structure are formed simultaneously. In some embodiments, the method further includes: forming an interconnect on the substrate at the first side; forming a plurality of dielectric isolators in the substrate at the first side; and patterning the dielectric isolators to form a plurality of vias communicating with the opening space, wherein the conductive structure is formed to further extend into the vias to electrically connect the interconnect and the conductive grid. In some embodiments, the method further includes: forming an interconnect on the substrate at the first side; and forming a plurality of doped isolators in the substrate at the first side, wherein the opening is formed to expose the surface of the doped isolator, and the conductive structure is formed to contact the doped isolator to electrically connect the interconnect and the conductive grid through the doped isolator.

[0196] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. An image sensor, comprising: The substrate has an active region and a peripheral region adjacent to the active region; A pixel is located within the active region and includes a photosensitive region and a circuit region adjacent to the photosensitive region; An isolation structure is disposed on a first side of the substrate surrounding the photosensitive region, wherein the isolation structure includes a conductive grid and a dielectric structure covering the sidewalls of the conductive grid; A conductive structure is disposed in the substrate within the peripheral region, wherein the conductive grid is electrically connected to the conductive structure; and An isolator is disposed on a second side of the substrate below the conductive structure, opposite to the first side of the substrate. The conductive structure is in contact with the isolator and the conductive grid is electrically connected to the conductive component on the second side of the substrate through the isolator.

2. The image sensor according to claim 1, wherein, The isolation structure overlaps with the circuit region, and the isolation structure is electrically isolated from the pixel.

3. The image sensor according to claim 1, wherein, The dielectric structure also covers the bottom surface of the conductive grid.

4. The image sensor according to claim 1, wherein, The material of the conductive grid includes metals or metal alloys.

5. The image sensor according to claim 1, wherein, The conductive component is a wire disposed on the second side of the substrate.

6. The image sensor according to claim 1, wherein, The conductive grid is separated from the substrate by the dielectric structure.

7. The image sensor according to claim 1, wherein, The material of the conductive grid is exactly the same as the material of the conductive structure.

8. The image sensor according to claim 1, wherein, The insulating element is a shallow trench insulating element made of dielectric material.

9. The image sensor according to claim 1, further comprising: A conductive pattern is located on the substrate within the peripheral region, electrically connecting the conductive grid and the conductive structure.

10. The image sensor according to claim 9, wherein, The material of the conductive structure is exactly the same as the material of the conductive pattern.

11. The image sensor according to claim 10, wherein, The material of the conductive grid is exactly the same as the material of the conductive structure.

12. The image sensor according to claim 1, wherein, The isolation element includes a doped region that is electrically connected to the conductive structure and the conductive component.

13. The image sensor according to claim 1, wherein, The conductive grid can be in the form of a conformal layer or a solid block.

14. A semiconductor device, comprising: A substrate having a first side and a second side opposite to the first side; Interconnectors are located on the first side; Multiple isolation elements are located on a first side of the substrate and are electrically isolated from the interconnects; A photodiode array is disposed in the active region of the substrate and electrically connected to the interconnect; An isolation structure extends from a second side of the substrate into a location within the active region of the substrate, wherein the photodiode array is surrounded by and spaced apart from the isolation structure, and the isolation structure includes a conductive grid; and Multiple conductive structures are disposed in the substrate within a peripheral region of the substrate and electrically connected to the interconnect, wherein the conductive grid is electrically connected to the interconnect through the conductive structures and electrically isolated from the photodiode array. The conductive structure penetrates the insulating member to be electrically connected to the interconnect.

15. The semiconductor device according to claim 14, wherein, A portion of the isolation structure is located between two adjacent photodiodes of the photodiode array in the substrate within the active region, in a direction perpendicular to the stacking direction of the substrate and the interconnects.

16. The semiconductor device according to claim 14, wherein, The isolation element includes a doped region.

17. A method for manufacturing an image sensor, comprising: A pixel is formed in the substrate at a first side of the substrate, the pixel including a photosensitive region and a circuit region adjacent to the photosensitive region; Interconnects are formed on the substrate at the first side; An isolation element located on the first side of the substrate is formed in the substrate; The substrate is recessed at a second side opposite to the first side to form a grid cavity surrounding the photosensitive region above the circuit region; A first dielectric structure is disposed within the grid cavity; A conductive grid is formed on the first dielectric structure in the grid cavity to form an isolation structure including the first dielectric structure and the conductive grid; The substrate is recessed at the second side to form a plurality of openings on the side immediately adjacent to the grid cavity; A second dielectric structure is provided in the opening; as well as A plurality of conductive structures are formed on the second dielectric structure in the opening, wherein the conductive structures are electrically connected to the conductive grid of the isolation structure, and the isolation structure is electrically isolated from the pixel, wherein the conductive structures are in contact with the isolation member and electrically connect the conductive grid to the interconnect member through the isolation member.

18. The method according to claim 17, wherein, The grid cavity and the opening are formed simultaneously, and the grid cavity and the opening are spatially connected. The first dielectric structure and the second dielectric structure are formed simultaneously, and The conductive grid and the conductive structure are formed simultaneously.

19. The method of claim 17, further comprising: Interconnects are formed on the substrate at the first side; A plurality of dielectric isolation elements are formed in the substrate at the first side; as well as The dielectric isolator is patterned to form a plurality of through-holes communicating with the opening space. The conductive structure is formed to extend further into the through-hole to electrically connect the interconnect and the conductive grid.

20. The method of claim 17, wherein, The isolation element includes a doped region.

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