Display device

Abstract

Disclosed is a display device including: a substrate; first thin film transistors each including a first active layer, a first gate insulating layer, a first gate electrode provided so as to overlap the first active layer, a first interlayer insulating layer, and a first source electrode and a first drain electrode formed through the first gate insulating layer; a gate line formed integrally with the first gate electrode; an isolation insulating layer provided on the first interlayer insulating layer; second thin film transistors each including a second active layer provided on the isolation insulating layer, a second gate insulating layer, a second gate electrode provided so as to overlap the second active layer, a second interlayer insulating layer, and a second source electrode and a second drain electrode formed through the second gate insulating layer and the second interlayer insulating layer; and an overlapping pattern provided on the isolation insulating layer so as to be connected to the gate line.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2020-0149302, filed on November 10, 2020, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0002] This invention relates to a display device. Background Technology

[0003] Image displays that show various information on a screen are a core technology of the information and communication age, and are evolving towards thinner, lighter, more portable, and higher-performance displays. Therefore, various display devices such as liquid crystal displays (LCDs), electroluminescent displays (ELDs), and quantum dot (QD) displays are currently in use.

[0004] Among electroluminescent displays, organic light-emitting displays (OLEDs) are primarily used, where the light-emitting layer uses organic materials. As a self-emissive device, OLEDs feature low power consumption, high response speed, high luminous efficiency, high brightness, and wide viewing angle. OLEDs display images through multiple sub-pixels arranged in a matrix. Each sub-pixel includes a light-emitting device and pixel circuitry, with the pixel circuitry comprising multiple transistors configured to independently drive the light-emitting device.

[0005] To provide high-quality image information, organic light-emitting displays (OLEDs) are being developed to increase their resolution and size.

[0006] However, as the resolution and size of organic light-emitting diodes (OLEDs) increase, the resistance of the wiring in the panel also increases. This increased wiring resistance makes it difficult to handle the high-speed driving required for OLEDs. Summary of the Invention

[0007] Therefore, the present invention aims to provide a display device that substantially overcomes one or more problems caused by the limitations and disadvantages of related technologies.

[0008] The purpose of this invention is to provide a display device that, by forming an overlapping pattern that overlaps with or is adjacent to a wiring with increased resistance, and then connecting the overlapping pattern to the wiring with increased resistance, can reduce the resistance of the wiring with increased resistance, thereby improving the driving speed.

[0009] Other advantages, objects, and features of the invention will be set forth in part in the description which follows, some of which will become apparent to those skilled in the art upon review of the following description or will be learned by practice of the invention. These objects and other advantages of the invention may be realized and obtained by means of structures particularly pointed out in the specification, claims, and drawings.

[0010] To achieve these objectives and other advantages, and according to the purposes of the invention, as specifically and generally described herein, a display device includes: a substrate comprising an effective region and an ineffective region; first thin-film transistors, each of the first thin-film transistors including: a first active layer disposed in the effective region; a first gate insulating layer disposed on the first active layer; a first gate electrode disposed on the first gate insulating layer and disposed overlapping the first active layer; a first interlayer insulating layer disposed on the first gate electrode; and a first source electrode and a first drain electrode formed through the first gate insulating layer and connected to the first active layer; a gate line integrally formed with the first gate electrode; an isolation insulating layer disposed on the first interlayer insulating layer; and a second thin-film transistor disposed in the effective region. Each of the second thin-film transistors includes: a second active layer disposed on the isolation insulating layer; a second gate insulating layer disposed on the second active layer; a second gate electrode disposed on the second gate insulating layer and disposed overlapping the second active layer; a second interlayer insulating layer disposed on the second gate insulating layer and the second gate electrode; and a second source electrode and a second drain electrode formed through the second gate insulating layer and the second interlayer insulating layer to be connected to the second active layer; and an overlapping pattern disposed on the isolation insulating layer and connected to the gate line, wherein the overlapping pattern includes: a first overlapping pattern disposed on the isolation insulating layer and formed of the same material as the second active layer; and a second overlapping pattern disposed on the first overlapping pattern.

[0011] At least one contact hole may be provided in the insulating layer to connect the first overlapping pattern to the gate line.

[0012] The at least one contact hole may be provided in the effective area.

[0013] The first overlapping pattern and the second active layer may be formed of oxide semiconductor.

[0014] The second overlapping pattern may be formed from at least one of Mo / Ti, MoTi / Cu / MoTi, Mo / Al / Mo, and Ti / Al / Ti.

[0015] The overlapping pattern may have a width smaller than the width of the gate line, thereby completely overlapping with the gate line.

[0016] The overlapping pattern may further include overlapping pattern lines and overlapping pattern electrodes, wherein the overlapping pattern electrodes may be configured to overlap with the first gate electrode, and the overlapping pattern lines may be configured to overlap with the gate lines.

[0017] The gate line may have a width smaller than the width of the overlapping pattern, thereby completely overlapping the overlapping pattern.

[0018] The overlapping pattern and the gate line may be spaced apart from each other so as to be arranged parallel to each other. The gate line may include a gate branch configured to protrude from the length direction of the gate line toward the overlapping pattern, and a contact hole may be formed in the region where each gate branch overlaps with a portion of the overlapping pattern, the contact hole being configured to connect each gate branch to the overlapping pattern.

[0019] The overlapping pattern and the gate line may be spaced apart from each other so as to be arranged parallel to each other. The gate line may include a gate branch configured to protrude from the length direction of the gate line toward the overlapping pattern. A connection pattern may be formed in the same layer as the second gate electrode. Each of the connection patterns may be configured to: connect to the corresponding gate branch in the gate branch through a first contact hole formed in a first overlap region where each connection pattern overlaps with the corresponding gate branch in the gate branch; and connect to the overlapping pattern through a second contact hole formed in a second overlap region where each connection pattern overlaps with the overlapping pattern.

[0020] One side of each connecting pattern can be connected to the second overlapping pattern in the second overlapping area.

[0021] The first contact hole may be formed through the second gate insulating layer and the isolation insulating layer in the first overlapping region.

[0022] The second contact hole may be formed through the second gate insulating layer in the second overlapping region where the overlapping pattern overlaps with each connection pattern.

[0023] The second gate electrode and the connection pattern may be disposed on the second gate insulating layer.

[0024] The connection pattern can connect the gate line and the overlapping pattern to each other.

[0025] The display device may further include: a first extension line and a second extension line configured to extend from the gate line disposed in the effective region toward the ineffective region; an extended overlapping pattern configured to extend from the overlapping pattern disposed in the effective region and thus overlapping the gate line toward the ineffective region and thus overlapping the first extension line; and a connecting line disposed in the connecting region of the ineffective region and thus overlapping the second extension line, the connecting region including: a third contact hole configured to connect the connecting line to the second extension line; and a fourth contact hole configured to connect the extended overlapping pattern to the first extension line.

[0026] The third and fourth contact holes may be formed through the insulating layer.

[0027] The first extension line may be configured to be connected to the gate line, and the second extension line may be configured to be connected to the first extension line.

[0028] It should be understood that the foregoing general description and the following detailed description of the invention are illustrative and explanatory, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0029] The accompanying drawings, which provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:

[0030] Figure 1 This is a plan view illustrating a schematic structure of a display device according to an embodiment of the present invention;

[0031] Figure 2 This is a cross-sectional view of a display device according to an embodiment of the present invention;

[0032] Figure 3 yes Figure 1 An enlarged plan view of region A;

[0033] Figure 4 It is along Figure 3 A cross-sectional view taken from line I-I';

[0034] Figure 5 This is a plan view illustrating a display device according to another embodiment of the present invention;

[0035] Figure 6 It is along Figure 5 A cross-sectional view taken from line II-II';

[0036] Figure 7 This is a plan view illustrating a display device according to another embodiment of the present invention;

[0037] Figure 8 It is along Figure 7 A cross-sectional view taken from line III-III';

[0038] Figure 9 This is a plan view illustrating a display device according to yet another embodiment of the present invention;

[0039] Figure 10 It is along Figure 9 A cross-sectional view taken from line IV-IV';

[0040] Figure 11 This is a plan view illustrating a display device according to yet another embodiment of the present invention;

[0041] Figure 12 It is along Figure 11 A cross-sectional view taken from line V-V'. Detailed Implementation

[0042] Referring now to exemplary embodiments of the invention, some examples of which are illustrated in the accompanying drawings. In the following description of the embodiments and drawings, the same or similar elements are denoted throughout by the same reference numerals. In the following description of embodiments of the invention, detailed descriptions of known functions and constructions incorporated herein will be omitted where such inclusion would obscure the main body of the invention. Furthermore, in the following description of embodiments of the invention, elements of substantially the same few embodiments will be described once in the first embodiment, and then their repetition in other embodiments will be omitted as it is considered unnecessary.

[0043] In the following description of the embodiments, it will be understood that when the terms "first," "second," etc., are used to describe the elements, these elements are not limited by these terms. These terms are only used to distinguish the same or similar elements.

[0044] The various features of the embodiments of the present invention can be combined or integrated with each other in part or in whole, and can be interoperated or driven in various technical ways. Furthermore, the embodiments can be implemented independently of each other or jointly implemented through the connection between them.

[0045] Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0046] Figure 1 This is a plan view illustrating a schematic structure of a display device according to an embodiment of the present invention. Figure 2 This is a cross-sectional view of a display device according to an embodiment of the present invention. Figure 3 yes Figure 1 An enlarged plan view of region A. Figure 4 It is along Figure 3The cross-sectional view taken from line I-I'.

[0047] like Figures 1 to 4 As shown, a display device according to one embodiment of the present invention includes: a display panel 10 configured to display an image; and a panel driver configured to drive the display panel 10. The panel driver includes a data driver 20, gate drivers 40A and 40B, and a timing controller 30.

[0048] The timing controller 30 can generate data control signals and gate control signals for controlling the driving timing of the data driver 20 and the gate drivers 40A and 40B, respectively, and can provide the data control signals and gate control signals to the data driver 20 and the gate drivers 40A and 40B. The timing controller 30 can process image data and provide the processed image data to the data driver 20.

[0049] The data driver 20 can be controlled by a data control signal provided by the timing controller 30, and can convert the image data provided by the timing controller 30 into an analog data signal and provide the analog data signal to the data line DL of the display panel 10.

[0050] Gate drivers 40A and 40B can be implemented as in-panel gate-in-place (GIP) circuits formed directly in the inactive region NA in the manner of thin-film transistors. Gate drivers 40A and 40B can be disposed in the inactive region NA located on at least one of the left and right sides of the display panel 10.

[0051] Gate drivers 40A and 40B can output gate signals while simultaneously switching the level of the gate voltage in response to a gate control signal provided from the timing controller 30. Gate drivers 40A and 40B can output gate signals via gate line GL.

[0052] Here, a connection area LK can be configured where the gate line GL of the display panel 10 is connected to the gate drivers 40A and 40B. Specifically, the output lines of the gate drivers 40A and 40B ( Figure 11 45) can extend into the interconnect region LK, and the gate line GL can extend into the interconnect region LK. Although the output lines of the gate drivers 40A and 40B can be connected to the gate line GL in the interconnect region LK via the interconnect Ln, this disclosure is not limited thereto, and the output lines and the gate line GL can be integrally formed.

[0053] The display panel 10 includes: an effective area AA of the screen configured to display an input image; and an ineffective area NA located on at least one side of the effective area AA.

[0054] The inactive region NA is a region where the input image is not displayed and sub-pixels SP can be set. Signal lines and gate drivers 40A and 40B can be set in the inactive region NA.

[0055] Within the effective area AA, sub-pixels SP connected to intersecting data lines DL and gate lines GL can be arranged in a matrix. For example... Figure 2 As shown, each sub-pixel SP includes a light-emitting device 500, and at least one driving transistor 100 and at least one switching transistor 200 electrically connected to the light-emitting device 500.

[0056] The substrate 101, configured to support the switching transistor 200 and the driving transistor 100, may include multiple polyimide (PI) layers. When the substrate 101 is formed of polyimide (PI), a process for manufacturing a display device can be performed with a glass-formed support substrate disposed beneath the substrate 101, and the support substrate can be released from the substrate 101 after the display device manufacturing process is completed. Furthermore, when the support substrate is released from the substrate 101, a backplate configured to support the substrate 101 can be disposed beneath the substrate 101. Additionally, the substrate 101 may be formed of glass or a flexible plastic material.

[0057] A buffer layer 110, including a multi-buffer layer 112 and a lower buffer layer 115, can be formed on the substrate 101. The multi-buffer layer 112 can delay the diffusion of moisture and / or oxygen into the substrate 101. This can be achieved by alternately stacking silicon nitride (SiN). x ) layer and silicon oxide (SiO) x (112) The layers are formed at least once to create multiple buffer layers.

[0058] The lower buffer layer 115 can be used to protect the second active layer 220 and cut off various defects introduced from the substrate 101. The lower buffer layer 115 can be made of a-Si, silicon nitride (SiN) x ), silicon dioxide (SiO) x (and so on)

[0059] A drive transistor 100 may be disposed on the buffer layer 110. The drive transistor 100 is operable in response to the data voltage stored in the storage capacitor, causing a drive current to flow between the high-voltage supply line and the low-voltage supply line. Figure 2 As shown, the driving transistor 100 may include: a first gate electrode 130 conductively connected to the second drain electrode of the switching transistor 200, a first source electrode 142 connected to a high voltage supply line, a first drain electrode 145 connected to the light-emitting device 500, and a first active layer 120, wherein the first active layer 120 is configured to form a channel between the first source electrode 142 and the first drain electrode 145.

[0060] That is, the driving transistor 100 may include a first active layer 120, a first gate electrode 130, a first source electrode 142 and a first drain electrode 145, and may further include an overlapping pattern 1000 connected to a gate line GL integrally formed with the first gate electrode 130.

[0061] The first active layer 120 of the driving transistor 100 may be disposed on the buffer layer 110. The first active layer 120 may include low-temperature polycrystalline silicon (LTPS). This is because polycrystalline silicon material has a high mobility (equal to or greater than 100 cm⁻¹). 2 Polycrystalline silicon ( / Vs) thus exhibits low power consumption and excellent reliability. Therefore, it can be used in gate drivers and / or multiplexers of driving devices for thin-film transistors in display devices, and can also be used in the first active layer 120 of the driving transistor 100 in a display device according to an embodiment of the present invention. Amorphous silicon (a-Si) can be deposited on the buffer layer 110, a polycrystalline silicon layer can be formed by a dehydrogenation process and a crystallization process, and the first active layer 120 can be formed by patterning the polycrystalline silicon layer.

[0062] The first active layer 120 may include a first channel region 120a that forms a channel when the driving transistor 100 is driven, and a first source region 120b and a first drain region 120c located on both sides of the first channel region 120a. The first source region 120b refers to the portion of the first active layer 120 connected to the first source electrode 142, and the first drain region 120c refers to the portion of the first active layer 120 connected to the first drain electrode 145. The first channel region 120a, the first source region 120b, and the first drain region 120c can be defined by performing ion doping (impurity doping) on ​​the first active layer 120. The first source region 120b and the first drain region 120c can be formed by doping the first active layer 120, which is formed of polysilicon material, with ions used as dopant. Here, the first channel region 120a may be the undoped portion of the first active layer 120, which is formed of polysilicon material.

[0063] A first gate insulating layer 125 may be disposed on the first active layer 120 of the driving transistor 100. The first gate insulating layer 125 may be formed comprising silicon nitride (SiN). x ) layer or silicon dioxide (SiO) x It can be a single-layer structure including silicon nitride (SiN) layers, or it can be formed as a single-layer structure including silicon nitride (SiN). x ) layer and silicon oxide (SiO) xThe first gate insulating layer 125 may have a multilayer structure. Contact holes configured to connect the first source electrode 142 and the first drain electrode 145 of the driving transistor 100 to the first source region 120b and the first drain region 120c of the first active layer 120, respectively.

[0064] A first gate electrode 130 of the driving transistor 100 is disposed on the first gate insulating layer 125. The first gate electrode 130 can be formed by forming a metal layer of molybdenum (Mo) or the like on the first gate insulating layer 125 and then patterning the metal layer. The first gate electrode 130 can be disposed on the first gate insulating layer 125 so as to overlap with the first channel region 120a of the first active layer 120 of the driving transistor 100.

[0065] Here, when the first gate electrode 130 is formed on the first gate insulating layer 125, a light-shielding pattern 210 may be further provided in the region where the switching transistor 200 is disposed. The light-shielding pattern 210 may be provided to prevent the second active layer 220, which will be described below, from being exposed to light.

[0066] A first interlayer insulating layer 305 may be formed on the first gate insulating layer 125 and the first gate electrode 130. The first interlayer insulating layer 305 serves as an insulating layer to insulate the first gate electrode 130 and the first active layer 120 from the upper layer of the driving transistor 100, and to stabilize the first active layer 120 during heat treatment. The first interlayer insulating layer 305 may, for example, be made of silicon nitride (SiN). x The first active layer 120 is formed, thereby providing hydrogen to the first active layer 120 of the driving transistor 100 during the hydrogenation process of the first active layer 120.

[0067] An insulating layer 300 may be provided on the first interlayer insulating layer 305. The insulating layer 300 may, for example, be made of silicon oxide (SiO2). x An isolation insulating layer 300 is formed to prevent hydrogen ions from being introduced into the second active layer 220. When the second active layer 220 is an oxide semiconductor layer, the introduction of hydrogen ions into the second active layer 220 will lead to the degradation of normal cutoff characteristics. Therefore, an isolation insulating layer 300 formed of an oxide insulating material for preventing hydrogen ions from being introduced into the second active layer 220 is provided. The isolation insulating layer 300 can be used as a buffer film configured to form a switching transistor 200 thereon. In addition, contact holes configured to expose the first source region 120b and the first drain region 120c of the first active layer 120 of the driving transistor 100 can be formed in the isolation insulating layer 300, the first interlayer insulating layer 305 and the first gate insulating layer 125.

[0068] A second active layer 220 for the switching transistor 200 may be provided on the isolation insulating layer 300. Furthermore, an overlapping pattern 1000 may be provided on the isolation insulating layer 300 in the region where the driving transistor 100 is provided.

[0069] The overlapping pattern 1000 may include a first overlapping pattern 1010 and a second overlapping pattern 1020 that overlap each other on the gate line GL and / or the first gate electrode 130.

[0070] The first overlapping pattern 1010 may be formed on the insulating layer 300 using the same material as the second active layer 220. The second overlapping pattern 1020 may be formed on the first overlapping pattern 1010 using a single metal or multiple metals.

[0071] Reference Figure 3 and Figure 4 The overlapping pattern 1000 may be configured to overlap with the gate line GL and the first gate electrode 130. The overlapping pattern 1000 may include an overlapping pattern line 1100 and an overlapping pattern electrode 1200. The overlapping pattern electrode 1200 may be configured to overlap with the first gate electrode 130. Alternatively, in another embodiment described later, the overlapping pattern electrode 1200 may not be configured to overlap with the first gate electrode 130, but may be configured as a branch connected to the gate line GL. Here, the overlapping pattern electrode 1200 may be selectively formed.

[0072] The overlapping pattern 1000 can be disposed in the effective region AA and can have a width smaller than the width of the gate line GL. Therefore, the overlapping pattern 1000 can be disposed to completely overlap with the gate line GL.

[0073] The overlapping pattern 1000 can be connected to the gate line GL via contact holes CNT. Contact holes CNT are formed through the isolation insulating layer 300 and the first interlayer insulating layer 305 in the region where the overlapping pattern 1000 and the gate line GL overlap. Multiple contact holes can be formed to connect the overlapping pattern 1000 and the gate line GL to each other. Although the first interlayer insulating layer 305 is shown in these figures, it is optional to be disposed on the isolation insulating layer 300.

[0074] A gate line GL may be connected to a first overlapping pattern 1010, and a second overlapping pattern 1020 may be disposed on the first overlapping pattern 1010. The first overlapping pattern 1010 may be formed of an oxide semiconductor in the same manner as the second active layer 220. The second overlapping pattern 1020 may be formed of at least one of Mo / Ti, MoTi / Cu / MoTi, Mo / Al / Mo, and Ti / Al / Ti.

[0075] Therefore, in a display device according to one embodiment of the present invention, the overlapping pattern 1000 is connected to the gate line GL, and thus can be used as redundancy for the gate line GL. That is, the overlapping pattern 1000 can reduce the resistance of the gate line GL, and thus can cope with the high-speed driving of the display device.

[0076] Next, the switching transistor 200 may include a second active layer 220, a second gate electrode 230, a second gate insulating layer 225, a second source electrode 242, and a second drain electrode 245.

[0077] The second active layer 220 disposed on the insulating layer 300 can be formed of an oxide semiconductor. Because oxide semiconductor materials have a larger band gap than silicon materials, electrons cannot pass through their band gap in the off state, thus oxide semiconductor materials have a low cutoff current. Therefore, a thin-film transistor including an active layer formed of oxide semiconductor can have a shorter on-time and a longer off-time. Therefore, such a thin-film transistor is suitable for performing switching operations. Furthermore, because the cutoff current of this thin-film transistor is low, the amplitude of the auxiliary capacitor can be reduced, thus making the thin-film transistor suitable for high-resolution display devices. Specifically, the second active layer 220 can be formed of a metal oxide, for example, oxides of various metals, such as indium gallium zinc oxide.

[0078] The second active layer 220 can be formed by depositing a metal oxide on the insulating layer 300, performing a heat treatment process for stabilization, and then patterning the metal oxide. The second active layer 220 may include a second channel region 220a that forms a channel when the switching transistor 200 is driven, and a second source region 220b and a second drain region 220c located on either side of the second channel region 220a. The second source region 220b refers to the portion of the second active layer 220 connected to the second source electrode 242, and the second drain region 220c refers to the portion of the second active layer 220 connected to the second drain electrode 245. The second channel region 220a, the second source region 220b, and the second drain region 220c can be defined by performing ion doping (impurity doping) on ​​the second active layer 220. The second source region 220b and the second drain region 220c can be formed by doping the second active layer 220 with ions.

[0079] A second gate insulating layer 225 may be disposed on the second active layer 220, the overlapping pattern 1000, and the isolation insulating layer 300. The second gate insulating layer 225 may be formed to include silicon nitride (SiN). x ) layer or silicon dioxide (SiO) x It can be a single-layer structure including silicon nitride (SiN) layers, or it can be formed as a single-layer structure including silicon nitride (SiN). x ) layer and silicon oxide (SiO) xThe second gate insulating layer 225 can be patterned to overlap with the second channel region 220a of the second active layer 220. As another example, the second gate insulating layer 225 can be patterned to overlap with the second channel region 220a of the second active layer 220.

[0080] A second gate electrode 230 may be disposed on the second gate insulating layer 225. The second gate electrode 230 may be formed by forming a metal layer of molybdenum (Mo) or the like on the second gate insulating layer 225 and then patterning the metal layer. The second gate electrode 230 may be patterned to overlap with the second channel region 220a of the second active layer 220 and the second gate insulating layer 225.

[0081] A second interlayer insulating layer 405 may be disposed on the second gate electrode 230 and the second gate insulating layer 225. The second interlayer insulating layer 405 may be a passivation layer. Contact holes configured to expose the first source electrode 142, the first drain electrode 145, the second source electrode 242, and the second drain electrode 245 may be formed through the second gate insulating layer 225 and the second interlayer insulating layer 405.

[0082] The light-emitting device 500 includes an anode 510, a cathode 530, and a light-emitting stack 520 formed between the anode 510 and the cathode 530.

[0083] The anodes 510 of each sub-pixel can be independently disposed on the second planarization layer 420. The anodes 510 can be connected to the pixel connection electrode 450 exposed through the second pixel contact hole CH2 formed through the second planarization layer 420. Here, the pixel connection electrode 450 can be connected to the first drain electrode 145 exposed through the first pixel contact hole CH1 formed through the first planarization layer 410.

[0084] The anode 510 may be disposed on the second planarization layer 420, thereby overlapping not only with the light-emitting area defined by the embankment 570, but also with at least one of the driving transistor 100 and the switching transistor 200, thereby increasing the light-emitting area.

[0085] The dam 570 is formed to expose the anode 510 of each sub-pixel, thus forming the light-emitting region of each sub-pixel. The dam 570 may be formed in the effective region AA by an opaque material (e.g., a black material) to prevent optical interference between adjacent sub-pixels, or it may be formed in the ineffective region NA in addition to being formed in the effective region AA, overlapping with the gate drivers 40A and 40B. In this case, the dam 570 may include a light-shielding material comprising at least one of colored pigments, organic black, and carbon.

[0086] The light-emitting stack 520 can be formed by stacking the hole-correlated layer, the organic light-emitting layer, and the electron-correlated layer in either the following order or the reverse order. The light-emitting stack 520 is formed using a fine metal mask (FMM) manufacturing process. Spacers may be further provided on the embankment 570 to prevent damage to adjacent light-emitting stacks 520 and / or the embankment 570 due to the fine metal mask (FMM). The spacers may be formed of the same material as the embankment 570 or the first planarization layer 410 and the second planarization layer 420.

[0087] The cathode 530 can be formed on the upper and side surfaces of the light-emitting stack 520, thus facing the anode 510 with the light-emitting stack 520 sandwiched between them. The cathode 530 can be commonly formed in all sub-pixels disposed in the effective area AA, thus being shared by the sub-pixels. An encapsulation unit 600 is disposed on the substrate 101 on which the cathode 530 is formed.

[0088] The encapsulation unit 600 prevents external moisture or oxygen from penetrating into the light-emitting device 500, which is susceptible to external moisture or oxygen. For this purpose, the encapsulation unit 600 includes a plurality of inorganic encapsulation layers 610 and 620, and an organic encapsulation layer 650 disposed between the inorganic encapsulation layers 610 and 620, with the inorganic encapsulation layer 620 being the uppermost layer. Here, the encapsulation unit 600 may include at least two inorganic encapsulation layers 610 and 620 and at least one organic encapsulation layer 650. In this invention, the structure of the encapsulation unit 600 in which the organic encapsulation layer 650 is disposed between the first inorganic encapsulation layer 610 and the second inorganic encapsulation layer 620 will be described as an example.

[0089] An organic encapsulation layer 650 disposed between inorganic encapsulation layers 610 and 620 can serve as a buffer layer to alleviate stress between the respective inorganic encapsulation layers 610 and 620. In some examples, the organic encapsulation layer 650 can be used to alleviate stress caused by bending of the flexible display device. The organic encapsulation layer 650 can be formed of an organic insulating material such as acrylic resin, epoxy resin, polyimide, polyethylene, polycaprolactone (PCL), or silicon oxycarbide (SiOC).

[0090] The first inorganic encapsulation layer 610 is formed on the substrate 101 on which the cathode 530 is formed, thereby being closest to the light-emitting device 500. The first inorganic encapsulation layer 610 may be made of an inorganic insulating material that can be deposited at low temperatures, such as silicon nitride (SiN). x ), silicon dioxide (SiO) xThe first inorganic encapsulation layer 610 is formed by deposition at a low temperature, which prevents damage to the light-emitting stack 520, which is susceptible to high-temperature environments, during the deposition process of the first inorganic encapsulation layer 610.

[0091] The second inorganic encapsulation layer 620 is formed on the substrate 101 on which the organic encapsulation layer 650 is formed, thereby covering the upper and side surfaces of the organic encapsulation layer 650 and the first inorganic encapsulation layer 610. The second inorganic encapsulation layer 620 can minimize or prevent external moisture or oxygen from penetrating into the first inorganic encapsulation layer 610 or the organic encapsulation layer 650. The second inorganic encapsulation layer 620 may be made of materials such as silicon nitride (SiN). x ), silicon dioxide (SiO) x It is formed from inorganic insulating materials such as silicon oxynitride (SiON) or aluminum oxide (Al2O3).

[0092] Thus, in a display device according to an embodiment of the present invention, the overlapping pattern 1000 is configured to overlap with and be connected to the gate line GL, thereby enabling it to serve as redundancy for the gate line GL. Therefore, by connecting the overlapping pattern 1000, configured to overlap with the gate line GL, to the gate line GL, the resistance of the gate line GL can be reduced, thereby increasing the driving speed of the display device.

[0093] Figure 5 This is a plan view illustrating a display device according to another embodiment of the present invention. Figure 6 It is along Figure 5 The cross-sectional view taken from line II-II'.

[0094] Here, will be omitted Figure 5 and Figure 6 The embodiment shown in the figure is related to Figures 1 to 4 The detailed description of some parts that are substantially the same as those in the aforementioned embodiments is deemed unnecessary and will be referenced for ease of description. Figures 1 to 4 .

[0095] Reference Figure 5 and Figure 6 According to another embodiment of the present invention, the overlapping pattern 1000-1 may be formed in a region larger than the width of the gate line GL. The gate line GL may have a width smaller than the width of the overlapping pattern 1000-1, thereby completely overlapping with the overlapping pattern 1000-1. That is, the overlapping pattern 1000-1 may have a width larger than the width of the gate line GL, so that the gate line GL may completely overlap with the overlapping pattern 1000-1.

[0096] On the isolation insulating layer 300, a second active layer 220 may be provided in the region where the switching transistor 200 is formed, and an overlapping pattern 1000-1 may be provided in the region where the driving transistor 100 is formed, thereby forming in a region larger than the width of the gate line GL.

[0097] The overlapping pattern 1000-1 may include a first overlapping pattern 1010 and a second overlapping pattern 1020 that are disposed on the gate line GL and the first gate electrode 130 respectively.

[0098] The first overlapping pattern 1010 may be formed on the insulating layer 300 using the same material as the second active layer 220. Both the first overlapping pattern 1010 and the second active layer 220 may be formed using an oxide semiconductor. The second overlapping pattern 1020 may be formed on the first overlapping pattern 1010 using a single metal or multiple metals. The second overlapping pattern 1020 may be formed using at least one of Mo / Ti, MoTi / Cu / MoTi, Mo / Al / Mo, and Ti / Al / Ti.

[0099] The overlapping pattern 1000-1 can be configured to overlap with the gate line GL and the first gate electrode 130. The overlapping pattern 1000-1 can be configured to correspond to a portion of the first gate electrode 130.

[0100] The overlapping pattern 1000-1 can be connected to the gate line GL via contact holes CNTs. Multiple contact holes CNTs can be formed in the isolation insulating layer 300 and the first interlayer insulating layer 305 in the region where the overlapping pattern 1000-1 overlaps with the gate line GL, thereby enabling the overlapping pattern 1000-1 to be connected to the gate line GL. Although the first interlayer insulating layer 305 is shown in these figures, it is optionally disposed on the isolation insulating layer 300.

[0101] The gate line GL can be connected to the first overlapping pattern 1010 through the contact hole CNT, and the second overlapping pattern 1020 can be disposed on the first overlapping pattern 1010.

[0102] Thus, in a display device according to another embodiment of the present invention, the overlapping pattern 1000-1 is connected to the gate line GL, and can therefore be used as redundancy for the gate line GL. That is, the overlapping pattern 1000-1 has a width larger than the width of the gate line GL, thereby further reducing the resistance of the gate line GL, thereby enabling high-speed driving of the display device.

[0103] Furthermore, in the region where the gate electrode 130 is formed in the gate line GL, the overlapping pattern 1000-1 ensures a region larger than the width of the gate line GL, thus making it easy to form the contact hole CNT.

[0104] Therefore, in a display device according to another embodiment of the present invention, the overlapping pattern 1000-1 is disposed on the driving transistor 100 and thus formed in a region larger than the width of the gate line GL and connected to the gate line GL, thereby further reducing the resistance of the gate line GL and thereby increasing the driving speed of the display device.

[0105] Figure 7 This is a plan view illustrating a display device according to another embodiment of the present invention. Figure 8 It is along Figure 7 The cross-sectional view taken from line III-III'.

[0106] Here, will be omitted Figure 7 and Figure 8 The embodiment shown in the figure is related to Figures 1 to 4 The detailed description of some parts that are substantially the same as those in the foregoing embodiments shown is deemed unnecessary and will be referenced for ease of description. Figures 1 to 4 .

[0107] Reference Figure 7 and Figure 8 According to another embodiment of the present invention, the overlapping pattern 1000-3 may be configured to be spaced apart from the gate line GL. Furthermore, the overlapping pattern 1000-3 may be configured parallel to the gate line GL. Here, the gate line GL may include a gate branch GL-1 protruding from the length direction of the gate line GL toward the overlapping pattern 1000-3.

[0108] The gate branch GL-1 may have an overlap region OVA that overlaps with a portion of the overlap pattern 1000-3. A contact hole configured to connect the gate branch GL-1 to the overlap pattern 1000-3 may be formed in the overlap region OVA.

[0109] Specifically, a second active layer 220 may be formed on the isolation insulating layer 300 in the region where the switching transistor 200 is disposed, and an overlapping pattern 1000-3 may be formed in the region where the driving transistor 100 is formed. Furthermore, the overlapping pattern 1000-3 is disposed on the isolation insulating layer 300 to be spaced apart from the gate line GL in a planar view. That is, the gate line GL and the overlapping pattern 1000-3 may be arranged parallel to each other in a planar view. Additionally, the gate line GL may include a gate branch GL-1 protruding from the length direction of the gate line GL toward the overlapping pattern 1000-3.

[0110] The overlapping pattern 1000-3 may include a first overlapping pattern 1010 and a second overlapping pattern 1020 disposed on the insulating layer 300. Some portions of the overlapping pattern 1000-3 overlap with the gate branch GL-1.

[0111] The first overlapping pattern 1010 may be formed of the same material as the second active layer 220 disposed on the insulating layer 300. The first overlapping pattern 1010 and the second active layer 220 may be formed of an oxide semiconductor. The second overlapping pattern 1020 may be formed on the first overlapping pattern 1010 by a single metal or multiple metals. The second overlapping pattern 1020 may be formed of at least one of Mo / Ti, MoTi / Cu / MoTi, Mo / Al / Mo, and Ti / Al / Ti.

[0112] The gate line GL and the overlapping pattern 1000-3 can be arranged parallel to each other in the plan view, thus being spaced apart from each other. Here, in order to connect the gate line GL to the overlapping pattern 1000-3, a gate branch GL-1 protruding from the gate line GL can be provided. Specifically, the gate branch GL-1 can be configured to protrude from the length direction of the gate line GL toward the overlapping pattern 1000-3. The gate branch GL-1 can be configured to overlap with a portion of the overlapping pattern 1000-3.

[0113] The overlapping pattern 1000-3 may have an overlapping region OVA, each overlapping region OVA overlapping a portion of a corresponding gate branch in the gate branch GL-1. The overlapping pattern 1000-3 may be connected to the gate line GL via contact holes CNTs. Contact holes CNTs may be formed through the isolation insulating layer 300 and the first interlayer insulating layer 305 in the overlapping region OVA where the overlapping pattern 1000-3 and the gate branch GL-1 of the gate line GL overlap. Multiple contact holes CNTs may be provided to connect the overlapping pattern 1000-3 and the gate branch GL-1 to each other. Although the first interlayer insulating layer 305 is shown in these figures, the first interlayer insulating layer 305 is optionally provided on the isolation insulating layer 300.

[0114] The gate branch GL-1 can be configured to be connected to the first overlapping pattern 1010 via the contact hole CNT, and the second overlapping pattern 1020 can be disposed on the first overlapping pattern 1010.

[0115] Thus, in a display device according to another embodiment of the present invention, the overlapping pattern 1000-3 is connected to the gate line GL via contact holes CNT in the overlapping region OVA where the overlapping pattern 1000-3 and the gate branch GL-1 overlap, thereby enabling it to be used as redundancy for the gate line GL. That is, the overlapping pattern 1000-3 is spaced apart from the gate line GL and the gate branch GL-1 is configured to selectively overlap with the overlapping pattern 1000-3, thereby reducing the resistance of the gate line GL while providing freedom in forming the overlapping pattern 1000-3, thereby enabling high-speed driving of the display device.

[0116] Therefore, in a display device according to another embodiment of the present invention, the overlapping pattern 1000-3 is spaced apart from the gate line GL and connected to the gate line GL through the gate branch GL-1, thereby reducing the resistance of the gate line GL and thereby increasing the driving speed of the display device.

[0117] Figure 9 This is a plan view illustrating a display device according to yet another embodiment of the present invention. Figure 10 It is along Figure 9 A cross-sectional view taken from line IV-IV'.

[0118] Here, will be omitted Figure 9 and Figure 10 The embodiment shown in the figure is related to Figures 1 to 4 The detailed description of some parts that are substantially the same as those in the foregoing embodiments shown is deemed unnecessary and will be referenced for ease of description. Figures 1 to 4 .

[0119] Reference Figure 9 and Figure 10 According to another embodiment of the present invention, the overlapping pattern 1000-4 may be configured to be spaced apart from the gate line GL. Furthermore, the overlapping pattern 1000-4 may be configured parallel to the gate line GL. Here, the gate line GL may include a gate branch GL-2 protruding from the length direction of the gate line GL toward the overlapping pattern 1000-4.

[0120] Furthermore, in a display device according to yet another embodiment of the present invention, a connection pattern 1500 may be provided that overlaps with the gate branch GL-2 and the overlapping pattern 1000-4. Here, the connection pattern 1500 may be formed in the same layer as the second gate electrode 230. That is, the connection pattern 1500 and the second gate electrode 230 may be formed simultaneously on the second gate insulating layer 225.

[0121] The gate branch GL-2 may have a region that overlaps with a portion of the overlapping pattern 1000-4, or the gate branch GL-2 may not overlap with the overlapping pattern 1000-4. Although these figures show the gate branch GL-2 having a region that overlaps with a portion of the overlapping pattern 1000-4, the gate branch GL-2 may not have a region that overlaps with the overlapping pattern 1000-4.

[0122] The connection pattern 1500 may have a first overlapping region OVA1 that overlaps with the gate branch GL-2. A first contact hole CNT1 may be formed in the first overlapping region OVA1. The first contact hole CNT1 can connect the gate branch GL-2 to the connection pattern 1500.

[0123] The connecting pattern 1500 may have a second overlapping region OVA2 that overlaps with the overlapping pattern 1000-4. A second contact hole CNT2 may be formed in the second overlapping region OVA2. The second contact hole CNT2 can connect the overlapping pattern 1000-4 to the connecting pattern 1500.

[0124] Specifically, a second active layer 220 may be disposed on the isolation insulating layer 300 in the region where the switching transistor 200 is disposed, and an overlapping pattern 1000-4 may be disposed in the region where the driving transistor 100 is formed. Furthermore, the overlapping pattern 1000-4 may be disposed on the isolation insulating layer 300 to be spaced apart from the gate line GL in a planar view. That is, the gate line GL and the overlapping pattern 1000-4 may be arranged parallel to each other in a planar view. Additionally, the gate line GL may include a gate branch GL-2 protruding from the length direction of the gate line GL toward the overlapping pattern 1000-4.

[0125] The overlapping pattern 1000-4 may include a first overlapping pattern 1010 and a second overlapping pattern 1020 disposed on the insulating layer 300. Some portions of the overlapping pattern 1000-4 overlap with and are connected to the gate branch GL-2.

[0126] The first overlapping pattern 1010 may be formed of the same material as the second active layer 220 disposed on the insulating layer 300. The first overlapping pattern 1010 and the second active layer 220 may be formed of an oxide semiconductor. The second overlapping pattern 1020 may be formed on the first overlapping pattern 1010 by a single metal or multiple metals. The second overlapping pattern 1020 may be formed of at least one of Mo / Ti, MoTi / Cu / MoTi, Mo / Al / Mo, and Ti / Al / Ti.

[0127] The gate line GL and the overlapping pattern 1000-4 can be arranged parallel to each other in the plan view and thus spaced apart from each other. Here, in order to connect the gate line GL to the overlapping pattern 1000-4, a connection pattern 1500 can be further provided on the second gate insulating layer 225. One side of each connection pattern 1500 can overlap with the overlapping pattern 1000-4, and the other side of each connection pattern 1500 can overlap with the gate branch GL-2.

[0128] Depending on the arrangement between the gate line GL and the overlapping pattern 1000-4, the connecting pattern 1500 can be configured in various shapes. In these figures of the present invention, the overlapping pattern 1000-4 and the gate branch GL-2 are configured to be perpendicular to each other. Therefore, in order to connect the gate branch GL-2 and the overlapping pattern 1000-4 to each other, the connecting pattern 1500 may have a structure including a bending region.

[0129] The connection pattern 1500 may have a first overlapping region OVA1 that overlaps with a portion of the gate branch GL-2. In the first overlapping region OVA1, the gate branch GL-2 may be connected to the connection pattern 1500 through a first contact hole CNT1.

[0130] The connecting pattern 1500 may have a second overlapping region OVA2 that overlaps with a portion of the overlapping pattern 1000-4. In the second overlapping region OVA2, the overlapping pattern 1000-4 can be connected to the connecting pattern 1500 through a second contact hole CNT2. Here, the connecting pattern 1500 can be connected to the second overlapping pattern 1020 of the overlapping pattern 1000-4.

[0131] Therefore, the gate branch GL-2 and the overlapping pattern 1000-4 can be connected to each other through the connecting pattern 1500.

[0132] A first contact hole CNT1 is formed through the second gate insulating layer 225, the isolation insulating layer 300, and the first interlayer insulating layer 305 in the first overlapping region OVA1 where the gate branch GL-2 overlaps with the connection pattern 1500. The gate branch GL-2 can be connected to the connection pattern 1500 through the first contact hole CNT1. Although the first interlayer insulating layer 305 is shown in these figures, the first interlayer insulating layer 305 is optionally disposed on the isolation insulating layer 300.

[0133] A second contact hole CNT2 can be formed through the second gate insulating layer 225 in the second overlapping region OVA2 where the overlapping pattern 1000-4 and the connecting pattern 1500 overlap. The overlapping pattern 1000-4 can be connected to the connecting pattern 1500 through the second contact hole CNT2.

[0134] Thus, in a display device according to another embodiment of the present invention, the overlapping pattern 1000-4 is connected to the gate branch GL-2 via the connecting pattern 1500, and can therefore be used as redundancy for the gate line GL. That is, the overlapping pattern 1000-4 is spaced apart from the gate line GL, and the connecting pattern 1500 is configured to overlap with the overlapping pattern 1000-4 and the gate branch GL-2, thereby connecting the overlapping pattern 1000-4 and the gate branch GL-2 to each other. This reduces the resistance of the gate line GL and provides freedom in forming the overlapping pattern 1000-4, thereby enabling high-speed driving of the display device.

[0135] Therefore, in a display device according to another embodiment of the present invention, the overlapping pattern 1000-4 is spaced apart from the gate line GL, and the gate branch GL-2 is connected to the overlapping pattern 1000-4 via the connecting pattern 1500, thereby reducing the resistance of the gate line GL and thereby increasing the driving speed of the display device.

[0136] Figure 11 This is a plan view illustrating a display device according to yet another embodiment of the present invention. Figure 12 It is along Figure 11 A cross-sectional view taken from line V-V'.

[0137] Here, will be omitted Figure 11 and Figure 12 The embodiment shown in the figure is related to Figures 1 to 4 The detailed description of some parts that are substantially the same as those in the foregoing embodiments shown is deemed unnecessary and will be referenced for ease of description. Figures 1 to 4 .

[0138] Reference Figure 11 and Figure 12 According to another embodiment of the present invention, the display device may include an overlapping pattern 1000-5 disposed in an effective area AA and an extended overlapping pattern 1000-6 disposed in an ineffective area NA. Here, the ineffective area NA may include a wiring area LK in which the gate driver 40A is connected to the display panel 10.

[0139] A connection LN can be provided in the connection region LK to connect to the output line 45 led out from the gate driver 40A. The output line 45 can be provided on the first gate insulating layer 125 in the same manner as the gate line GL. In addition, the connection LN can be provided on the isolation insulating layer 300 in the inactive region NA.

[0140] The first extension line GL-5 and the second extension line GL-6 extending to the connection region LK of the non-effective region NA can be integrally formed with the gate line GL.

[0141] The overlapping pattern 1000-5 set in the effective area AA can be set to overlap with the gate line GL.

[0142] In the connection area LK of the non-effective area NA, an extended overlapping pattern 1000-6 extending from the overlapping pattern 1000-5 to the connection area LK can be provided, and the extended overlapping pattern 1000-6 can be configured to overlap with the first extension line GL-5. In order to connect the extended overlapping pattern 1000-6 to the first extension line GL-5, a fourth contact hole CNT4 can be provided in the area where the extended overlapping pattern 1000-6 and the first extension line GL-5 overlap with each other.

[0143] The first extension line GL-5 is configured to be connected to the gate line GL, and the second extension line GL-6 is configured to be connected to the first extension line GL-5.

[0144] Furthermore, in the wiring area LK of the non-effective area NA, the wiring LN and the second extension line GL-6 can be arranged to overlap each other. In order to connect the wiring LN to the second extension line GL-6, a third contact hole CNT3 can be provided in the area where the wiring LN and the second extension line GL-6 overlap.

[0145] Specifically, a second active layer 220 may be provided on the isolation insulating layer 300 in the effective region AA, in the region where the switching transistor 200 is disposed, and an overlapping pattern 1000-5 may be provided in the region where the driving transistor 100 is formed. That is, the overlapping pattern 1000-5 may be provided on the isolation insulating layer 300 in the effective region AA, thereby overlapping with the gate line GL.

[0146] Furthermore, on the isolation insulation layer 300 in the non-effective area NA, the connecting line LN and the second extension line GL-6 are connected through the third contact hole CNT3, and the extended overlapping pattern 1000-6 and the first extension line GL-5 are connected through the fourth contact hole CNT4.

[0147] The first overlapping pattern 1010 may be formed of the same material as the second active layer 220 disposed on the insulating layer 300. The first overlapping pattern 1010 and the second active layer 220 may be formed of an oxide semiconductor. The second overlapping pattern 1020 may be formed on the first overlapping pattern 1010 by a single metal or multiple metals. The second overlapping pattern 1020 may be formed of at least one of Mo / Ti, MoTi / Cu / MoTi, Mo / Al / Mo, and Ti / Al / Ti.

[0148] Thus, in a display device according to another embodiment of the present invention, the overlapping pattern 1000-5 is configured to overlap with the gate line GL, and the extended overlapping pattern 1000-6 and the connecting line LN are respectively connected to the first extended line GL-5 and the second extended line GL-6 disposed in the connecting area LK of the ineffective area NA through the fourth contact hole CNT4 and the third contact hole CNT3. Therefore, the overlapping pattern 1000-5 can be used as redundancy for the gate line GL. That is, by configuring the overlapping pattern 1000-5 to overlap with the gate line GL, and connecting the connecting line LN and the extended overlapping pattern 1000-6 in the ineffective area NA through the extended lines GL-5 and GL-6, the resistance of the gate line GL can be reduced while simultaneously reducing the bezel size, thereby enabling high-speed driving of the display device.

[0149] Therefore, in a display device according to another embodiment of the present invention, the overlapping pattern 1000-5 and the gate line GL extend to the ineffective region NA, such that the gate line GL and the overlapping pattern 1000-5 are connected to each other in the ineffective region NA, thereby reducing the resistance of the gate line GL and thereby increasing the driving speed of the display device.

[0150] As is evident from the above description, the display device according to one embodiment of the present invention can reduce the resistance of the wiring with increased resistance by forming an overlapping pattern that overlaps with or is adjacent to the wiring with increased resistance, and then connecting the overlapping pattern to the wiring with increased resistance.

[0151] Furthermore, according to one embodiment of the present invention, the display device extends the gate lines to connect to the overlapping pattern and wiring, thereby increasing the driving speed due to the reduced resistance of the wiring and reducing the bezel size.

[0152] Various modifications and variations may be made to this invention without departing from the spirit or scope thereof, as will be apparent to those skilled in the art. Therefore, this invention is intended to cover modifications and variations falling within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: The substrate includes both effective and ineffective regions; A first thin-film transistor, each of the first thin-film transistors comprising: a first active layer disposed in the effective region, a first gate insulating layer disposed on the first active layer, a first gate electrode disposed on the first gate insulating layer and disposed overlapping the first active layer, a first interlayer insulating layer disposed on the first gate electrode, and a first source electrode and a first drain electrode formed through the first gate insulating layer and thus connected to the first active layer. Gate line integrally formed with the first gate electrode; An insulating layer disposed on the first interlayer insulating layer; A second thin-film transistor disposed in the effective region, each of the second thin-film transistors comprising: a second active layer disposed on the isolation insulating layer; a second gate insulating layer disposed on the second active layer; a second gate electrode disposed on the second gate insulating layer and disposed overlapping the second active layer; a second interlayer insulating layer disposed on the second gate insulating layer and the second gate electrode; and a second source electrode and a second drain electrode formed through the second gate insulating layer and the second interlayer insulating layer to be connected to the second active layer; and An overlapping pattern disposed on the insulating layer and connected to the gate line. The overlapping pattern includes: A first overlapping pattern, wherein the first overlapping pattern is disposed on the insulating layer and formed of the same material as the second active layer; and A second overlapping pattern is set on top of the first overlapping pattern.

2. The display device according to claim 1, wherein at least one contact hole is provided in the insulating layer for connecting the first overlapping pattern to the gate line.

3. The display device according to claim 2, wherein at least one contact hole is disposed in the effective area.

4. The display device according to claim 1, wherein the first overlapping pattern and the second active layer are formed of oxide semiconductor.

5. The display device according to claim 1, wherein the second overlapping pattern is formed by at least one of Mo / Ti, MoTi / Cu / MoTi, Mo / Al / Mo, and Ti / Al / Ti.

6. The display device of claim 1, wherein the overlapping pattern has a width smaller than the width of the gate line, thereby completely overlapping the gate line.

7. The display device according to claim 6, wherein the overlapping pattern further comprises overlapping pattern lines and overlapping pattern electrodes, wherein: The overlapping patterned electrode is configured to overlap with the first gate electrode; and The overlapping pattern lines are configured to overlap with the gate lines.

8. The display device of claim 1, wherein the gate line has a width smaller than the width of the overlapping pattern, thereby completely overlapping the overlapping pattern.

9. The display device according to claim 1, wherein: The overlapping pattern and the gate line are spaced apart from each other, so that they are arranged parallel to each other; The gate line includes a gate branch configured to protrude from the length direction of the gate line toward the overlapping pattern; and A contact hole is formed in the region where each gate branch overlaps with a portion of the overlapping pattern, the contact hole being configured to connect each gate branch to the overlapping pattern.

10. The display device according to claim 1, wherein: The overlapping pattern and the gate line are spaced apart from each other and thus arranged parallel to each other, and the gate line includes a gate branch configured to project from the length direction of the gate line toward the overlapping pattern; and A connection pattern is formed in the same layer as the second gate electrode. Each of the connection patterns is configured as follows: A first contact hole is formed in a first overlap region where each connection pattern overlaps with a corresponding gate branch in the gate branch, and is connected to the corresponding gate branch in the gate branch; and The connection is made with the overlapping pattern by forming a second contact hole in the second overlapping area where each connection pattern overlaps with the overlapping pattern.

11. The display device of claim 10, wherein one side of each connecting pattern is connected to the second overlapping pattern of the overlapping pattern in the second overlapping region.

12. The display device of claim 10, wherein the first contact hole is formed through the second gate insulating layer and the isolation insulating layer in the first overlapping region.

13. The display device of claim 10, wherein the second contact hole is formed through the second gate insulating layer in the second overlapping region where the overlapping pattern overlaps with each connection pattern.

14. The display device of claim 10, wherein the second gate electrode and the connection pattern are disposed on the second gate insulating layer.

15. The display device of claim 10, wherein the connection pattern connects the gate lines to each other with the overlapping pattern.

16. The display device according to claim 10, further comprising: A first extension line and a second extension line are configured to extend from the gate line disposed in the effective region toward the ineffective region; An extended overlapping pattern is configured to extend from the overlapping pattern disposed in the effective region to overlap with the gate line toward the ineffective region to overlap with the first extended line; and A line that is set in the line region of the non-effective region and thus overlaps with the second extension line. The connected area includes: Configured to connect the connection line to the third contact hole of the second extension line; and Configured to connect the extended overlapping pattern to the fourth contact hole of the first extension line.

17. The display device of claim 16, wherein the third contact hole and the fourth contact hole are formed through the insulating layer.

18. The display device according to claim 16, wherein: The first extension line is configured to connect to the gate line; and The second extension line is configured to connect to the first extension line.

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