Display panel and display device comprising the same

Abstract

A display panel and a display device including the same are provided. The display panel includes a first area, a second area, and a third area, a resolution of the second area being less than a resolution of the first area; a substrate; a first pixel electrode on the substrate at the first area; a first pixel circuit on the substrate at the first area, the first pixel circuit connected to the first pixel electrode; a second pixel electrode on the substrate at the second area; a second pixel circuit on the substrate at the third area, the second pixel circuit connected to the second pixel electrode; and an opaque layer between the substrate and the second pixel electrode at the second area, the opaque layer including an insulating pattern superposed with the second pixel electrode.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2020-0148611, filed on November 9, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] One or more embodiments of this disclosure relate to a display panel and a display device including the display panel. More specifically, one or more embodiments of this disclosure relate to a display panel and a display device including the display panel, the display panel having an extended display area for displaying images in areas where components such as electronic components are disposed. Background Technology

[0003] Display devices have been used for a variety of purposes. Furthermore, because the thickness and weight of display devices have been reduced, their applications have expanded.

[0004] Different methods have been developed to design the shape of the display device, depending on its intended use, and more functions have been embedded in or linked to the display device.

[0005] The information disclosed in this background section is intended to enhance the understanding of the background technology of this disclosure, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0006] One or more embodiments of this disclosure relate to a display panel and a display device including the display panel, the display panel having an extended display area for displaying images in areas where components (such as electronic components) are disposed.

[0007] However, this disclosure is not limited to the foregoing aspects and features, and other aspects and features will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practicing one or more of the embodiments presented in this disclosure.

[0008] According to one or more embodiments of the present disclosure, a display panel includes: a first region, a second region, and a third region, the second region having a lower resolution than the first region; a substrate; a first pixel electrode on the substrate at the first region; a first pixel circuit on the substrate at the first region, the first pixel circuit being connected to the first pixel electrode; a second pixel electrode on the substrate at the second region; a second pixel circuit on the substrate at the third region, the second pixel circuit being connected to the second pixel electrode; and an opaque layer between the substrate and the second pixel electrode at the second region, the opaque layer including an insulating pattern superimposed on the second pixel electrode.

[0009] In an embodiment, the display panel may further include: a first organic insulating layer located in the second region between the substrate and the second pixel electrode; and a second organic insulating layer on the first organic insulating layer.

[0010] In one embodiment, the opaque layer may be located between the second organic insulating layer and the second pixel electrode.

[0011] In one embodiment, the upper surface of the opaque layer can contact the second pixel electrode, and the lower surface of the opaque layer can contact the second organic insulating layer.

[0012] In an embodiment, the second organic insulating layer may include a recess corresponding to the second pixel electrode, and the opaque layer may be located in the recess of the second organic insulating layer.

[0013] In one embodiment, the opaque layer may be located between the first organic insulating layer and the second organic insulating layer.

[0014] In an embodiment, the first organic insulating layer may include a recess corresponding to the second pixel electrode, and the opaque layer may be located in the recess of the first organic insulating layer.

[0015] In one embodiment, the hole at the position corresponding to the second pixel electrode can penetrate the first organic insulating layer, and the opaque layer can be in the hole of the first organic insulating layer.

[0016] In an embodiment, the display panel may further include: a first connecting line located in the second region between the first organic insulating layer and the second organic insulating layer, the first connecting line connecting the second pixel electrode to the second pixel circuit.

[0017] In an embodiment, the display panel may further include a second connecting line, wherein at a third region, the second connecting line connects the first connecting line to a second pixel circuit.

[0018] In an embodiment, the display panel may further include: a first connecting line located in the second region between the substrate and the first organic insulating layer, the first connecting line connecting the second pixel electrode to the second pixel circuit.

[0019] In an embodiment, the display panel may further include a second connecting line, wherein at a third region, the second connecting line connects the first connecting line to a second pixel circuit.

[0020] In an embodiment, the display panel may further include: a first organic insulating layer covering a first pixel circuit in a first region and a second pixel circuit in a third region, the first organic insulating layer including holes corresponding to the second region; and a second organic insulating layer on the first organic insulating layer in the first and third regions, the second organic insulating layer filling the holes of the first organic insulating layer between the substrate and the second pixel electrode in the second region.

[0021] In one embodiment, the opaque layer may be located in the second region between the substrate and the second organic insulating layer.

[0022] In an embodiment, the display panel may further include: a first connecting line located in the second region between the substrate and the second organic insulating layer, the first connecting line connecting the second pixel electrode to the second pixel circuit, and the opaque layer may at least partially cover the first connecting line.

[0023] In an embodiment, the display panel may further include a second connecting line, wherein at a third region, the second connecting line connects the first connecting line to a second pixel circuit.

[0024] According to one or more embodiments of the present disclosure, a display device includes: a display panel including: a first region, a second region, and a third region; a substrate; a first display element at the first region; a second display element at the second region, the second display element including a second pixel electrode on the substrate at the second region; a second pixel circuit on the substrate at the third region, the second pixel circuit being connected to the second pixel electrode; an organic insulating layer at the second region between the substrate and the second pixel electrode; and an opaque layer at the second region between the substrate and the second pixel electrode, the opaque layer including an insulating pattern superimposed on the second pixel electrode; and an assembly below the display panel, the assembly corresponding to the second region.

[0025] In an embodiment, the organic insulating layer may include: a first organic insulating layer between the substrate and the second pixel electrode; and a second organic insulating layer on the first organic insulating layer.

[0026] In one embodiment, the opaque layer may be located between the second organic insulating layer and the second pixel electrode.

[0027] In an embodiment, the second organic insulating layer may include a recess corresponding to the second pixel electrode, and the opaque layer may be located in the recess of the second organic insulating layer.

[0028] In one embodiment, the opaque layer may be located between the first organic insulating layer and the second organic insulating layer.

[0029] In an embodiment, the first organic insulating layer may include a recess corresponding to the second pixel electrode, and the opaque layer may be located in the recess of the first organic insulating layer.

[0030] In one embodiment, the first organic insulating layer may include a hole that penetrates the first organic insulating layer and corresponds to the position of the second pixel electrode, and the opaque layer may be in the hole of the first organic insulating layer.

[0031] In an embodiment, the organic insulating layer may include: a first organic insulating layer covering the second pixel circuit at the third region, the first organic insulating layer including a hole corresponding to the second region; and a second organic insulating layer on the first organic insulating layer at the third region, the second organic insulating layer filling the hole of the first organic insulating layer between the substrate and the second pixel electrode at the second region. An opaque layer may be present between the substrate and the second organic insulating layer. Attached Figure Description

[0032] The above and other aspects and features of this disclosure will become more apparent to those skilled in the art from the following detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0033] Figure 1 This is a perspective view of a display device according to an embodiment;

[0034] Figures 2A to 2B This is a partial cross-sectional view of a display device according to one or more embodiments;

[0035] Figures 3A to 3B It can be included in Figure 1 A plan view of the display panel in the display device;

[0036] Figure 4 This is an equivalent circuit diagram of the pixel circuit according to an embodiment;

[0037] Figure 5 This is a plan view showing the area of ​​the display panel according to an embodiment;

[0038] Figures 6A to 6B This is a cross-sectional view showing some portions of a display panel according to one or more embodiments;

[0039] Figure 7 It is based on Figure 6A A plan view of the second pixel electrode and the opaque layer in an embodiment;

[0040] Figures 8A to 8C It shows the basis for formation Figure 6A Cross-sectional views of various processes for the second pixel electrode and opaque layer in the embodiments;

[0041] Figure 9 This is a partial cross-sectional view of the display panel according to an embodiment;

[0042] Figure 10 It is based on Figure 9 A plan view of the second pixel electrode and the opaque layer in an embodiment;

[0043] Figures 11A to 11C It shows the basis for formation Figure 9Cross-sectional views of various processes for the second pixel electrode and opaque layer in the embodiments;

[0044] Figure 12 This is a cross-sectional view showing some portions of the display panel according to an embodiment;

[0045] Figures 13A to 13D It shows the basis for formation Figure 12 Cross-sectional views of various processes for the second pixel electrode and opaque layer in the embodiments;

[0046] Figure 14 This is a cross-sectional view showing some portions of the display panel according to an embodiment;

[0047] Figure 15 This is a cross-sectional view showing some portions of the display panel according to an embodiment;

[0048] Figures 16A to 16D It shows the basis for formation Figure 15 Cross-sectional views of various processes for the second pixel electrode and opaque layer in the embodiments;

[0049] Figure 17 This is a cross-sectional view showing some portions of the display panel according to an embodiment;

[0050] Figure 18 This is a cross-sectional view showing some portions of the display panel according to an embodiment;

[0051] Figures 19A to 19C It shows the basis for formation Figure 18 Cross-sectional views of various processes for the second pixel electrode and opaque layer in the embodiments;

[0052] Figure 20 This is a cross-sectional view showing some portions of the display panel according to an embodiment; and

[0053] Figures 21 to 22 This is a cross-sectional view showing some portions of a display panel according to one or more embodiments. Detailed Implementation

[0054] In the following, exemplary embodiments will be described in more detail with reference to the accompanying drawings. In the drawings, the same reference numerals consistently refer to the same elements. However, this disclosure can be implemented in a variety of different ways and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and these embodiments will fully convey to those skilled in the art the aspects and features of this disclosure. Therefore, processes, elements, and techniques not essential for a person of ordinary skill in the art to fully understand the aspects and features of this disclosure may not be described. Unless otherwise stated, the same reference numerals denote the same elements throughout the drawings and written description, and therefore their description need not be repeated.

[0055] When an embodiment can be implemented differently, the specific process sequence may differ from the order in which it is described. For example, two consecutively described processes may be performed simultaneously or substantially simultaneously, or in the reverse order of their description.

[0056] In the accompanying drawings, for clarity, the relative dimensions of elements, layers, and regions may be exaggerated and / or simplified. For ease of interpretation, spatial relative terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., may be used herein to describe the relationship of one element or feature as shown in the drawings to another element or feature. It will be understood that spatial relative terms are intended to include different orientations of the device in use or operation other than those included in the orientation depicted in the drawings. For example, if the device in the drawings is flipped, an element described as “below” or “below” or “below” other elements or features will then be oriented “above” said other elements or features. Thus, the example terms “below” and “below” can include both above and below orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly.

[0057] In the accompanying diagram, the x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system, but can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other or substantially perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0058] As used in this specification, when a line is described as “extending in a first direction or a second direction”, this means that the line extends in a zigzag or curved shape in the first or second direction, and that the line extends in a straight line in the first or second direction.

[0059] Throughout the specification, the phrase "in a plan view" indicates a view of the target portion from above, and the phrase "in a cross-sectional view" indicates a cross-section of the target portion that has been vertically cut, viewed from the side. Throughout the specification, when a first element is described as "overlapping" with a second element or a variation thereof, this means that the first element is located on top of or below the second element.

[0060] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the spirit and scope of this disclosure, the first element, first component, first region, first layer, or first portion described below may be referred to as a second element, second component, second region, second layer, or second portion.

[0061] It will be understood that when an element or layer is referred to as being "on," "connected to," or "bonded to" another element or layer, it can be directly on, directly connected to, or directly bonded to the other element or layer, or there may be intermediate elements or layers. Similarly, when a layer, region, or element is referred to as being "electrically connected" to another layer, region, or element, it can be directly electrically connected to the other layer, region, or element, and / or can be indirectly electrically connected with one or more intermediate layers, regions, or elements between them. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there may be one or more intermediate elements or layers.

[0062] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “an” are also intended to include the plural forms. It will also be understood that when the terms “comprising,” “including,” “having,” and / or variations thereof are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” means A, B, or A and B. When an expression such as “at least one of…” follows a list of elements, such an expression modifies the entire list of elements without modifying any individual elements within the list. For example, the expression "at least one of a, b and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c, or variations thereof.

[0063] As used herein, the terms “substantially,” “approximately,” and similar terms are used as approximate terms rather than as terms of degree and are intended to account for inherent biases in measured or calculated values ​​that will be recognized by one of ordinary skill in the art. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.” As used herein, the terms “use” and variations thereof may be considered synonymous with the terms “utilize” and variations thereof, respectively. Additionally, the term “exemplary” is intended to indicate or illustrate.

[0064] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless so explicitly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the relevant field and in the context of this specification, and not in an idealized or overly formal sense.

[0065] Figure 1 This is a perspective view of the display device 1 according to an embodiment.

[0066] Reference Figure 1The display device 1 may include a display area DA and a peripheral area DPA located at the outer portion of the display area DA (e.g., in or on the outer portion of the display area DA). For example, the peripheral area DPA may at least partially surround the display area DA (e.g., on the periphery of the display area DA). The display area DA may include a component area (e.g., a second area) CA and a main display area (e.g., a first area) MDA that at least partially surrounds the component area CA (e.g., on the periphery of the component area CA). In other words, the component area CA and the main display area MDA may display images independently or together. The peripheral area (e.g., a third area) DPA may be a non-display area where no pixels are arranged (e.g., in or on it). In some embodiments, the display area DA may be completely surrounded by the peripheral area DPA (e.g., the peripheral area DPA may be around the periphery of the display area DA).

[0067] The display device 1 according to the embodiment can be folded or bent. The display device 1 can be arranged in various suitable shapes (such as a rectangular plate shape with two pairs of sides, each pair of sides having sides that are parallel or substantially parallel to each other). When the display device 1 is arranged in a rectangular plate shape, one pair of sides can be longer than the other pair of sides. For ease of explanation and description, the direction along which the short side extends is represented as the x-direction, the direction along which the long side extends is represented as the y-direction, and the direction perpendicular or substantially perpendicular to the extension directions of the long and short sides is represented as the z-direction (e.g., the thickness direction).

[0068] The display device 1 according to the embodiments of this disclosure is not limited to the examples above, and may have various suitable shapes. For example, the display device 1 may be configured as a closed polygonal shape including straight edges, a circular or elliptical shape including curved edges, a semi-circular or semi-elliptical shape including straight and curved edges, etc. When the display device 1 has straight edges, at least some corners of each of its shapes may be curved.

[0069] exist Figure 1 In the main display area MDA (e.g., within or on the main display area MDA), a component area CA is shown. In another embodiment, the display device 1 may include two or more component areas CA, and the shapes and / or sizes of the multiple component areas CA may differ from each other. When viewed from a direction perpendicular or substantially perpendicular to the upper surface of the display device 1 (e.g., in a plan view), the component areas CA can have various suitable shapes, such as polygonal shapes (e.g., square shapes, star shapes, rhombus shapes, etc.), circular shapes, elliptical shapes, etc. Additionally, in Figure 1In the diagram, when viewed from a direction perpendicular or substantially perpendicular to the upper surface of the display device 1 (e.g., in a plan view), the component region CA is shown as located at the upper center region (e.g., in the +y direction) of the main display region MDA having a rectangular shape. However, this disclosure is not limited thereto, and the component region CA may be located on one side of the main display region MDA having a rectangular shape (e.g., on the upper right or upper left side).

[0070] The display device 1 can provide an image by using a plurality of first sub-pixels (e.g., main sub-pixels) Pm at the main display area MDA (e.g., in or on the main display area MDA) and a plurality of second sub-pixels (e.g., auxiliary sub-pixels) Pa at the component area CA (e.g., in or on the component area CA).

[0071] See below for reference. Figure 2A and Figure 2B In more detail, component 40 (such as an electronic component) may be located below the display panel (e.g., under) to correspond to component area CA. For example, component 40 may include a camera (imaging device, etc.) using infrared or visible light. As some other examples, component 40 may include a solar cell, a flash, an illuminance sensor, a proximity sensor, or an iris sensor. As another example, component 40 may have the function of receiving sound. To reduce limitations and constraints on the functionality of component 40, component area CA may include a transmission area TA through which light and / or sound output from component 40 to the outside or traveling from the outside toward component 40 may pass. In the display panel according to the embodiment or the display device 1 including the display panel, when light passes through component area CA, the transmittance of component area CA may be about 10% or greater, such as 40% or greater, 25% or greater, 50% or greater, 85% or greater, or 90% or greater.

[0072] Multiple second sub-pixels Pa may be located at component region CA (e.g., in or on component region CA). The multiple second sub-pixels Pa emit light to provide a desired image (e.g., a predetermined or specific image). The image displayed at component region CA (e.g., in or on component region CA) may be referred to as an auxiliary image and may have a lower resolution than the image displayed at main display region MDA (e.g., in or on main display region MDA). In other words, component region CA may include a transmission region TA through which light and / or sound can be transmitted, and when no sub-pixels are present at transmission region TA (e.g., in or on transmission region TA), the number of second sub-pixels Pa per unit area at component region CA (e.g., in or on component region CA) may be less than the number of first sub-pixels Pm per unit area at main display region MDA (e.g., in or on main display region MDA).

[0073] Figure 2A and Figure 2B This is a cross-sectional view of a display device 1 according to one or more embodiments.

[0074] Reference Figure 2A The display device 1 may include a display panel 10 and a component 40 stacked with the display panel 10. A cover window for protecting the display panel 10 may be further provided above the display panel 10.

[0075] The display panel 10 may include a component area CA, which is an area superimposed on the component 40, and a main display area MDA for displaying the main image. The display panel 10 may include a substrate 100, a display layer DISL, a touch screen layer TSL, an optical functional layer OFL, and a panel protection member PB below (e.g., under) the substrate 100.

[0076] The display layer (DISL) may include a circuit layer (PCL), light-emitting elements (EDm and EDA) as display components, and an encapsulation component (ENCM, such as...). Figure 2A (Taking the thin-film encapsulation layer TFEL or sealing substrate as an example), the circuit layer PCL includes multiple thin-film transistors (TFTs). The insulating layer IL' can be between the substrate 100 and the display layer DISL, or the insulating layer IL can be within the display layer DISL.

[0077] The substrate 100 may include an insulating material, such as glass, quartz, and / or polymer resin. The substrate 100 may include a rigid substrate, or it may be a flexible substrate that is bendable, foldable, and / or rollable.

[0078] A first pixel circuit (e.g., a main pixel circuit) PCm and a first light-emitting element (e.g., a main light-emitting device) EDm connected to the first pixel circuit PCm can be located at the main display area MDA of the display panel 10 (e.g., in or on the main display area MDA). The first pixel circuit PCm may include at least one thin-film transistor (TFT) and can control light emission from the first light-emitting element EDm. A first sub-pixel Pm can be implemented by light emission from the first light-emitting element EDm.

[0079] The second light-emitting element (e.g., an auxiliary light-emitting element) EDa can be located at the component region CA of the display panel 10 (e.g., in or on the component region CA) to implement the second sub-pixel Pa. In this embodiment, the second pixel circuit (e.g., an auxiliary pixel circuit) PCa may not be located at the component region CA (e.g., not in or on the component region CA), but may be located at the peripheral region DPA, which is a non-display area (e.g., in or on the peripheral region DPA). In another embodiment, the second pixel circuit PCa may be partially located at the main display region MDA (e.g., in or on the main display region MDA), or may be located between the main display region MDA and the component region CA. In other words, the second pixel circuit PCa may be configured (e.g., positioned) not to overlap with the second light-emitting element EDa.

[0080] The second pixel circuit PCa may include at least one thin-film transistor (TFT) and may be electrically connected to the second light-emitting element EDA via a connection line TWL. The connection line TWL may include a transparent conductive material. The second pixel circuit PCa can control light emission from the second light-emitting element EDA. The second sub-pixel Pa can be implemented by light emission from the second light-emitting element EDA. The area where the second light-emitting element EDA is disposed (e.g., positioned) at the component region CA (e.g., in or on the component region CA) may be referred to as the auxiliary pixel region ADA.

[0081] Furthermore, the area at component region CA (e.g., within or on component region CA) where the second light-emitting element EDa, serving as a display element, is not disposed can be referred to as the transmission region TA. The transmission region TA can be an area through which light and / or signals emitted from component 40 or incident on component 40 corresponding to component region CA can be transmitted. Auxiliary pixel regions ADA and transmission regions TA can be alternately arranged at component region CA (e.g., within or on component region CA). Connecting lines TWL for connecting the second pixel circuit PCa and the second light-emitting element EDa to each other can be located at the transmission region TA (e.g., within or on the transmission region TA). Connecting lines TWL can comprise a transparent conductive material with high transmittance; therefore, even when connecting lines TWL are located at the transmission region TA (e.g., within or on the transmission region TA), the transmittance of the transmission region TA can be ensured.

[0082] In this embodiment, since the second pixel circuit PCa is not located at the component region CA (e.g., not in or on the component region CA), the area of ​​the transmission region TA can be ensured, and its transmittance can be further improved.

[0083] In this embodiment, the opaque layer SHL, serving as a light-absorbing layer, may be located at the component region CA (e.g., within or on the component region CA). The opaque layer SHL may be below the reflective layer at the component region CA (e.g., within or on the component region CA). The opaque layer SHL may be directly below the reflective layer (e.g., directly below) to contact the reflective layer, or one or more insulating layers may be between the reflective layer and the opaque layer SHL. No reflective layer may be positioned between the opaque layer SHL and the substrate 100 at the component region CA (e.g., within or on the component region CA). Here, the reflective layer may have a suitable value (e.g., a predetermined or specific value) or a greater reflectivity and a suitable value (e.g., a predetermined or specific value) or a smaller transmittance. In this embodiment, the reflective layer at the component region CA (e.g., within or on the component region CA) may include (e.g., may be) a pixel electrode (e.g., an anode) contained in the second light-emitting element EDa.

[0084] Because light reflected from component 40 (such as a camera lens) may be reflected by the pixel electrode included in the second light-emitting element EDa at component region CA (e.g., in or on component region CA) and then may be incident on the camera again, ghosting or glare effects may occur in images captured by the camera. In this embodiment, the opaque layer SHL may be located between the substrate 100 and the pixel electrode at a position corresponding to the auxiliary pixel region ADA. Therefore, light incident on the pixel electrode can be absorbed, preventing or reducing light reflection from the pixel electrode, thereby reducing ghosting and glare effects in images captured by the camera.

[0085] The circuit layer PCL and display elements (e.g., EDm and EDa) can be covered by a thin-film encapsulation layer TFEL or by an encapsulation substrate. In one or more embodiments, as Figure 2A As shown, the thin-film encapsulation layer TFEL may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In an embodiment, the thin-film encapsulation layer TFEL may include a first inorganic encapsulation layer 131, a second inorganic encapsulation layer 133, and an organic encapsulation layer 132 between the first inorganic encapsulation layer 131 and the second inorganic encapsulation layer 133.

[0086] The first inorganic encapsulation layer 131 and the second inorganic encapsulation layer 133 may each include one or more inorganic insulating materials (such as silicon oxide (SiO2), silicon nitride (SiN)). x ), silicon oxynitride (SiO) x N y Aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and / or zinc oxide (ZnO) x For example, ZnO x It can be ZnO and / or ZnO2), and can be formed by chemical vapor deposition (CVD) or similar methods. The organic encapsulation layer 132 can include polymeric materials. Polymeric materials can include silicone resins, acrylic resins, epoxy resins, polyimide, polyethylene, etc.

[0087] The first inorganic encapsulation layer 131, the organic encapsulation layer 132, and the second inorganic encapsulation layer 133 can be integrally configured to cover the main display area MDA and the component area CA.

[0088] When the encapsulation component ENCM is an encapsulation substrate, the encapsulation substrate can be positioned facing the substrate 100 with the display element between the encapsulation substrate and the substrate 100. A gap can exist between the encapsulation substrate and the display element. The encapsulation substrate may include glass. A sealant including glass frit, etc., may be present between the substrate 100 and the encapsulation substrate, and the sealant may be located at the peripheral region DPA (e.g., within or on the peripheral region DPA). The sealant at the peripheral region DPA (e.g., within or on the peripheral region DPA) may surround the display area DA (e.g., around the periphery of the display area DA) to prevent or substantially prevent moisture penetration through the side surfaces.

[0089] A touchscreen layer (TSL) can obtain coordinate information based on external inputs, such as touch events. A TSL can include touch electrodes and touch lines connected to them. The TSL can sense external inputs using either self-capacitance or mutual capacitance methods.

[0090] The touchscreen layer TSL can be on the thin-film encapsulation layer TFEL. As another example, the touchscreen layer TSL can be formed independently on the touch substrate and then attached to the thin-film encapsulation layer TFEL via an adhesive layer (such as optically clear adhesive (OCA)). In embodiments, the touchscreen layer TSL can be directly on the thin-film encapsulation layer TFEL, in which case the adhesive layer may not be disposed between the touchscreen layer TSL and the thin-film encapsulation layer TFEL.

[0091] The optical functional layer OFL may include an anti-reflective layer. The anti-reflective layer can reduce the reflectivity of light (e.g., external light) incident on the display device 1 from the outside.

[0092] In some embodiments, the optical functional layer OFL may include a polarizing film. The OFL may include an opening OFL_OP corresponding to the transmission region TA. Therefore, the transmittance of the transmission region TA can be significantly improved. A transparent material (such as optically transparent resin (OCR) as an example) may be filled in the opening OFL_OP.

[0093] In some embodiments, the optical functional layer OFL may include a filter plate, which includes a black matrix and color filters.

[0094] In some embodiments, the optical functional layer (OFL) may also include a multilayer structure on the antireflective layer. The multilayer structure may include a first layer and a second layer on top of the first layer. The first and second layers may include organic insulating materials and may have different refractive indices than each other. For example, the refractive index of the second layer may be greater than that of the first layer.

[0095] A cover window may be further attached to the display panel 10 to protect the display panel 10. The optical functional layer OFL may be attached to (e.g., adhered to) the cover window via an optically clear adhesive, or may be attached to (e.g., adhered to) the touch screen layer TSL via an optically clear adhesive.

[0096] A panel protection member PB is attached to the lower portion (e.g., the rear surface) of the substrate 100 to support and protect the substrate 100. The panel protection member PB may include an opening PB_OP corresponding to the component region CA. When the panel protection member PB includes an opening PB_OP, the light transmittance of the component region CA can be improved. The panel protection member PB may include polyethylene terephthalate (PET) or polyimide (PI).

[0097] The area of ​​component region CA can be larger than the area where component 40 is arranged (e.g., in or on). Therefore, the area of ​​opening PB_OP in panel protection member PB can be different from (e.g., not equal to) the area of ​​component region CA.

[0098] In some embodiments, multiple components 40 may be located at component region CA (e.g., within or on component region CA). The multiple components 40 may have different functions than each other. For example, the multiple components 40 may include at least two of a camera (e.g., an imaging device), a solar cell, a flash, a proximity sensor, an illumination sensor, and an iris sensor.

[0099] exist Figure 2A In the middle, the bottom metal layer BML is not located below (e.g., under) the second pixel circuit PCa at the peripheral region DPA (e.g., not in or on the peripheral region DPA), but as Figure 2B As shown, the display device 1 according to some embodiments may include a bottom metal layer BML below (e.g., beneath) the second pixel circuit PCa. The bottom metal layer BML may be between the substrate 100 and the second pixel circuit PCa so as to be superimposed on the second pixel circuit PCa. The bottom metal layer BML can prevent or substantially prevent external light from reaching the second pixel circuit PCa.

[0100] Figure 3A and Figure 3B It can be included in Figure 1 A plan view of the display panel 10 in the display device 1.

[0101] Reference Figure 3AVarious elements of the display panel 10 are mounted on a substrate 100. The substrate 100 includes a display area DA and a peripheral area DPA surrounding the display area DA (e.g., around the periphery of the display area DA). The display area DA may include a main display area MDA for displaying a main image and a component area CA for displaying an auxiliary image and including a transmissive area TA. The auxiliary image may form a single image with the main image (e.g., a total image), or it may be an image independent of the main image.

[0102] Multiple first sub-pixels Pm are located at the main display area MDA (e.g., in or on the main display area MDA). Each of the multiple first sub-pixels Pm can be implemented as, for example, in an organic light-emitting diode (OLED) (see...). Figure 4 The display element is illustrated in the example below. A first pixel circuit PCm for driving a first sub-pixel Pm is located at the main display area MDA (e.g., in or on the main display area MDA) and may be superimposed on the first sub-pixel Pm. Each of the first sub-pixels Pm may emit, for example, red, green, blue, or white light. The main display area MDA is covered by an encapsulation component to protect it from external air and / or moisture.

[0103] As described above, the component region CA can be located on one side of the main display region MDA, or it can be located at the display region DA (e.g., in or on the display region DA) and surrounded by the main display region MDA (e.g., around the periphery of the component region CA). A plurality of second sub-pixels Pa are located at the component region CA (e.g., in or on the component region CA). Each of the second sub-pixels Pa can include a display element such as an organic light-emitting diode. The second pixel circuit PCa for driving the second sub-pixels Pa can be located in the region of the peripheral region DPA adjacent to the component region CA (e.g., in or on the region of the peripheral region DPA adjacent to the component region CA). For example, when the component region CA is located above the display region DA (e.g., in or on the upper side of the display region DA), the second pixel circuit PCa can be located in the portion of the peripheral region DPA adjacent to the upper side (e.g., in or on the portion of the peripheral region DPA adjacent to the upper side). The second pixel circuit PCa and the display element included in the second sub-pixel Pa can be connected to each other via a connecting line TWL that can extend in the y-direction. Each of the second sub-pixels Pa can emit, for example, red, green, blue, or white light. The component area CA is covered by an encapsulation component to protect it from external air and / or moisture.

[0104] The component region CA may include a transmission region TA. For example, the transmission region TA may surround a plurality of second sub-pixels Pa (e.g., around the periphery of the plurality of second sub-pixels Pa). As another example, the transmission region TA may be arranged as a grid having a plurality of second sub-pixels Pa.

[0105] Because the component area CA includes the transmission area TA, the resolution of the component area CA can be smaller than the resolution of the main display area MDA. For example, the resolution of the component area CA can be approximately 1 / 2, 3 / 8, 1 / 3, 1 / 4, 2 / 9, 1 / 8, 1 / 9, or 1 / 16 of the resolution of the main display area MDA. For instance, the main display area MDA can have a resolution of approximately 400 ppi, and the component area CA can have a resolution of approximately 200 ppi or approximately 100 ppi.

[0106] The first pixel circuit PCm and the second pixel circuit PCa used to drive the first sub-pixel Pm and the second sub-pixel Pa can be electrically connected to external circuitry at the peripheral region DPA (e.g., in or on the peripheral region DPA). The first scan drive circuits SDRV1 to SDRV4, the terminal portion PAD, the drive voltage supply line 11, and the common voltage supply line 13 can be located at the peripheral region DPA (e.g., in or on the peripheral region DPA).

[0107] The first scan driving circuit SDRV1 and the second scan driving circuit SDRV2 face each other with the main display area MDA between them, and can be located on the left and right sides of the substrate 100, respectively, at the peripheral area DPA (e.g., in or on the peripheral area DPA). The first scan driving circuit SDRV1 can apply a scan signal to each of the first pixel circuits PCm driving the first sub-pixel Pm via the main scan line SLm. The first scan driving circuit SDRV1 can apply an emission control signal to each of at least some of the first pixel circuits PCm via the main emission control line ELm. The second scan driving circuit SDRV2 can be positioned relative to the first scan driving circuit SDRV1 based on the main display area MDA, and can be positioned parallel or substantially parallel to the first scan driving circuit SDRV1. Some of the first pixel circuits PCm of the first sub-pixel Pm at the main display area MDA (e.g., in or on the main display area MDA) can be electrically connected to the first scan driving circuit SDRV1, and other first pixel circuits PCm can be electrically connected to the second scan driving circuit SDRV2.

[0108] The third scan drive circuit SDRV3 and the fourth scan drive circuit SDRV4 face each other with the second pixel circuit PCa between them, and can be located on the upper side of the substrate 100 at the left and right sides of the peripheral region DPA, respectively. The third scan drive circuit SDRV3 and the fourth scan drive circuit SDRV4 can apply scan signals to the second pixel circuit PCa, which is used to drive the second sub-pixel Pa at the component region CA (e.g., in or on the component region CA), via an auxiliary scan line SLa. The third scan drive circuit SDRV3 and the fourth scan drive circuit SDRV4 can apply emission control signals to the second pixel circuit PCa via an auxiliary emission control line ELa. Some of the second pixel circuits PCa in the second sub-pixel Pa can be electrically connected to the third scan drive circuit SDRV3, and other second pixel circuits PCa in the second pixel circuit PCa can be electrically connected to the fourth scan drive circuit SDRV4.

[0109] The terminal portion PAD may be located on one side of the substrate 100. The terminal portion PAD may not be covered by an insulating layer and may be exposed for connection to the display circuit board 30. The display driver 32 may be located on the display circuit board 30.

[0110] The display driver 32 can generate control signals that will be transmitted to the first scan drive circuits SDRV1 through the fourth scan drive circuits SDRV4. The display driver 32 can generate data signals that can be transmitted to the main pixel circuit PCm via the fan-out line FW and the main data line DLm connected to the fan-out line FW.

[0111] The display driver 32 can also supply drive voltage ELVDD to drive voltage supply line 11 (see...). Figure 4 And can supply common voltage ELVSS to common voltage supply line 13 (see...) Figure 4 The driving voltage ELVDD is applied via the driving voltage line PL connected to the driving voltage supply line 11 to the first pixel circuit PCm of the first sub-pixel Pm and the second pixel circuit PCa of the second sub-pixel Pa. The common voltage ELVSS can be connected to the common voltage supply line 13 to be applied to the counter electrode of the display element.

[0112] The drive voltage supply line 11 may extend in the x direction below the main display area MDA. The common voltage supply line 13 may have a ring shape with an open side to partially surround the main display area MDA (e.g., around the periphery of the main display area MDA).

[0113] Figure 3AA component region CA is shown, but multiple component regions CA can be configured. In this case, the multiple component regions CA are spaced apart from each other (e.g., separated). As an example, a first camera may correspond to one component region CA, and a second camera may correspond to another component region CA. As another example, a camera may correspond to one component region CA, and an infrared sensor may correspond to another component region CA. The shapes and / or sizes of the multiple component regions CA can differ from each other.

[0114] The component area CA can have a circular, elliptical, polygonal, or non-limited shape. In some embodiments, the component area CA can have an octagonal shape. The component area CA can have various suitable polygonal shapes, such as rectangular or hexagonal shapes. The component area CA can be surrounded by the main display area MDA (e.g., the main display area MDA can be around the periphery of the component area CA).

[0115] exist Figure 3A In the diagram, the second pixel circuit PCa is shown as being arranged adjacent to the outer side of the component region CA, but this disclosure is not limited thereto. Figure 3B As shown, the second pixel circuit PCa can be arranged adjacent to the outside of the main display area MDA. In some embodiments, the connection line TWL can be connected via an additional connection line TWL' (e.g., see...). Figure 3B The additional connection line TWL' is connected to the second pixel circuit PCa. In this case, the connection line TWL can be at the component region CA (e.g., in or on the component region CA), and the additional connection line TWL' can be at the peripheral region DPA (e.g., in or on the peripheral region DPA). The connection line TWL can include a transparent conductive material, and the additional connection line TWL' can include a highly conductive metal. In some embodiments, the additional connection line TWL' can be on the same layer as the connection line TWL. In another embodiment, the additional connection line TWL' can be on a different layer than the connection line TWL and can be connected to the connection line TWL via a contact hole.

[0116] When the second pixel circuit PCa and the display element included in the second sub-pixel Pa are connected to each other via the connecting line TWL and the additional connecting line TWL', the connecting line TWL and the additional connecting line TWL' can be referred to as the first connecting line and the second connecting line, respectively.

[0117] Figure 4 This is an equivalent circuit diagram of the pixel circuit PC according to an embodiment. Figure 4 This can be an equivalent circuit diagram of the first pixel circuit PCm and / or the second pixel circuit PCa. In the following text, for ease of description, the first pixel circuit PCm and / or the second pixel circuit PCa will be referred to as pixel circuit PC.

[0118] Reference Figure 4 The pixel circuit PC may include a first transistor (e.g., a driving thin-film transistor) T1, a second transistor (e.g., a switching thin-film transistor) T2, a third transistor (e.g., a compensation thin-film transistor) T3, a fourth transistor (e.g., a first initialization thin-film transistor) T4, a fifth transistor (e.g., a first emission control thin-film transistor) T5, a sixth transistor (e.g., a second emission control thin-film transistor) T6, a seventh transistor (e.g., a second initialization thin-film transistor) T7, and a capacitor Cst.

[0119] Figure 4 The illustration shows that each pixel circuit PC includes signal lines SL, SL-1, SL+1, EL, and DL, an initialization voltage line VL, and a drive voltage line PL; however, this disclosure is not limited thereto. For example, in another embodiment, at least one of the signal lines SL, SL-1, SL+1, EL, and DL and / or the initialization voltage line VL may be shared by neighboring pixel circuits (e.g., by adjacent pixel circuits).

[0120] The drain electrode of the first transistor T1 can be electrically connected to the organic light-emitting diode (OLED) as a display element via the sixth transistor T6. The first transistor T1 receives the data signal Dm according to the switching operation of the second transistor T2, and can supply driving current to the OLED.

[0121] The gate electrode of the second transistor T2 is connected to the scan line SL, and the source electrode of the second transistor T2 is connected to the data line DL. The drain electrode of the second transistor T2 is connected to the source electrode of the first transistor T1, and can be connected to the drive voltage line PL via the fifth transistor T5.

[0122] The second transistor T2 is turned on according to the scan signal Sn received through the scan line SL, and performs a switching operation to transmit the data signal Dm transmitted through the data line DL to the source electrode of the first transistor T1.

[0123] The gate electrode of the third transistor T3 can be connected to the scan line SL. The source electrode of the third transistor T3 is connected to the drain electrode of the first transistor T1, and can be connected to the pixel electrode of the organic light-emitting diode (OLED) via the sixth transistor T6. The drain electrode of the third transistor T3 can be connected to the first electrode of the capacitor Cst, the source electrode of the fourth transistor T4, and the gate electrode of the first transistor T1. The third transistor T3 is turned on according to the scan signal Sn transmitted through the scan line SL, and the gate electrode and drain electrode of the first transistor T1 are connected to each other to make the first transistor T1 diode connected, so that the threshold voltage of the first transistor T1 can be compensated.

[0124] The gate electrode of the fourth transistor T4 can be connected to the previous scan line SL-1. The drain electrode of the fourth transistor T4 can be connected to the initialization voltage line VL. The source electrode of the fourth transistor T4 can be connected to the first electrode of capacitor Cst, the drain electrode of the third transistor T3, and the gate electrode of the first transistor T1. The fourth transistor T4 is turned on according to the previous scan signal Sn-1 transmitted through the previous scan line SL-1 to transmit the initialization voltage Vint to the gate electrode of the first transistor T1 and to perform an initialization operation to initialize the voltage at the gate electrode of the first transistor T1.

[0125] The gate electrode of the fifth transistor T5 can be connected to the emitter control line EL. The source electrode of the fifth transistor T5 can be connected to the drive voltage line PL. The drain electrode of the fifth transistor T5 is connected to the source electrode of the first transistor T1 and the drain electrode of the second transistor T2.

[0126] The gate electrode of the sixth transistor T6 can be connected to the emitter control line EL. The source electrode of the sixth transistor T6 can be connected to the drain electrode of the first transistor T1 and the source electrode of the third transistor T3. The drain electrode of the sixth transistor T6 can be electrically connected to the pixel electrode of the organic light-emitting diode (OLED). The fifth transistor T5 and the sixth transistor T6 are concurrently (e.g., simultaneously) turned on according to the emitter control signal En transmitted through the emitter control line EL to transmit the drive voltage ELVDD to the OLED, thus driving current flows through the OLED.

[0127] The gate electrode of the seventh transistor T7 can be connected to the next scan line SL+1. The source electrode of the seventh transistor T7 can be connected to the pixel electrode of the organic light-emitting diode (OLED). The drain electrode of the seventh transistor T7 can be connected to the initialization voltage line VL. The seventh transistor T7 is turned on according to the next scan signal (e.g., the next scan signal) Sn+1 transmitted through the next scan line SL+1 to initialize the pixel electrode of the OLED.

[0128] Figure 4 An example is shown in which the fourth transistor T4 and the seventh transistor T7 are connected to the previous scan line SL-1 and the next scan line SL+1, respectively, but this disclosure is not limited thereto. For example, in another embodiment, both the fourth transistor T4 and the seventh transistor T7 may be connected to the previous scan line SL-1 to operate according to the previous scan signal Sn-1.

[0129] The second electrode of capacitor Cst can be connected to the drive voltage line PL. The first electrode of capacitor Cst can be connected to the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, and the source electrode of the fourth transistor T4.

[0130] The counter electrode (e.g., cathode) of an organic light-emitting diode (OLED) can receive a common voltage ELVSS. The OLED emits light after receiving a drive current from a first transistor T1.

[0131] Pixel circuit PC is not limited to Figure 4 The number of transistors and capacitors and the circuit design are shown, and the number and / or circuit design can be modified differently as needed or desired.

[0132] Figure 5 This is a plan view showing the area of ​​the display panel according to an embodiment. More specifically, Figure 5 The diagram shows the component area CA, the portion of the main display area MDA surrounding (e.g., adjacent to) the component area CA, and a portion of the peripheral area DPA.

[0133] Reference Figure 5 Multiple first subpixels Pm may be located at the main display area MDA (e.g., in or on the main display area MDA). As used in this specification, a subpixel is the smallest unit for realizing an image and represents a light-emitting area through which light is emitted by a display element. When an organic light-emitting diode is used as the display element, the light-emitting area may be defined by an opening in the pixel-defining layer. This will be described in more detail below. Each of the multiple first subpixels Pm may emit a suitable one of red, green, blue, and white light.

[0134] In some embodiments, the first sub-pixel Pm at the main display area MDA (e.g., in or on the main display area MDA) may include a first color sub-pixel Pr, a second color sub-pixel Pg, and a third color sub-pixel Pb. The first color sub-pixel Pr, the second color sub-pixel Pg, and the third color sub-pixel Pb may emit red, green, and blue light, respectively. The first sub-pixel Pm may be in an RGBG structure (e.g., ...). structure, (This is an officially registered trademark of Samsung Display Co., Ltd.)

[0135] For example, within the vertices of a virtual square whose center point is at the second color sub-pixel Pg is the center point of a square, the first color sub-pixel Pr can be located at the first and third vertices, and the third color sub-pixel Pb can be located at the second and fourth vertices. The size of the second color sub-pixel Pg can be smaller than the sizes of the first color sub-pixel Pr and the third color sub-pixel Pb.

[0136] This pixel arrangement structure is called an RGBG structure or an RGBG matrix structure (e.g., Structure or (Matrix structure). By applying rendering (where the color of a pixel is represented by sharing the colors of its neighboring pixels), high resolution can be achieved with a smaller number of pixels.

[0137] Figure 5 Multiple first sub-pixels Pm are shown in an RGBG matrix structure (e.g., The arrangement can be a matrix structure, but this disclosure is not limited thereto. For example, multiple first sub-pixels Pm can be arranged in various suitable shapes and structures (such as strip structures, mosaic arrangements, triangular arrangements, etc.).

[0138] At the main display area MDA (e.g., in or on the main display area MDA), a first pixel circuit PCm may be stacked with a first sub-pixel Pm, and the first pixel circuit PCm may be arranged in a matrix along the x and y directions. In this specification, the first pixel circuit PCm represents a unit of pixel circuit used to drive a first sub-pixel Pm.

[0139] Multiple second sub-pixels Pa may be located at component region CA (e.g., in or on component region CA). Each of the multiple second sub-pixels Pa may emit a suitable one of red, green, blue, and white light. The second sub-pixels Pa may include a first color sub-pixel Pr', a second color sub-pixel Pg', and a third color sub-pixel Pb'. The first color sub-pixel Pr', the second color sub-pixel Pg', and the third color sub-pixel Pb' may emit red, green, and blue light, respectively.

[0140] The number of second subpixels Pa per unit area at component region CA (e.g., in or on component region CA) can be less than the number of first subpixels Pm per unit area at main display region MDA (e.g., in or on main display region MDA). For example, for the same unit area size, the ratio of the number of second subpixels Pa to the number of first subpixels Pm can be 1:2, 1:4, 1:8, or 1:9. In other words, the resolution of component region CA can be 1 / 2, 1 / 4, 1 / 8, or 1 / 9 of the resolution of main display region MDA. Figure 5 An example is shown in which the component region CA has a resolution of approximately 1 / 8 that of the main display region MDA, but this disclosure is not limited thereto.

[0141] The second sub-pixel Pa at component region CA (e.g., within or on component region CA) can be arranged in various suitable shapes and structures. For example, the second sub-pixel Pa can be arranged in pixel group units, and within each pixel group, the second sub-pixel Pa can be arranged in various suitable structures (such as strip structures, mosaic arrangements, triangular arrangements, etc.). Here, the distance between the second sub-pixels Pa in the pixel group can be equal to or substantially equal to the distance between the first sub-pixels Pm.

[0142] As another example, such as Figure 5 As shown, the second sub-pixels Pa can be distributed at the component region CA (e.g., in or on the component region CA). In other words, the distance between the second sub-pixels Pa can be greater than the distance between the first sub-pixels Pm. Additionally, the area at the component region CA (e.g., in or on the component region CA) where no second sub-pixels Pa are disposed can be a transmissive region TA with high light transmittance.

[0143] The second pixel circuit PCa, used to control light emission from the second sub-pixel Pa, can be located in the peripheral region DPA (e.g., in or on the peripheral region DPA). Because the second pixel circuit PCa is not located in the component region CA (e.g., not in or on the component region CA), the component region CA can have a relatively large transmission region TA. Furthermore, the voltage lines and signal lines used to apply constant voltage and signals to the second pixel circuit PCa are not located in the component region CA (e.g., not in or on the component region CA), therefore, the second sub-pixel Pa can be arranged differently (e.g., freely) without considering the arrangement of the lines.

[0144] The second pixel circuit PCa can be distributed at the peripheral region DPA (e.g., in or on the peripheral region DPA) at the first pixel circuit region PCA1 and the second pixel circuit region PCA2, which are spaced apart from each other (e.g., separated). For example, the second pixel circuit PCa for driving the second sub-pixel Pa located to the left of the component region CA can be located at the first pixel circuit region PCA1 (e.g., in or on the first pixel circuit region PCA1). The second pixel circuit PCa for driving the second sub-pixel Pa located to the right of the component region CA can be located at the second pixel circuit region PCA2 (e.g., in or on the second pixel circuit region PCA2).

[0145] The first pixel circuit region PCA1 and the second pixel circuit region PCA2 may not correspond to the side of the component region CA, and may be adjacent to the outer side of the main display region MDA. In other words, the first pixel circuit region PCA1 and the second pixel circuit region PCA2 may be closer to the main display region MDA than to the component region. The first pixel circuit region PCA1 and the second pixel circuit region PCA2 may be spaced apart from each other in the x-direction by approximately the width of the component region CA. However, this disclosure is not limited thereto. For example, the first pixel circuit region PCA1 and the second pixel circuit region PCA2 may be adjacent to one or more sides of the component region CA.

[0146] The second pixel circuit PCa can be connected to the second sub-pixel Pa via a connecting line TWL and an additional connecting line TWL'. The connecting line TWL is located at the component region CA (e.g., in or on the component region CA) and may include a transparent conductive material. For example, the connecting line TWL may include a transparent conductive oxide (TCO). The connecting line TWL may include conductive oxides, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide, or aluminum zinc oxide (AZO).

[0147] The additional connection line TWL' can be located at the peripheral region DPA (e.g., in or on the peripheral region DPA) and connected to the second pixel circuit PCa. The additional connection line TWL' can include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and can have a single-layer or multi-layer structure. The additional connection line TWL' can be connected to the connection line TWL at the edge of the component region CA (e.g., in or on the edge of the component region CA) or near the edge of the component region CA (e.g., adjacent to the edge of the component region CA).

[0148] When the connecting line TWL and the additional connecting line TWL' are connected to the second sub-pixel Pa, this indicates that the connecting line TWL and the additional connecting line TWL' are electrically connected to the pixel electrode of the display element included in the second sub-pixel Pa.

[0149] Additional connection line TWL' and connection line TWL can be on the same layer or on different layers. When additional connection line TWL' and connection line TWL are on different layers, they can be connected to each other via contact holes.

[0150] The additional connecting wire TWL' can have a higher conductivity than the connecting wire TWL. Because the additional connecting wire TWL' is located at the peripheral region DPA (e.g., in or on the peripheral region DPA), it is not necessary to ensure its transmittance. Therefore, the additional connecting wire TWL' can comprise a material having a lower transmittance than the connecting wire TWL and a higher conductivity than the connecting wire TWL. This reduces the resistance of the connecting wire TWL.

[0151] The scan line SL may include a main scan line SLm connected to the first pixel circuit PCm and an auxiliary scan line SLa connected to the second pixel circuit PCa.

[0152] The main scan line SLm extends in the x-direction at the main display area MDA (e.g., in or on the main display area MDA) to connect to the main pixel circuits PCm that are in the same row as each other. The main scan line SLm may not be at the component area CA (e.g., not in or on the component area CA). In other words, the main scan line SLm may be disconnected at the component area CA. In this case, the main scan line SLm at the left side of the component area CA can be connected from the first scan drive circuit SDRV1 (e.g., see...). Figure 3A The main scan line SLm at the right side of component region CA can receive signals from the second scan drive circuit SDRV2 (e.g., see...). Figure 3A ) Receive signals.

[0153] The auxiliary scan line SLa extends in the x-direction at the peripheral region DPA (e.g., in or on the peripheral region DPA) and can be connected to the second pixel circuit PCa, which is in the same row as the others. The auxiliary scan line SLa can be disconnected. In this case, the auxiliary scan line SLa at the left side of the component region CA can be connected from the third scan drive circuit SDRV3 (e.g., see...). Figure 3A The auxiliary scan line SLa, located to the right of component region CA, can receive signals from the fourth scan drive circuit SDRV4 (e.g., see...). Figure 3A ) Receive signals.

[0154] The data line DL may include a main data line DLm connected to a first pixel circuit PCm and an auxiliary data line DLa connected to a second pixel circuit PCa. The main data line DLm extends in the y-direction and may be connected to the first pixel circuit PCm, which is in the same column as the main data line DLm. The auxiliary data line DLa extends in the y-direction and may be connected to the second pixel circuit PCa, which is in the same column as the main data line DLm.

[0155] The main data line DLm and the auxiliary data line DLa are connected to each other via the data connection line DWL. This is used to drive the first pixel circuit PCm and the second pixel circuit PCa of the first sub-pixel Pm and the second sub-pixel Pa, which are in the same column. They can be connected via the same fan-out line FW (e.g., see...). Figure 3A The data connection line (DWL) receives data signals. The DWL can bypass the component area (CA) (e.g., it can extend around the component area (CA)). The DWL can be superimposed on the first pixel circuit (PCm) at the main display area (MDA) (e.g., in or on the main display area (MDA)). Because the DWL is at the main display area (MDA) (e.g., in or on the main display area (MDA)), additional space for arranging the DWL can be eliminated or eliminated, thus reducing the dead zone area.

[0156] The data connection line DWL can be located on a different layer than the main data line DLm and the auxiliary data line DLa. Therefore, the data connection line DWL can be connected to the main data line DLm and the auxiliary data line DLa respectively via contact holes.

[0157] Figure 6A and Figure 6B This is a cross-sectional view showing some portions of the display panel 10 according to one or more embodiments. Figure 6A and Figure 6B This is a cross-sectional view showing some portions of the main display area MDA, component area CA, and peripheral area DPA in the display panel 10. Figure 7 It is based on Figure 6AA plan view of the second pixel electrode 121' and the opaque layer SHL in the embodiment. Figures 8A to 8C It shows the basis for formation Figure 6A Cross-sectional views of the second pixel electrode 121' and various processes of the opaque layer SHL in the embodiment.

[0158] Reference Figure 6A A first sub-pixel Pm is located at the main display area MDA (e.g., in or on the main display area MDA), and a second sub-pixel Pa is located at the component area CA (e.g., in or on the component area CA). The component area CA includes a transmissive area TA. A first pixel circuit PCm, including a thin-film transistor TFT and a capacitor Cst, and a first organic light-emitting diode (OLED) serving as a first display element connected to the first pixel circuit PCm, can be located at the main display area MDA (e.g., in or on the main display area MDA). A second organic light-emitting diode OLED' can serve as a second display element at the component area CA (e.g., in or on the component area CA). A second pixel circuit PCa, including a thin-film transistor TFT and a storage capacitor Cst, can be located at the peripheral area DPA (e.g., in or on the peripheral area DPA). Additionally, a connection line TWL for connecting the second pixel circuit PCa to the second organic light-emitting diode OLED' can be located at the component area CA (e.g., in or on the component area CA). Figure 6A The thin-film transistor (TFT) shown can be Figure 4 An example of one of the transistors shown.

[0159] In this embodiment, an organic light-emitting diode (OLED) is used as a display element; however, this disclosure is not limited thereto. In other embodiments, inorganic light-emitting diodes or quantum dot light-emitting diodes can be used as display elements.

[0160] The structure in which the components of the display panel 10 are stacked on top of each other will be described in more detail below. The display panel 10 may include a substrate 100, a buffer layer 111, a circuit layer PCL, and a display element layer EDL stacked in sequence.

[0161] The substrate 100 may include an insulating material, such as glass, quartz, and / or polymer resin. The substrate 100 may include a rigid substrate, or it may be a flexible substrate that is bendable, foldable, and / or rollable.

[0162] A buffer layer 111 is disposed on a substrate 100 to reduce or block the penetration of impurities, moisture, and / or external air from the lower portion of the substrate 100, and provides a flat or substantially flat surface on the substrate 100. The buffer layer 111 may comprise an inorganic material (such as an oxide or nitride material), an organic material, or an inorganic-organic composite material, and may have a single-layer or multi-layer structure comprising both inorganic and organic materials. A barrier layer for preventing or reducing the penetration of external air may be further disposed between the substrate 100 and the buffer layer 111. In some embodiments, the buffer layer 111 may comprise silicon oxide (SiO2) or silicon nitride (SiN). x ).

[0163] The circuit layer PCL is on the buffer layer 111 and may include a first pixel circuit PCm and a second pixel circuit PCa, a first gate insulating layer 112, a second gate insulating layer 113, an interlayer insulating layer 115, and a planarization layer 117. Both the first pixel circuit PCm and the second pixel circuit PCa may include a thin-film transistor (TFT) and a capacitor Cst.

[0164] Thin-film transistors (TFTs) can be mounted on buffer layer 111. Each TFT includes a semiconductor layer AL, a gate electrode GE, a source electrode SE, and a drain electrode DE. The TFT of the first pixel circuit PCm is connected to a first organic light-emitting diode (OLED) to drive the OLED. The TFT of the second pixel circuit PCa can be connected to a second organic light-emitting diode (OLED') to drive the OLED'. Because the TFT of the second pixel circuit PCa has the same or substantially the same (or similar) structure as the TFT of the first pixel circuit PCm, its redundant description is omitted.

[0165] The semiconductor layer AL is on the buffer layer 111 and may comprise polycrystalline silicon. In another embodiment, the semiconductor layer AL may comprise amorphous silicon. In another embodiment, the semiconductor layer AL may comprise an oxide selected from at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The semiconductor layer AL may comprise impurity-doped source and drain regions and a channel region between the source and drain regions.

[0166] The first gate insulating layer 112 may cover the semiconductor layer AL. The first gate insulating layer 112 may include an inorganic insulating material, such as silicon oxide (SiO2) or silicon nitride (SiN). x ), silicon oxynitride (SiO) x N yAluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and / or zinc oxide (ZnO) x For example, ZnO. x It can be ZnO and / or ZnO2. The first gate insulating layer 112 can have a single-layer structure or a multi-layer structure including one or more inorganic insulating materials.

[0167] The gate electrode GE is disposed on the first gate insulating layer 112 so as to be stacked with the channel region of the semiconductor layer AL. The gate electrode GE may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a single-layer structure or a multi-layer structure. As an example, the gate electrode GE may include a single layer containing Mo.

[0168] The second gate insulating layer 113 may cover the gate electrode GE. The second gate insulating layer 113 may include an inorganic insulating material, such as silicon oxide (SiO2) or silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y Aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and / or zinc oxide (ZnO) x For example, ZnO. x It can be ZnO and / or ZnO2. The second gate insulating layer 113 can have a single-layer structure or a multi-layer structure including one or more inorganic insulating materials.

[0169] The upper electrode CE2 of capacitor Cst can be on the second gate insulating layer 113. The upper electrode CE2 of capacitor Cst can be stacked with its lower gate electrode GE. When the second gate insulating layer 113 is between the gate electrode GE and the upper electrode CE, the gate electrode GE and the upper electrode CE stacked on top of each other can constitute capacitor Cst. The gate electrode GE can be the lower electrode CE1 of capacitor Cst.

[0170] The upper electrode CE2 can be a single-layer or multi-layer structure, including aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu).

[0171] Interlayer insulating layer 115 may cover the upper electrode CE2. Interlayer insulating layer 115 may include insulating materials, such as silicon oxide (SiO2) or silicon nitride (SiN). x ), silicon oxynitride (SiO) x N yAluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and / or zinc oxide (ZnO) x For example, ZnO. x It can be ZnO and / or ZnO2. The interlayer insulation layer 115 can have a single-layer structure or a multilayer structure including one or more inorganic insulating materials.

[0172] The source electrode SE and drain electrode DE can be on the interlayer insulating layer 115. The data line DL can be on the interlayer insulating layer 115. The data line DL can include a main data line DLm and an auxiliary data line DLa. The source electrode SE, drain electrode DE, and data line DL can all include conductive materials comprising molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and can have a single-layer structure or a multilayer structure comprising one or more of the above materials. For example, the source electrode SE, drain electrode DE, and data line DL can all have a multilayer structure comprising Ti / Al / Ti. The source electrode SE and drain electrode DE can be connected to the source region and drain region of the semiconductor layer AL respectively via contact holes formed in the inorganic insulating layer 115. In an embodiment, the source region and drain region of the semiconductor layer AL can be respectively included as part of the source electrode SE and part of the drain electrode DE of a thin-film transistor TFT.

[0173] The inorganic insulating layer IIL of the display panel 10 may include a hole corresponding to the component region CA. For example, when the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 115 are collectively referred to as the inorganic insulating layer IIL, the inorganic insulating layer IIL may include a first hole H1 corresponding to the component region CA. The first hole H1 may partially expose the upper surface of the buffer layer 111 or the upper surface of the substrate 100. The first hole H1 may be formed by stacking the openings of the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 115 on top of each other, wherein the openings correspond to the component region CA (e.g., at the component region CA). The openings may be formed independently by separate processes or concurrently (e.g., simultaneously) by the same process. When the openings are formed independently by separate processes, the inner surface of the first hole H1 may be non-smooth and may have steps.

[0174] The planarization layer 117 may cover the source electrode SE, the drain electrode DE, and the data line DL. The planarization layer 117 may have a flat or substantially flat upper surface, such that the first pixel electrode 121 and the second pixel electrode 121' disposed thereon may be flat or substantially flat.

[0175] The planarization layer 117 may comprise organic or inorganic materials and may have a single-layer or multi-layer structure. In an embodiment, the planarization layer 117 may comprise a first planarization layer 117a as a first organic insulating layer and a second planarization layer 117b as a second organic insulating layer. Therefore, conductive patterns (such as wiring) can be disposed between the first planarization layer 117a and the second planarization layer 117b, and high integration can be achieved.

[0176] Both the first planarization layer 117a and the second planarization layer 117b can be made of siloxane-based organic materials with high light transmittance and high flatness. Siloxane-based organic materials may include hexamethyldisiloxane, octamethyltrisiloxane, decamethyltetrasiloxane, dodecylpentasiloxane, and / or polydimethylsiloxane. As another example, both the first planarization layer 117a and the second planarization layer 117b may include general-purpose polymers (e.g., benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS)), phenolic polymer derivatives, acryloyl polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, or vinyl alcohol polymers. As another example, both the first planarization layer 117a and the second planarization layer 117b may include photosensitive polyimide (PSPI), polycarbonate (PC), etc.

[0177] In this embodiment, the organic insulating layer may be on the interconnect TWL, and the difference between the refractive index of the organic insulating layer and the refractive index of the interconnect TWL may be small (e.g., negligible). For example, the first planarization layer 117a may comprise a siloxane-based organic material, and the second planarization layer 117b may comprise a photosensitive polyimide.

[0178] The first planarization layer 117a may cover the first pixel circuit PCm and the second pixel circuit PCa at the main display area MDA and the peripheral area DPA (e.g., in or on the main display area MDA and the peripheral area DPA). The first planarization layer 117a may fill the first hole H1 of the inorganic insulating layer IIL and may be on the buffer layer 111 at the component area CA (e.g., in or on the component area CA). The second planarization layer 117b may be on the first planarization layer 117a and may have a flat or substantially flat upper surface, such that the first pixel electrode 121 and the second pixel electrode 121' may be formed as flat or substantially flat.

[0179] The connecting electrode CM, the connecting line TWL, and the data connecting line DWL can be on the first planarization layer 117a.

[0180] The connecting line TWL can be located at component region CA (e.g., in component region CA or on component region CA) and can be connected to the second organic light-emitting diode OLED'. The connecting line TWL can be connected to an additional connecting line TWL' located at peripheral region DPA (e.g., in peripheral region DPA or on peripheral region DPA) (e.g., see...). Figure 5 The additional connection line TWL' can be connected to the second pixel circuit PCa, for example, to the thin-film transistor TFT. In one embodiment, the additional connection line TWL' can be located on the same layer as the connection line TWL (e.g., on the first planarization layer 117a) and can comprise a different material than the connection line TWL. In this case, the connection line TWL can directly contact and connect to the additional connection line TWL'. In another embodiment, the additional connection line TWL' can be located on the same layer as the data line DL (e.g., on the interlayer insulating layer 115) and can comprise the same material as the data line DL. In this case, the connection line TWL can be connected to the additional connection line TWL' via a contact hole.

[0181] The trace wire (TWL) may include a transparent conductive material. For example, the trace wire TWL may include a transparent conductive oxide (TCO). The trace wire TWL may include conductive oxides, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide, or aluminum zinc oxide (AZO). The trace wire TWL may include a transparent conductive oxide with a transmittance of 50% or greater.

[0182] The additional connecting line TWL' can have a higher conductivity than the connecting line TWL. Because the additional connecting line TWL' is located at the peripheral region DPA (e.g., in or on the peripheral region DPA), it is not necessary to ensure its transmittance. Therefore, the additional connecting line TWL' can include a material with a lower transmittance than the connecting line TWL and a higher conductivity than the connecting line TWL. The additional connecting line TWL' can include conductive materials containing molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and can have a single-layer or multi-layer structure.

[0183] The first organic light-emitting diode (OLED) and the second organic light-emitting diode (OLED') are located on the second planarization layer 117b. The first pixel electrode 121 of the first OLED can be connected to the first pixel circuit PCm via a connection electrode CM on the first planarization layer 117a. The second pixel electrode 121' of the second OLED can be connected to the second pixel circuit PCa via a connection line TWL on the first planarization layer 117a. The first planarization layer 117a and the second planarization layer 117b can be sequentially stacked between the substrate 100 and the second pixel electrode 121' at the component region CA (e.g., in or on the component region CA).

[0184] The first pixel electrode 121 and the second pixel electrode 121' may include conductive oxides, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide, or aluminum zinc oxide (AZO). Both the first pixel electrode 121 and the second pixel electrode 121' may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof or a mixture thereof. For example, both the first pixel electrode 121 and the second pixel electrode 121' may have a structure comprising a film including ITO, IZO, ZnO, or In2O3 on and / or under the aforementioned reflective layer. In this case, both the first pixel electrode 121 and the second pixel electrode 121' may have a stacked structure comprising ITO / Ag / ITO.

[0185] The opaque layer SHL may be located at component region CA (e.g., in or on component region CA) on the second planarization layer 117b. The opaque layer SHL is an insulating pattern between the second pixel electrode 121' and the substrate 100 to correspond to the second pixel electrode 121', and may be a floating layer. The opaque layer SHL may correspond to at least one area of ​​the second pixel electrode 121' exposed by the pixel defining layer 119.

[0186] The opaque layer SHL may comprise an organic or inorganic material having an optical density (OD) of 1 or greater, and may have a single-layer or multi-layer structure. In embodiments, the opaque layer SHL may comprise an opaque insulating material, such as carbon, carbon black, diamond-like carbon, black acrylic, a black matrix, etc. In another embodiment, the opaque layer SHL may comprise a colored pigment, such as a black pigment or another colored pigment. For example, the opaque layer SHL may comprise a polyimide (PI) binder and pigments in which red, green, and blue are mixed together. As another example, the opaque layer SHL may comprise a cardo-based binder resin and a mixture of lactam black and blue pigments. In another embodiment, the opaque layer SHL may comprise molybdenum (Mo) / molybdenum oxide (MoO). x ).

[0187] The opaque SHL layer can have a light reflectance of 5.5% or less. The opaque SHL layer can have a thickness of about 0.2 micrometers (μm) or greater.

[0188] like Figure 7 As shown, the opaque layer SHL can have a size smaller than that of the second pixel electrode 121'. For example, the distance D between the edge of the opaque layer SHL and the edge of the second pixel electrode 121' can be less than or equal to 4 μm. For example, when the second pixel electrode 121' has a size of 12 μm × 12 μm, the opaque layer SHL can have a size of 8 μm × 8 μm or larger. The opaque layer SHL can have a shape corresponding to the shape of the second pixel electrode 121'.

[0189] An opaque layer SHL can be located between the second planarization layer 117b and the second pixel electrode 121'. The upper surface of the opaque layer SHL is in contact with the lower surface of the second pixel electrode 121', and the lower surface of the opaque layer SHL can be in contact with the upper surface of the second planarization layer 117b.

[0190] exist Figure 7 In the illustration, the second pixel electrode 121' and the opaque layer SHL are shown to have a square shape, but this disclosure is not limited thereto. For example, the second pixel electrode 121' and the opaque layer SHL may have a circular shape or a polygonal shape similar to a circle.

[0191] like Figure 8A As shown, the connecting line TWL can be between the substrate 100 and the second planarization layer 117b, or more specifically, between the first planarization layer 117a and the second planarization layer 117b.

[0192] The connecting line TWL can be on the first planarization layer 117a, and the second planarization layer 117b can be on the connecting line TWL. Contact holes CH that partially expose the connecting line TWL can be formed in the second planarization layer 117b. The second planarization layer 117b may also include contact holes that partially expose the connecting electrode CM at the main display area MDA (e.g., in or on the main display area MDA).

[0193] like Figure 8B As shown, the opaque layer SHL can be located on the second planarization layer 117b at a position corresponding to the second pixel electrode 121', and can have a pattern similar to that of the second pixel electrode 121'. The opaque layer SHL may not be superimposed on the contact hole CH of the second planarization layer 117b.

[0194] like Figure 8C As shown, the opaque layer SHL can be located between the second planarization layer 117b and the second pixel electrode 121'.

[0195] The second pixel electrode 121' is on the opaque layer SHL and can be connected to the connection line TWL via the contact hole CH. The first pixel electrode 121 is on the second planarization layer 117b at the main display area MDA (e.g., in or on the main display area MDA) and can be connected to the connection electrode CM via the contact hole.

[0196] Refer again Figure 6A The pixel defining layer 119 is on the planarization layer 117 and covers the edges of the first pixel electrode 121 and the second pixel electrode 121'. The pixel defining layer 119 may have a first opening OP1 and a second opening OP2 that respectively expose some portions of the first pixel electrode 121 and some portions of the second pixel electrode 121'. The first opening OP1 and the second opening OP2 may not be superimposed on the location of the contact hole connecting the first pixel electrode 121 to the connecting electrode CM and the location of the contact hole CH connecting the second pixel electrode 121' to the connecting line TWL. In other words, the pixel defining layer 119 may be superimposed on the contact hole connecting the first pixel electrode 121 to the connecting electrode CM and the contact hole CH connecting the second pixel electrode 121' to the connecting line TWL, and may cover the contact hole and the contact hole CH. The size and shape of the light-emitting areas of the first organic light-emitting diode OLED and the second organic light-emitting diode OLED' (or in other words, the first sub-pixel Pm and the second sub-pixel Pa) are defined by the first opening OP1 and the second opening OP2.

[0197] The pixel defining layer 119 can prevent or substantially prevent electric arcing at the edges of the first pixel electrode 121 and the second pixel electrode 121' by increasing the distance between the edges of the first pixel electrode 121 and the second pixel electrode 121' and the counter electrode 123 on the first pixel electrode 121 and the second pixel electrode 121'. The pixel defining layer 119 may comprise an organic insulating material (such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO) and / or phenolic resin, for example), and may be formed by spin coating.

[0198] The first emitting layer 122b and the second emitting layer 122b', corresponding to the first pixel electrode 121 and the second pixel electrode 121', are respectively located in the first opening OP1 and the second opening OP2 of the pixel defining layer 119. The first emitting layer 122b and the second emitting layer 122b' may include polymer materials or low molecular weight materials, and may emit red light, green light, blue light or white light.

[0199] Functional layer 122e may be on and / or below the first emission layer 122b and the second emission layer 122b'. Functional layer 122e may include the first functional layer 122a and / or the second functional layer 122c. The first functional layer 122a or the second functional layer 122c may be omitted as needed or desired.

[0200] The first functional layer 122a may be located below (e.g., beneath) the first emission layer 122b and the second emission layer 122b'. The first functional layer 122a may have a single-layer or multi-layer structure comprising organic materials. For example, the first functional layer 122a may include a hole transport layer (HTL) with a single-layer structure. As another example, the first functional layer 122a may include a hole injection layer (HIL) and an HTL. The first functional layer 122a may be integrally configured to correspond to the first organic light-emitting diode (OLED) and the second organic light-emitting diode (OLED') at the main display area MDA and the component area CA (e.g., within or on the main display area MDA and the component area CA).

[0201] The second functional layer 122c may be located on the first emission layer 122b and the second emission layer 122b'. The second functional layer 122c may have a single-layer structure or a multi-layer structure including organic materials. The second functional layer 122c may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The second functional layer 122c may be integrally configured to correspond to the first organic light-emitting diode (OLED) and the second organic light-emitting diode (OLED') at the main display area MDA and the component area CA (e.g., in or on the main display area MDA and the component area CA).

[0202] The counter electrode 123 is located on the second functional layer 122c. The counter electrode 123 may include a conductive material with low work function. For example, the counter electrode 123 may include a transparent or translucent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. As another example, the counter electrode 123 may also include a layer comprising ITO, IZO, ZnO, or In2O3 on a transparent or translucent layer comprising one or more of the above materials. The counter electrode 123 may be integrally configured to correspond to the first organic light-emitting diode (OLED) and the second organic light-emitting diode (OLED') at the main display area MDA and the component area CA (e.g., in or on the main display area MDA and the component area CA).

[0203] The layer from the first pixel electrode 121 to the counter electrode 123 at the main display area MDA (e.g., in or on the main display area MDA) can constitute a first organic light-emitting diode (OLED). The layer from the second pixel electrode 121' to the counter electrode 123 at the component area CA (e.g., in or on the component area CA) can constitute a second organic light-emitting diode (OLED').

[0204] An upper layer 150, comprising organic material, may be placed on the counter electrode 123. The upper layer 150 may be configured to protect the counter electrode 123 and improve light extraction efficiency. The upper layer 150 may comprise an organic material having a higher refractive index than the counter electrode 123. As another example, the upper layer 150 may comprise stacked layers having different refractive indices from each other. For example, the upper layer 150 may comprise a high refractive index layer / a low refractive index layer / a high refractive index layer. The high refractive index layer may have a refractive index of 1.7 or greater, and the low refractive index layer may have a refractive index of 1.3 or less.

[0205] The upper layer 150 may additionally include LiF. As another example, the upper layer 150 may additionally include inorganic insulating materials, such as silicon oxide (SiO2) and / or silicon nitride (SiN). x For example, ).

[0206] Connector TWL Figure 6A It is shown as being on the first planarization layer 117a, but in another embodiment, such as Figure 6B As shown, the connecting line TWL can be in the first hole H1. For example, the connecting line TWL can be on the buffer layer 111 at component region CA (e.g., in component region CA or on component region CA).

[0207] Reference Figure 6BThe connecting line TWL can be between the substrate 100 and the first planarization layer 117a, or between the buffer layer 111 and the first planarization layer 117a. The connecting line TWL can be connected to the connecting electrode CM' on the first planarization layer 117a via a contact hole, and can be connected to the second pixel electrode 121' via the connecting electrode CM'. The connecting line TWL can be connected to an additional connecting line TWL' at the peripheral region DPA (e.g., in or on the peripheral region DPA) via a contact hole, and can be connected to the second pixel circuit PCa via the additional connecting line TWL'. In this case, the first planarization layer 117a above the connecting line TWL (e.g., directly on the connecting line TWL) may include photosensitive polyimide, and the second planarization layer 117b may include a siloxane-based organic material.

[0208] Figure 9 This is a partial cross-sectional view of the display panel 10 according to an embodiment. Figure 10 It is based on Figure 9 A plan view of the second pixel electrode 121' and the opaque layer SHL in the embodiment. Figures 11A to 11C It shows the basis for formation Figure 9 Cross-sectional views of the second pixel electrode 121' and the opaque layer SHL in various processes of an embodiment. Figure 9 In, with Figure 6A The same reference numerals indicate the same or substantially the same elements, components and layers, so their redundant descriptions need not be repeated.

[0209] Reference Figure 9 The opaque layer SHL can be located at component region CA (e.g., in component region CA or on component region CA) on the second planarization layer 117b. For example... Figure 10 As shown, the opaque layer SHL can have a size larger than the size of the second pixel electrode 121'.

[0210] like Figure 11A As shown, the connecting line TWL is on the first planarization layer 117a, and the second planarization layer 117b is on the connecting line TWL. An organic insulating layer SHL' comprising an opaque organic material may be on the second planarization layer 117b.

[0211] like Figure 11BAs shown, the contact hole CH' that partially exposes the connecting line TWL can be in the second planarization layer 117b and the organic insulating layer SHL' (e.g., it can penetrate the second planarization layer 117b and the organic insulating layer SHL'). The second planarization layer 117b may also include a contact hole that partially exposes the connecting electrode CM at the main display area MDA (e.g., in or on the main display area MDA). The contact hole CH1 in the second planarization layer 117b and the contact hole CH2 in the organic insulating layer SHL' can be stacked on top of each other. When the contact hole CH2 is formed in the organic insulating layer SHL', the organic insulating layer SHL' can be patterned to form an opaque layer SHL. The opaque layer SHL can be formed in a pattern having a shape similar to that of the second pixel electrode 121' at the position corresponding to the second pixel electrode 121'.

[0212] like Figure 11C As shown, the second pixel electrode 121' can be on the opaque layer SHL and can be connected to the connection line TWL via the contact hole CH'. The first pixel electrode 121 is on the second planarization layer 117b and can be connected to the connection electrode CM via the contact hole at the main display area MDA (e.g., in or on the main display area MDA).

[0213] exist Figure 9 In the embodiment, the connection line TWL is shown on the first planarization layer 117a, but as Figure 6B As shown, the connecting line TWL can be in the first hole H1 (or in other words, on the buffer layer 111) and can be connected to the connecting electrode CM' on the first planarization layer 117a.

[0214] Figure 12 and Figure 14 This is a cross-sectional view showing some portions of the display panel 10 according to one or more embodiments. Figures 13A to 13D It shows the basis for formation Figure 12 Cross-sectional views of the second pixel electrode 121' and the opaque layer SHL in various processes of an embodiment. Figure 12 and Figure 14 In the same diagram, the same symbols indicate the same as... Figure 6A The components, components, and layers are the same or substantially the same, therefore, their redundant descriptions need not be repeated.

[0215] Reference Figure 12The opaque layer SHL can be located at component region CA (e.g., in or on component region CA) on the second planarization layer 117b. In other words, the opaque layer SHL can be located between the second planarization layer 117b and the second pixel electrode 121'. The second planarization layer 117b includes a recess REC1 that accommodates the opaque layer SHL at a location corresponding to the second pixel electrode 121', and the opaque layer SHL can be located in the recess REC1 of the second planarization layer 117b. The second pixel electrode 121' is on the opaque layer SHL and can be connected to the connection line TWL on the first planarization layer 117a via a contact hole CH.

[0216] like Figure 13A As shown, the connecting line TWL can be between the first planarization layer 117a and the second planarization layer 117b.

[0217] The connecting line TWL can be on the first planarization layer 117a, and the second planarization layer 117b can be on the connecting line TWL. The second planarization layer 117b can include a recess REC1 in the position corresponding to the second pixel electrode 121'. Since the recess REC1 is formed in the second planarization layer 117b by using a halftone mask, the second planarization layer 117b can include regions with different thicknesses from each other, or in other words, a region with a first thickness TH1 and a region with a second thickness TH2 that is smaller than the first thickness TH1. The recess REC1 can have a shape similar to the shape of the second pixel electrode 121' in the position corresponding to the second pixel electrode 121'.

[0218] like Figure 13B As shown, the contact hole CH that partially exposes the connection line TWL can be in the second planarization layer 117b. The second planarization layer 117b may also include a contact hole that partially exposes the connection electrode CM at the main display area MDA (e.g., in or on the main display area MDA).

[0219] like Figure 13C As shown, a light-shielding organic material is filled into the recess REC1 of the second planarization layer 117b to form an opaque layer SHL. The upper surface of the opaque layer SHL and the upper surface of the region with a first thickness TH1 in the second planarization layer 117b can overlap each other (e.g., they can be coplanar).

[0220] like Figure 13DAs shown, the second pixel electrode 121' is on the opaque layer SHL and the second planarization layer 117b, and can be connected to the connection line TWL via the contact hole CH. The first pixel electrode 121 is on the second planarization layer 117b, and can be connected to the connection electrode CM via the contact hole at the main display area MDA (e.g., in or on the main display area MDA).

[0221] exist Figure 12 In the embodiment shown, the size of the opaque layer SHL and the size of the recess REC1 in the second planarization layer 117b can be smaller than the size of the second pixel electrode 121'. However, in another embodiment, such as Figure 14 As shown, the size of the opaque layer SHL and the size of the recess REC1 in the second planarization layer 117b can be greater than or equal to the size of the second pixel electrode 121'. In this case, the second pixel electrode 121' can be connected to the connection line TWL via the contact hole CH1 in the second planarization layer 117b and the contact hole CH2 in the opaque layer SHL. The contact hole CH2 in the opaque layer SHL can be stacked with the contact hole CH1 in the second planarization layer 117b.

[0222] exist Figure 12 and Figure 14 In the embodiment shown, the interconnect TWL is on the first planarization layer 117a, but as Figure 6B As shown, the connecting line TWL can be in the first hole H1 (or in other words, between the buffer layer 111 and the first planarization layer 117a) and can be connected to the connecting electrode CM' on the first planarization layer 117a.

[0223] Figure 15 and Figure 17 This is a cross-sectional view showing some portions of the display panel 10 according to one or more embodiments. Figures 16A to 16D It shows the basis for formation Figure 15 Cross-sectional views of the second pixel electrode 121' and the opaque layer SHL in various processes of an embodiment. Figure 15 and Figure 17 In the same diagram, the same symbols indicate the same as... Figure 6A The components, elements, and layers are the same, so their redundant descriptions need not be repeated.

[0224] Reference Figure 15An opaque layer SHL may be located at component region CA (e.g., in or on component region CA) on the first planarization layer 117a. The opaque layer SHL may be located between the first planarization layer 117a and the second planarization layer 117b. The first planarization layer 117a may include a recess REC2 for accommodating the opaque layer SHL, and the opaque layer SHL may be included in the recess REC2 of the first planarization layer 117a. A connecting line TWL may be located on the opaque layer SHL, and the second planarization layer 117b may be located on the connecting line TWL. A portion of the connecting line TWL may be directly on the opaque layer SHL, and the remaining portion of the connecting line TWL may be directly on the first planarization layer 117a. The second planarization layer 117b may cover the connecting line TWL, the opaque layer SHL, and the first planarization layer 117a. A second pixel electrode 121' may be located on the second planarization layer 117b and may be connected to the connecting line TWL via a contact hole CH. Figure 15 In one embodiment, the opaque layer SHL can block or reduce light reflection from the second pixel electrode 121' and light reflection from the connecting line TWL.

[0225] like Figure 16A As shown, the first planarization layer 117a may be on the buffer layer 111 and may include a recess REC2 at a position corresponding to the second pixel electrode 121'. Since the recess REC2 is formed in the first planarization layer 117a using a halftone mask, the first planarization layer 117a may include regions with different thicknesses than each other, or in other words, a region with a third thickness TH3 and a region with a fourth thickness TH4 that is smaller than the third thickness TH3. The recess REC2 may have a shape similar to that of the second pixel electrode 121' at the position corresponding to the second pixel electrode 121'.

[0226] like Figure 16B As shown, a light-shielding organic material is filled into the recess REC2 of the first planarization layer 117a to form an opaque layer SHL. The upper surface of the opaque layer SHL and the upper surface of the region with a third thickness TH3 in the first planarization layer 117a can overlap each other (e.g., they can be coplanar).

[0227] like Figure 16C As shown, the connecting line TWL is on the opaque layer SHL, and the second planarization layer 117b is on the connecting line TWL. A contact hole CH that partially exposes the connecting line TWL can be formed in the second planarization layer 117b. The second planarization layer 117b may also include a contact hole that partially exposes the connecting electrode CM at the main display area MDA (e.g., in or on the main display area MDA).

[0228] like Figure 16DAs shown, the second pixel electrode 121' is on the second planarization layer 117b and can be connected to the connection line TWL via the contact hole CH. The first pixel electrode 121 is on the second planarization layer 117b and can be connected to the connection electrode CM via the contact hole at the main display area MDA (e.g., in or on the main display area MDA).

[0229] In another embodiment, such as Figure 17 As shown, a second hole H2, instead of a recess REC2, can be formed in the first planarization layer 117a at a position corresponding to the second pixel electrode 121', penetrating the first planarization layer 117a. Additionally, an opaque layer SHL can be formed in the second hole H2 to fill it. The second hole H2 can be obtained (e.g., it can be formed) in a process that forms contact holes in the first planarization layer 117a at the main display area MDA and the peripheral area DPA (e.g., in or on the main display area MDA and the peripheral area DPA). A portion of the connection line TWL can be directly on the opaque layer SHL, and the remainder of the connection line TWL can be directly on the first planarization layer 117a. A second planarization layer 117b can cover the connection line TWL, the opaque layer SHL, and the first planarization layer 117a.

[0230] exist Figure 15 and Figure 17 In the embodiments described, the connecting line TWL is shown on the opaque layer SHL, but as Figure 6B As shown, the connecting line TWL can be in the first hole H1 (or in other words, on the buffer layer 111) and can be connected to the connecting electrode CM' on the first planarization layer 117a.

[0231] Figure 18 and Figure 20 This is a cross-sectional view showing some portions of the display panel 10 according to one or more embodiments. Figures 19A to 19C It shows the basis for formation Figure 18 Cross-sectional views of the second pixel electrode 121' and the opaque layer SHL in various processes of an embodiment. Figure 18 and Figure 20 In the same diagram, the same symbols indicate the same as... Figure 6A The components, elements, and layers are the same or substantially the same, therefore, their redundant descriptions need not be repeated.

[0232] Reference Figure 18The connecting line TWL and the opaque layer SHL can be located at the component region CA (e.g., in or on the component region CA) on the first planarization layer 117a. The opaque layer SHL can be located at a position corresponding to the second pixel electrode 121'. The second planarization layer 117b can be located on the connecting line TWL and the opaque layer SHL.

[0233] The opaque layer SHL can at least partially cover the connecting line TWL. In other words, a portion of the connecting line TWL can be between the first planarization layer 117a and the opaque layer SHL, and another portion of the connecting line TWL can be between the first planarization layer 117a and the second planarization layer 117b.

[0234] The second pixel electrode 121' can be on the second planarization layer 117b and can be connected to the connection line TWL via the contact hole CH.

[0235] like Figure 19A As shown, a first planarization layer 117a may be on a buffer layer 111, and a connection line TWL may be on the first planarization layer 117a. An opaque layer SHL may be on the first planarization layer 117a to correspond to the second pixel electrode 121'. A portion of the opaque layer SHL may partially cover the portion of the connection line TWL that overlaps with the second pixel electrode 121'. For example, the opaque layer SHL may partially cover the portion of the connection line TWL except for the area of ​​the connection line TWL that will be exposed by the contact hole CH subsequently formed in the second planarization layer 117b.

[0236] like Figure 19B As shown, the second planarization layer 117b can simultaneously cover the connection line TWL and the opaque layer SHL on the first planarization layer 117a. Contact holes CH that partially expose the connection line TWL can be formed in the second planarization layer 117b. The second planarization layer 117b may also include contact holes that partially expose the connection electrode CM at the main display area MDA (e.g., in or on the main display area MDA).

[0237] like Figure 19C As shown, the second pixel electrode 121' is on the second planarization layer 117b and can be connected to the connection line TWL via the contact hole CH. The first pixel electrode 121 is also on the second planarization layer 117b and can be connected to the connection electrode CM via the contact hole at the main display area MDA (e.g., where or above).

[0238] In reference Figure 18 In the illustrated embodiment, the size of the opaque layer SHL is smaller than (e.g., smaller than) the size of the second pixel electrode 121', but as Figure 20As shown, the size of the opaque layer SHL can be equal to or larger than the size of the second pixel electrode 121'. In this case, the opaque layer SHL can cover the area of ​​the connection line TWL that overlaps with the second pixel electrode 121'. The second pixel electrode 121' can be connected to the connection line TWL via contact hole CH1 in the second planarization layer 117b and contact hole CH2 in the opaque layer SHL. Contact hole CH1 in the second planarization layer 117b can overlap with contact hole CH2 in the opaque layer SHL.

[0239] exist Figure 18 and Figure 20 In the embodiment, the connection line TWL is shown on the first planarization layer 117a, but as Figure 6B As shown, the connecting line TWL can be in the first hole H1 (or in other words, on the buffer layer 111) and can be connected to the connecting electrode CM' on the first planarization layer 117a. In this case, the opaque layer SHL can partially or completely cover the area of ​​the connecting electrode CM' that overlaps with the second pixel electrode 121'.

[0240] Figure 21 and Figure 22 This is a cross-sectional view showing some portions of a display panel 10 according to one or more embodiments. Figure 21 and Figure 22 In the same diagram, the same symbols indicate the same as... Figure 6A The components, elements, and layers are the same or substantially the same, therefore, their redundant descriptions need not be repeated.

[0241] exist Figure 21 and Figure 22 In the illustrated embodiment, the first planarization layer 117a includes a second hole H2 corresponding to the component region CA, with the connecting line TWL and the opaque layer SHL residing in the second hole H2. Here, the first planarization layer 117a may comprise the same material as the opaque layer SHL.

[0242] At component region CA (e.g., in or on component region CA), the connection line TWL is on buffer layer 111, and the opaque layer SHL can be located between buffer layer 111 and second planarization layer 117b at a position corresponding to the second pixel electrode 121'. After the connection line TWL is formed on buffer layer 111, the opaque layer SHL can be formed on the connection line TWL to partially or completely cover the connection line TWL. The second planarization layer 117b fills the second hole H2 of the first planarization layer 117a and can cover the exposed buffer layer 111, connection line TWL, and opaque layer SHL. In other words, a portion of the connection line TWL can be between buffer layer 111 and second planarization layer 117b, and another portion of the connection line TWL can be between buffer layer 111 and opaque layer SHL.

[0243] The second planarization layer 117b may be located at the main display area MDA and the peripheral area DPA (e.g., in the main display area MDA and the peripheral area DPA or on the main display area MDA and the peripheral area DPA) on the first planarization layer 117a.

[0244] When the second aperture H2 is formed in the first planarization layer 117a above the substrate 100, an opaque layer SHL can be obtained (e.g., an opaque layer SHL can be formed) by patterning the remaining portion of the first planarization layer 117a in the second aperture H2 at the component region CA (e.g., in or on the component region CA). According to this embodiment, the process of forming the opaque layer SHL, which can be a separate process from the process of forming the planarization layer 117, can be omitted.

[0245] The connecting line TWL can be connected to the second pixel electrode 121' via the contact hole CH in the second planarization layer 117b. The connecting line TWL is connected to the additional connecting line TWL' via the contact hole, and can also be connected to the second pixel circuit PCa via the additional connecting line TWL'. The opaque layer SHL can be as follows... Figure 21 The area shown partially covers the connection line TWL overlapping with the second pixel electrode 121', or it can be as follows: Figure 22 The area shown completely covers the connecting line TWL and overlaps with the second pixel electrode 121'.

[0246] According to one or more embodiments of this disclosure, the opaque layer SHL is located at component region CA (e.g., in or on component region CA) between the second pixel electrode 121' (or in other words, the reflective layer) and the substrate 100, thus eliminating the presence of a reflective layer between the opaque layer SHL and the substrate 100. A connecting line TWL comprising a transparent conductive material having a suitable level (e.g., a predetermined or specific level) or lower of reflectivity and a transparent organic / inorganic layer may (e.g., may be present only) be present between the opaque layer SHL and the substrate 100. Therefore, light reflection caused by the reflective layer at component region CA (e.g., in or on component region CA) can be reduced.

[0247] As described above, in the display panel and display device according to one or more embodiments of the present disclosure, the pixel circuitry is not located at the component region (e.g., not located in the component region or not located on the component region), thus ensuring a relatively wide transmission area and thereby improving its transmittance. However, the present disclosure is not limited to these aspects and features.

[0248] Although some exemplary embodiments have been described, it will be readily understood by those skilled in the art that various modifications may be made to the exemplary embodiments without departing from the spirit and scope of this disclosure. It will be understood that, unless otherwise specified, the description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Therefore, it will be apparent to those skilled in the art that, unless otherwise specifically indicated, features, characteristics, and / or elements described in connection with specific embodiments may be used independently or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, it will be understood that the foregoing is illustrative of various exemplary embodiments and should not be construed as limiting to the specific exemplary embodiments disclosed herein, and various modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the spirit and scope of this disclosure as defined in the appended claims and their equivalents.

Claims

1. A display panel, the display panel comprising: The region consists of a first region, a second region, and a third region, wherein the resolution of the second region is smaller than the resolution of the first region. Base; A first pixel electrode is located on the substrate at the first region; A first pixel circuit is connected to a first pixel electrode at the first region on the substrate. A second pixel electrode is located on the substrate at the second region; A second pixel circuit is located on the substrate at the third region, and the second pixel circuit is connected to the second pixel electrode. as well as An opaque layer, located in the second region between the substrate and the second pixel electrode, the opaque layer comprising an insulating pattern superimposed on the second pixel electrode.

2. The display panel according to claim 1, further comprising: A first organic insulating layer is located in the second region between the substrate and the second pixel electrode; as well as A second organic insulating layer is disposed on the first organic insulating layer.

3. The display panel of claim 2, wherein, The opaque layer is located between the second organic insulating layer and the second pixel electrode.

4. The display panel according to claim 3, wherein, The upper surface of the opaque layer contacts the second pixel electrode, and The lower surface of the opaque layer contacts the second organic insulating layer.

5. The display panel according to claim 3, wherein, The second organic insulating layer includes a recess corresponding to the second pixel electrode, and The opaque layer is located in the recess of the second organic insulating layer.

6. The display panel according to claim 2, wherein, The opaque layer is located between the first organic insulating layer and the second organic insulating layer.

7. The display panel according to claim 6, wherein, The first organic insulating layer includes a recess corresponding to the second pixel electrode, and The opaque layer is located in the recess of the first organic insulating layer.

8. The display panel according to claim 2, wherein, The hole at the position corresponding to the second pixel electrode penetrates the first organic insulating layer, and The opaque layer is located within the pores of the first organic insulating layer.

9. The display panel according to claim 2, further comprising: A first connecting line is located in the second region between the first organic insulating layer and the second organic insulating layer, and the first connecting line connects the second pixel electrode to the second pixel circuit.

10. The display panel according to claim 9, further comprising: A second connecting line, located in the third region, connects the first connecting line to the second pixel circuit.

11. The display panel according to claim 2, further comprising: A first connecting line is located in the second region between the substrate and the first organic insulating layer, the first connecting line connecting the second pixel electrode to the second pixel circuit.

12. The display panel according to claim 11, further comprising: A second connecting line, located in the third region, connects the first connecting line to the second pixel circuit.

13. The display panel according to claim 1, further comprising: A first organic insulating layer covers the first pixel circuit in the first region and the second pixel circuit in the third region, the first organic insulating layer including holes corresponding to the second region; as well as A second organic insulating layer is located on the first organic insulating layer in the first region and the third region, and the second organic insulating layer fills the pores of the first organic insulating layer in the second region between the substrate and the second pixel electrode.

14. The display panel according to claim 13, wherein, The opaque layer is located in the second region between the substrate and the second organic insulating layer.

15. The display panel according to claim 14, further comprising: A first connecting line is located in the second region between the substrate and the second organic insulating layer, the first connecting line connecting the second pixel electrode to the second pixel circuit. The opaque layer at least partially covers the first connecting line.

16. The display panel according to claim 15, further comprising: A second connecting line, located in the third region, connects the first connecting line to the second pixel circuit.

17. A display device, the display device comprising: The display panel includes: Region 1, Region 2, and Region 3; Base; A first display element is located in the first region; The second display element, in the second region, includes a second pixel electrode on the substrate in the second region; A second pixel circuit is located on the substrate at the third region, and the second pixel circuit is connected to the second pixel electrode. An organic insulating layer is located in the second region between the substrate and the second pixel electrode; and An opaque layer, located in the second region between the substrate and the second pixel electrode, the opaque layer comprising an insulating pattern superimposed on the second pixel electrode; and The component is located below the display panel and corresponds to the second area.

18. The display device according to claim 17, wherein, The organic insulating layer comprises: A first organic insulating layer is disposed between the substrate and the second pixel electrode; and A second organic insulating layer is disposed on the first organic insulating layer.

19. The display device according to claim 18, wherein, The opaque layer is located between the second organic insulating layer and the second pixel electrode.

20. The display device according to claim 18, wherein, The second organic insulating layer includes a recess corresponding to the second pixel electrode, and The opaque layer is located in the recess of the second organic insulating layer.

21. The display device according to claim 18, wherein, The opaque layer is located between the first organic insulating layer and the second organic insulating layer.

22. The display device according to claim 18, wherein, The first organic insulating layer includes a recess corresponding to the second pixel electrode, and The opaque layer is located in the recess of the first organic insulating layer.

23. The display device according to claim 18, wherein, The first organic insulating layer includes a hole that penetrates the first organic insulating layer and corresponds to the position of the second pixel electrode, and The opaque layer is located within the pores of the first organic insulating layer.

24. The display device according to claim 17, wherein, The organic insulating layer comprises: A first organic insulating layer covers the second pixel circuit at the third region, the first organic insulating layer including holes corresponding to the second region; and A second organic insulating layer is located on top of the first organic insulating layer in the third region, and the second organic insulating layer fills the pores of the first organic insulating layer in the second region between the substrate and the second pixel electrode. The opaque layer is located between the substrate and the second organic insulating layer.

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