Chalcogenide compound, semiconductor device, and semiconductor device

Abstract

Provided are a chalcogenide compound, a semiconductor device, and a semiconductor apparatus. The chalcogenide compound includes five or more elements and can have stable switching characteristics and a low off current value (leakage current value). The chalcogenide compound includes selenium (Se) and tellurium (Te); a first element including at least one of indium (In), aluminum (Al), strontium (Sr), and calcium (Ca); and a second element including germanium (Ge) and / or tin (Sn), and can further include at least one of arsenic (As), antimony (Sb), and bismuth (Bi).

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0149586 filed with the Korean Intellectual Property Office on November 10, 2020, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to chalcogenide compounds and / or semiconductor devices including said chalcogenide compounds. Background Technology

[0004] With the trend towards lighter, thinner, simpler, and smaller electronic products, the demand for highly integrated semiconductor devices is increasing. Therefore, various types of semiconductor devices have been proposed, such as those including variable resistance layers and selectable device layers. Summary of the Invention

[0005] Chalcogenide compounds with ovonic threshold switching properties are provided.

[0006] We provide switching devices, semiconductor devices, and / or semiconductor apparatuses with low turn-off current and high reliability (durability).

[0007] Other aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments presented in this disclosure.

[0008] According to an embodiment, the semiconductor device may include a selectable device layer comprising a chalcogenide compound. The chalcogenide compound may include a first element, a second element, a third element, selenium (Se), and tellurium (Te). The first element may include at least one of indium (In), aluminum (Al), strontium (Sr), and calcium (Ca). The second element may include germanium (Ge) and / or tin (Sn). The third element may include at least one of arsenic (As), antimony (Sb), and bismuth (Bi).

[0009] In some embodiments, the elemental ratio of tellurium (Te) to selenium (Se) in the chalcogenide compound may be greater than 0.0 but less than or equal to 0.5. The elemental ratio of tellurium (Te) to selenium (Se) in the chalcogenide compound may be greater than 0.0 but less than or equal to 0.2. The elemental ratio of tellurium (Te) to selenium (Se) in the chalcogenide compound may range from 0.07 to 0.20. These elemental ratios are expressed atomically.

[0010] In some embodiments, tellurium (Te) is included in the chalcogen compound in an amount of 0.5 atomic % to 20.0 atomic % based on the total amount of elements. Tellurium (Te) may be included in an amount of 2.0 atomic % to 15.0 atomic % based on the total amount of elements.

[0011] In some embodiments, tellurium (Te) is included in the chalcogen compound in an amount of 3.0 atomic % to 9.0 atomic % based on the total amount of elements, and the elemental ratio of Te / Se may be greater than or equal to about 0.06 and less than or equal to about 0.19.

[0012] In some embodiments, selenium (Se) is included in the chalcogen compound in an amount greater than 0.0 atomic % and equal to or less than 70.0 atomic % based on the total amount of elements. Selenium (Se) may be included in an amount of 20.0 atomic % to 70.0 atomic % based on the total amount of elements.

[0013] In some embodiments, based on the total amount of elements, the chalcogen compound may include the first element in an amount of 0.1 atomic % to 10.0 atomic %. Based on the total amount of elements, the chalcogen compound may include the second element in an amount of 5.0 atomic % to 30.0 atomic %. Based on the total amount of elements, the chalcogen compound may include the third element in an amount of 20.0 atomic % to 50.0 atomic %.

[0014] In some embodiments, the chalcogen compound may be represented by any one of the following Chemical Formula 1, 2, or 3.

[0015] [Chemical Formula 1]

[0016] A a1 B b1 C c1 Se d1 Te e1

[0017] wherein, in Chemical Formula 1, A represents the first element, B represents the second element, C represents the third element, and 0.01≤a1≤0.10, 0.05≤b1≤0.30, 0.05≤c1≤0.50, 0.20≤d1≤0.70, 0.0<e1≤0.1, and the sum of a1, b1, c1, d1 and e1 is 1.

[0018] [Chemical Formula 2]

[0019] A a2 B b2 C c2 Se d2 Te e2

[0020] wherein, in Chemical Formula 2, A represents the first element, B represents the second element, C represents the third element, 0.01≤a2≤0.10, 0.05≤b2≤0.30, 0.05≤c2≤0.50, 0.20≤d2≤0.70, 0.05≤e2≤0.2, and the sum of a2, b2, c2, d2 and e2 is 1.

[0021] [Chemical Formula 3]

[0022] A a3 B b3 C c3 Se d3 Te e3

[0023] wherein, in Chemical Formula 3, A represents the first element, B represents the second element, C represents the third element, 0.001≤a3≤0.10, 0.05≤b3≤0.30, 0.20≤c3≤0.50, 0.20≤d3≤0.70, 0<e3≤0.2, and the sum of a3, b3, c3, d3 and e3 is 1.

[0024] In some embodiments, the chalcogenide compound may further comprise at least one of carbon (C), nitrogen (N), and oxygen (O).

[0025] In some embodiments, the chalcogenide compound may have a crystallization temperature of 350°C to 600°C.

[0026] In some embodiments, the chalcogenide compound may have a sublimation temperature of 250°C to 400°C.

[0027] In some embodiments, the semiconductor device may further comprise a variable resistance layer, and the selection device layer may be electrically connected to the variable resistance layer. The semiconductor device may further comprise a first electrode layer, a second electrode layer, and a third electrode layer, wherein the selection device layer may be disposed between the first electrode layer and the second electrode layer, and the variable resistance layer may be disposed between the second electrode layer and the third electrode layer.

[0028] In some embodiments, each of the first electrode layer, the second electrode layer, and the third electrode layer may independently comprise at least one of carbon (C), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium carbonitride (TiCN), titanium carbon silicon nitride (TiCSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), and tungsten nitride (WN).

[0029] In some embodiments, the variable resistance layer may include a material capable of reversibly changing between a crystalline and amorphous phase according to temperature variations.

[0030] In some embodiments, the variable resistance layer may include a compound containing at least one of Te and Se, and further containing at least one of Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, P, B, O, and C.

[0031] In some embodiments, the compound in the variable resistance layer may further include at least one of the following: aluminum (Al), zinc (Zn), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), molybdenum (Mo), ruthenium (Ru), palladium (Pd), hafnium (Hf), tantalum (Ta), iridium (Ir), platinum (Pt), zirconium (Zr), thallium (Tl), and polonium (Po).

[0032] In some embodiments, the semiconductor device may include a heating electrode in contact with the variable resistance layer.

[0033] In some embodiments, the variable resistance layer may include a material in which the resistance can be reversibly varied depending on an external voltage applied thereto.

[0034] In some embodiments, the variable resistance layer may include an oxide of at least one of Ta, Zr, Ti, Hf, Mn, Y, Ni, Co, Zn, Nb, Cu, Fe, and Cr.

[0035] In some embodiments, the variable resistance layer may include a material in which polarization is reversibly changed according to an external voltage applied thereto.

[0036] In some embodiments, the variable resistance layer may include at least one perovskite compound, which includes one of the following: niobium oxide, titanium oxide, nickel oxide, zirconium oxide, vanadium oxide, PCMO ((Pr,Ca)MnO3), strontium titanium oxide (strontium titanium oxide), barium strontium titanium oxide (barium strontium titanium oxide), strontium zirconium oxide (strontium zirconium oxide), barium zirconium oxide (barium zirconium oxide), and barium strontium zirconium oxide (barium strontium zirconium oxide).

[0037] In some embodiments, the variable resistance layer may include a material in which magnetization is reversibly changeable depending on an external voltage applied thereto.

[0038] In some embodiments, the variable resistance layer may include: two electrodes comprising a magnetic material; and a dielectric disposed between the two electrodes.

[0039] In some implementations, the selector layer may have a threshold voltage of 2.5V-5.0V.

[0040] In some implementations, by using pulses with a rise / fall time of 10 ns and a width of 100 ns, the selection device layer may be able to repeatedly perform on-off operations 5 × 10 7 Multiple times or more. The selection device layer may have dual threshold switching characteristics. The selection device layer may have low current leakage and high durability. In some embodiments, the selection device layer may have a threshold voltage variation of 50mV / dec or less. th _drift.

[0041] In some embodiments, a semiconductor device may include: a substrate; a plurality of first electrode lines on the substrate, the plurality of first electrode lines extending parallel to a top surface of the substrate and extending in a first direction; a plurality of second electrode lines above the plurality of first electrode lines and parallel to the top surface of the substrate, the plurality of second electrode lines extending in a second direction different from the first direction; and a first semiconductor device including the above semiconductor device, wherein the first semiconductor device may be disposed at the intersection of the plurality of first electrode lines and the plurality of second electrode lines.

[0042] In some embodiments, the semiconductor device may further include: a plurality of third electrode lines above the plurality of first electrode lines and the plurality of second electrode lines; and a second semiconductor device similar to the first semiconductor device. The second semiconductor device may be disposed at the intersection of the plurality of second electrode lines and the plurality of third electrode lines. The plurality of third electrode lines may extend in the first direction.

[0043] In some embodiments, the semiconductor device may further include circuit units configured to drive the first semiconductor device and the second semiconductor device or to perform arithmetic processing.

[0044] In an exemplary embodiment, the semiconductor device may include a memory cell comprising a chalcogenide compound. The chalcogenide compound may include a first element, a second element, a third element, selenium (Se), and tellurium (Te). The first element may include at least one of indium (In), aluminum (Al), strontium (Sr), and calcium (Ca). The second element may include at least one of germanium (Ge) and tin (Sn). The third element may include at least one of arsenic (As), antimony (Sb), and bismuth (Bi).

[0045] In some embodiments, in the chalcogen compound, tellurium (Te) may be included in an amount of about 3 atomic% to 9 atomic% based on the total amount of elements, and the elemental ratio of tellurium (Te) to selenium (Se) may be greater than or equal to about 0.06 and less than or equal to about 0.19.

[0046] In some embodiments, the chalcogen compound may be represented by any one of the following Chemical Formulas 1, 2, or 3.

[0047] [Chemical Formula 1]

[0048] A a1 B b1 C c1 Se d1 Te e1

[0049] wherein, in Chemical Formula 1, A represents the first element, B represents the second element, C represents the third element, and 0.01≤a1≤0.10, 0.05≤b1≤0.30, 0.05≤c1≤0.50, 0.20≤d1≤0.70, 0.0<e1≤0.1, and the sum of a1, b1, c1, d1 and e1 is 1.

[0050] [Chemical Formula 2]

[0051] A a2 B b2 C c2 Se d2 Te e2

[0052] wherein, in Chemical Formula 2, A represents the first element, B represents the second element, C represents the third element, and 0.01≤a2≤0.10, 0.05≤b2≤0.30, 0.05≤c2≤0.50, 0.20≤d2≤0.70, 0.05≤e2≤0.2, and the sum of a2, b2, c2, d2 and e2 is 1.

[0053] [Chemical Formula 3]

[0054] A a3 B b3 C c3 Se d3 Te e3

[0055] Wherein, in Chemical Formula 3, A represents the first element, B represents the second element, C represents the third element, and 0.001≤a3≤0.10, 0.05≤b3≤0.30, 0.20≤c3≤0.50, 0.20≤d3≤0.70, 0<e3≤0.2, and the sum of a3, b3, c3, d3 and e3 is 1.

[0056] In some embodiments, the memory cell may include a variable resistance layer.

[0057] In some embodiments, in the chalcogenide compound, based on the total amount of elements, the first element may be included in an amount of 0.1 atomic% to 10.0 atomic%, based on the total amount of elements, the second element may be included in an amount of 5.0 atomic% to 30.0 atomic%, and based on the total amount of elements, the third element may be included in an amount of 5.0 atomic% to 50.0 atomic%.

[0058] In some embodiments, the chalcogenide compound may further include at least one of carbon (C), nitrogen (N), and oxygen (O).

[0059] In some embodiments, the semiconductor device may further include: a substrate; a first electrode line extending on a top surface of the substrate in a first direction; a second electrode line extending above the first electrode line in a second direction different from the first direction; and a first memory cell including the memory cell, wherein the first memory cell may be disposed at an intersection between the first electrode line and the second electrode line.

[0060] In some embodiments, the semiconductor device may further include: a third electrode line above the first electrode line and the second electrode line, the third electrode line extending in the first direction; and a second memory cell disposed at an intersection between the second electrode line and the third electrode line.

[0061] In some embodiments, an electronic device may include the semiconductor device and a processing circuitry configured to drive the semiconductor device. Description of Drawings

[0062] The above and other aspects, features and advantages of some embodiments of the present disclosure will become more apparent from the following description considered in conjunction with the accompanying drawings, in which:

[0063] Figure 1 is an equivalent circuit diagram illustrating a semiconductor device according to an embodiment;

[0064] Figure 2 is a diagram schematically illustrating a voltage-current curve of a material having bidirectional threshold switching characteristics;

[0065] Figure 3A A perspective view illustrating a semiconductor device according to one embodiment;

[0066] Figure 3B For along Figure 3A Cross-sectional views of lines 1X-1X' and 1Y-1Y' are used to illustrate this. Figure 3A The semiconductor device shown;

[0067] Figure 4 A schematic cross-sectional view illustrating a semiconductor device according to another embodiment;

[0068] Figures 5A to 5C A schematic diagram illustrating the process for manufacturing a semiconductor device according to an embodiment;

[0069] Figures 6A to 6C This section explains the selection of device layers based on some example implementation methods;

[0070] Figure 6D To explain Figure 6C A graph showing the concentration of the selected device layer or the Te / Se ratio curve; and

[0071] Figure 7 A diagram of an electronic device including a semiconductor device according to an example embodiment. Detailed Implementation

[0072] The embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this respect, the embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, the embodiments are described below only by reference to the accompanying drawings to illustrate aspects. As used herein, the term “and / or” includes any and all combinations of one or more of the associated enumerated items. Expressions such as “at least one of” modify the entire list of elements and not individual elements of the list when appearing before or after the list of elements. For example, “at least one of A, B, and C,” “at least one of A, B, or C,” “one of A, B, C, or a combination thereof,” and “one of A, B, C, and a combination thereof” can be interpreted to cover any of the following: A; B; A and B; A and C; B and C; and A, B, and C.

[0073] In the following description, the terminology is used only to illustrate specific embodiments and does not limit the scope of this disclosure. When an element is referred to as being "above" or "on" another element, it may be directly above, below, to the left, or to the right of the other element while in contact with the other element, or it may be above, below, to the left, or to the right of the other element without being in contact with the other element.

[0074] Singular terms may also include plural forms unless otherwise specified. Unless otherwise specified, the terms “comprising” and / or “including” as used herein indicate the presence of the stated features, figures, steps, processes, elements, components, materials, or combinations thereof, but do not exclude the presence or addition of one or more additional features, figures, steps, processes, elements, components, materials, or combinations thereof.

[0075] It will be understood that although terms such as “first,” “second,” and “third” are used to describe various elements, these terms are only used to distinguish one element from another, and the characteristics of the elements, such as their order and type, should not be limited by the terms. Additionally, terms such as “unit,” “tool,” “module,” or “component” can be used to refer to a unit having at least one function or operation and implemented in a complex structure using hardware, software, or a combination of hardware and software.

[0076] When the terms “about” or “substantially” are used in this specification to refer to numerical values, it is intended that the relevant numerical values ​​include manufacturing or operational tolerances (e.g., ±10%) near the stated numerical values. Similarly, when the terms “generally” and “substantially” are used to refer to geometry, it is intended that precision of the geometry is not required, but tolerances for the shape are within the scope of this disclosure. Furthermore, regardless of whether a numerical value or shape is modified to “about” or “substantially”, it will be understood that these values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) near the stated numerical values ​​or shapes.

[0077] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the drawings, the same reference numerals refer to the same elements, and for clarity of explanation, the dimensions of elements (e.g., the width and thickness of layers or regions) may be enlarged. The embodiments described herein are for illustrative purposes only and various changes may be made therein.

[0078] According to one aspect, a semiconductor device with high reliability (durability) and a semiconductor apparatus including said semiconductor device are provided. For example, the semiconductor apparatus may include a plurality of semiconductor devices between two separate sets of electrode lines, and each of the semiconductor devices may include a variable resistance layer and a selector layer electrically connected to each other. Additionally, the semiconductor apparatus may have a three-dimensional structure in which said two sets of electrode lines intersect. The semiconductor device and / or the semiconductor apparatus may be a memory device.

[0079] Figure 1 An equivalent circuit diagram of the semiconductor device 100 according to an embodiment is provided. (See reference...) Figure 1 The semiconductor device 100 may include a plurality of first electrode lines WL1 and WL2 extending parallel to each other in a first direction (X direction). Additionally, the semiconductor device 100 may include second electrode lines BL1, BL2, BL3, and BL4 spaced apart from the first electrode lines WL1 and WL2 in a third direction (Z direction) and extending parallel to each other in a second direction (Y direction). A semiconductor device MC may be disposed between the first electrode lines WL1 and WL2 and the second electrode lines BL1, BL2, BL3, and BL4. For example, the semiconductor device MC may be disposed at the intersections of the first electrode lines WL1 and WL2 with the second electrode lines BL1, BL2, BL3, and BL4, and may be electrically connected to the first electrode lines WL1 and WL2 and the second electrode lines BL1, BL2, BL3, and BL4. Furthermore, each semiconductor device MC may include a variable resistor layer ME and a selector layer SW electrically connected to each other. For example, the variable resistance layer ME and the selector layer SW can be connected in series with each other in the third direction (Z direction), wherein the selector layer SW can be electrically connected to the first electrode lines WL1 and WL2 or the second electrode lines BL1, BL2, BL3 and BL4, and the variable resistance layer ME can be electrically connected to another electrode line.

[0080] In brief, the semiconductor device 100 can be driven by applying a voltage to the variable resistance layer ME of the semiconductor device MC through first electrode lines WL1 and WL2 and second electrode lines BL1, BL2, BL3, and BL4 to induce current flow. For example, a semiconductor device MC (a specific semiconductor device MC) can be addressed by selectively selecting one of the first electrode lines WL1 and WL2 and one of the second electrode lines BL1, BL2, BL3, and BL4, and the semiconductor device MC can be programmed by applying a signal between the selected electrode lines of the first electrode lines WL1 and WL2 and the second electrode lines BL1, BL2, BL3, and BL4. Furthermore, by measuring the current values ​​through the second electrode lines BL1, BL2, BL3, and BL4, information dependent on the resistance value of the variable resistance layer ME of the semiconductor device MC—that is, the programmed information—can be read.

[0081] The variable resistance layer ME can have the function of storing information. For example, the resistance of the variable resistance layer ME can change according to the voltage applied to it. The semiconductor device MC can store and erase digital information, such as "0" or "1", according to the change in the resistance of the variable resistance layer ME. The semiconductor device MC can write data, for example, write the high resistance state of the variable resistance layer ME as "0" and write the low resistance state of the variable resistance layer ME as "1". Here, the writing from the high resistance state "0" to the low resistance state "1" can be called a "set operation", and the writing from the low resistance state "1" to the high resistance state "0" can be called a "reset operation".

[0082] The selector layer SW can function to select (address) the semiconductor device MC by controlling the current to the variable resistor layer ME electrically connected to the selector layer SW. For example, the selector layer SW may include materials in which the resistance is variable depending on the voltage applied across the selector layer SW. For example, the selector layer SW may have bidirectional threshold switch (OTS) characteristics.

[0083] Figure 2 A plot illustrating the voltage-current profile of the selectable device layer SW with OTS characteristics. (Reference) Figure 2 The first curve 21 shows the voltage-current relationship in a state where very little current flows through the selector layer SW. As the voltage gradually increases from a state where both voltage and current are zero, the selector layer SW remains in a high-resistance state where very little current flows through it until the voltage reaches the threshold voltage V. th (First voltage level 23). However, the voltage exceeds the threshold voltage V. th When the selected device layer SW enters a low-resistance state, the current flowing through the selected device layer SW can be significantly increased, and the voltage applied to the selected device layer SW can be reduced to the saturation voltage V. S (Second voltage level 24). The second curve 22 shows the voltage-current relationship in a state where current flows more smoothly through the selector layer SW. When the current flowing through the selector layer SW becomes greater than the first current level 26, the voltage applied to the selector layer SW can become slightly larger than the second voltage level 24. For example, when the current flowing through the selector layer SW increases significantly from the first current level 26 to the second current level 27, the voltage applied to the selector layer SW can increase slightly from the second voltage level 24. In other words, once a current greater than the first current level 26 flows through the selector layer SW, the voltage applied to the selector layer SW can be maintained at the saturation voltage V.S When the current drops below the sustaining current level (first current level 26), the selected device layer SW returns to a high-resistance state, and thus the current can be effectively blocked until the voltage increases to the threshold voltage V. th Due to these characteristics, selecting the device layer SW can achieve a threshold voltage V at the first voltage level 23. th The function of switching devices.

[0084] However, even when the voltage is less than the threshold voltage V th When a low voltage is applied to the semiconductor device MC (when the semiconductor device MC is in the off state), a certain level of current can also flow in the selector layer SW, such as... Figure 2 As shown in the diagram. When the off-state current (leakage current) is high, it can be difficult to operate the semiconductor device 100, which includes a large number of semiconductor devices MC. Furthermore, when the threshold voltage V of the selected device layer SW is high... th Or the ratio of the on-current to the off-current (I) 导通 / I 关断 The reliability and durability of the selected device layer SW can deteriorate as the cumulative usage time or cumulative number of turn-on / turn-off operations of the semiconductor device MC changes.

[0085] According to an embodiment, the selected device layer SW may include a chalcogenide compound containing five or more elements, and may have stable switching characteristics while having a low turn-off current value (leakage current value). In an embodiment, for example, the chalcogenide compound may include selenium (Se) and tellurium (Te), and may further include: one or more first elements selected from (or including one of the following): indium (In), aluminum (Al), strontium (Sr), and calcium (Ca); a second element including germanium (Ge) and / or tin (Sn); and one or more third elements selected from (or including one of the following): arsenic (As), antimony (Sb), and bismuth (Bi).

[0086] Chalcogenide compounds (GeAsSe) composed of three elements can exhibit OTS (On-Switch) characteristics, but suffer from poor durability and thus poor suitability for semiconductor devices. Since the chalcogenide compounds of the embodiments further include the first element and, in addition to selenium (Se), tellurium (Te), i.e., two chalcogenide elements, the chalcogenide compounds of the embodiments can exhibit high switching durability and a similar level of turn-off current (leakage current). Although the chalcogenide compounds of the embodiments are not limited to a specific theory, since the chalcogenide compounds of the embodiments simultaneously include tellurium (Te) and the first element, they can have fewer carrier hopping sites than the three-element chalcogenide compounds (GeAsSe). Therefore, the specific resistivity of the chalcogenide compounds of the embodiments can be increased. Furthermore, the chalcogenide compounds of the embodiments have a higher density than the three-component chalcogenide compounds (GeAsSe), and therefore, when an external voltage is applied to the chalcogenide compounds of the embodiments, the movement of atoms caused by the electric field is suppressed, thereby improving the durability of the chalcogenide compounds.

[0087] The elemental ratio of tellurium (Te) to selenium (Se) in the chalcogenide compound can be greater than about 0.0 but equal to or less than about 0.5. For example, the elemental ratio of tellurium (Te) to selenium (Se) can be about 0.01 or greater, about 0.03 or greater, about 0.05 or greater, about 0.07 or greater, about 0.10 or greater, about 0.30 or less, about 0.25 or less, about 0.20 or less, about 0.17 or less, or about 0.15 or less. When the selenium (Se) content is too high, the threshold voltage V th The change can increase with the cumulative usage time, and the shutdown current (leakage current) can increase when the tellurium (Te) content is too high.

[0088] Based on the total amount of elements in the chalcogenide compound, the amount of tellurium (Te) in the chalcogenide compound can range from about 0.5 atomic% to about 20.0 atomic%. For example, based on the total amount of elements in the chalcogenide compound, the amount of tellurium (Te) can be about 1.0 atomic% or more, about 2.0 atomic% or more, about 3.0 atomic% or more, about 5.0 atomic% or more, about 15.0 atomic% or less, about 12.0 atomic% or less, about 10.0 atomic% or less, or about 7.0 atomic% or less.

[0089] Based on the total amount of elements in the chalcogenide compound, the amount of selenium (Se) in the chalcogenide compound may be greater than about 0.0 atomic% but equal to or less than about 70.0 atomic%. For example, based on the total amount of elements in the chalcogenide compound, the amount of selenium (Se) may be about 10.0 atomic% or greater, about 15 atomic% or greater, about 20.0 atomic% or greater, about 25.0 atomic% or greater, about 30.0 atomic% or greater, about 35.0 atomic% or greater, about 40.0 atomic% or greater, about 65.0 atomic% or less, about 60.0 atomic% or less, or about 55.0 atomic% or less.

[0090] Based on the total amount of elements in the chalcogenide compound, the amount of the first element in the chalcogenide compound can range from about 0.1 atomic% to about 10.0 atomic%. For example, based on the total amount of elements in the chalcogenide compound, the amount of the first element can be about 0.5 atomic% or more, about 1.0 atomic% or more, about 1.5 atomic% or more, about 2.0 atomic% or more, about 7.0 atomic% or less, about 6.0 atomic% or less, or about 5.0 atomic% or less.

[0091] Based on the total amount of elements in the chalcogenide compound, the amount of the second element in the chalcogenide compound can range from about 5.0 atomic% to about 30.0 atomic%. For example, based on the total amount of elements in the chalcogenide compound, the amount of the second element can be about 7.0 atomic% or more, about 10.0 atomic% or more, about 25.0 atomic% or less, about 23.0 atomic% or less, or about 20.0 atomic% or less.

[0092] Based on the total amount of elements in the chalcogenide compound, the amount of the third element in the chalcogenide compound can range from about 5.0 atomic% to about 50.0 atomic%. For example, based on the total amount of elements in the chalcogenide compound, the amount of the third element can be about 7.0 atomic% or more, about 10.0 atomic% or more, about 15.0 atomic% or more, about 20.0 atomic% or more, about 45.0 atomic% or less, about 40.0 atomic% or less, or about 35.0 atomic% or less.

[0093] Based on the content of the first element, the second element, the third element, selenium (Se), and / or tellurium (Te), the performance factor, for example, the threshold voltage V, is determined. th Turn-off current value (leakage current value), threshold voltage change V th Drift and durability can be balanced (traded out). For example, as the tellurium (Te) content increases relative to the selenium (Se) content, the threshold voltage change V... th Drift and / or durability can be improved, but the threshold voltage Vth The current that can be reduced or turned off (leakage current) can be increased. In addition, when the content of the first element decreases, the threshold voltage change V th _drift can be increased, and the off-state current (leakage current) can be reduced. Therefore, the contents of the first element, the second element, the third element, selenium (Se), and tellurium (Te) can be adjusted according to a desired performance level.

[0094] For example, the chalcogen compound may include a compound represented by Chemical Formula 1, a compound represented by Chemical Formula 2, and / or a compound represented by Chemical Formula 3.

[0095] [Chemical Formula 1]

[0096] A a1 B b1 C c1 Se d1 Te e1

[0097] In Chemical Formula 1, A represents the first element, B represents the second element, C represents the third element, and 0.01≤a1≤0.10, 0.05≤b1≤0.30, 0.05≤c1≤0.50, 0.20≤d1≤0.70, 0.0<e1≤0.1, and the sum of a1, b1, c1, d1 and e1 is 1. Alternatively, in Chemical Formula 1, 0.0<e1≤0.075.

[0098] [Chemical Formula 2]

[0099] A a2 B b2 C c2 Se d2 Te e2

[0100] In Chemical Formula 2, A represents the first element, B represents the second element, C represents the third element, and 0.01≤a2≤0.10, 0.05≤b2≤0.30, 0.05≤c2≤0.50, 0.20≤d2≤0.70, 0.05≤e2≤0.2, and the sum of a2, b2, c2, d2 and e2 is 1. Alternatively, in Chemical Formula 2, 0.05≤e2≤0.15.

[0101] [Chemical Formula 3]

[0102] A a3 B b3 C c3 Se d3 Te e3

[0103] In Chemical Formula 3, A represents said first element, B represents said second element, C represents said third element, and 0.001≤a3≤0.10, 0.05≤b3≤0.30, 0.20≤c3≤0.50, 0.20≤d3≤0.70, 0<e3≤0.2, and the sum of a3, b3, c3, d3 and e3 is 1. Alternatively, in Chemical Formula 3, 0.01≤a3≤0.07, 0.10≤b3≤0.20, 0.20≤c3≤0.40, 0.30≤d3≤0.60 or 0.35≤d3≤0.55, and 0<e3≤0.15 or 0.05≤e3≤0.10.

[0104] The chalcogen compound according to the embodiment may further include carbon (C), nitrogen (N) and / or oxygen (O). Although the chalcogen compound is not limited to a particular theory, said additional elements may limit and / or inhibit the formation and growth of nuclei in said chalcogen compound, and may thereby improve the thermal stability of said chalcogen compound.

[0105] The chalcogen compound of the embodiment may have high thermal stability, and may thereby be less damaged or deteriorated during a manufacturing process, for example, a semiconductor device manufacturing process. For example, the crystallization temperature of said chalcogen compound may range from about 350°C to about 600°C. For example, the crystallization temperature of said chalcogen compound may be about 380°C or higher, about 400°C or higher, about 580°C or lower, or about 550°C or lower. In addition, the sublimation temperature of said chalcogen compound may range from about 250°C to about 400°C. For example, the sublimation temperature of said chalcogen compound may be about 280°C or higher, about 300°C or higher, about 380°C or lower, or about 350°C or lower.

[0106] In some embodiments, said chalcogen compound may include any one of the compound represented by Chemical Formula 4, the compound represented by Chemical Formula 5, and / or the compound represented by Chemical Formula 6.

[0107] [Chemical Formula 4]

[0108] A’ a4 B b4 C c4 Se d4 Te e4

[0109] [Chemical Formula 5]

[0110] A a5 B b5 C c5 Se d5 Te e5

[0111] [Chemical Formula 6]

[0112] In a6 Ge b6 As c6 Se d6 Te e6

[0113] In Chemical Formulas 4 to 6,

[0114] A' comprises N and any one of the first elements described above (e.g., In, Al, Sr, or Ca);

[0115] A is the first element (e.g., In, Al, Sr, or Ca); B is the second element (e.g., at least one of Ge or Sn); and

[0116] C is the third element (e.g., at least one of As, Sb, or Bi).

[0117] Furthermore, in Chemical Formulas 4 to 6,

[0118] 0.005≤a4≤0.05, 0.001≤a5, a6≤0.10,

[0119] 0.10≤b4≤0.40, and 0.05≤b5, b6≤0.30,

[0120] 0.05≤c4≤0.50, and 0.20≤c5, c6≤0.50,

[0121] 0.30≤d4≤0.70, and 0.20≤d5, d6≤0.70,

[0122] 0.01<e4≤0.1, and 0.03≤e5, e6≤0.12,

[0123] the sum of a4, b4, c4, d4 and e4 is 1,

[0124] the sum of a5, b5, c5, d5 and e5 is 1, and

[0125] the sum of a6, b6, c6, d6 and e6 is 1.

[0126] In Chemical Formulas 4 to 6, the ratio of Te / Se may be in the range of 0.05 to 0.30, but is not limited thereto.

[0127] According to an embodiment, the semiconductor device MC and the semiconductor apparatus 100 may further comprise electrodes electrically connecting the components to each other. Figure 3A and 3BPerspective and cross-sectional views are provided to illustrate a semiconductor device 100 according to one embodiment. (See reference...) Figure 3A and 3B The semiconductor device 100 may include a first electrode line layer 110L, a second electrode line layer 120L, and a semiconductor device layer MCL provided on a substrate 101.

[0128] The first electrode wire layer 110L may include a plurality of first electrode wires 110 extending parallel to each other in a first direction (X direction). The second electrode wire layer 120L may be arranged at a distance from the first electrode wire layer 110L and may include a plurality of second electrode wires 120 extending parallel to each other in a second direction (Y direction). The first direction and the second direction may be different from each other and may intersect each other perpendicularly, like... Figure 3A The X and Y directions shown are the same, but the first and second directions are not limited to this. Regarding the driving semiconductor device 100, the first electrode line 110 may be a word line or a bit line, and the second electrode line 120 may be a bit line or a word line.

[0129] The first electrode line 110 and the second electrode line 120 may each independently comprise a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. For example, the first electrode line 110 and the second electrode line 120 may each independently comprise W, WN, Au, Ag, Cu, Al, TiAlN, Ir, Pt, Pd, Ru, Zr, Rh, Ni, Co, Cr, Sn, Zn, ITO, alloys thereof, or combinations thereof. Additionally, the first electrode line 110 and the second electrode line 120 may each independently comprise a metal film and a conductive barrier layer that partially or completely covers the metal film. The conductive barrier layer may include, for example, Ti, TiN, Ta, TaN, or a combination thereof.

[0130] The semiconductor device layer MCL may include multiple semiconductor devices MC. The semiconductor devices MC may be separated from each other and may have a three-dimensional structure in which the semiconductor devices MC are arranged at the intersection between the first electrode line 110 and the second electrode line 120.

[0131] The semiconductor device MC may be further included in the selected device layer 143 ( Figure 1 (SW) and variable resistor layer 149 ( Figure 1 The semiconductor device MC may further include electrode layers between the first electrode line 110 and the select device layer 143 and / or between the second electrode line 120 and the variable resistor layer 149. For example, the select device layer 143 may be disposed between the first electrode layer 141 and the second electrode layer 145, and the variable resistor layer 149 may be disposed between the second electrode layer 145 and the third electrode layer 148.

[0132] The first electrode layer 141, the second electrode layer 145, and the third electrode layer 148 can serve as channels through which current flows and may include conductive materials. Each of the first electrode layer 141, the second electrode layer 145, and the third electrode layer 148 may independently include a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. For example, each of the first electrode layer 141, the second electrode layer 145, and the third electrode layer 148 may independently include one or more of the following: carbon (C), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium carbon nitride (TiCN), titanium silicon carbon nitride (TiCSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), and tungsten nitride (WN).

[0133] Selectable device layer 143 can be provided as described above.

[0134] The variable resistance layer 149 may include a material in which the resistance is variable depending on the conditions applied thereto.

[0135] According to an embodiment, the variable resistance layer 149 may include a phase change material whose phase is reversibly changeable depending on its temperature. In other words, the variable resistance layer 149 may include a phase change material that is reversibly changeable between a crystalline and amorphous phase depending on the heating time (the amount of heat applied to it). For example, the variable resistance layer 149 may include a phase change material that is reversibly changeable between an amorphous and a crystalline phase under the influence of Joule heating generated when an electrical pulse is applied externally to the variable resistance layer 149, and therefore has a variable resistance due to such a reversible phase change. For example, the phase change material may be in a high-resistance state when it has an amorphous phase and in a low-resistance state when it has a crystalline phase. Data can be stored in the variable resistance layer 149 by defining the high-resistance state as "0" and the low-resistance state as "1".

[0136] The phase change material may include selenium (Se) and / or tellurium (Te), and may include one or more elements selected from: Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, P, B, O, and C. The phase change material may include Ge-Sb-Te (GST). For example, Ge-Sb-Te (GST) may be a compound containing Ge, Sb, and Te, and may include Ge2Sb2Te5, Ge2Sb2Te7, Ge1Sb2Te4, and / or Ge1Sb4Te7.

[0137] The phase change material may further include one or more metallic elements selected from the following: aluminum (Al), zinc (Zn), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), molybdenum (Mo), ruthenium (Ru), palladium (Pd), hafnium (Hf), tantalum (Ta), iridium (Ir), platinum (Pt), zirconium (Zr), thallium (Tl), and polonium (Po). These metallic elements can improve the electrical and thermal conductivity of the variable resistivity layer 149 and increase its crystallization rate.

[0138] The stoichiometric composition of the elements in the phase change material can be selected in various ways. Based on the stoichiometric composition of the elements in the phase change material, the crystallization temperature, melting point, phase change rate (dependent on crystallization energy), and information retention capability of the phase change material can be adjusted. For example, the stoichiometric composition of the phase change material can be adjusted so that the melting point of the phase change material can be in the range of approximately 500°C to approximately 800°C.

[0139] The variable resistance layer 149 may have a multilayer structure comprising alternating layers of different materials. For example, the variable resistance layer 149 may have a structure comprising alternating layers of Ge-Te and Sb-Te. Such a stacked structure may be a superlattice structure. Furthermore, a barrier layer may be provided between the multiple layers. The barrier layer may function to prevent material diffusion between the multiple layers.

[0140] The semiconductor device MC may further include a heating electrode layer 147 capable of heating the variable resistance layer 149. The heating electrode layer 147 may be disposed between the second electrode layer 145 and the variable resistance layer 149, and may be in contact with the variable resistance layer 149. The heating electrode layer 147 may include a conductive material capable of generating sufficient heat to induce a phase change in the variable resistance layer 149 without reacting with the variable resistance layer 149. The heating electrode layer 147 may include a carbon-based conductive material. The heating electrode layer 147 may include at least one of the following: TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, TiAlON, WON, TaON, carbon (C), silicon carbide (SiC), silicon carbon nitride (SiCN), carbon nitride (CN), titanium carbon nitride (TiCN), tantalum carbon nitride (TaCN), or combinations thereof.

[0141] The second electrode layer 145 may have a thickness such that the heat generated by the heated electrode layer 147 does not substantially affect the thickness of the selectable device layer 143. The second electrode layer 145 may be thicker than the first electrode layer 141 or the third electrode layer 148, and may have a thickness of about 10 nm to about 100 nm. Additionally, the second electrode layer 145 may further include a heat-blocking layer and may have a structure in which the heat-blocking layer and electrode material layers are alternately stacked. In embodiments where the heated electrode layer 147 is provided to heat a variable resistance layer 149 comprising a phase change material whose phase can be thermally changed, and where the variable resistance layer 149 comprises a different material, the heated electrode layer 147 may be omitted.

[0142] According to another embodiment, the variable resistance layer 149 may comprise a material in which the resistance is reversibly changed when defects in the compound move due to an external voltage applied thereto. For example, the variable resistance layer 149 may comprise a transition metal oxide. The transition metal oxide may reversibly change between a low resistance state and a high resistance state when electrical channels are formed / destroyed due to the movement of oxygen vacancies caused by an external voltage applied thereto. The transition metal oxide may comprise one or more metals selected from: Ta, Zr, Ti, Hf, Mn, Y, Ni, Co, Zn, Nb, Cu, Fe, and Cr. For example, the transition metal oxide may comprise one or more metals selected from: Ta₂O. 5-x ZrO 2-x TiO 2-x HfO 2-x MnO 2-x Y2O 3-x NiO 1-y Nb2O 5-x CuO 1-y and Fe2O 3-x (For example, 0≤x≤1.5, 0≤y≤0.5).

[0143] In another embodiment, the variable resistance layer 149 may comprise a material whose resistance is reversibly changeable when the polarization state of the material is changed by an external voltage applied thereto. For example, the variable resistance layer 149 may comprise a perovskite compound. The variable resistance layer 149 may comprise one or more selected from: niobium oxide, titanium oxide, nickel oxide, zirconium oxide, vanadium oxide, PCMO ((Pr,Ca)MnO3), strontium titanium oxide, barium strontium titanium oxide, strontium zirconium oxide, barium zirconium oxide, and barium strontium zirconium oxide.

[0144] In another embodiment, the variable resistance layer 149 may include a material whose resistance is reversibly changeable when the magnetization state of the material is changed by an external voltage applied thereto. The variable resistance layer 149 may have a magnetic tunnel junction (MTJ) structure. For example, the variable resistance layer 149 may include: two electrodes having a magnetic material; and a dielectric disposed between the two magnetic electrodes. The two electrodes comprising the magnetic material may be a magnetization pinned layer and a magnetization free layer, and the dielectric disposed therebetween may be a tunnel blocking layer. The magnetization pinned layer may have a magnetization direction fixed in one direction, and the magnetization free layer may have a magnetization direction changeable by the spin torque of internal electrons. For example, the magnetization direction of the magnetization free layer may be reversibly changed to be parallel or antiparallel to the magnetization direction of the magnetization pinned layer, and the variable resistance layer 149 may reversibly change between a high resistance state and a low resistance state depending on the magnetization direction of the magnetization free layer. The magnetization pinning layer and the magnetization free layer may comprise ferromagnetic materials, and the magnetization pinning layer may further comprise an antiferromagnetic material that fixes the magnetization direction of the internal ferromagnetic material. Additionally, the tunnel blocking layer may comprise one or more oxides selected from Mg, Ti, Al, MgZn, and MgB.

[0145] Semiconductor devices MC can have a cylindrical shape. For example, semiconductor devices MC can have a shape like... Figure 3A and 3B The rectangular column shape shown may also have different column shapes, such as cylindrical, elliptical, and polygonal column shapes.

[0146] In addition, such as Figure 3A and 3B As shown, the side surface of the semiconductor device MC may be perpendicular to the substrate 101, that is, the cross-sectional area of ​​the semiconductor device MC perpendicular to the stacking direction (Z direction) of the semiconductor device MC may be constant. However, this is just an example, and the semiconductor device MC may have a structure in which the lower side is wider than the upper side, or the upper side is wider than the lower side. In addition, the first electrode layer 141, the second electrode layer 145, the heating electrode layer 147, the third electrode layer 148, the selection device layer 143, and the variable resistor layer 149 may each independently have upper and lower sides with the same or different areas. The shape of the layers may vary depending on the method of forming the layers. For example, the first electrode layer 141 and the selection device layer 143 may be formed by a damascene process and may therefore have a structure in which the upper side is wider than the lower side, and the second electrode layer 145, the heating electrode layer 147, the third electrode layer 148, and the variable resistor layer 149 may be formed by a relief etching process and may therefore have a structure in which the side surfaces are vertical.

[0147] Insulating layers may be further disposed between the first electrode lines 110, between the second electrode lines 120, and / or between the semiconductor devices MC. For example, a first insulating layer 160a may be disposed between the first electrode lines 110, a second insulating layer 160b may be disposed between spaced-apart semiconductor devices MC in the semiconductor device layer MCL, and a third insulating layer 160c may be disposed between the second electrode lines 120. The first insulating layer 160a, the second insulating layer 160b, and / or the third insulating layer 160c may each comprise a dielectric material containing oxides and / or nitrides, and may be formed of the same material or different materials. Alternatively, the first insulating layer 160a, the second insulating layer 160b, and / or the third insulating layer 160c may be an air gap. In this case, an insulating liner (not shown) may be formed between the air gap and the first electrode lines 110, the second electrode lines 120, or the semiconductor devices MC.

[0148] For example, substrate 101 may include semiconductor materials such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), etc., and may include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0149] The semiconductor device 100 may further include an interlayer insulating layer 105 on a substrate 101. The interlayer insulating layer 105 may be disposed between the substrate 101 and the first electrode line layer 110L, and may electrically isolate the substrate 101 and the first electrode line layer 110L from each other. The interlayer insulating layer 105 may include oxides such as silicon oxide, and / or nitrides such as silicon nitride.

[0150] Semiconductor device 100 may include two or more semiconductor device layers (MCLs). (See reference) Figure 4The semiconductor device 400 may include a first electrode line layer 110L, a second electrode line layer 120L, a third electrode line layer 130L, a first semiconductor device layer MCL1, and a second semiconductor device layer MCL2 provided on a substrate 101. The first semiconductor device layer MCL1 may include a plurality of first semiconductor devices MC-1, and the second semiconductor device layer MCL2 may include a plurality of second semiconductor devices MC-2. The first semiconductor device MC-1 may include a first electrode layer 141-1, a selection device layer 143-1, a second electrode layer 145-1, a heating electrode layer 147-1, a variable resistor layer 149-1, and a third electrode layer 148-1, and the second semiconductor device MC-2 may include a first electrode layer 141-2, a selection device layer 143-2, a second electrode layer 145-2, a heating electrode layer 147-2, a variable resistor layer 149-2, and a third electrode layer 148-2. These layers may include the same materials as those included in the first electrode layer 141, the selection device layer 143, the second electrode layer 145, the heating electrode layer 147, the variable resistor layer 149, and the third electrode layer 148 described above. A first semiconductor device layer MCL1 may be disposed between the first electrode line layer 110L and the second electrode line layer 120L, and a second semiconductor device layer MCL2 may be disposed between the second electrode line layer 120L and the third electrode line layer 130L. For example, the first electrode line layer 110L and the third electrode line layer 130L may extend in the same direction (first direction, X direction) and may be spaced apart from each other in a third direction (Z direction). Additionally, the second electrode line layer 120L may extend in a second direction (Y direction) and may be disposed in the third direction (Z direction) between the first electrode line layer 110L and the third electrode line layer 130L at a position away from them. The first semiconductor device layer MCL1 may be disposed at the intersection between the first electrode line layer 110L and the second electrode line layer 120L, and the second semiconductor device layer MCL2 may be disposed at the intersection between the second electrode line layer 120L and the third electrode line layer 130L. With respect to the driving semiconductor device 400, the first electrode line layer 110L and the third electrode line layer 130L may correspond to word lines (or bit lines), and the second electrode line layer 120L may correspond to a common bit line (or common word line).

[0151] exist Figure 4 In the semiconductor device 400, there are two semiconductor device layers MCL1 and MCL2, but the number of semiconductor device layers and the number of electrode line layers can be adjusted according to the desired performance level.

[0152] The semiconductor device 400 may further include a drive circuit region 410 on the substrate 101. (See reference...) Figure 4The driving circuit region 410 may include circuit units such as peripheral circuits, driving circuits, and core circuits, which drive semiconductor devices MC-1 and MC-2 or perform arithmetic processing. The circuits may include, for example, page buffers, latch circuits, cache circuits, column decoders, sense amplifiers, data input / output circuits, or row decoders. Furthermore, the circuits may be arranged between the substrate 101 and the first and second semiconductor device layers MCL1 and MCL2. In other words, the driving circuit region 410 and the first and second semiconductor device layers MCL1 and MCL2 may be sequentially arranged on the substrate 101, and this arrangement may be a cell onperi (COP) structure.

[0153] The driving circuit region 410 may include one or more transistors TR and wiring structure 414 electrically connected to the transistors TR.

[0154] Transistors TR may be disposed in the active region AC of substrate 101 defined by device isolation layer 104. Each transistor TR may include a gate G, a gate insulating layer GD, and a source / drain SD. Additionally, insulating spacers 106 may be disposed on the two sidewalls of the gate G, and an etch stop layer 108 may be disposed on the gate G and / or the insulating spacers 106. The etch stop layer 108 may include an insulating material such as silicon nitride or silicon oxynitride.

[0155] The number and location of the wiring structures 414 can be determined based on the layout of the drive circuit region 410 and the type and arrangement of the gate G. The wiring structures 414 can have a multilayer structure with two or more layers. Specifically, as... Figure 4 As shown, each of the wiring structures 414 may include a first contact 416A, a first wiring layer 418A, a second contact 416B, and a second wiring layer 418B that are electrically connected to each other and sequentially stacked on the substrate 101. The first contact 416A, the first wiring layer 418A, the second contact 416B, and the second wiring layer 418B may each independently include a metal, a conductive metal nitride, a metal silicide, or a combination thereof, and may include conductive materials such as tungsten, molybdenum, titanium, cobalt, tantalum, nickel, tungsten silicide, titanium silicide, cobalt silicide, tantalum silicide, nickel silicide, etc.

[0156] The wiring structure 414 may include interlayer insulation layers 412A, 412B, and 412C that electrically isolate the components from each other. (See reference) Figure 4 Interlayer insulating layers 412A, 412B, and 412C may be disposed between transistors TR, between first and second wiring layers 418A and 418B, and / or between first and second contacts 416A and 416B. Interlayer insulating layers 412A, 412B, and 412C may include silicon oxide, silicon nitride, silicon oxynitride, etc.

[0157] The semiconductor device 400 may further include a wiring structure (not shown) electrically connecting the first and second semiconductor devices MC-1 and MC-2 to the drive circuit region 410, and the wiring structure (not shown) may be arranged through an interlayer insulating layer 105.

[0158] Such a selection device layer, as described above, can together with two electrodes arranged on both sides of the selection device layer to form a switching device. For example, the switching device can be used in various technical fields to control the flow of current according to changes in current and / or voltage. For example, the switching device can be used in technical fields where PN diodes are used instead of PN diodes. See reference... Figure 3A The above description of the first electrode layer 141, the second electrode layer 145, and the selection device layer 143 shown provides an understanding of the details regarding the two electrodes and the selection device layer of the switching device.

[0159] The ratio of the on-current to the off-current of the selected device layer and / or switching device in the implementation method is I. 导通 / I 关断 It can be approximately 1.0 × 10 2 Or larger, approximately 5.0 × 10 2 Or larger, approximately 1.0 × 10 3 Or larger, approximately 5.0 × 10 3 Or larger, or approximately 1.0 × 10 4 Or larger.

[0160] Additionally, the threshold voltage V of the switching device, semiconductor device, and / or semiconductor apparatus in the embodiment th It can be approximately 2.5V or greater, approximately 2.6V or greater, approximately 2.7V or greater, approximately 2.8V or greater, approximately 2.9V or greater, approximately 3.0V or greater, approximately 5.0V or less, approximately 4.9V or less, approximately 4.7V or less, approximately 4.6V or less, or approximately 4.5V or less.

[0161] The switching devices, semiconductor devices, and / or semiconductor devices of the embodiments can have high durability. For example, the switching devices, semiconductor devices, and / or semiconductor devices can have approximately 5.0 × 10⁻⁶. 7 Multiple times or more, approximately 1.0 × 10 8 More than once, approximately 5.0 × 10 8 Multiple times or more, approximately 1.0 × 10 9 More than once, approximately 5.0 × 10 9 Times or more, or about 1.0 × 10 10 Durability of one or more times. The durability of each device can be assessed by using a pulse with a voltage rise / fall time of approximately 10 ns and a width of approximately 100 ns in which the threshold voltage V of the device is measured.th The number of on-off operations performed within a range of ±15% of the initial threshold voltage (the average threshold voltage value for 1000 on-off cycles) is defined. Additionally, the threshold voltage variation V of the switching device, semiconductor device, and / or semiconductor apparatus is defined. th The drift can be about 60 mV / dec or less, about 55 mV / dec or less, or about 50 mV / dec or less.

[0162] The switching device, semiconductor device, and / or semiconductor apparatus may be manufactured by conventional methods known in the art. Figures 5A to 5C A cross-sectional view illustrating the process of manufacturing a semiconductor device according to an embodiment.

[0163] refer to Figure 5A An interlayer insulating layer 105 is formed on a substrate 101. A first electrode line layer 110L is formed on the interlayer insulating layer 105, comprising a plurality of first electrode lines 110 extending in a first direction (X direction) and spaced apart from each other. The first electrode line layer 110L can be formed by forming a conductive layer for the first electrode lines 110 and then patterning the conductive layer by etching. A first insulating layer 160a can be filled between the first electrode lines 110. The first insulating layer 160a can be formed by filling the gaps between the first electrode lines 110 with an insulating material and flattening the insulating material by a chemical mechanical polishing (CMP) process until the top surface of the first electrode lines 110 is exposed. The first electrode material layer 141k, the selection device material layer 143k, the second electrode material layer 145k, the heating electrode material layer 147k, the variable resistor material layer 149k, and the third electrode material layer 148k are sequentially stacked on the first electrode line layer 110L and the first insulating layer 160a to form a stacked structure 140k.

[0164] refer to Figure 5B A mask pattern (not shown) spaced apart from each other in a first direction (X direction) and a second direction (Y direction) is formed on the stacked structure 140k, and the stacked structure 140k is etched using the mask pattern until a portion of the top surface of the first insulating layer 160a and the first electrode line 110 is exposed. Depending on the structure of the mask pattern, a plurality of semiconductor devices MC spaced apart from each other in the first and second directions can be formed. Each of the plurality of semiconductor devices MC may include a first electrode layer 141, a selectable device layer 143, a second electrode layer 145, a heating electrode layer 147, a variable resistor layer 149, and a third electrode layer 148, and may be electrically connected to the first electrode line 110. Additionally, the mask pattern can be removed by an ashing and stripping process.

[0165] refer to Figure 5CA second insulating layer 160b may be filled between the semiconductor device MC. A second electrode line layer 120L comprising a plurality of second electrode lines 120 extending in a second direction (Y direction) and separated from each other is formed on the semiconductor device MC and the second insulating layer 160b. A third insulating layer 160c may be filled between the second electrode lines 120.

[0166] Components such as first and second electrode lines 110 and 120, first, second, and third electrode layers 141, 145, and 148, heating electrode layer 147, insulating layers 105, 160a, 160b, and 160c, selector layer 143, and variable resistance layer 149 can be formed by methods known in the art. Each component can be independently formed with a desired composition and thickness by deposition methods such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or sputtering. For example, the selector material layer 143k can be formed using a source or target including indium (In), germanium (Ge), arsenic (As), selenium (Se), and tellurium (Te) by PVD or sputtering.

[0167] Additionally, the components can be independently patterned using methods known in the art. For example, in addition to the patterning methods described above, a damascene method can also be used. For instance, when forming the second electrode line 120 using a damascene process, a thick insulating material layer is formed between and on the semiconductor devices MC, and then the insulating material layer is etched to form trenches. The trenches can extend in the second direction and can expose the top surface of the variable resistance layer 149. The second electrode line 120 can be formed by filling the trenches with a conductive material and flattening the conductive material. The second insulating layer 160b and the third insulating layer 160c can be integral.

[0168] Figures 6A to 6C This section explains the selection of device layers based on some example implementations. Figure 6D To explain Figure 6C The graph shows the concentration of the selected device layer or the Te / Se ratio curve.

[0169] refer to Figures 6A to 6B Selecting device layers 143A and 143B can include multiple sublayers (sub-layers). Figure 6A and 6B In this configuration, each of the selected device layers 143A and 143B may include two or more sublayers with different compositions. Figure 6A The selected device layer 143A includes a first sublayer 143a and a second sublayer 143b on the first sublayer 143a. Figure 6B The selected device layer 143B can be connected with Figure 6AThe selected device layer 143A is the same as that in the second sublayer 143b, and may be further included in the third sublayer 143c on the second sublayer 143b.

[0170] Sublayers 143a, 143b, and 143c may differ from each other in chemical composition and / or ratios. For example, sublayers 143a, 143b, and 143c may comprise chalcogenide compounds represented by the same or different chemical expressions among those discussed above, namely chemical expressions 1, 2, 3, 4, 5, and 6. For example, sublayers 143a, 143b, and 143c may independently have a first element A (or A' for chemical expression 4), a second element B, or a third element C that differ from each other. Figure 6A and 6B Sublayers 143a, 143b, and 143c may also have different values ​​for the stoichiometric coefficients in chemical expressions 1-3.

[0171] In the implementation method, such as Figure 6C As shown, Figure 6C The selected device layer 143C can have varying concentrations at different thicknesses h0 to h4. (Reference) Figure 6C and 6D The concentration of elements (A, A', B, or C in chemical formulas 1-6) or the Te / Se ratio in the selected device layer 143C can vary based on the thickness h0 to h4. Figure 6D Explain the curves ac and df for element concentration or T / Se ratio curves.

[0172] Figures 6A to 6C The selected device layers 143A to 143C in this application can replace the present application. Figure 3A , 3B Selected device layers 143, 143-1, 143-2, and 143k in 5A to 5C.

[0173] Figure 7 A diagram of an electronic device including a semiconductor device according to an example embodiment.

[0174] refer to Figure 7The electronic device 1000 may include a controller 500, a storage controller 550, a display 600 (e.g., an OLED display, a holographic display), and a semiconductor device 100. The storage controller 550 may include a read / write circuitry 560 and a word line driver circuitry 570. The read / write circuitry 560 and the word line driver circuitry 570 are electrically connected to the semiconductor device 100 via a first electrode line (e.g., WL1) and a second electrode line (e.g., BL1). The controller 500 controls the operation of the electronic device 1000 and may include a processing circuitry system 510, a host interface 515, and a power management circuitry 520. The semiconductor device 100 may be implemented using one of the semiconductor devices 100 and 400 described above. In the electronic device 1000, the semiconductor device 100 may utilize the technology described in this application. Figure 3A , 3B The above-described device layers 143, 143-1, 143-2, 143k, and 143A to 143C are implemented.

[0175] When controller 500 receives commands from an external host (not shown) via host interface 515, processing circuitry 510 can operate in response to those commands and control the operation of display 600, storage controller 550, and / or semiconductor device 100. Controller 500 can control display 600 by providing commands and information to display 600 and by controlling the power of display 600 through power management circuitry 520. Controller 500 can use power management circuitry 520 to control the power supplied to storage controller 550 and semiconductor device 100. Controller 500 can control the operation of semiconductor device 100 by providing commands to storage controller 550. Controller 500 can also provide storage controller 550 with data to be written to semiconductor device 100 and / or receive data to be read from semiconductor device 100. In response to receiving a command from controller 500 and / or in response to receiving data for a write operation, storage controller 550 may use read / write circuitry 560 and word line driver circuitry 570 to control semiconductor device 100 to write, read, and / or erase data in one or more selected semiconductor cell devices MC of semiconductor device 100. In response to receiving a command from controller 500, storage controller 550 may read data from semiconductor device 100 and provide the data read from semiconductor device 100 to controller 500.

[0176] One or more of the elements discussed above may include or be implemented in a processing circuitry system, such as hardware including logic circuitry; a hardware / software combination such as a processor executing software; or a combination thereof. More specifically, the processing circuitry system may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0177] The semiconductor device will be described below through examples. However, the following examples are for illustrative purposes only and do not limit the scope of this disclosure.

[0178] Examples 1 to 4

[0179] The first electrode layer is formed by DC sputtering or ALD.

[0180] A chalcogenide compound layer is formed on the first electrode layer by sputtering. Specifically, the chalcogenide compound layer is formed to a thickness of 15 nm-20 nm using a target containing indium (In), germanium (Ge), arsenic (As), selenium (Se), and tellurium (Te). The composition of the target is adjusted such that the chalcogenide compound layer has an indium (In) content of 0.1 atomic%-10 atomic% of indium (In), a germanium (Ge) content of 5 atomic%-30 atomic% of germanium (Ge), a arsenic (As) content of 20 atomic%-50 atomic% of arsenic (As), a selenium (Se) content of 20 atomic%-70 atomic% of selenium (Se), and a tellurium (Te) content of 3 atomic%-12 atomic% of tellurium (Te) in the chalcogenide compound layer, as shown in Table 1.

[0181] For Examples 1 to 4, the concentrations of In, Ge, and As are the same.

[0182] A second electrode layer is formed on the chalcogenide compound layer by DC sputtering or ALD method.

[0183] Comparative Example 1

[0184] The semiconductor device was manufactured in the same manner as in Example 1, except that a chalcogenide compound layer was formed using a target containing germanium (Ge), arsenic (As), and selenium (Se) but not indium (In) and tellurium (Te).

[0185] Comparative Example 2

[0186] The semiconductor device was manufactured in the same manner as in Example 1, except that a chalcogenide compound layer was formed using a target containing indium (In), germanium (Ge), arsenic (As), and selenium (Se) but not tellurium (Te).

[0187] Electrical property evaluation 1

[0188] The threshold voltage V of the semiconductor devices in Examples 1 to 4, Comparative Example 1, and Comparative Example 2 was measured. th Turn-off current I 关断 Threshold voltage change V th Drift and durability were measured, and the measured values ​​were normalized based on the measurements of Comparative Example 1, as shown in Table 1.

[0189] Referring to Table 1, the semiconductor device of Example 2 has similar turn-off currents (I0) to the semiconductor device of Comparative Example 2. 关断 ) value, threshold voltage (V th Value and threshold voltage change V th The drift value is improved, and the durability is enhanced compared to those of the semiconductor devices in Comparative Example 2. Furthermore, in the semiconductor devices of Examples 1 to 4, as the elemental ratio of tellurium (Te) to selenium (Se) increases, the threshold voltage change V... th _Drift and durability are improved, and the threshold voltage V decreases as the elemental ratio of tellurium (Te) to selenium (Se) decreases. th Increase and turn off current I 关断 Decrease.

[0190] As shown in Table 1, referring to Examples 1 to 4, increasing the Te / Se ratio causes the normalized threshold voltage change V to be... th The drift is reduced and the normalized durability is increased, but the increase in the Te / Se ratio in Examples 1 to 4 also reduces the normalized turn-off current I. 关断 However, in Examples 1 to 4, the standardized turn-off current (Iturn-off) remains less than or equal to 15 nA, which is suitable for many device applications.

[0191] [Table 1]

[0192]

[0193] The chalcogenide compound may have bidirectional threshold switching characteristics.

[0194] The switching devices, semiconductor devices, and / or semiconductor devices can have low turn-off current values ​​(low leakage current) and high durability. These devices and / or devices can improve integration and contribute to the miniaturization of electronic devices.

[0195] It should be understood that the embodiments described herein are to be considered in the descriptive sense only and are not intended for limiting purposes. The descriptions of features or aspects in each embodiment should typically be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. Semiconductor devices, including: Including a selective device layer of chalcogenide compounds, wherein The chalcogenide compounds include the first element, the second element, the third element, selenium (Se), and tellurium (Te). The first element includes at least one of indium (In), aluminum (Al), strontium (Sr), and calcium (Ca). The second element includes at least one of germanium (Ge) and tin (Sn), and The third element includes at least one of arsenic (As), antimony (Sb), and bismuth (Bi).

2. The semiconductor device as claimed in claim 1, wherein, In the chalcogenide compound, the elemental ratio of tellurium (Te) to selenium (Se) is greater than 0.0 but equal to or less than 0.

5.

3. The semiconductor device as claimed in claim 1, wherein, In the chalcogenide compound, the elemental ratio of tellurium (Te) to selenium (Se) is greater than 0.0 and equal to or less than 0.

2.

4. The semiconductor device as claimed in claim 1, wherein, In the chalcogenide compounds, the elemental ratio of tellurium (Te) to selenium (Se) ranges from 0.07 to 0.

20.

5. The semiconductor device as claimed in claim 1, wherein, In the chalcogenide compounds, tellurium (Te) is included in amounts ranging from 0.5 atomic% to 20.0 atomic% based on the total elemental mass.

6. The semiconductor device of claim 1, wherein, In the chalcogenide compounds, tellurium (Te) is included in amounts ranging from 2.0 atomic% to 15.0 atomic% based on the total elemental mass.

7. The semiconductor device of claim 1, wherein, In the chalcogenide compounds, Based on the total elemental mass, including tellurium (Te) in amounts of 3-9 atomic percent, and The elemental ratio of tellurium (Te) to selenium (Se) is greater than or equal to 0.06 and less than or equal to 0.

19.

8. The semiconductor device of claim 1, wherein, In the chalcogenide compounds, selenium (Se) is included in an amount greater than 0.0 atomic% and equal to or less than 70.0 atomic% based on the total elemental mass.

9. The semiconductor device of claim 1, wherein, The chalcogenide compounds include selenium (Se) in amounts ranging from 20.0 atomic% to 70.0 atomic% based on the total elemental mass.

10. The semiconductor device of claim 1, wherein, In the chalcogenide compound, the first element is included in an amount of 0.1 atomic% to 10.0 atomic% based on the total elemental mass.

11. The semiconductor device of claim 1, wherein, In the chalcogenide compound, the second element is included in an amount of 5.0 atomic% to 30.0 atomic% based on the total elemental mass.

12. The semiconductor device of claim 1, wherein, In the chalcogenide compound, the third element is included in an amount of 5.0 atomic% to 50.0 atomic% based on the total elemental mass.

13. The semiconductor device of claim 1, wherein, In the chalcogenide compound, the third element is included in an amount of 20.0 atomic% to 50.0 atomic% based on the total elemental mass.

14. The semiconductor device of claim 1, wherein the chalcogenide compound is represented by any one of the following chemical formulas 1, 2, or 3: [Chemical Expression 1] TO a1 B b1 C c1 HE d1 Tea e1 in, In chemical expression 1, A refers to the first element, B refers to the second element, C refers to the third element, and 0.01 ≤ a1 ≤ 0.10, 0.05 ≤ b1 ≤ 0.30, 0.05 ≤ c1 ≤ 0.50, 0.20 ≤ d1 ≤ 0.70, 0.0 < e1 ≤ 0.1, and the sum of a1, b1, c1, d1 and e1 is 1; [Chemical Expression 2] TO a2 B b2 C c2 HE d2 Tea e2 In chemical expression 2, A refers to the first element, B refers to the second element, and C refers to the third element, and 0.01 ≤ a² ≤ 0.10, 0.05 ≤ b² ≤ 0.30, 0.05 ≤ c² ≤ 0.50, 0.20 ≤ d² ≤ 0.70, 0.05 ≤ e² ≤ 0.2, and the sum of a², b², c², d², and e² is 1; and [Chemical Expression 3] TO a3 B b3 C c3 HE d3 Tea e3 In chemical expression 3, A refers to the first element, B refers to the second element, C refers to the third element, and 0.001 ≤ a3 ≤ 0.10, 0.05 ≤ b3 ≤ 0.30, 0.20 ≤ c3 ≤ 0.50, 0.20 ≤ d3 ≤ 0.70, 0 < e3 ≤ 0.2, and the sum of a3, b3, c3, d3 and e3 is 1.

15. The semiconductor device of claim 1, wherein the chalcogenide compound further comprises at least one of carbon (C), nitrogen (N), and oxygen (O).

16. The semiconductor device of claim 1, wherein the chalcogenide compound has a crystallization temperature of 350°C-600°C.

17. The semiconductor device of claim 1, wherein the chalcogenide compound has a sublimation temperature of 250°C-400°C.

18. The semiconductor device of claim 1, comprising: Variable resistance layer, in which The selection device layer is electrically connected to the variable resistor layer.

19. The semiconductor device of claim 18, further comprising: First electrode layer; Second electrode layer; and The third electrode layer, in which The selection device layer is disposed between the first electrode layer and the second electrode layer, and The variable resistance layer is disposed between the second electrode layer and the third electrode layer.

20. The semiconductor device of claim 19, wherein the first electrode layer, the second electrode layer, and the third electrode layer each independently comprise at least one of the following: carbon (C), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium carbon nitride (TiCN), titanium silicon carbon nitride (TiCSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), and tungsten nitride (WN).

21. The semiconductor device of claim 18, wherein the variable resistance layer comprises a material capable of reversibly changing between a crystalline and amorphous phase according to temperature variations.

22. The semiconductor device of claim 21, wherein... The variable resistance layer comprises a compound containing at least one of Te and Se, and further containing at least one of Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, P, B, O, and C.

23. The semiconductor device of claim 22, wherein... The compound in the variable resistance layer further comprises at least one of the following: aluminum (Al), zinc (Zn), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), molybdenum (Mo), ruthenium (Ru), palladium (Pd), hafnium (Hf), tantalum (Ta), iridium (Ir), platinum (Pt), zirconium (Zr), thallium (Tl), and polonium (Po).

24. The semiconductor device of claim 21, further comprising: Heating electrode layer in contact with the variable resistance layer.

25. The semiconductor device of claim 18, wherein the variable resistance layer comprises a material in which the resistance is reversibly changeable according to an external voltage applied thereto.

26. The semiconductor device of claim 24, wherein the variable resistance layer comprises an oxide of at least one of Ta, Zr, Ti, Hf, Mn, Y, Ni, Co, Zn, Nb, Cu, Fe, and Cr.

27. The semiconductor device of claim 18, wherein the variable resistance layer comprises a material in which polarization is reversibly changed according to an external voltage applied thereto.

28. The semiconductor device of claim 27, wherein The variable resistance layer comprises at least one perovskite compound, which includes one of the following: niobium oxide, titanium oxide, nickel oxide, zirconium oxide, vanadium oxide, PCMO ((Pr,Ca)MnO3), strontium titanium oxide, barium strontium titanium oxide, strontium zirconium oxide, barium zirconium oxide, and barium strontium zirconium oxide.

29. The semiconductor device of claim 18, wherein the variable resistance layer comprises a material in which magnetization is reversibly changeable according to an external voltage applied thereto.

30. The semiconductor device of claim 29, wherein the variable resistance layer comprises: It includes two electrodes made of magnetic material; as well as The dielectric material disposed between the two electrodes.

31. The semiconductor device of claim 18, wherein the selectable device layer has a threshold voltage of 2.5 V to 5.0 V.

32. The semiconductor device of claim 18, wherein the selection device layer is capable of repeatedly performing on-off operations by using pulses having a rise / fall time of 10 ns and a width of 100 ns. 7 Once or more.

33. The semiconductor device of claim 18, wherein the selectable device layer has a threshold voltage variation of 50 mV / dec or less. th _drift.

34. A semiconductor device, comprising: substrate; Multiple first electrode lines on a substrate, the multiple first electrode lines extending parallel to the top surface of the substrate and extending in a first direction; Above the plurality of first electrode lines and parallel to the top surface of the substrate, there are a plurality of second electrode lines extending in a second direction different from the first direction; and A first semiconductor device comprising the semiconductor device as described in any one of claims 1-18 and 21-33, wherein the first semiconductor device is disposed at the intersection of the plurality of first electrode lines and the plurality of second electrode lines.

35. The semiconductor device of claim 34, further comprising: Above the plurality of first electrode lines and the plurality of second electrode lines, there are a plurality of third electrode lines extending in the first direction; and A second semiconductor device, similar to the first semiconductor device, is disposed at the intersection of the plurality of second electrode lines and the plurality of third electrode lines.

36. The semiconductor device of claim 35, further comprising: A circuit unit configured to drive the first semiconductor device and the second semiconductor device or to perform arithmetic processing.

37. Chalcogenide compounds, including: The first element includes at least one of indium (In), aluminum (Al), strontium (Sr), and calcium (Ca); The second element includes at least one of germanium (Ge) and tin (Sn); A third element, comprising at least one of arsenic (As), antimony (Sb), and bismuth (Bi); and The sulfide elements include selenium (Se) and tellurium (Te), wherein the elemental ratio of tellurium (Te) to selenium (Se) is in the range of greater than 0.0 and equal to or less than 0.

5.

38. The chalcogenide compound of claim 37, wherein the elemental ratio of tellurium (Te) to selenium (Se) is greater than 0.0 and equal to or less than 0.

3.

39. The chalcogenide compound of claim 37, wherein the elemental ratio of tellurium (Te) to selenium (Se) is greater than 0.07 and equal to or less than 0.

20.

40. The chalcogenide compound of claim 37, wherein the chalcogenide compound is as defined in any one of claims 5-17.

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