Wide bandwidth adc circuit

Abstract

A wide bandwidth ADC circuit combines a resistive input continuous-time sigma-delta ADC circuit with a second ADC circuit having a switched capacitor input. The combination of these two ADC circuits can achieve an ADC that is easy to drive, aliasing free, wide bandwidth, with excellent DC accuracy.

Description

Technical Field

[0001] This document typically, but not exclusively, relates to integrated circuits, and more specifically to analog-to-digital converter circuits and systems. Background Technology

[0002] In many electronic applications, analog input signals are converted into digital output signals (e.g., for further digital signal processing). For example, in a precision measurement system, electronic equipment may be equipped with one or more sensors that generate analog signals. These analog signals can then be fed as input to an analog-to-digital converter (ADC) to generate a digital output signal for further processing. In another example, in a mobile device receiver, an antenna may generate an analog signal in the air based on electromagnetic waves carrying information / signals. The analog signal generated by the antenna can then be fed as input to an ADC to generate a digital output signal for further processing.

[0003] The difference between the input and output voltages of an ADC corresponds to the ADC's quantization error. In some ADCs, the quantization error can be further processed by the ADC circuitry to "shape" it, which manifests as quantization noise in the frequency domain. For example, noise shaping techniques can push quantization noise from the signal band of interest to higher frequencies.

[0004] A Σ-Δ modulator is a feedback system that enables high-resolution digital signals. Σ-Δ modulators have been implemented in various electronic circuits, including but not limited to analog-to-digital converters (ADCs), digital-to-analog converters (DACs), frequency synthesizers, and other electronic circuits.

[0005] Σ-Δ modulation-based ADCs are widely used in digital audio and high-precision instrumentation systems. Typically, a Σ-Δ ADC encodes an analog signal using a Σ-Δ modulator (e.g., a low-resolution ADC such as a 1-bit ADC, Flash ADC, Flash quantizer, etc.), and then (if applicable) applies a digital filter to the output of the Σ-Δ modulator to form a higher-resolution digital output. Loop filters can be provided to offer error feedback to the Σ-Δ modulator. A key characteristic of Σ-Δ modulators is their noise shaping capability. Therefore, Σ-Δ ADCs are generally capable of achieving high-resolution analog-to-digital conversion. Summary of the Invention

[0006] This disclosure describes a wide-bandwidth ADC circuit that combines a resistive-input continuous-time Σ-Δ ADC circuit with a second ADC circuit having a switched-capacitor input. This combination of ADC circuits enables an easy-to-drive, aliasing-free, wide-bandwidth ADC with excellent DC accuracy.

[0007] In some aspects, this disclosure relates to a wideband analog-to-digital converter (ADC) circuit, comprising: a continuous-time Σ-Δ ADC circuit having a first input coupled to a resistive element to receive a first analog input signal and generate a first digital output signal; a second ADC circuit independent of the continuous-time Σ-Δ ADC circuit having a second input coupled to a switched capacitor circuit to receive a second analog input signal and an output to generate a second digital output signal independent of the first digital output signal; and a digital signal processor coupled to receive the first digital output signal and the second digital output signal and to output to generate at least one processed digital output signal.

[0008] In some aspects, this disclosure relates to a method of operating a wide-bandwidth ADC circuit, the method comprising: receiving a first analog input signal using a continuous-time Σ-Δ ADC circuit and generating a first digital output signal; receiving a second analog input signal using a second ADC circuit independent of the continuous-time Σ-Δ ADC circuit and generating a second digital output signal independent of the first digital output signal; and processing the first digital output signal and the second digital output signal and generating at least one processed digital output signal.

[0009] In some aspects, this disclosure relates to a wideband analog-to-digital converter (ADC) circuit, comprising: a first continuous-time Σ-Δ ADC circuit having a first input coupled to a resistive element to receive a first analog input signal and generate a first digital output signal; a second continuous-time Σ-Δ ADC circuit, independent of the first continuous-time Σ-Δ ADC circuit, having a second input coupled to a switched-capacitor circuit to receive a second analog input signal and an output to generate a second digital output signal independent of the first digital output signal; and a digital signal processor coupled to receive the first digital output signal and the second digital output signal and to output to generate at least one processed digital output signal. Attached Figure Description

[0010] In accompanying drawings that are not necessarily drawn to scale, similar numbers may describe similar parts in different views. The same numbers with different letter suffixes may represent different instances of similar components. The accompanying drawings illustrate, by way of example and not limitation, the various embodiments discussed in this document.

[0011] Figure 1 This is a schematic block diagram of an example data acquisition system that can implement a Σ-Δ modulator.

[0012] Figure 2 This is a block diagram of an example of a first-order single-bit Σ-Δ ADC.

[0013] Figure 3 This is a block diagram of an example of a wide-bandwidth ADC circuit according to the present disclosure.

[0014] Figure 4 This is a block diagram of another example of a wide-bandwidth ADC circuit according to this disclosure.

[0015] Figure 5 This is a block diagram of an example of a wide-bandwidth ADC circuit including an RC filter circuit according to the present disclosure.

[0016] Figure 6 This is a block diagram of an example wide-bandwidth ADC circuit including a multiplexer according to the present disclosure. Detailed Implementation

[0017] Many applications benefit from or sometimes require wide-bandwidth analog-to-digital converter (ADC) solutions with good AC response and high DC accuracy. The bandwidth of an ADC refers to the frequency range of an analog signal that it can correctly convert to a digital signal. High DC accuracy means that the ADC has low gain error, low offset error, low gain and offset drift, low integral nonlinearity, and low 1 / f noise.

[0018] The inventors have recognized that existing ADC architectures have limitations in combining DC performance with high bandwidth and good AC performance. Some ADC architectures are suitable for narrowband measurements, such as DC measurements. For example, an ADC may include an input coupled to a capacitor circuit and can have very good DC performance. However, when used for AC measurements, such ADCs can present system-level challenges.

[0019] ADCs with inputs coupled to capacitor circuitry can be difficult to drive, especially when high bandwidth and high accuracy are required. Therefore, ADCs with inputs coupled to capacitor circuitry may require dedicated high-bandwidth ADC driver amplifiers. Driver amplifiers increase power consumption, DC error, noise, and signal distortion.

[0020] Furthermore, ADCs with inputs coupled to capacitor circuits are prone to aliasing. That is, even with oversampling and digital filtering, at a sampling rate f... S There may also be no suppression at all. Therefore, such ADCs may require analog anti-aliasing filters to help prevent signal aliasing. However, active anti-aliasing filters increase power consumption, DC error, noise and signal distortion, as well as inter-channel phase matching error.

[0021] Some ADC architectures are better suited for AC measurements, such as high-speed measurements. For example, some continuous-time ADC circuits may include inputs coupled to resistive elements (also known as "resistive-input ADCs"), which makes them easy to drive and provides inherent anti-aliasing characteristics. However, these resistive-input ADCs can also present challenges for designers.

[0022] For example, resistive input ADCs may struggle to achieve good DC performance compared to ADCs with inputs coupled to capacitor circuitry. The resistors used in resistive input ADCs, especially polysilicon resistors, may have a higher voltage coefficient than capacitors, leading to worse integral nonlinearity (INL). Furthermore, unlike capacitors, resistors, especially polysilicon resistors, produce flicker noise. Additionally, resistors may exhibit poorer stability with respect to temperature and aging compared to capacitors, resulting in worse gain error drift and offset error drift over temperature and time.

[0023] For resistive input ADCs, achieving a flexible input common-mode range is difficult. Common-mode offset causes current to flow into the resistors, increasing noise. Furthermore, common-mode offset combined with a mismatched resistor network can lead to offset errors.

[0024] This disclosure describes a wide-bandwidth ADC circuit that combines a resistive-input continuous-time Σ-Δ ADC circuit with a second ADC circuit having a switched-capacitor input. This combination of ADC circuits enables an easy-to-drive, aliasing-free, wide-bandwidth ADC with excellent DC accuracy.

[0025] Figure 1 This is a schematic block diagram of an example data acquisition system 10, which can implement a Σ-Δ modulator. The data acquisition system 10 can be an electronic device (including electronic circuitry and / or one or more components) configured to convert signals (such as analog signals) into a usable form. In various embodiments, the data acquisition system 10 can convert physical conditions into a digital form that can be stored and / or analyzed. For clarity, Figure 1 This has been simplified. Additional features can be added to the data acquisition system 10, and some of the described features can be replaced or eliminated in other embodiments of the data acquisition system 10.

[0026] exist Figure 1 In this system, the data acquisition system 10 may include input signals 15 representing physical conditions, such as temperature, pressure, velocity, flow rate, position, other physical conditions, or combinations thereof. The sensor circuit block 20 may receive the input signals 15 and convert the physical conditions (represented by the input signals 15) into electrical signals, such as analog signals 25. The analog signals 25 may be voltage or current representing the physical conditions (represented by the input signals 15).

[0027] Signal conditioning circuit block 30 can receive and condition analog signal 25 within the acceptable range of the analog-to-digital converter (ADC), providing a conditioned analog signal 35. The conditioned analog signal 35 can be provided at ADC circuit block 40, allowing signal conditioning circuit block 30 to act as an interface between sensor circuit block 20 and ADC circuit block 40, conditioning analog signal 25 (and thus providing conditioned analog signal 35) before ADC circuit block 40 digitizes the analog signal. Signal conditioning circuit block 30 can amplify, attenuate, filter, and / or perform other conditioning functions on analog signal 25. ADC circuit block 40 can receive the conditioned analog signal 35 and convert it into digital form, providing digital signal 45. Digital signal 45 can represent the physical quantity received by the sensor through input signal 15. Digital signal processor (DSP) circuit block 50 can receive and process digital signal 45.

[0028] ADC circuit block 40 may include a Σ-Δ ADC that generates a digital signal using feedback techniques, wherein the Σ-Δ ADC may oversample its input signal (here, the conditioned analog signal 35) and perform noise shaping to achieve a high-resolution digital signal (here, digital signal 45). The Σ-Δ ADC may include a Σ-Δ modulator 60 and a digital filter / decimator 70. The Σ-Δ modulator 60 may use oversampling (e.g., a sampling rate higher than the Nyquist rate) and filtering to generate a digital signal (such as the conditioned analog signal 35) representing the input signal received by the Σ-Δ ADC.

[0029] In various implementations, the Σ-Δ ADC feedback loop forces the modulator's output to represent the input signal well within the bandwidth of interest. A digital filter / decimator 70 can attenuate noise and / or slow down the data rate of the digital signal (e.g., the Nyquist sampling rate) to provide the digital signal 45. The digital filter / decimator 70 may include a digital filter, a decimator, or both. A digital filter can attenuate the digital signal received from the Σ-Δ modulator 60, and a decimator can reduce the sampling rate of the digital signal received from the Σ-Δ modulator 60.

[0030] Figure 2 This is a block diagram of an example of a first-order single-bit Σ-Δ ADC. The Σ-Δ modulator 100 can be... Figure 1 An example of a Σ-Δ modulator 60. The Σ-Δ modulator 100 can operate at a sampling clock frequency Kf. SA predetermined rate converts the input signal (Vin) into a continuous serial stream of 1s and 0s. A one-bit digital-to-analog converter (DAC) 102 can be driven by the serial output data stream to generate a feedback signal. The output of the DAC 102 can be subtracted from the input signal using a summing element 104. The summing element 104 can be implemented as a summing node of an operational amplifier, such as the operational amplifier of integrator 106.

[0031] Integrator 106 integrates the output of summing element 104, and the output of integrator 106 can be applied to clock-latch comparator 108. For a zero input signal, the comparator output can include approximately equal numbers of 1s and 0s. For a positive input voltage, the comparator output contains more 1s than 0s. For a negative input voltage, the comparator output contains more 0s than 1s. The average value of the comparator output over multiple cycles represents the input voltage. The comparator output can be applied to a digital filter and decimator 110 that averages every M cycles, where M is a positive integer greater than 1. The digital filter and decimator 110 can be... Figure 1 Example of a digital filter / decimator 70. The decimator reduces the effective sampling rate at the output to a sampling rate f. S .

[0032] Figure 3 This is a block diagram of an example of a wide-bandwidth ADC circuit 200 according to the present disclosure. Figure 3 The ADC circuit 200 may include two ADC circuits 202, 204 that operate simultaneously with combined inputs and outputs. The first ADC circuit 202 may be a continuous-time Σ-Δ ADC circuit having a first input 206 coupled to a resistive element 208 and configured to receive a first analog input signal 210 and generate a corresponding first digital output signal 212. Although shown separately, in some examples, the resistive element 208 may be part of the first ADC circuit 202. The first ADC circuit 202 may be used for wide-bandwidth AC performance.

[0033] The second ADC circuit 204, independent of the continuous-time Σ-Δ ADC circuit 202 (the two ADC circuits 202 and 204 can operate independently of each other), has a second input 214 coupled to a capacitive input, such as a switched capacitor circuit 216, and is configured to receive a second analog input signal 218 and produce a corresponding second digital output signal 220 independent of the first digital output signal 212. Although shown separately, in some examples, the switched capacitor circuit 216 may be part of the second ADC circuit 204. The second ADC circuit 204 may focus on narrow-bandwidth DC performance and may provide a strong DC common-mode rejection ratio (CMRR). In some examples, both ADC circuits 202 and 204 may operate, while the second ADC circuit 204 operates at a slower sampling rate.

[0034] In some examples, the second ADC circuit 204 may include a continuous-time Σ-Δ ADC circuit with a switched-capacitor input. In other examples, the second ADC circuit 204 may include a discrete-time ADC circuit. For example, the second ADC circuit 204 may include a successive approximation register (SAR) ADC circuit, a fast ADC circuit, a Σ-Δ ADC circuit, or a pipelined ADC circuit.

[0035] Furthermore, the ADC circuit 200 may include a digital signal processor 222 configured to receive a first digital output signal 212 and a second digital output signal 220 and generate at least one processed digital output signal 224. For example, in Figure 3 In this embodiment, digital signal processor 222 can be configured to combine a first digital output signal 212 and a second digital output signal 220, such that at least one processed digital output signal 224 is a single combined digital output signal. That is, the first digital output signal 212 and the second digital output signal 220 can be digitally reassembled into a single bit stream. An example of this reassembly technique is described in U.S. Patent No. 9,083,369, commonly assigned to Coln et al., entitled “Splittered Data Acquisition Signal Chain,” the entire contents of which are incorporated herein by reference.

[0036] In some examples, the ADC circuit 200 may include a single channel. For example, Figure 3 The ADC circuit 200 may include a first channel 226 configured to receive a first analog input signal 210. In such a configuration, the first analog input signal 210 and the second analog input signal 218 may be the same analog input signal, i.e. Figure 3 The analog signal VIN in the data. Figure 3 In the example shown, the continuous-time Σ-Δ ADC circuit 202 includes a first input 206, and the second ADC circuit 204 includes a second input 214. The first input and the second input are coupled to the first channel 226.

[0037] Figure 4 This is a block diagram of another example of a wide-bandwidth ADC circuit according to this disclosure. Figure 4 The ADC circuit 300 may include two ADC circuits 202, 204 that operate in parallel with separate inputs 226, 302 and separate corresponding outputs 224, 304. As an example, Figure 4 The ADC circuit 300 can support sensor cluster operation, such as monitoring vibration and temperature through individual channels.

[0038] like Figure 4 As seen in the diagram, the ADC circuit 300 may include multiple input channels. For example, Figure 4 The ADC circuit 300 may include a first channel 226 configured to receive a first analog input signal 210 and a second channel 302 configured to receive a second analog input signal 218. The first analog input signal 210 may be an analog signal VIN1, and the second analog input signal 218 may be an analog signal VIN2. Figure 4 In the example shown, the continuous-time Σ-Δ ADC circuit 202 includes a first input 206 coupled to a first channel 226, and the second ADC circuit 204 includes a second input 214 coupled to a second channel 302.

[0039] Digital signal processor 222 can be configured to receive a first digital output signal 212 and a second digital output signal 220, process the two corresponding output signals 212 and 220, and then output a first processed digital output signal 224 and a separate second processed digital output signal 304. In some examples and as described in more detail below, digital signal processor 222 can generate and apply a first wake-up signal 306 or a second wake-up signal 308 to a continuous-time Σ-Δ ADC circuit (wake-up signal 306) or a second ADC circuit (wake-up signal 308) in response, for example, to an amplitude exceeding a threshold. Figure 5 This is a block diagram of another example of a wide-bandwidth ADC circuit 400 according to this disclosure. Figure 5 The ADC circuit 400 may include two ADC circuits 202 and 204 that operate simultaneously with combined inputs and outputs. Furthermore, the ADC circuit 400 may include an RC filter circuit 402 with a resistor R and a capacitor C.

[0040] The RC filter circuit 402 can be coupled to the switched-capacitor second ADC circuit 204 and can protect the switched-capacitor second ADC circuit 204 from aliasing, such as sampling and chopping aliasing. The RC filter circuit 402 can also suppress any backlash interference to the input of the continuous-time Σ-Δ ADC circuit 202, such as channels with wide-bandwidth AC performance. Both the continuous-time Σ-Δ ADC circuit 202 and the second ADC circuit 204 can measure the same analog signal VIN, but the RC filter circuit 402 can remove the AC component in the second channel 302, so that the second ADC circuit 204 is free from aliasing. Then, the two digital output signals 212, 220 can be recombined by the digital signal processor 222.

[0041] Similar to Figure 3 The ADC circuit 200, in some examples, Figure 5The digital signal processor 222 can be configured to combine the first digital output signal 212 and the second digital output signal 220, and at least one processed digital output signal 224 is a single combined processed digital output signal. However, in other examples, Figure 5 The digital signal processor 222 can be configured to provide digital output signals for parallel processing, such as... Figure 4 As shown.

[0042] Figure 6 This is a block diagram of another example of a wide-bandwidth ADC circuit 500 according to this disclosure. Figure 6 The ADC circuit 500 can combine multiple wide-bandwidth and narrow-bandwidth channels. Figure 6 The non-limiting examples shown may include a first continuous-time Σ-Δ ADC circuit 202 having an input 206 coupled to a resistive element 208 and configured to receive an analog input signal 210; a second continuous-time Σ-Δ ADC circuit 502 having an input 504 coupled to a resistive element 506 and configured to receive an analog input signal 507; and an ADC circuit 204 having an input 214 coupled to a switched capacitor circuit 216 and configured to receive an analog input signal 218.

[0043] As described above, in some examples, ADC circuit 204 may include a continuous-time Σ-Δ ADC circuit with switched-capacitor inputs. In other examples, ADC circuit 204 may include a discrete-time ADC circuit. For example, ADC circuit 204 may include a successive approximation register (SAR) ADC circuit, a fast ADC circuit, a Σ-Δ ADC circuit, or a pipelined ADC circuit.

[0044] The input 206 of the first continuous-time Σ-Δ ADC circuit 202 can be coupled to the first channel 226 and configured to generate a corresponding first digital output signal 212. The input 504 of the second continuous-time Σ-Δ ADC circuit 502 can be coupled to the second channel 508 and configured to generate a corresponding second digital output signal 510.

[0045] Figure 6 The ADC circuit 500 may include a multiplexer 512. The multiplexer 512 may include inputs correspondingly coupled to a first channel 226, a second channel 508, a third channel 302, and, in some examples, a fourth channel 514. Channel 226 is configured to receive analog signal VIN2, the second channel 508 is configured to receive analog signal VIN2, the third channel 302 is configured to receive analog signal VIN3, and the fourth channel 514 is configured to receive analog signal VIN4.

[0046] The multiplexer 512 may include an output coupled to the input 214 of the ADC circuit 204 and may be configured to select one of the first channel 226, the second channel 508, the third channel 302, and, in some examples, the fourth channel 514.

[0047] Digital signal processor 222 can be configured to receive the digital output signal 212 of a first continuous-time Σ-Δ ADC circuit 202, the digital output signal 510 of a second continuous-time Σ-Δ ADC circuit 502, and the signal 220 of a digital output ADC circuit 204. Figure 6 In the example shown, digital signal processor 222 can be configured to output digital output signals 224, 516, 304 corresponding to parallel processing of digital output signals 212, 510, 220. In the example, digital signal processor 222 can be configured to combine at least one of digital output signals 212, 510, or 220 and output a single combined digital output signal.

[0048] Figure 6 The ADC circuit 500 can combine multiple wide-bandwidth and narrow-bandwidth channels. For example, for wideband AC measurements, two parallel continuous-time Σ-Δ ADC circuits 202 and 502 can continuously sample channels 226 and 508, which can be AC ​​measurement channels. Channels 302 and 514 can be DC measurement channels. For narrowband DC measurements, the ADC circuit 204 does not need to sample simultaneously between channels, such as channels 302 and 514, because narrowband signals can move slowly. Figure 6 As shown, multiplexer 512 can multiplex inputs from multiple AC channels, such as channels 226 and 508.

[0049] Above Figure 3-6 In some cases, it may be necessary to intentionally disable the continuous-time Σ-Δ ADC circuit or the second ADC circuit, either temporarily or permanently. For example, one of the continuous-time Σ-Δ ADC circuits or the second ADC circuit can be intentionally disabled by software techniques, such as through register programming, or by hardware, such as by disconnecting the input pin or using a fuse.

[0050] In a non-limiting example, by disabling the second ADC circuit 204, for example in Figure 4 In this case, it might be desirable to operate in AC-only mode, such as for sonar, audio, or Coriolis flow meter applications. In another non-limiting example, by disabling the continuous-time Σ-Δ ADC circuit 202, for example, when only measuring DC signals (e.g., temperature and pressure), it might be desirable to operate in DC-only mode. Figure 4 .

[0051] Above Figure 3-6 In a scenario where one ADC circuit might trigger another, for example, waking it from a low-power state, it might be necessary. As a non-limiting example, the ADC circuit could be used in a vibration application, and the DC channel could be used to monitor vibration. Important information may exist in the AC domain, but customers can save power by temporarily disabling the AC channel by placing the continuous-time Σ-Δ ADC circuit in a low-power state. If significant vibration occurs, the DC channel can detect signal amplitude changes over a wide bandwidth due to aliasing, but it cannot distinguish amplitude changes by signal frequency (e.g., 1 kHz or 10 kHz). In such an example, the DC channel could be used to wake up the continuous-time Σ-Δ ADC circuit in the AC channel, which could then analyze the frequency information of the signal.

[0052] For example, Figure 4 The second ADC circuit 204 (coupled to DC channel 302) can be compared to Figure 4 The continuous-time Σ-Δ ADC circuit 202 (coupled to AC channel 226) operates at much lower power. The continuous-time Σ-Δ ADC circuit 202 can be in a low-power state, such as a quiescent state, until it receives a wake-up signal from the digital signal processor 222. Figure 4 The signal processor 222 can use amplitude triggering and output a wake-up signal 306 to the continuous-time Σ-Δ ADC circuit 202 when the amplitude exceeds a threshold, for example, putting the continuous-time Σ-Δ ADC circuit 202 into a fully powered state. In other words, Figure 4 The digital signal processor 222 may, for example, compare the amplitude of one of the first processed digital output signal 212 and the second processed digital output signal 220 with a threshold, and in response to an amplitude exceeding the threshold, generate a wake-up signal and apply the wake-up signal to either the continuous-time Σ-Δ ADC circuit (wake-up signal 306) or the second ADC circuit (wake-up signal 308).

[0053] In another example, Figure 4 The continuous-time Σ-Δ ADC circuit 202 (coupled to AC channel 226) can operate continuously and Figure 4 The digital signal processor 222 can periodically send... Figure 4 The second ADC circuit 204 (coupled to DC channel 302) outputs signal 308 to wake up from a low-power state (e.g., quiescent state) in order to correct DC offset and / or drift. Although regarding Figure 4 It was described, but Figure 3 , 5 The digital signal processor 222 of the 6 can generate similar signals 306 and 308.

[0054] exist Figure 4In some configurations, such as those with separate inputs and outputs, a duty cycle between two or more ADC circuits may be required, allowing the wide-bandwidth ADC circuit to switch between AC and DC channels. For example, Figure 4 The wide-bandwidth analog-to-digital converter (ADC) circuit 300 can use signals 306, 308 from the digital signal processor 222, and the duty cycle between the continuous-time Σ-Δ ADC circuit 202 (coupled to AC channel 226) and the second ADC circuit 204 (coupled to DC channel 302). In a non-limiting example, the continuous-time Σ-Δ ADC circuit 202 can perform continuous vibration monitoring and the second ADC circuit 204 can perform periodic temperature measurement. In another non-limiting example, the continuous-time Σ-Δ ADC circuit 202 can perform periodic vibration monitoring and the second ADC circuit 204 can perform continuous temperature monitoring.

[0055] Various annotations

[0056] Each non-limiting aspect or example described herein may exist independently, or may be in various permutations and combinations or combined with one or more other examples.

[0057] The above detailed description includes references to the accompanying drawings, which form part of the detailed description. The drawings illustrate, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as “examples.” Such examples may include elements other than those shown or described. However, the inventors also contemplate examples providing only those elements shown or described. Furthermore, the inventors also contemplate examples of any combination or arrangement of those elements (or one or more aspects thereof) shown or described, or with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0058] In the event of any inconsistency between the usage in this document and any other document incorporated by reference, the usage in this document shall prevail.

[0059] In this document, the terms “a” or “some” are common in patent documents and are used to include one or more, independent of any other instances or uses of “at least one” or “one or more.” In this document, unless otherwise stated, the term “or” is used to refer to a non-exclusive or, for example, “A or B” includes “A but not B,” “B but not A,” and “A and B.” In this document, the terms “comprising” and “wherein” are used as simple equivalents of the corresponding terms “comprising” and “wherein.” Furthermore, in the following claims, the terms “comprising” and “including” are open-ended, meaning that a system, apparatus, article, composition, formulation, or process that includes elements in addition to those listed after the term in the claim is still considered to fall within the scope of that claim. Additionally, in the appended claims, terms such as “first,” “second,” and “third” are used merely as labels and do not impose numerical requirements on their objects.

[0060] The method examples described herein may be implemented, at least in part, by a machine or computer. Some examples may include computer-readable or machine-readable media encoded with instructions operable to configure an electronic device to perform the methods described in the examples above. Implementations of this method may include code, such as microcode, assembly language code, high-level language code, etc. Such code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. Furthermore, in one example, the code may be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, for example, during execution or at other times. Examples of such tangible computer-readable media may include, but are not limited to, hard disks, removable disks, removable optical disks (e.g., compact discs and digital video discs), magnetic tapes, memory cards or memory sticks, random access memory (RAM), read-only memory (ROM), etc.

[0061] The above description is intended to be illustrative and not restrictive. For example, the examples (or one or more aspects thereof) described above may be used in combination with each other. Other embodiments may be used, for example, by one of ordinary skill in the art after reading the above description. An abstract is provided to conform to 37C.FR §1.72(b) to enable the reader to quickly determine the nature of the technical disclosure. It is understood that this submission is not intended to interpret or limit the scope or meaning of the claims. Furthermore, in the detailed description above, various features may be combined together to simplify this disclosure. This should not be construed as meaning that any unclaimed disclosed feature is essential to any claim. Rather, the subject matter of the invention may lie in fewer than all features of a particular disclosed embodiment. Therefore, the following claims are hereby incorporated in the detailed description as examples or embodiments, each claim being an independent, separate embodiment, and these embodiments are contemplated to be combined with each other in various combinations or arrangements. The scope of the invention should be determined with reference to the appended claims and the full scope of the equivalents conferred by those claims.

Claims

1. A wide-bandwidth analog-to-digital converter circuit, including: A continuous-time Σ-Δ first analog-to-digital converter circuit has a first input coupled to a resistive element to receive a first analog input signal and to generate a first digital output signal; A second analog-to-digital converter circuit, independent of the first continuous-time Σ-Δ analog-to-digital converter circuit, has a second input and an output, the second input being coupled to a switched capacitor circuit to receive a second analog input signal, and the output being used to generate a second digital output signal independent of the first digital output signal; and A digital signal processor, coupled to receive the first digital output signal and the second digital output signal, and an output for generating at least one processed digital output signal.

2. The wide bandwidth analog-to-digital converter circuit of claim 1, comprising: The first channel is used to receive the first analog input signal. The continuous-time Σ-Δ first analog-to-digital converter circuit includes a first input. The second analog-to-digital converter circuit includes a second input and... The first input and the second input are coupled to the first channel.

3. The wide-bandwidth analog-to-digital converter circuit of claim 2, wherein the digital signal processor is used to combine the first digital output signal and the second digital output signal, and wherein the at least one processed digital output signal is a single combined digital output signal.

4. The wide bandwidth analog-to-digital converter circuit of claim 1, comprising: The first channel is used to receive the first analog input signal; and The second channel is used to receive the second analog input signal; The continuous-time Σ-Δ first analog-to-digital converter circuit includes a first input coupled to the first channel, and The second analog-to-digital converter circuit includes a second input coupled to the second channel.

5. The wide-bandwidth analog-to-digital converter circuit of claim 4, wherein the digital signal processor coupled to receive the first digital output signal and the second digital output signal and the output for generating at least one processed digital output signal is further coupled to: Receive the first digital output signal and generate a corresponding first-processed digital output signal; and Receive the second digital output signal and generate a corresponding second processed digital output signal.

6. The wide bandwidth analog-to-digital converter circuit of claim 4, comprising: An RC filter coupled to the second channel, the digital signal processor is used to combine the first digital output signal and the second digital output signal, wherein the digital output signal processed by at least one of them is a single combined digital output signal.

7. The wide-bandwidth analog-to-digital converter circuit of claim 1, wherein the continuous-time Σ-Δ first analog-to-digital converter circuit includes a first input coupled to a first channel, and wherein the second analog-to-digital converter circuit includes a second input coupled to a second channel, the wide-bandwidth analog-to-digital converter circuit further comprising: A continuous-time Σ-Δ third analog-to-digital converter circuit includes a third input coupled to a third channel and generates a third digital output signal, wherein the digital signal processor is used to receive the third digital output signal; The first channel is used to receive the first analog input signal; The second channel is used to receive the second analog input signal; The third channel is used to receive a third analog input signal; and A multiplexer includes inputs corresponding to the first channel, the second channel, and the third channel, and an output coupled to the input of the second analog-to-digital converter circuit. The multiplexer is used to select one of the first channel, the second channel, and the third channel.

8. The wide-bandwidth analog-to-digital converter circuit of claim 7, wherein the digital signal processor is coupled to receive the first digital output signal and the second digital output signal, and the output for generating at least one processed digital output signal is further coupled to: Receive the first digital output signal and generate a corresponding first-processed digital output signal; Receive the second digital output signal and generate a corresponding second-processed digital output signal; and Receive the third digital output signal and generate a corresponding third processed digital output signal.

9. The wide bandwidth analog-to-digital converter circuit of claim 1, wherein the second analog-to-digital converter circuit includes a switched capacitor input.

10. The wide bandwidth analog-to-digital converter circuit of claim 1, wherein the second analog-to-digital converter circuit includes a successive approximation register (SAR) analog-to-digital converter.

11. The wide bandwidth analog-to-digital converter circuit of claim 1, wherein the continuous-time Σ-Δ first analog-to-digital converter circuit or the second analog-to-digital converter circuit is configured to be intentionally disabled.

12. The wide bandwidth analog-to-digital converter circuit of claim 1, wherein the digital signal processor is used to generate a wake-up signal and apply it to the continuous-time Σ-Δ first analog-to-digital converter circuit or the second analog-to-digital converter circuit.

13. A method for operating a wide-bandwidth analog-to-digital converter circuit. The wide bandwidth analog-to-digital converter circuit is the wide bandwidth analog-to-digital converter circuit according to any one of claims 1-12; The method includes: A continuous-time Σ-Δ first analog-to-digital converter circuit is used to receive a first analog input signal and generate a first digital output signal; A second analog-to-digital converter circuit, independent of the first analog-to-digital converter circuit with a continuous-time Σ-Δ, receives the second analog input signal and generates a second digital output signal independent of the first digital output signal; and The first digital output signal and the second digital output signal are processed to generate at least one processed digital output signal.

14. The method of claim 13, wherein processing the first digital output signal and the second digital output signal and generating the at least one processed digital output signal comprises: A first processed digital output signal and a second processed digital output signal are generated, respectively corresponding to the first digital output signal and the second digital output signal.

15. The method of claim 13, comprising: The input signal applied to the wide-bandwidth analog-to-digital converter circuit is filtered using an RC filter coupled to the second analog-to-digital converter circuit.

16. The method of claim 13, comprising: A wake-up signal is generated and applied to the continuous-time Σ-Δ first analog-to-digital converter circuit or the second analog-to-digital converter circuit.

17. The method of claim 16, comprising: The amplitude of one of the processed first digital output signal and the processed second digital output signal is compared with a threshold. and A wake-up signal is generated in response to the amplitude exceeding a threshold and applied to the first analog-to-digital converter circuit or the second analog-to-digital converter circuit for the continuous time ∑-Δ.

18. A widebandwidth analog-to-digital converter circuit, including: A first continuous-time Σ-Δ analog-to-digital converter circuit has a first input coupled to a resistive element to receive a first analog input signal and to generate a first digital output signal; A second continuous-time Σ-Δ analog-to-digital converter circuit, independent of the first continuous-time Σ-Δ analog-to-digital converter circuit, has a second input and an output, the second input being coupled to a switched capacitor circuit to receive a second analog input signal, and the output being used to generate a second digital output signal independent of the first digital output signal; and A digital signal processor, coupled to receive the first digital output signal and the second digital output signal, and an output for generating at least one processed digital output signal.

19. The wide bandwidth analog-to-digital converter circuit of claim 18, comprising: The first channel that receives the first analog input signal. The first continuous-time Σ-Δ analog-to-digital converter circuit includes a first input. The second continuous-time Σ-Δ analog-to-digital converter circuit includes a second input, and The first input and the second input are coupled to the first channel.

20. The wide bandwidth analog-to-digital converter circuit of claim 18, comprising: The first channel that receives the first analog input signal; and The second channel that receives the second analog input signal. The first continuous-time Σ-Δ analog-to-digital converter circuit includes a first input coupled to the first channel, and The second continuous-time ∑-Δ analog-to-digital converter circuit includes a second input coupled to the second channel.

Images