Semiconductor element and electronic device

Abstract

A photodetector is provided. The photodetector includes: a first substrate, the first substrate including a first electrode, a semiconductor layer, a first insulating film, and a via; and a second substrate facing the first substrate and electrically connected to the semiconductor layer through the via. The semiconductor layer comprises a compound semiconductor material. The first electrode includes a first portion and a second portion. The first portion of the first electrode is in contact with the semiconductor layer, and the second portion is in contact with the first insulating film and the via.

Description

[0001] [Cross-references to related applications]

[0002] This application claims priority to Japanese priority patent application JP2019-219712, filed on December 4, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor element and an electronic device including the semiconductor element. The semiconductor element is used, for example, in an infrared sensor. Background Technology

[0004] Image sensors or infrared sensors sensitive to the infrared region have been commercialized. For example, Patent Document 1 discloses a semiconductor element. In this semiconductor element, the element substrate and the circuit substrate are bonded to each other by Cu-Cu bonding. In this element substrate, a compound semiconductor layer and a wiring layer are stacked on top of each other.

[0005] [List of cited references]

[0006] [Patent Literature]

[0007] [Patent Document 1] International Publication No. WO2018 / 194030 Summary of the Invention

[0008] [Technical Issues]

[0009] In such semiconductor devices as described above, there is currently a demand for improved electrical characteristics.

[0010] The aim is to provide a semiconductor element and electronic device that can improve electrical characteristics.

[0011] [Technical solution to the problem]

[0012] According to embodiments of this disclosure, a photodetector is provided. The photodetector includes: a first substrate, the first substrate including a first electrode, a semiconductor layer comprising a compound semiconductor material, a first insulating film, and a via; and a second substrate facing the first substrate and electrically connected to the semiconductor layer through the via. The first electrode includes a first portion and a second portion, the first portion of the first electrode contacting the semiconductor layer, and the second portion contacting the first insulating film and the via.

[0013] According to embodiments of this disclosure, a method for manufacturing a photodetector is provided. The method includes: forming a first substrate, the first substrate including a first electrode, a semiconductor layer comprising a compound semiconductor material, a first insulating film, and a via; and forming a second substrate facing the first substrate and electrically connected to the semiconductor layer through the via. The first electrode includes a first portion and a second portion, the first portion contacting the semiconductor layer, and the second portion contacting the first insulating film and the via.

[0014] According to embodiments of this disclosure, an electronic device is provided. The electronic device includes a photodetector. The photodetector includes: a first substrate, the first substrate including a first electrode, a semiconductor layer comprising a compound semiconductor material, a first insulating film, and a via; and a second substrate facing the first substrate and electrically connected to the semiconductor layer through the via. The first electrode includes a first portion and a second portion, the first portion contacting the semiconductor layer, and the second portion contacting the first insulating film and the via. According to this technology, the contact between the first electrode and the via, including a through-silicon via or a through-wire, can be improved. It should be understood that the effects described herein are not necessarily limiting, and the effects can be any of the effects described in the specification or effects different from those described herein. Attached Figure Description

[0015] The accompanying drawings are included to provide a further understanding of the technology, and are incorporated in and constitute a part of this specification. The drawings illustrate illustrative embodiments and, together with the specification, serve to explain various principles of the technology.

[0016] [ Figure 1 ]

[0017] Figure 1 This is a schematic cross-sectional view illustrating an example construction of an optical receiving element according to an embodiment of the present disclosure.

[0018] [ Figure 2 ]

[0019] Figure 2 It shows Figure 1 A schematic plan view of the general structure of the light receiving element shown.

[0020] [ Figure 3A ]

[0021] Figure 3A It shows Figure 1 The diagram shows a schematic cross-sectional view (A) and a schematic plan view (B) of the main part of the optical receiving element.

[0022] [ Figure 3B ]

[0023] Figure 3B It shows, as Figure 3A A schematic plan view of another example arrangement of the connecting parts and through holes shown.

[0024] [ Figure 3C ]

[0025] Figure 3C It shows, as Figure 3A A schematic plan view showing another example of the arrangement of the connecting parts and through holes.

[0026] [ Figure 3D ]

[0027] Figure 3D It shows, as Figure 3A A schematic plan view showing another example of the arrangement of the connecting parts and through holes.

[0028] [ Figure 3E ]

[0029] Figure 3E It shows, as Figure 3A A schematic plan view showing another example of the arrangement of the connecting parts and through holes.

[0030] [ Figure 4 ]

[0031] Figure 4 This is a characteristic graph showing the relationship between the film thickness of InP and the light absorption rate at various wavelengths, obtained through simulation.

[0032] [ Figure 5 ]

[0033] Figure 5 It shows Figure 1 A schematic diagram illustrating an example of the construction of a passivation film in a light-receiving element.

[0034] [ Figure 6A ]

[0035] Figure 6A It shows Figure 1 A schematic cross-sectional view of the steps in the manufacturing method of the light receiving element shown.

[0036] [ Figure 6B ]

[0037] Figure 6B It shows Figure 6A A schematic cross-sectional view of the subsequent steps.

[0038] [ Figure 6C ]

[0039] Figure 6C It shows Figure 6BA schematic cross-sectional view of the subsequent steps.

[0040] [ Figure 7 ]

[0041] Figure 7 It shows Figure 6C A schematic floor plan showing an example of the steps in the diagram.

[0042] [ Figure 8 ]

[0043] Figure 8 It shows Figure 7 A schematic plan view of another example of the construction of a semiconductor layer, shown in Figure 1.

[0044] [ Figure 9A ]

[0045] Figure 9A It shows Figure 7 A schematic plan view of another example of the construction of the semiconductor layer shown in Figure 2.

[0046] [ Figure 9B ]

[0047] Figure 9B It shows along Figure 9A A schematic diagram of the cross-sectional structure cut by line II-II'.

[0048] [ Figure 10A ]

[0049] Figure 10A It shows Figure 6C A schematic cross-sectional view of the subsequent steps.

[0050] [ Figure 10B ]

[0051] Figure 10B It shows Figure 10A A schematic cross-sectional view of the subsequent steps.

[0052] [ Figure 11A ]

[0053] Figure 11A It shows Figure 10A A schematic diagram illustrating an example of a planar construction of the steps shown.

[0054] [ Figure 11B ]

[0055] Figure 11B It shows Figure 10B A schematic diagram illustrating an example of a planar construction of the steps shown.

[0056] [ Figure 12A ]

[0057] Figure 12A It shows Figure 10A A schematic diagram of another example 1 of the planar construction of the steps shown.

[0058] [ Figure 12B ]

[0059] Figure 12B It shows Figure 10B A schematic diagram of another example 1 of the planar construction of the steps shown.

[0060] [ Figure 13A ]

[0061] Figure 13A It shows Figure 10A A schematic diagram of another example 2 of the planar construction of the steps shown.

[0062] [ Figure 13B ]

[0063] Figure 13B It shows Figure 10B A schematic diagram of another example 2 of the planar construction of the steps shown.

[0064] [ Figure 14 ]

[0065] Figure 14 It shows Figure 10B A schematic cross-sectional view of another example 1 of the steps shown.

[0066] [ Figure 15 ]

[0067] Figure 15 It shows Figure 10B A schematic cross-sectional view of another example 2 of the steps shown.

[0068] [ Figure 16A ]

[0069] Figure 16A It shows Figure 10B A schematic cross-sectional view of the steps following the steps shown.

[0070] [ Figure 16B ]

[0071] Figure 16B It shows Figure 16A A schematic cross-sectional view of the steps following the steps shown.

[0072] [ Figure 16C ]

[0073] Figure 16C It shows Figure 16B A schematic cross-sectional view of the steps following the steps shown.

[0074] [ Figure 16D ]

[0075] Figure 16D It shows Figure 16C A schematic cross-sectional view of the steps following the steps shown.

[0076] [ Figure 16E ]

[0077] Figure 16E It shows Figure 16D A schematic cross-sectional view of the steps following the steps shown.

[0078] [ Figure 16F ]

[0079] Figure 16F It shows Figure 16E A schematic cross-sectional view of the steps following the steps shown.

[0080] [ Figure 16G ]

[0081] Figure 16G It shows Figure 16F A schematic cross-sectional view of the steps following the steps shown.

[0082] [ Figure 16H ]

[0083] Figure 16H It shows Figure 16G A schematic cross-sectional view of the steps following the steps shown.

[0084] [ Figure 16I ]

[0085] Figure 16I It shows Figure 16H A schematic cross-sectional view of the steps following the steps shown.

[0086] [ Figure 16J ]

[0087] Figure 16J It shows Figure 16I A schematic cross-sectional view of the steps following the steps shown.

[0088] [ Figure 16K ]

[0089] Figure 16K It shows Figure 16J A schematic cross-sectional view of the steps following the steps shown.

[0090] [ Figure 17A ]

[0091] Figure 17AThis is a schematic cross-sectional view of a variation of Example 1 of this disclosure, showing... Figure 1 Another example of a method for manufacturing a light-receiving element.

[0092] [ Figure 17B ]

[0093] Figure 17B It shows Figure 17A A schematic cross-sectional view of the steps following the steps shown.

[0094] [ Figure 18A ]

[0095] Figure 18A This is a schematic cross-sectional view of a variation of this disclosure, showing... Figure 1 Another example of a method for manufacturing the light receiving element shown.

[0096] [ Figure 18B ]

[0097] Figure 18B It shows Figure 18A A schematic cross-sectional view of the steps following the steps shown.

[0098] [ Figure 18C ]

[0099] Figure 18C It shows Figure 18B A schematic cross-sectional view of the steps following the steps shown.

[0100] [ Figure 18D ]

[0101] Figure 18D It shows Figure 18C A schematic cross-sectional view of the steps following the steps shown.

[0102] [ Figure 18E ]

[0103] Figure 18E It shows Figure 18D A schematic cross-sectional view of the steps following the steps shown.

[0104] [ Figure 18F ]

[0105] Figure 18F It shows Figure 18E A schematic cross-sectional view of the steps following the steps shown.

[0106] [ Figure 19 ]

[0107] Figure 19 This is a schematic cross-sectional view showing a construction example of the light receiving element according to Modification 3 of the present disclosure.

[0108] [ Figure 20 ]

[0109] Figure 20 It is a block diagram showing the structure of the camera device.

[0110] [ Figure 21 ]

[0111] Figure 21 This is a schematic diagram illustrating an example of the construction of a stacked camera device.

[0112] [ Figure 22 ]

[0113] Figure 22 It shows including Figure 20 The diagram shows an operational block diagram of an exemplary electronic device (e.g., a camera) with a camera device.

[0114] [ Figure 23 ]

[0115] Figure 23 This is a diagram illustrating an example of a schematic construction of an endoscopic surgical system.

[0116] [ Figure 24 ]

[0117] Figure 24 This is a block diagram illustrating an example of the functional structure of a camera and camera control unit (CCU).

[0118] [ Figure 25 ]

[0119] Figure 25 This is a block diagram illustrating an example of a schematic construction of a vehicle control system.

[0120] [ Figure 26 ]

[0121] Figure 26 This diagram illustrates the installation locations of the vehicle exterior information detection unit and the camera unit. Detailed Implementation

[0122] In the following detailed description, some embodiments of the present disclosure are illustrated with reference to the accompanying drawings. The embodiments described below are specific but non-limiting examples of the present disclosure, and the present disclosure is not limited to the aspects described below. The present disclosure is also not limited to the arrangement, dimensions, aspect ratios, and other factors of the components shown in the drawings. It should be noted that the description is given in the following order.

[0123] 1. Example: A light-receiving element in which a through-hole is connected to a generally planar surface of an extension of the first electrode.

[0124] 1-1. Structure of a light receiving element

[0125] 1-2. Manufacturing method of optical receiving element

[0126] 1-3. Operation of the optical receiving element

[0127] 1-4. Functions and Effects

[0128] 2. Variations

[0129] 2-1. Variation Example 1: Another example of a manufacturing method

[0130] 2-2. Variation Example 2: Another example of a manufacturing method

[0131] 2-3. Variation Example 3: An example of a light-receiving element including a color filter and a lens on the chip on the side closer to the light incident surface.

[0132] 3. Applicable Examples

[0133] 4. Application Examples

[0134] (1. Example)

[0135] Figure 1 An example of a cross-sectional structure of a semiconductor element (light receiving element 1) according to an embodiment of the present disclosure is shown schematically. Figure 2 schematically shown Figure 1 The light receiving element 1 shown has a planar structure. It should be noted that... Figure 1 It shows along Figure 2 The cross-sectional structure shown is taken by line I-I'. The light-receiving element 1 is applied, for example, to an infrared sensor containing a compound semiconductor material (e.g., a III-V semiconductor). The light-receiving element 1 photoelectrically converts light into light with wavelengths ranging from the visible region (e.g., greater than or equal to 380 nm and less than 780 nm) to the short infrared region (e.g., greater than or equal to 780 nm and less than 2400 nm). The light-receiving element 1 has multiple light-receiving unit regions, for example, serving as pixels P arranged in a two-dimensional configuration.

[0136] (1-1. Construction of a light receiving element)

[0137] like Figure 1 As shown, the light receiving element 1 has a stacked structure of an element substrate 10 and a readout circuit substrate 20. The element substrate 10 has one side that serves as a light incident surface S1 and another side that is opposite to the light incident surface S1 and serves as a bonding surface S2 with the readout circuit substrate 20.

[0138] The component substrate 10, adjacent to the readout circuit substrate 20, sequentially includes a wiring layer 10W, a first electrode 11, a semiconductor layer 10S, a second electrode 15, and passivation films 16A and 16B. The semiconductor layer 10S has an opposing surface and an end surface (side surface) facing the wiring layer 10W. The opposing surface and end surface are covered by insulating films 17A and 17B. The readout circuit substrate 20 is a so-called read-out integrated circuit (ROIC). The readout circuit substrate 20 includes a wiring layer 20W, a multilayer wiring layer 22C, and a semiconductor substrate 21 that are in contact with the bonding surface S2 of the component substrate 10. The semiconductor substrate 21 faces the component substrate 10 across the wiring layer 20W and the multilayer wiring layer 22C.

[0139] The component substrate 10 has a component region R1 at its central portion. Component region R1 serves as a light-receiving region. A semiconductor layer 10S is disposed in component region R1. In other words, component region R1 represents the region in which the semiconductor layer 10S is disposed. Component region R1 includes an optical black (OPB) region R1B, which is adjacent to the peripheral region R2 and covered by a conductive film 15B. The OPB region R1B is disposed in a manner that surrounds the light-receiving region. The OPB region R1B is used to acquire pixel signals at black levels.

[0140] A peripheral region R2 is disposed outside and surrounds the component region R1. A buried layer 18 is disposed in the peripheral region R2 of the component substrate 10 together with insulating films 17A and 17B. Through-holes H1 and H2 are also disposed in the peripheral region R2. Through-holes H1 and H2 pass through the component substrate 10 and reach the readout circuit substrate 20. In the light receiving element 1, light is output from the light incident surface S1 of the component substrate 10 to the semiconductor layer 10S via passivation films 16A and 16B, the second electrode 15, and the second contact layer 14. The signal charge that has undergone photoelectric conversion in the semiconductor layer 10S moves to the readout circuit substrate 20 via the wiring layer 10W. Then, the readout circuit substrate 20 reads the signal charge. The structure of these components will now be described herein.

[0141] The wiring layer 10W is disposed across the component region R1 and the peripheral region R2. The wiring layer 10W includes a bonding surface S2 with the readout circuit board 20. In the light receiving element 1 in which the bonding surface S2 of the component board 10 is disposed across the component region R1 and the peripheral region R2, for example, the bonding surface S2 is flush with the component region R1 and the peripheral region R2.

[0142] The wiring layer 10W includes, for example, contact electrodes 19E and dummy electrodes 19ED in the interlayer insulating films 19A and 19B. In the wiring layer 10W, for example, the interlayer insulating film 19B is disposed adjacent to the readout circuit board 20, and the interlayer insulating film 19A is disposed adjacent to the first contact layer 12. The interlayer insulating films 19A and 19B are stacked on top of each other. The interlayer insulating films 19A and 19B each comprise, for example, an inorganic insulating material. Non-limiting examples of inorganic insulating materials include, for example, silicon nitride (SiN), aluminum oxide (Al2O3), silicon oxide (SiO2), and hafnium oxide (HfO2). The interlayer insulating films 19A and 19B may comprise the same inorganic insulating material.

[0143] Contact electrodes 19E are provided, for example, in component region R1. Contact electrodes 19E are electrically connected to the first electrode 11 and the readout circuit board 20. Contact electrodes 19E are provided in each pixel P within component region R1. Adjacent contact electrodes 19E are electrically separated by a buried layer 18 and interlayer insulating films 19A and 19B. For example, contact electrodes 19E include copper (Cu) pads. Contact electrodes 19E are exposed on the bonding surface S2. For example, dummy electrodes 19ED are provided in peripheral region R2. Dummy electrodes 19ED are connected to each dummy electrode 22ED in wiring layer 20W, described later. The dummy electrodes 19ED and dummy electrodes 22ED provided as described above can improve the strength of peripheral region R2. Dummy electrodes 19ED and contact electrodes 19E are formed, for example, in a single step. For example, dummy electrodes 19ED include copper (Cu) pads. Dummy electrodes 19ED are exposed on the bonding surface S2.

[0144] A first electrode 11, disposed between the contact electrode 19E and the semiconductor layer 10S, serves as an electrode or anode to receive a voltage for reading signal charges generated in the photoelectric conversion layer 13. The signal charges can be holes or electrons. Hereinafter, for convenience, the signal charges will be described as holes. The first electrode 11 is disposed in each pixel P within the element region R1. The first electrode 11 is configured to fill each opening 17H of the insulating film 17A. The first electrode 11 is in contact with the semiconductor layer 10S, and more specifically, with each diffusion region 12A, which will be described later.

[0145] Figure 3A The main parts of the light receiving element 1 according to this embodiment are schematically shown. That is, Figure 3AThe cross-sectional structure (A) and planar structure (B) of the connection portion and its peripheral portion between the first electrode 11 and the contact electrode 19E are schematically shown. In the planar view, the shape of the first electrode 11 has a size larger than the shape of the opening 17H of the insulating film 17A. The first electrode 11 is partially disposed in the buried layer 18. In other words, the first electrode 11 includes a connection portion 11X and an extension portion 11Y. The connection portion 11X contacts the semiconductor layer 10S in the opening 17H. The insulating film 17A is located between the semiconductor layer 10S and the extension portion 11Y.

[0146] The extension portion 11Y is formed to extend around the connecting portion 11X. Figure 3A In one example shown in part (B), the first electrode 11 has a generally rectangular shape in the plan view. The first electrode 11 is formed asymmetrically, for example, around the connection portion 11X and the opening 17H. That is, the first electrode 11 is located at a position offset relative to the connection portion 11X and the opening 17H, for example, along the X-axis direction. By forming the extension portion 11Y asymmetrically with respect to the connection portion 11X, area efficiency can be improved. For example, the first electrode 11 has a surface facing the bonding surface S2 and is generally planar except for the portion above the generally circular opening 17H. Above the opening 17H, a generally circular recess is formed as a recess 11C. That is, the extension portion 11Y is formed on the insulating film 17A such that the width W1 from one peripheral portion of the recess 11C to one end of a pair of opposite sides of the extension portion 11Y in the X-axis direction is different from the width W2 from the other peripheral portion of the recess 11C to one end of the other pair of opposite sides of the extension portion 11Y. For example, the width W1 is greater than the width W2 (W1>W2).

[0147] In this embodiment, as Figure 3A As shown, a through-hole 19V extending from the contact electrode 19E connects to the extension portion 11Y of the first electrode 11. Therefore, the first electrode 11 and the contact electrode 19E are electrically connected to each other. In particular, when the extension portion 11Y is formed asymmetrically with respect to the connecting portion 11X, as... Figure 1 and Figure 3A As shown, for example, via 19V is connected to a relatively wide region W1 along the extension 11Y. The first electrode 11 and the contact electrode 19E are electrically connected to each other via the wider region. Via 19V corresponds to a specific example, but not a limiting example, of a “through wiring” and / or a “through silicon via” in the embodiments of this disclosure.

[0148] As described above, the through-hole 19V, connected to the extension 11Y of the first electrode 11, connects the first electrode 11 and the contact electrode 19E to each other. This configuration improves the ease of contact between the first electrode 11 and the through-hole 19V. The extension 11Y at the connection point between the first electrode 11 and the through-hole 19V also reduces the area of ​​the opening 17H through which the first electrode 11 and the semiconductor layer 10S are electrically connected. This helps prevent the generation of dark current. Furthermore, the extension 11Y is asymmetrically formed on the insulating film 17A, with a wider area connected to the through-hole 19V. This configuration increases the diameter of the through-hole 19V, thus reducing the contact resistance between the first electrode 11 and the contact electrode 19E.

[0149] It should be noted that this disclosure is not limited to, for example Figure 3A The example shown illustrates this. In this example, each first electrode 11 has a connection portion 11X and is connected to a through-hole 19V. Alternatively, each first electrode 11 may have two or more connection portions 11X and / or may be connected to two or more through-holes 19V. In the example where each first electrode 11 has two or more connection portions 11X and is connected to two or more through-holes 19V, electrical connection can be ensured even if one of the connection portions 11X and the through-holes 19V is disconnected. In embodiments, the electrode area of ​​the first electrode 11 can be reduced to minimize the capacitance of the first electrode 11. For example, the size and / or shape of the first electrode 11 can be changed. The first electrode 11 may have a square, rectangular, or circular shape that at least covers the through-hole 19V and the opening 17H / connection portion 11X.

[0150] The first electrode 11 is, for example, a metal of titanium (Ti), tungsten (W), titanium nitride (TiN), platinum (Pt), gold (Au), germanium (Ge), palladium (Pd), zinc (Zn), nickel (Ni), or aluminum (Al), or a metal alloy comprising at least one of these. The first electrode 11 can be a single-layer film comprising the constituent materials described above. The first electrode 11 can also be a multilayer film comprising two or more of the constituent materials described above. For example, the first electrode 11 is a multilayer film comprising titanium and tungsten. For example, the thickness of the first electrode 11 varies from tens of nanometers to hundreds of nanometers.

[0151] Semiconductor layer 10S, for example, includes a first contact layer 12, a photoconversion layer 13, and a second contact layer 14, starting from a position adjacent to wiring layer 10W. In a plan view, the first contact layer 12, photoconversion layer 13, and second contact layer 14 each have the same planar shape and end faces disposed at the same positions.

[0152] For example, a first contact layer 12 is provided across all pixels P. The first contact layer 12 is disposed between the insulating film 17A and the photoelectric conversion layer 13. The first contact layer 12 electrically separates adjacent pixels P. In the first contact layer 12, for example, a plurality of diffusion regions 12A are provided. In the first contact layer 12, dark current can be suppressed by using a compound semiconductor material with a band gap larger than that of the compound semiconductor material contained in the photoelectric conversion layer 13. The first contact layer 12 may include, for example, n-type indium phosphide (InP).

[0153] The diffusion regions 12A disposed in the first contact layer 12 are separated from each other. A diffusion region 12A is disposed in each pixel P. A first electrode 11 is connected to the diffusion region 12A. The OPB region R1B also includes the diffusion region 12A. The diffusion regions 12A are used to read the signal charge generated in the photoelectric conversion layer 13 from each pixel P. The diffusion regions 12A include, for example, p-type impurities. Non-limiting examples of p-type impurities include zinc (Zn). As described above, pn bonding interfaces are formed between the diffusion regions 12A and the first contact layer 12 (excluding the diffusion regions 12A) to electrically isolate adjacent pixels P. The diffusion regions 12A are disposed, for example, in the thickness direction of the first contact layer 12. The diffusion regions 12A are also partially disposed in the thickness direction of the photoelectric conversion layer 13.

[0154] A photoelectric conversion layer 13 is disposed between the first electrode 11 and the second electrode 15, and more specifically, between the first contact layer 12 and the second contact layer 14, for example, across all pixels P. The photoelectric conversion layer 13 absorbs light of a predetermined wavelength and generates a signal charge. The photoelectric conversion layer 13 includes, for example, a compound semiconductor material such as a type III-V semiconductor. Non-limiting examples of compound semiconductor materials included in the photoelectric conversion layer 13 include, for example, indium gallium arsenide (InGaAs), indium antimony arsenide (InAsSb), indium arsenide (InAs), indium antimonide (InSb), and mercury cadmium telluride (HgCdTe). The photoelectric conversion layer 13 may include germanium (Ge). In the photoelectric conversion layer 13, light of wavelengths from the visible region to the short infrared region is photoelectrically converted, for example.

[0155] For example, a second contact layer 14 is disposed together across all pixels P. The second contact layer 14 is disposed between the photoelectric conversion layer 13 and the second electrode 15, and is in contact with the photoelectric conversion layer 13 and the second electrode 15. Charge discharged from the second electrode 15 moves to the second contact layer 14. The second contact layer 14 includes, for example, a compound semiconductor containing n-type impurities. The second contact layer 14 may include, for example, n-type indium phosphide (InP).

[0156] It should be noted that the light absorption rate of the compound semiconductor contained in the second contact layer 14 varies with wavelength. Therefore, by adjusting the film thickness of the second contact layer 14, light with wavelengths within the desired wavelength band can reach the photoelectric conversion layer 13. For example, Figure 4 This is a characteristic graph showing the relationship between the thickness of the simulated InP film and the light absorption rate at various wavelengths. To allow light in the visible region to reach the photoelectric conversion layer 13, the thickness of the second contact layer 14 is preferably in the range of 5 nm to 300 nm. A second contact layer (InP film) 14 with a thickness within this range allows visible light with a wavelength of 600 nm to pass through with a light absorption rate of 0% to 90%. To allow only light in the short infrared region to reach the photoelectric conversion layer 13, the thickness of the second contact layer 14 only needs to be in the range of 5 nm to 750 μm. By adjusting the thickness of the second contact layer 14 as described above, both light in the visible region and light in the short infrared region can undergo photoelectric conversion in the photoelectric conversion layer 13.

[0157] Similar to the second contact layer 14, the light absorption rate of the photoelectric conversion layer 13, which contains a compound semiconductor, also varies with wavelength. Therefore, in order to enable photoelectric conversion of blue light with a wavelength of 400 nm (used as light in the visible region) in the photoelectric conversion layer 13, it is preferable that the thickness of the photoelectric conversion layer 13 is, for example, 100 nm or more. Similarly, in order to enable photoelectric conversion of light with wavelengths in the short infrared region, it is preferable that the thickness of the photoelectric conversion layer 13 is, for example, 3 μm or more. Furthermore, in order to enable photoelectric conversion of light with wavelengths in the region from the visible region to the short infrared region, it is preferable that the thickness of the photoelectric conversion layer 13 is, for example, in the range of 500 nm to 6 μm.

[0158] The second electrode 15 serves as a common electrode for, for example, pixel P. The second electrode 15 is disposed on and in contact with the light-incident side of the second contact layer 14. The second electrode 15 serves as a cathode to discharge charges generated in the photoelectric conversion layer 13 that are not used as signal charges. For example, when holes, which are signal charges, are read from the first electrode 11, the second electrode 15 discharges electrons. The second electrode 15 includes, for example, a conductive film that allows incident light, such as infrared light, to pass through. The second electrode 15 may include, for example, indium tin oxide (ITO) or ITiO (In₂O₃-TiO₂).

[0159] Passivation films 16A and 16B cover the second electrode 15 from the light incident surface S1 side. Preferably, passivation films 16A and 16B each contain a material that does not absorb light in the region from the visible region (e.g., above 380 nm and below 780 nm) to the short infrared region (e.g., above 780 nm and below 2400 nm). Passivation films 16A and 16B may contain the same material. Alternatively, passivation films 16A and 16B may each contain different materials. Furthermore, passivation films 16A and 16B may have anti-reflection properties. Passivation films 16A and 16B can be formed by, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or coating methods.

[0160] As described above, a passivation film 16A is disposed on the second electrode 15. The passivation film 16A extends to, for example, the chip end E in the peripheral region R2. The passivation film 16A has an opening 16H in the OPB region R1B. For example, as... Figure 2 As shown, the opening 16H has a frame shape that surrounds the light-receiving region. Alternatively, for example in a plan view, the opening 16H can be a square or circular hole. The conductive film 15B, described later, is electrically connected to the second electrode 15 via the opening 16H of the passivation film 16A.

[0161] Preferably, the passivation film 16A comprises a non-reducing material. Non-limiting examples of non-reducing materials include, for example, oxides (M... x O y ), nitrides (M) x N y ) and nitrogen oxides (M x O y N z For example, M represents, for example, silicon (Si), titanium (Ti), hafnium (Hf), zirconium (Zr), or yttrium (Y). The letters x, y, and z represent integers of 1 or greater. For silicon nitride (SiN), it is desirable to apply a film-forming method that does not use a reducing gas. Non-limiting examples of such film-forming methods include, for example, sputtering and coating. For example, passivation film 16A can be formed as a monolayer containing the above-described materials. Preferably, in order to set passivation film 16A as a monolayer, the monolayer has a density of 2.0 g / cm³. 3 The above refers to membrane densities. No specific upper limit is specified for membrane density. For example, membrane density can be equal to or less than 8.0 g / cm³. 3 It is important to note that membrane density is defined by the following expression: the mass of the membrane divided by the volume of the membrane (g / cm³). 3 For example, the film density is obtained by measuring X-ray reflectance (XRR). Therefore, the passivation film 16A has sealing properties. Alternatively, the passivation film 16A can be formed as a multilayer film. Furthermore, as... Figure 5As shown, the passivation film 16A can be a multilayer film containing three or more layers (i.e., films 16A1, 16A2, 16A3, 16A4 to 16AX) stacked on the second electrode 15.

[0162] Passivation film 16B is configured to cover passivation film 16A and conductive film 15B. For example, similar to passivation film 16A, passivation film 16B extends to the chip end E in the peripheral region R2. For example, passivation film 16B may comprise silicon nitride (SiN), aluminum oxide (Al2O3), silicon oxide (SiO2), or tantalum oxide (Ta2O3). It should be noted that no specific method is specified for forming the silicon nitride (SiN) film when forming passivation film 16B. Passivation film 16B may be a silicon nitride (SiN) film formed by plasma CVD using a reducing gas, instead of sputtering and coating methods.

[0163] Insulating films 17A and 17B are disposed between the first contact layer 12 and the buried layer 18. Specifically, insulating film 17A covers the opposing surface of the first contact layer 12 facing the wiring layer 10W. Insulating film 17A further covers the end face of the first contact layer 12, the end face of the photoelectric conversion layer 13, the end face of the second contact layer 14, and the end face of the second electrode 15. In the peripheral region R2, insulating film 17A is in contact with passivation films 16A and 16B. Insulating film 17B is disposed along and in contact with the first electrode 11 and insulating film 17A. In other words, insulating film 17B covers the bonding surface of the first contact layer 12 across the first electrode 11 and insulating film 17A. Insulating film 17B also covers the end face of the first contact layer 12, the end face of the photoelectric conversion layer 13, the end face of the second contact layer 14, and the end face of the second electrode 15 across insulating film 17A. In the peripheral region R2, for example, insulating film 17B extends together with insulating film 17A to the chip end E. More specifically, the insulating film 17B covers the end face of the first contact layer 12, the end face of the photoelectric conversion layer 13, and the end face of the second contact layer 14, separated by the insulating film 17A retained on the side of the semiconductor layer 10S and the metal film 11A described later.

[0164] For example, insulating film 17A contains materials such as silicon oxide (SiO2). XThe insulating film 17A may be an oxide such as aluminum oxide (Al2O3). The insulating film 17A may have a layered structure comprising multiple films. For example, the insulating film 17A may contain silicon (Si)-based insulating materials such as silicon oxynitride (SiON), silicon carbon oxide (SiOC), silicon nitride (SiN), or silicon carbide (SiC). For example, the thickness of the insulating film 17A is in the range of tens of nm to hundreds of nm. It is desirable that the insulating film 17B contains a material with high passivation properties among the aforementioned insulating materials used as the material of the insulating film 17A. For example, it is desirable to use silicon nitride (SiN). Therefore, the protective performance of the semiconductor layer 10S can be improved. For example, the thickness of the insulating film 17B is in the range of 100 nm to 200 nm.

[0165] The conductive film 15B extends from the OPB region R1B to a through-hole H1 in the peripheral region R2. The conductive film 15B contacts the second electrode 15 via an opening 16H of the passivation film 16A disposed in the OPB region R1B. The conductive film 15B also contacts the wiring (wiring 22CB described later) of the readout circuit board 20 via the through-hole H1. Therefore, voltage is supplied from the readout circuit board 20 to the second electrode 15 via the conductive film 15B. As described above, the conductive film 15B serves as a path for supplying voltage to the second electrode 15. The conductive film 15B also serves as a light-shielding film. The conductive film 15B forms the OPB region R1B. For example, the conductive film 15B contains a metallic material such as tungsten (W), aluminum (Al), titanium (Ti), molybdenum (Mo), tantalum (Ta), or copper (Cu). The passivation film 16B may be disposed on the conductive film 15B.

[0166] An adhesive layer B may be disposed between the end of the second contact layer 14 and the end of the second electrode 15. As described later, the adhesive layer B is used to form the light-receiving element 1. The adhesive layer B bonds the semiconductor layer 10S to the [other electrode described later]. Figure 6C The temporary substrate 33 is shown. For example, the adhesive layer B comprises tetraethoxysilane (TEOS) or silicon oxide (SiO). For example, the width of the adhesive layer B is greater than the width of the end face of the semiconductor layer 10S. The adhesive layer B and the semiconductor layer 10S are covered by a buried layer 18. Insulating films 17A and 17B are disposed between the adhesive layer B and the buried layer 18.

[0167] The adhesive layer B can extend across most of the peripheral region R2. For example, the adhesive layer B can extend from a location adjacent to the edge of the semiconductor layer 10S (i.e., the device region R1) to various locations between the vias H1 and H2. The adhesive layer B can also extend from a location adjacent to the edge of the semiconductor layer 10S (i.e., the device region R1) to the chip edge (i.e., the chip edge E).

[0168] In the manufacturing steps of the light receiving element 1, the semiconductor layer 10S and the layer described later... Figure 6CThe step gap between the temporary substrates 33 shown is filled by the buried layer 18. As will be explained in detail later, the buried layer 18 formed as described above suppresses the inconvenience caused by the step gap between the semiconductor layer 10S and the temporary substrate 33 during the manufacturing process.

[0169] In the peripheral region R2, a buried layer 18 is disposed between the wiring layer 10W and the insulating film 17B, and between the wiring layer 10W and the passivation film 16A. For example, the thickness of the buried layer 18 is greater than the thickness of the semiconductor layer 10S. In this embodiment, the buried layer 18 is configured to surround the semiconductor layer 10S, thereby forming a peripheral region R2 surrounding the semiconductor layer 10S. Therefore, a bonding surface S2 with the readout circuit board 20 can be provided in the peripheral region R2. With the bonding surface S2 formed in the peripheral region R2, the thickness of the buried layer 18 can be reduced. However, it is desirable that the buried layer 18 covers the semiconductor layer 10S in the thickness direction. It is further desirable that the buried layer 18 completely covers the end face of the semiconductor layer 10S. The buried layer 18, which completely covers the end face of the semiconductor layer 10S via the insulating films 17A and 17B, can effectively suppress moisture from entering the semiconductor layer 10S. In the element region R1, the buried layer 18 is disposed between the semiconductor layer 10S and the wiring layer 10W to cover the first electrode 11.

[0170] The buried layer 18 has a planarized surface facing the mating surface S2. A wiring layer 10W is disposed along the planarized surface of the buried layer 18 in the peripheral region R2. The buried layer 18 may contain inorganic insulating materials such as silicon oxide (SiOX), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonate (SiOC), or silicon carbide (SiC).

[0171] In the manufacturing steps of the optical receiving element 1, as described later... Figure 16E As shown, a buried layer 18 is first formed, and then a wiring layer 10W, including interlayer insulating films 19A and 19B and contact electrodes 19E, is formed on top of the buried layer 18. (As described later...) Figure 16FAs shown, a readout circuit substrate 20 including a wiring layer 20W is bonded to a component substrate 10 including a wiring layer 10W to form a photoreceiving element 1. Contact electrodes 19E in wiring layer 10W and 22E in wiring layer 20W are connected to each other. For example, both contact electrodes 19E and 22E include Cu pads. Since the Cu pads are directly bonded to each other, contact electrodes 19E and 22E are connected to each other. To form contact electrodes 19E using chemical mechanical polishing (CMP), the buried layer 18 disposed under the copper film to be polished should be sufficiently hard to withstand the stress during polishing. To directly bond the Cu pads of contact electrodes 19E and 22E to each other, the component substrate 10 and the readout circuit substrate 20 should be highly planarized. Therefore, it is desirable that the buried layer 18 disposed under the copper film be sufficiently hard to withstand the stress during polishing. Specifically, it is desirable that the constituent material of the buried layer 18 is a material with a higher hardness than the sealant or organic material disposed around a die in a typical semiconductor package. Non-limiting examples of such high-hardness materials include inorganic insulating materials. For example, a film of such an inorganic insulating material can be formed by chemical vapor deposition (CVD), sputtering, or other coating methods, allowing the formation of a buried layer 18. However, in another embodiment, the component substrate 10 and the readout circuit substrate 20 are electrically connected via bump electrodes. Therefore, charge signals generated from the photoelectric conversion layer 13 are transmitted to the readout circuit substrate 20 via the bump electrodes. In the component substrate 10 or readout circuit substrate 20 according to different embodiments, bump electrodes may be disposed on the surface of the component substrate 10.

[0172] The buried layer 18 includes through-holes H1 and H2 extending through the buried layer 18. The through-holes H1 and H2 extend through the wiring layer 10W and the buried layer 18 to the readout circuit board 20. For example, the through-holes H1 and H2 have a square planar shape. Figure 2 As shown, through-holes H1 and H2 are arranged around the component region R1. Through-hole H1 is located closer to the component region R1 than through-hole H2. A conductive film 15B covers the sidewalls and bottom surface of through-hole H1. The conductive film 15B of the second electrode 15 and the wiring 22CB of the readout circuit board 20 (described later) are connected to each other via through-hole H1. Through-hole H1 extends through the passivation film 16A, the buried layer 18, and the wiring layer 10W.

[0173] For example, via H2 is located closer to the chip end E than via H1. Via H2 extends through passivation films 16A and 16B, buried layer 18, and wiring layer 10W to the pad electrode 22P of the readout circuit substrate 20 (described later). The light receiving element 1 achieves external electrical connection via via H2. Alternatively, vias H1 and H2 may not extend to the readout circuit substrate 20. For example, vias H1 and H2 may extend to wiring in wiring layer 10W. Wiring may connect to wiring 22CB and pad electrode 22P in readout circuit substrate 20. As described above, vias H1 and H2 may extend through adhesive layer B from a position adjacent to the edge of semiconductor layer 10S (i.e., element region R1) to a position between vias H1 and H2, or to the chip end (i.e., chip end E).

[0174] Holes and electrons generated in the photoelectric conversion layer 13 are read out from the first electrode 11 and the second electrode 15. To perform this readout at high speed, it is desirable that the first electrode 11 and the second electrode 15 be positioned at a sufficient distance for photoelectric conversion to avoid excessive separation between them. That is, it is desirable to reduce the thickness of the element substrate 10. For example, the distance between the first electrode 11 and the second electrode 15, or the thickness of the element substrate 10, is preferably 10 μm or less, more preferably 7 μm or less, or even more preferably 5 μm or less.

[0175] The semiconductor substrate 21 of the readout circuit substrate 20 faces the component substrate 10 across a wiring layer 20W and a multilayer wiring layer 22C. For example, the semiconductor substrate 21 comprises silicon (Si). Multiple transistors are disposed near the surface of the semiconductor substrate 21 facing the wiring layer 20W. For example, the multiple transistors are used to form the readout circuitry in each pixel P. For example, the wiring layer 20W includes interlayer insulating films 22A and 22B stacked sequentially starting from the side adjacent to the component substrate 10. For example, contact electrodes 22E and dummy electrodes 22ED are disposed in the interlayer insulating film 22A. The multilayer wiring layer 22C is positioned facing the component substrate 10 across the wiring layer 20W. For example, pad electrodes 22P and multiple wiring lines 22CB are disposed in the multilayer wiring layer 22C. For example, both interlayer insulating films 22A and 22B comprise inorganic insulating materials. For example, non-limiting examples of inorganic insulating materials include silicon nitride (SiN), aluminum oxide (Al2O3), silicon oxide (SiO2), and hafnium oxide (HfO2).

[0176] Contact electrodes 22E electrically connect the first electrode 11 and the wiring 22CB to each other. Contact electrodes 22E are disposed in each pixel P within the element region R1. Contact electrodes 22E contact each contact electrode 19E at the bonding surface S2 of the element substrate 10. An interlayer insulating film 22A electrically separates adjacent contact electrodes 22E.

[0177] The dummy electrode 22ED disposed in the peripheral region R2 contacts each dummy electrode 19ED at the bonding surface S2 of the component substrate 10. For example, the dummy electrode 22ED and the contact electrode 22E are formed in one step. For example, both the contact electrode 22E and the dummy electrode 22ED include copper (Cu) pads. The contact electrode 22E and the dummy electrode 22ED are exposed on the opposing surface of the readout circuit board 20. This opposing surface faces the component substrate 10. That is, for example, the contact electrode 19E and the contact electrode 22E, as well as the dummy electrode 19ED and the dummy electrode 22ED, are bonded to each other by Cu-Cu bonding respectively. As will be explained in detail later, this bonding can therefore allow for finer pixel P.

[0178] Wiring 22CB connected to each contact electrode 19E is connected to each transistor disposed adjacent to the surface of the semiconductor substrate 21. The first electrode 11 and the readout circuit are connected to each other in each pixel P. For example, wiring 22CB connected to the conductive film 15B via through-hole H1 has a predetermined potential. As described above, for example, the readout circuit reads out holes in the charge generated in the photoelectric conversion layer 13 from the first electrode 11 via contact electrodes 19E and 22E. The remaining charge (i.e., electrons) generated in the photoelectric conversion layer 13 is discharged from the second electrode 15 via the conductive film 15B at a predetermined potential.

[0179] The pad electrode 22P disposed in the peripheral region R2 allows for external electrical connection. A through-hole H2 extending through the component substrate 10 to the pad electrode 22P is positioned adjacent to the chip end E of the light-receiving element 1. Therefore, external electrical connection is achieved via the through-hole H2. For example, this connection can be achieved using a wiring method or a bump method. For example, a predetermined potential can be supplied from external terminals arranged within each through-hole H2 via the through-hole H2, the wiring 22CB of the readout circuit substrate 20, and the conductive film 15B to the second electrode 15. As a result of photoelectric conversion in the photoelectric conversion layer 13, the readout circuit in the semiconductor substrate 21 can read the signal voltage read from each of the first electrodes 11 via contact electrodes 19E and 22E. The signal voltage can be output via the readout circuit to the external terminals arranged within each through-hole H2. For example, the signal voltage can be output to the external terminals via the readout circuit and other circuits included in the readout circuit substrate 20. Non-limiting examples of other circuits include signal processing circuits and output circuits.

[0180] Preferably, the thickness of the readout circuit substrate 20 is greater than the thickness of the component substrate 10. For example, the readout circuit substrate 20 is preferably at least twice the thickness of the component substrate 10, more preferably at least five times, or even more preferably at least ten times. Additionally, for example, the thickness of the readout circuit substrate 20 is at least 100 μm, at least 150 μm, or at least 200 μm. As described above, the readout circuit substrate 20 with a larger thickness ensures the mechanical strength of the light receiving element 1. It should be noted that the readout circuit substrate 20 may consist only of the semiconductor substrate 21 in which circuitry is formed. Alternatively, in addition to the semiconductor substrate 21 in which circuitry is formed, the readout circuit substrate 20 may also include other substrates such as a support substrate.

[0181] (1-2. Manufacturing method of optical receiving element)

[0182] The optical receiving element 1 can be manufactured by the following steps. Figures 6A to 16K The manufacturing steps of the light receiving element 1 are shown in sequence.

[0183] For example, such as Figure 6A As shown, a semiconductor layer 10S is first epitaxially grown on a growth substrate 31 containing InP. For example, the thickness of the growth substrate 31 is several hundred μm. For example, the thickness of the semiconductor layer 10S is several μm. Then, as... Figure 6B As shown, an adhesion layer B is formed on the semiconductor layer 10S. For example, the diameter of the growth substrate 31 is 6 inches or less. For example, to form the semiconductor layer 10S, n-type InP for forming the first contact layer 12, i-type InGaAs for forming the photoelectric conversion layer 13, and n-type InP for forming the second contact layer 14 are epitaxially grown sequentially. For example, the semiconductor layer 10S can be formed after a buffer layer and a stop layer are formed on the growth substrate 31.

[0184] Next, as Figure 6CAs shown, a growth substrate 31 on which a semiconductor layer 10S is formed is bonded to a temporary substrate 33 via an adhesive layer B. For example, the temporary substrate 33 includes an insulating layer 33IA and a substrate 33S. For example, the insulating layer 33IA is disposed between the adhesive layer B and the substrate 33S. The diameter of the temporary substrate 33 is larger than the diameter of the growth substrate 31. For example, the substrate 33S is a silicon (Si) substrate. For example, the diameter of the temporary substrate 33 is in the range of 8 inches to 12 inches. Bonding the growth substrate 31 with a small diameter to the temporary substrate 33 with a large diameter allows the use of various equipment for large-diameter substrates to form the component substrate 10. For example, the readout circuit substrate 20 can be bonded to the component substrate 10 via Cu-Cu bonding to create finer pixels P. For example, the growth substrate 31 can be bonded to the temporary substrate 33 via plasma-activated bonding, room-temperature bonding, or bonding using adhesives (adhesive bonding). As described above, for example, the semiconductor layer 10S in wafer form is bonded to the temporary substrate 33. For example, the thickness of the temporary substrate 33 is several hundred μm.

[0185] Figure 7 and Figure 8 An example of a planar configuration of a temporary substrate 33 and a semiconductor layer 10S or a growth substrate 31 is shown. For example... Figure 7 As shown, a wafer-shaped semiconductor layer 10S, smaller than the temporary substrate 33, can be bonded to the wafer-shaped temporary substrate 33. Alternatively, as... Figure 8 As shown, multiple semiconductor layers 10S in chip form can be bonded to a temporary substrate 33 in wafer form. In this state, the multiple chips are separated from each other.

[0186] Alternatively, such as Figure 9A and Figure 9B As shown, the semiconductor layer 10S in wafer form and the temporary substrate 33 in wafer form, which are of the same size, can be bonded to each other. Figure 9A The planar structure of the temporary substrate 33 and the semiconductor layer 10S or the growth substrate 31 is shown. Figure 9B It shows along Figure 9A The cross-sectional structure cut by line II-II' in the middle.

[0187] like Figure 10A As shown, after the growth substrate 31 on which the semiconductor layer 10S is formed is bonded to the temporary substrate 33, the growth substrate 31 is removed. For example, the growth substrate 31 can be removed by mechanical polishing, chemical mechanical polishing (CMP), wet etching, or dry etching. After removal, the growth substrate 31 can be partially retained. The semiconductor layer 10S can be partially etched.

[0188] Next, as Figure 10BAs shown, for example, the semiconductor layer 10S is etched to a predetermined size according to the markings on the temporary substrate 33. Thus, the semiconductor layer 10S is formed into multiple chips.

[0189] Figure 11A An example of the planar configuration of the semiconductor layer 10S before forming is shown. Figure 11B It shows in Figure 11A The example shown is a planar configuration of the semiconductor layer 10S after it has been formed. Figure 12A Another planar configuration example of the semiconductor layer 10S before forming is shown. Figure 12B It shows in Figure 12A Another planar configuration example of the semiconductor layer 10S after its formation, as shown. As described above, the wafer-shaped semiconductor layer 10S is formed into multiple chips. For example... Figure 11A As shown, the size of the semiconductor layer 10S is smaller than the size of the temporary substrate 33. Alternatively, as... Figure 12A As shown, the size of the semiconductor layer 10S is the same as the size of the temporary substrate 33.

[0190] Alternatively, such as Figure 13A and Figure 13B As shown, the semiconductor layer 10S can be formed into a smaller chip.

[0191] For example, while etching the semiconductor layer 10S, the adhesion layer B is also etched together with the semiconductor layer 10S. The adhesion layer B can be etched to an area larger than that of the semiconductor layer 10S. Figure 10B As shown, the adhesive layer B can extend around the semiconductor layer 10S.

[0192] Alternatively, such as Figure 14 As shown, the adhesive layer B can be etched to a size smaller than the chip area of ​​the semiconductor layer 10S, thereby creating gaps between the chips of the semiconductor layer 10S and the temporary substrate 33. Alternatively, the adhesive layer B can be etched to the same size as the semiconductor layer 10S.

[0193] like Figure 15 As shown, the adhesion layer B can be etched without etching the semiconductor layer 10S.

[0194] The following attached figures Figure 16E A single chip of semiconductor layer 10S is shown among a plurality of chips of semiconductor layer 10S. (Compared to...) Figure 14 and Figure 15 similar, Figure 16F The accompanying figures show, for example, two chips of semiconductor layer 10S among a plurality of chips of semiconductor layer 10S.

[0195] like Figure 16AAs shown, after the semiconductor layer 10S is formed, diffusion regions 12A are formed in each pixel P within the semiconductor layer 10S. This results in element isolation. For example, to form the diffusion regions 12A, an insulating film 17A is used as a hard mask. Specifically, an insulating film 17A is formed to cover the upper surface (i.e., the surface opposite to the bonding surface of the temporary substrate 33) and side surfaces of the semiconductor layer 10S, and then an opening 17H is formed by etching on the insulating film 17A covering the upper surface of the semiconductor layer 10S. Subsequently, vapor-phase diffusion of p-type impurities is performed using the insulating film 17A as a hard mask to form the diffusion regions 12A in selected areas. For example, the diffusion proceeds substantially isotropically to a depth of several hundred nm. For example, the diffusion regions 12A can be formed using a resist mask via solid-phase diffusion or ion implantation. In this embodiment, the diffusion regions 12A are formed in the semiconductor layer 10S disposed on a temporary substrate 33 having a large diameter. This allows for finer pixel P.

[0196] After forming the diffusion region 12A in the semiconductor layer 10S, as Figure 16B As shown, a metal film 11A is formed on the semiconductor layer 10S. This metal film 11A can be a multilayer film comprising titanium (Ti) and tungsten (W). The metal film 11A will be formed as the first electrode 11. The metal film 11A is formed by, for example, CVD, PVD, ALD, or vapor deposition. Next, as... Figure 16C As shown, for example, the metal film 11A is patterned into the first electrode 11 by photolithography and etching. At this time, as... Figure 16C As shown, the metal film 11A is at least partially retained on the side surface of the semiconductor layer 10S. Specifically, the metal film 11A is at least partially retained on the insulating film 17A covering the side surface of the semiconductor layer 10S. Therefore, the passivation characteristics of the side surface of the semiconductor layer 10S are improved.

[0197] After the first electrode 11 is formed, an insulating film 17B is formed on the entire surface of the temporary substrate 33. For example... Figure 16D As shown, a buried layer 18 is then formed. For example, an insulating material is formed into a film to completely bury the semiconductor layer 10S in the temporary substrate 33. The film is then planarized by chemical mechanical polishing (CMP) to form the buried layer 18. During this process, the insulating film 17B acts as a barrier layer while the film undergoes planarization, thereby preventing over-polishing. The insulating film 17B also serves as another barrier layer during via processing to connect the contact electrode 19E to the corresponding first electrode 11. Therefore, the buried layer 18 is formed to cover the peripheral region R2 surrounding the semiconductor layer 10S and the upper surface of the semiconductor layer 10S (the surface furthest from the temporary substrate 33). The buried layer 18 fills the step gap between the semiconductor layer 10S and the temporary substrate 33, thereby suppressing the inconvenience caused by the step gap between the semiconductor layer 10S and the temporary substrate 33 during the manufacturing process.

[0198] After the formation of buried layer 18, as Figure 16E As shown, the wiring layer 10W is formed to span the buried layer 18 and face the semiconductor layer 10S. For example, after interlayer insulating films 19A and 19B are sequentially formed on the buried layer 18, openings 19H1 and 19H2 extending through the buried layer 18 and insulating film 17B are formed in the regions of the extension 11Y facing the first electrode 11 on the interlayer insulating films 19A and 19B. For example, after forming copper (Cu) films in the openings 19H1 and 19H2 of the interlayer insulating films 19A and 19B by evaporation, PVD, or plating, the surface of the copper films is polished, for example, using CMP, to form the contact electrode 19E. For example, during the formation step of the contact electrode 19E, a dummy electrode 19ED is simultaneously formed in the peripheral region R2. In this embodiment, the wiring layer 10W is formed on a temporary substrate 33 with a large diameter. Therefore, various devices for large-diameter substrates can be used.

[0199] After forming the 10W wiring layer, such as Figure 16F As shown, the readout circuit board 20 is bonded to the temporary board 33 via the wiring layer 10W. At this time, the wiring layer 20W is pre-formed in the readout circuit board 20. The wiring layer 20W in the readout circuit board 20 includes contact electrodes 22E and dummy electrodes 22ED. For example, to bond the readout circuit board 20 to the temporary board 33, the contact electrodes 22E and dummy electrodes 22ED in the wiring layer 20W, and the contact electrodes 19E and dummy electrodes 19ED in the wiring layer 10W, are bonded to each other by Cu-Cu bonding. More specifically, the bonding surfaces S2 of the contact electrodes 19E and 22E are each formed in the component region R1. The bonding surfaces S2 of the dummy electrodes 19ED and 22ED are formed in the peripheral region R2. In this embodiment, the peripheral region R2 on the component board 10 is also bonded to the readout circuit board 20. It should be noted that... Figure 1 , Figure 16F The accompanying drawings illustrate an example in which contact electrode 19E faces each contact electrode 22E and is bonded to each contact electrode 22E via a Cu-Cu bond, and dummy electrode 19ED faces each dummy electrode 22ED and is bonded to each dummy electrode 22ED via a Cu-Cu bond. However, they can also be bonded in a partially offset manner, provided that the bonding between these electrodes is ensured.

[0200] After the readout circuit board 20 is bonded to the temporary board 33, as Figure 16G As shown, substrate 33S is removed. For example, substrate 33S can be removed by mechanical polishing, wet etching, or dry etching.

[0201] After removing substrate 33S, for example, as Figure 16H As shown, insulating layer 33IA and adhesive layer B are also removed to expose the surface of semiconductor layer 10S. At this time, unwanted layers in semiconductor layer 10S can be removed. Insulating layer 33IA or insulating films 17A and 17B, except for the openings of semiconductor layer 10S, can be completely or partially retained. Buried layer 18 can also be partially excavated.

[0202] Next, as Figure 16I As shown, after removing the temporary substrate 33, a second electrode 15 and a passivation film 16A are sequentially formed on the exposed surface of the semiconductor layer 10S (the surface opposite to the surface where the wiring layer 10W is located). Then, as... Figure 16J As shown, a through-hole H1, a conductive film 15B, and a passivation film 16B are formed in sequence. Therefore, the second electrode 15 and the readout circuit board 20 are electrically connected to each other.

[0203] Finally, as Figure 16K As shown, a through-hole H2 is formed, extending through the component substrate 10 to the pad electrode 22P in the readout circuit substrate 20. Therefore, the process is complete. Figure 1 The light receiving element 1 shown is shown.

[0204] (1-3. Operation of the optical receiving element)

[0205] In the light receiving element 1, for example, when light of a wavelength in the region from the visible light region to the infrared region is incident on the photoelectric conversion layer 13 via passivation films 16A and 16B, the second electrode 15, and the second contact layer 14, the photoelectric conversion layer 13 absorbs the light. This results in the generation of pairs of holes and electrons in the photoelectric conversion layer 13. That is, the light undergoes photoelectric conversion. For example, since a predetermined voltage is applied to the first electrode 11 at this time, a potential gradient appears in the photoelectric conversion layer 13. One of the generated charges (e.g., holes) moves to the diffusion region 12A to be used as a signal charge and is collected from the diffusion region 12A to the first electrode 11. The signal charge moves to the semiconductor substrate 21 via contact electrodes 19E and 22E. The signal charge is then read out from each pixel P.

[0206] (1-4. Functions and Effects)

[0207] In the light-receiving element 1 according to this embodiment, an extension portion 11Y is formed along the insulating film 17A around the connection portion 11X of the first electrode 11. That is, the extension portion 11Y is formed in the opening 17H of the insulating film 17A. The connection portion 11X is electrically connected to the semiconductor layer 10S. The via 19V is connected to the corresponding extension portion 11Y. Therefore, the above-described structure improves the ease of contact between the first electrode 11 and the via 19V. The reasons for this improvement will now be explained.

[0208] As mentioned above, image sensors or infrared sensors sensitive to the infrared region have been commercialized. For example, semiconductor devices are known to include components and circuit boards bonded together by Cu-Cu bonding. The component substrate is a stack of compound semiconductor layers and wiring layers.

[0209] In the aforementioned semiconductor device, through-wires / through-silicon vias are connected through openings in an insulating film. The through-wires are used for electrical connections between the electrodes and the circuit board. In the insulating film, diffusion regions on the compound semiconductor layer are in contact with the electrodes. In a semiconductor device with the structure described above, the openings and the connections between the electrodes and through-wires affect the compound semiconductor layer and degrade electrical characteristics. Steps formed at or around the electrodes above the openings can lead to poor contact between the electrodes and the through-wires.

[0210] To suppress the occurrence of such poor contact, in this embodiment, an extension portion 11Y extending from each connection portion 11X is provided along the insulating film 17A around the connection portion 11X of the first electrode 11. The connection portion 11X contacts the semiconductor layer 10S. The via 19V is connected to the corresponding extension portion 11Y. The via 19V is also connected to the corresponding contact electrode 19E. Therefore, the above configuration can improve the ease of contact between the first electrode 11 and the via 19V.

[0211] In the light-receiving element 1 according to this embodiment, as described above, the through-hole 19V is connected to a corresponding extension 11Y of the first electrode 11. The through-hole 19V is also connected to a corresponding contact electrode 19E. The extension 11Y is disposed along the insulating film 17A. Therefore, this embodiment improves the ease of contact between the first electrode 11 and the through-hole 19V. The area of ​​the opening 17H through which the first electrode 11 and the semiconductor layer 10S are electrically connected to each other can also be reduced. Therefore, the generation of dark current is suppressed. That is, the electrical characteristics can be improved.

[0212] Furthermore, the extension 11Y is formed asymmetrically to allow the through-hole 19V to connect to the wider portion extending on the insulating film 17A. Therefore, the diameter of the through-hole 19V is increased. This reduces the contact resistance between the first electrode 11 and the contact electrode 19E, and further improves electrical characteristics.

[0213] The following will describe some variations of the above embodiment, namely, variations 1 to 3. Note that similar elements are denoted by the same reference numerals, and no further detailed descriptions will be provided.

[0214] (2. Variations)

[0215] (2-1. Variation Example 1)

[0216] In the above embodiment, the two insulating films 17A and 17B cover the opposing surface of the wiring layer 10W and the end face of the semiconductor layer 10S. However, it is permissible to cover only the insulating film 17A covering the opposing surface of the wiring layer 10W and the end face of the semiconductor layer 10S. Figure 17A and Figure 17B The manufacturing steps of the light receiving element 1 according to the above embodiment of Modification 1 are shown in sequence.

[0217] like Figure 17A As shown, as in the above embodiment, an insulating film 17A is first formed to cover the top and sides of the semiconductor layer 10S. Then, by etching, an opening 17H is formed on the insulating film 17A covering the top of the semiconductor layer 10S. Next, using the insulating film 17A as a hard mask, vapor diffusion of p-type impurities is performed to form a diffusion region 12A. After forming the diffusion region 12A, as in the above embodiment, a metal film 11A is formed on the semiconductor layer 10S. The metal film 11A will be formed as the first electrode 11. Then, for example, the first electrode 11 is formed by photolithography and etching. At this time, the metal film 11A is at least partially retained on the insulating film 17A covering the sides of the semiconductor layer 10S. Afterwards, as... Figure 17B As shown, a buried layer 18 is formed on the entire temporary substrate 33.

[0218] (2-2. Variation Example 2)

[0219] Figures 18A to 18F The manufacturing steps of the light receiving element 1 according to the above embodiment, variant 2, are shown in sequence.

[0220] like Figure 18A As shown in the above embodiment, firstly, a semiconductor layer 10S is formed on the temporary substrate 33 in the form of multiple chips. Next, as... Figure 18B As shown, an insulating film 17A is formed to cover the top surface (the surface opposite to the bonding surface of the temporary substrate 33) and sides of the semiconductor layer 10S. Next, as... Figure 18C As shown, an insulating film 18A for constituting the buried layer 18 is formed on the entire surface of the temporary substrate 33. Then, CMP is performed on the insulating films 18A and 17A to expose the surface of the semiconductor layer 10S. Therefore, the step between the semiconductor layer 10S and the temporary substrate 33 is filled.

[0221] Next, as Figure 18D As shown, an insulating film 18B is formed on the entire surface of the semiconductor layer 10S and the interlayer insulating film 18A, and an opening 18H is formed by etching. Subsequently, using the insulating film 18B as a hard mask, p-type impurities are vapor-phase diffused in the first contact layer 12 of the semiconductor layer 10S to form a diffusion region 12A in a selected area.

[0222] After forming the diffusion region 12A on the semiconductor layer 10S, as Figure 18E As shown, a metal film is formed on the insulating film 18B to fill the opening 18H. The metal film is, for example, a multilayer film comprising titanium (Ti) and tungsten (W). For example, the metal film is patterned into the first electrode 11 by photolithography and etching.

[0223] After the first electrode 11 is formed, as Figure 18F As shown, an insulating film 17B is formed to cover the insulating film 18B and the first electrode 11. Then, as in the embodiment described above, an insulating film constituting the buried layer 18 together with the insulating films 18A and 18B is formed on the insulating film 17B, and the surface of the insulating film is planarized, for example, by CMP. Thereafter, for example, the formation of the wiring layer 10W, the bonding of the readout circuit board 20, and the removal of the temporary board 33 are performed sequentially. The light receiving element 1 can be manufactured by these steps as described above.

[0224] It should be noted that, as in the above-described variant 1, the insulating film 17B covering the insulating film 18B and the first electrode 11 can be omitted. That is, the insulating film that forms the buried layer 18 together with the insulating films 18A and 18B can be directly formed on the insulating film 18B and the first electrode 11.

[0225] (2-3. Variation Example 3)

[0226] Figure 19 A cross-sectional structure of the light-receiving element 1A according to a variation of the above embodiment is shown. The light-receiving element 1A includes a color filter layer 41 and an on-chip lens (condenser lens) 42 on the light incident surface S1 (the opposite surface to the opposing surface of the readout circuit board 20) of the element substrate 10. Apart from this structure, the light-receiving element 1A has the same structure and effects as the light-receiving element 1. The color filter layer 41 may include at least one of RGB (red, green, and blue) color filters, IR color filters, CMYG (cyan, magenta, yellow, and green) color filters, a transparent filter with a wide transmission wavelength according to the embodiment, and other suitable filters. In another embodiment, the light-receiving element 1A includes an on-chip lens (condenser lens) 42 on the light incident surface S1, without a color filter layer therebetween.

[0227] In the light receiving element 1A, for example, a color filter layer 41 corresponding to RGB and an on-chip lens 42 are sequentially disposed on the passivation films 16A and 16B of the element substrate 10, separated by a planarization film 16C. The color filter layer 41 may include an infrared (IR) filter. By providing the color filter layer 41, light receiving data of light received at corresponding wavelengths in each pixel P can be acquired.

[0228] The on-chip lens 42 focuses light incident on the light-receiving element 1A onto the photoelectric conversion layer 13. The on-chip lens 42 comprises, for example, an organic material or silicon oxide (SiO2). In the light-receiving element 1A, a buried layer 18 is disposed in the peripheral region R2. Between the element region R1 and the peripheral region R2 of the element substrate 10, the step difference is reduced or eliminated, thereby forming a planar light incident surface S1. Therefore, the on-chip lens 42 can be formed with high precision, for example, using a photolithography step. For example, the color filter layer 41 and the on-chip lens 42 terminate in the element region R1. For example, a planarization film 16C is disposed between the passivation films 16A and 16B and the color filter layer 41 from the element region R1 to the peripheral region R2. The planarization film 16C terminates in the peripheral region R2. The color filter layer 41, the on-chip lens 42, and the planarization film 16C can terminate at any position in the element region R1 or the peripheral region R2.

[0229] In a modified example, the color filter layer 41 and the on-chip lens 42 can be disposed on the light incident surface S1 of the element substrate 10. Even in the modified example, effects equivalent to those in the above embodiment can be achieved. In the configuration according to the modified example, for example, by setting the second contact layer 14 to have a film thickness in the range of 5 nm to 300 nm, pixel signals can also be read based on color. Furthermore, the on-chip lens 42 can be easily formed with high precision on the light incident surface S1 planarized by the buried layer 18.

[0230] (3. Applicable Examples)

[0231] (Applicable Example 1)

[0232] Figure 20 The operational structure of an imaging device 2 using the device structure of the light receiving element 1 shown in the above embodiment is illustrated. For example, the imaging device 2 is an infrared image sensor. For example, the imaging device 2 has a circuit section 130 provided on the light receiving element 1, comprising an element region R1 and a driving element region R1. For example, the circuit section 130 includes a row scanning section 131, a horizontal selection section 133, a column scanning section 134, and a system control section 132.

[0233] For example, the element region R1 is arranged in a two-dimensional matrix. Multiple pixels P constituting the light receiving element 1 are provided in the element region R1. For example, pixel driving lines Lread are provided on each pixel row of pixel P. For example, the pixel driving line Lread is a row selection line or a reset control line. Furthermore, vertical signal lines Lsig are provided on each pixel column of pixel P. The pixel driving lines Lread transmit driving signals for reading signals from pixel P. One end of each pixel driving line Lread is connected to a corresponding output terminal of the line scanning unit 131.

[0234] For example, the line scanning unit 131 includes a shift register and an address decoder. For example, the line scanning unit 131 serves as a pixel driving unit for driving pixels P in the element region R1 on a row-by-row basis. Signals output from pixels P on the pixel rows selectively scanned by the line scanning unit 131 are supplied to the horizontal selection unit 133 via corresponding vertical signal lines Lsig. For example, the horizontal selection unit 133 includes amplifiers and horizontal selection switches provided on each vertical signal line Lsig.

[0235] For example, column scanning unit 134 includes a shift register and an address decoder. Column scanning unit 134 scans and sequentially drives the horizontal selection switches of horizontal selection unit 133. When column scanning unit 134 selects and scans these switches, signals transmitted from the pixels via vertical signal line Lsig are sequentially output to horizontal signal line 135. Then, for example, the signals enter a signal processing unit (not shown) via horizontal signal line 135.

[0236] In camera device 2, for example, such as Figure 21 As shown, a component substrate 10 having component region R1 and a readout circuit substrate 20 including circuit section 130 are stacked on top of each other. However, this disclosure is not limited to the configuration described above. Circuit section 130 and component region R1 may be formed on a single substrate. Circuit section 130 may also be disposed on an external control integrated circuit (IC). Alternatively, for example, circuit section 130 may be formed on another substrate connected to a cable.

[0237] The system control unit 132 receives external data such as clock data or data indicating the operating mode. For example, the system control unit 132 also outputs data including internal information about the camera device 2. The system control unit 132 also includes a timing generator that generates various timing signals. For example, based on the various types of timing signals generated in the timing generator, the system control unit 132 drives and controls the row scanning unit 131, the horizontal selection unit 133, and the column scanning unit 134.

[0238] (Applicable Example 2)

[0239] The aforementioned camera device 2 can be applied to various types of electronic devices, including, for example, cameras that capture images in the infrared region. As an example, Figure 22 The schematic configuration of a camera representing electronic device 3 is shown. For example, electronic device 3 is a camera capable of capturing still images or videos. Electronic device 3 includes an imaging device 2, an optical system or optical lens 210, a shutter 211, a drive unit 213, and a signal processing unit 212. The drive unit 213 drives the imaging device 2 and the shutter 211.

[0240] The optical system 210 guides image light or incident light from the subject to the imaging device 2. The optical system 210 may include multiple optical lenses. The shutter 211 controls the period of time light illuminates the imaging device 2. The shutter 211 also controls the period of light blocking. The drive unit 213 controls the transmission operation to the imaging device 2 and the shutter operation of the shutter 211. The signal processing unit 212 performs various types of signal processing on the signal output from the imaging device 2. For example, the processed image signal Dout is stored in a storage medium such as a memory, or output to a monitor.

[0241] Furthermore, the light receiving element 1 shown in this embodiment and other examples can also be applied to the electronic devices described below.

[0242] (4. Application Examples)

[0243] (Examples of the application of endoscopic surgical systems)

[0244] The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein can be applied to endoscopic surgical systems.

[0245] Figure 23 This is a diagram illustrating an example of a schematic construction of an endoscopic surgical system to which the technology (the technology) according to embodiments of the present disclosure can be applied.

[0246] exist Figure 23 The image shows a surgeon (physician) 11131 performing surgery on a patient 11132 on a bed 11133 using an endoscopic surgery system 11000. As shown, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy device 11112, a support arm assembly 11120 supporting the endoscope 11100, and a trolley 11200 on which various devices for endoscopic surgery are mounted.

[0247] Endoscope 11100 includes a lens tube 11101 inserted into a body cavity of patient 11132 at a predetermined distance from its distal end, and a camera 11102 connected to the proximal end of the lens tube 11101. In the example shown, an endoscope 11100 including a rigid endoscope with a rigid lens tube 11101 is illustrated; however, endoscope 11100 may also include a flexible endoscope with a flexible lens tube 11101.

[0248] The lens tube 11101 has an opening at its distal end in which an objective lens is mounted. A light source device 11203 is connected to the endoscope 11100 such that light generated by the light source device 11203 is introduced into the distal end of the lens tube 11101 via a light guide extending into the lens tube 11101, and emitted through the objective lens toward the object of observation within the body cavity of the patient 11132. It should be noted that the endoscope 11100 can be a direct-viewing endoscope, or it can be an oblique-viewing endoscope or a side-viewing endoscope.

[0249] An optical system and an image sensor are installed inside the camera 11102, so that reflected light from the observed object (observation light) is converged onto the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observed image. The image signal is transmitted to the CCU 11201 as RAW data.

[0250] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), etc., and comprehensively controls the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives image signals from the camera 11102 and, for example, performs various image processing operations for displaying images based on the image signals, such as image processing (de-mosaic processing).

[0251] The display device 11202 displays an image based on an image signal that has been image-processed by the CCU 11201 under the control of the CCU 11201.

[0252] For example, the light source device 11203 includes a light source such as a light-emitting diode (LED) and supplies illumination light to the endoscope 11100 when imaging the surgical area.

[0253] Input device 11204 is an input interface for endoscopic surgical system 11000. Users can input various types of information or commands into endoscopic surgical system 11000 through input device 11204. For example, users can input commands to change the imaging conditions of endoscope 11100 (type of illumination light, magnification, focal length, etc.).

[0254] The treatment tool control device 11205 controls the drive of the energy device 11112 for purposes such as tissue cauterization and incision, and sealing of blood vessels. The pneumoperitoneum device 11206 injects gas into the patient's body cavity 11132 through the pneumoperitoneum tube 11111 to inflate the cavity, ensuring the field of vision of the endoscope 11100 and the surgeon's working space. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphics.

[0255] It should be noted that the light source device 11203, which supplies illumination light to the endoscope 11100 for imaging the surgical area, may include, for example, an LED, a laser light source, or a combination thereof, as a white light source. When the white light source includes a combination of red, green, and blue (RGB) laser light sources, the white balance of the captured image can be adjusted by the light source device 11203 because the output intensity and timing of each color (wavelength) can be controlled with high precision. Furthermore, in this case, if lasers from each RGB laser source are emitted onto the object of observation in a time-division manner and the driving of the imaging element of the camera 11102 is controlled synchronously with the emission sequence, images corresponding to the R, G, and B colors can also be captured in a time-division manner. According to this method, color images can be obtained even if a color filter is not provided for the imaging element.

[0256] Furthermore, the light source device 11203 can be controlled to change the intensity of the light to be output at predetermined intervals. By controlling the driving of the imaging element of the camera 11102 in sync with the timing of the change in light intensity to acquire and synthesize images in a time-divided manner, high dynamic range images with high brightness and no occlusion shadows or overexposure can be generated.

[0257] Furthermore, the light source device 11203 can be configured to supply light of a predetermined wavelength band for special light observation. In special light observation, for example, narrow-band imaging (narrow-band imaging) can be performed by emitting light with a narrow band range compared to the illumination light used in ordinary observation (i.e., white light) by utilizing the wavelength dependence of light absorption in body tissues. Alternatively, in special light observation, fluorescence observation can be performed to obtain an image by emitting fluorescence generated by excitation light. In fluorescence observation, fluorescence observation from body tissues can be performed by irradiating body tissues with excitation light (autofluorescence observation), or a reagent such as indocyanine green (ICG) can be locally injected into body tissues and excitation light corresponding to the fluorescence wavelength of the reagent can be emitted to obtain a fluorescence image. The light source device 11203 can be configured to supply such narrow-band light and / or excitation light suitable for the aforementioned special light observation.

[0258] Figure 24 It is shown Figure 23 A block diagram illustrating an example of the functional configuration of the camera 11102 and CCU 11201.

[0259] Camera 11102 includes a lens unit 11401, an image capture unit 11402, a drive unit 11403, a communication unit 11404, and a camera control unit 11405. CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. Camera 11102 and CCU 11201 are communicatively connected to each other via a transmission cable 11400.

[0260] Lens unit 11401 is an optical system disposed at the connection position with lens barrel 11101. Observation light received from the distal end of lens barrel 11101 is guided to camera 11102 and incident on lens unit 11401. Lens unit 11401 includes a combination of multiple lenses, including zoom lenses and focusing lenses.

[0261] The number of imaging elements included in the imaging unit 11402 can be one (single-plate type) or multiple (multi-plate type). When the imaging unit 11402 is configured as a multi-plate type, for example, image signals corresponding to RGB are generated by the imaging elements, and the image signals can be synthesized to obtain a color image. The imaging unit 11402 can also be configured to have a pair of imaging elements for acquiring separate image signals for the right and left eyes corresponding to three-dimensional (3D) display. If 3D display is performed, the surgeon 11131 can more accurately grasp the depth of living tissue in the surgical area. It should be noted that when the imaging unit 11402 is configured as a three-dimensional unit, multiple systems of lens units 11401 corresponding to a single imaging element can be provided.

[0262] Furthermore, the camera unit 11402 does not necessarily need to be located within the camera 11102. For example, the camera unit 11402 can be located directly behind the objective lens inside the lens barrel 11101.

[0263] The drive unit 11403 includes an actuator that, under the control of the camera control unit 11405, moves the zoom lens and focusing lens of the lens unit 11401 a predetermined distance along the optical axis. As a result, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0264] Communication unit 11404 includes communication means for transmitting various types of information to CCU 11201 and receiving various types of information from CCU 11201. Communication unit 11404 transmits image signals acquired from camera unit 11402 as RAW data to CCU 11201 via transmission cable 11400.

[0265] Additionally, the communication unit 11404 receives control signals from the CCU 11201 for controlling the camera 11102 and supplies these control signals to the camera control unit 11405. For example, the control signals include information related to shooting conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value during shooting, and / or information specifying the magnification and focus of the captured image.

[0266] It should be noted that imaging conditions such as frame rate, exposure value, magnification, or focus can be specified by the user or automatically set by the control unit 11413 of CCU 11201 based on the acquired image signal. In the latter case, the automatic exposure (AE), automatic focus (AF), and automatic white balance (AWB) functions are integrated into the endoscope 11100.

[0267] The camera control unit 11405 controls the driving of the camera 11102 based on the control signals received from the CCU 11201 via the communication unit 11404.

[0268] The communication unit 11411 includes communication means for transmitting various types of information to and receiving various types of information from the camera 11102. The communication unit 11411 receives image signals transmitted from the camera 11102 via a transmission cable 11400.

[0269] In addition, the communication unit 11411 transmits control signals for controlling the camera 11102 to the camera 11102. Image signals and control signals can be transmitted via electrical communication, optical communication, etc.

[0270] The image processing unit 11412 performs various types of image processing on the image signal in RAW data format transmitted from the camera 11102.

[0271] The control unit 11413 performs various types of control related to imaging the surgical area, etc., via the endoscope 11100, and displaying the images obtained by imaging the surgical area, etc. For example, the control unit 11413 generates control signals for controlling the drive of the camera 11102.

[0272] Furthermore, the control unit 11413 controls the display device 11202 to display images captured by the camera, such as those of the surgical area, based on image signals that have already been processed by the image processing unit 11412. At this time, the control unit 11413 can use various image recognition technologies to identify various objects within the captured images. For example, the control unit 11413 can identify surgical instruments such as forceps, specific living body parts, bleeding, fog when the energy treatment device 11112 is used, etc., by detecting the edge shape, color, etc., of objects contained in the captured images. When the control unit 11413 controls the display device 11202 to display the captured images, the control unit 11413 can use the recognition results to display various types of surgical support information in an overlay manner with the image of the surgical area. When surgical support information is displayed and presented to the surgeon 11131 in an overlay manner, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can perform the surgery reliably.

[0273] The transmission cable 11400 that connects the camera 11102 and the CCU 11201 to each other is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable for both electrical and optical communication.

[0274] Here, in the example shown, although communication is conducted via wired communication using transmission cable 11400, communication between camera 11102 and CCU 11201 can be conducted wirelessly.

[0275] Examples of endoscopic surgical systems to which the technology according to this disclosure is applicable have been described above. For example, in the above configuration, the technology according to this disclosure can be applied to camera unit 11402. Applying the technology according to this disclosure to camera unit 11402 improves detection accuracy.

[0276] It should be noted that the above description uses an endoscopic surgical system as an example, and the technology according to this disclosure can be applied to, for example, microscopic surgical systems.

[0277] (Examples of applications involving moving objects)

[0278] The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein can be implemented as a device mounted on any type of mobile body. Non-limiting examples of mobile bodies may include automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, any personal mobility device, aircraft, unmanned aerial vehicles (drones), ships, and robots.

[0279] Figure 25 This is a block diagram illustrating a schematic construction example of a vehicle control system, which is an example of a mobile body control system to which the technology according to embodiments of the present disclosure is applicable.

[0280] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 25 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, as part of the functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0281] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 is a control device for generating drive force to produce the vehicle's driving force, such as an internal combustion engine or a drive motor, a drive force transmission mechanism to transmit drive force to the wheels, a steering mechanism to adjust the vehicle's steering angle, and a braking device to generate the vehicle's braking force.

[0282] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, taillights, brake lights, turn signals, and fog lights. In this case, radio waves transmitted from a portable device or signals from various types of switches, instead of a key, can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locking devices, power windows, lights, etc.

[0283] The exterior information detection unit 12030 detects information related to the exterior of the vehicle, including information from the vehicle control system 12000. For example, the exterior information detection unit 12030 is connected to a camera unit 12031. The exterior information detection unit 12030 causes the camera unit 12031 to capture images of the exterior of the vehicle and receives the captured images. Based on the received images, the exterior information detection unit 12030 can perform processing such as detecting objects like people, cars, obstacles, signs, and text on the road, or detecting their distance.

[0284] The camera unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The camera unit 12031 can output the electrical signal as an image or as information related to distance measurement. Furthermore, the light received by the camera unit 12031 can be visible light or invisible light such as infrared light.

[0285] The in-vehicle information detection unit 12040 detects information related to the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 that detects the driver's state. For example, the driver state detection unit 12041 includes a camera that captures images of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or determine whether the driver has fallen asleep.

[0286] The microcomputer 12051 can calculate control target values ​​for the drive force generating device, steering mechanism, or braking device based on information about the vehicle's interior and exterior obtained by the external information detection unit 12030 or the internal information detection unit 12040, and can output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to achieve functions of advanced driver assistance systems (ADAS), including collision avoidance or collision mitigation, following distance-based tracking, speed maintenance, collision warning, and lane departure warning.

[0287] In addition, the microcomputer 12051 can coordinate and control the drive force generating device, steering mechanism, braking device, etc., based on information about the outside or inside of the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, aiming to achieve autonomous driving, such as driving the vehicle autonomously without relying on the operation of the driver.

[0288] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on information about the vehicle's exterior obtained by the exterior information detection unit 12030. For example, the microcomputer 12051 can perform coordinated control aimed at preventing glare by controlling the headlights according to the position of the vehicle ahead or oncoming vehicle detected by the exterior information detection unit 12030, such as changing the high beams to low beams.

[0289] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or audibly informing vehicle occupants or the outside of the vehicle. Figure 25 In the example, an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown as output devices. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0290] Figure 26 This is a diagram showing an example of the mounting position of the camera unit 12031.

[0291] exist Figure 26In the middle, the camera unit 12031 includes camera units 12101, 12102, 12103, 12104 and 12105.

[0292] For example, cameras 12101, 12102, 12103, 12104, and 12105 are installed on the front of vehicle 12100, side mirrors, rear bumper, rear door, and the upper part of the windshield inside the vehicle. Camera 12101 on the front of the vehicle and camera 12105 on the upper part of the windshield inside the vehicle primarily acquire images of the front of vehicle 12100. Cameras 12102 and 12103 on the side mirrors primarily acquire images of the sides of vehicle 12100. Camera 12104 on the rear bumper or rear door primarily acquires images of the rear of vehicle 12100. Camera 12105 on the upper part of the windshield inside the vehicle is mainly used to detect vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc., ahead.

[0293] also, Figure 26 Examples of the shooting ranges of camera units 12101 to 12104 are shown. Camera range 12111 represents the shooting range of camera unit 12101 located on the front of the vehicle. Camera ranges 12112 and 12113 represent the shooting ranges of camera units 12102 and 12103 located on the side mirrors, respectively. Camera range 12114 represents the shooting range of camera unit 12104 located on the rear bumper or rear door. For example, a bird's-eye view of vehicle 12100 is obtained by overlaying image data captured by camera units 12101 to 12104.

[0294] At least one of the camera units 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the camera units 12101 to 12104 may be a stereo camera composed of multiple camera elements, or may be a camera element with pixels for phase difference detection.

[0295] For example, based on distance information obtained from cameras 12101 to 12104, microcomputer 12051 can determine the distance to each three-dimensional object within the camera range 12111 to 12114 and the time change of that distance (relative speed relative to vehicle 12100), thereby extracting the closest three-dimensional object located on the driving path of vehicle 12100 and traveling in approximately the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the vehicle ahead. Furthermore, microcomputer 12051 can set a pre-determined following distance in front of the vehicle ahead and can perform automatic braking control (including tracking stop control), automatic acceleration control (including tracking start control), etc. Therefore, coordinated control for achieving autonomous driving of the vehicle without relying on driver operation is possible.

[0296] For example, based on distance information obtained from cameras 12101-12104, microcomputer 12051 can classify three-dimensional object data into three-dimensional object data for two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that the driver of vehicle 12100 can visually recognize and obstacles that are difficult for the driver of vehicle 12100 to visually recognize. Then, microcomputer 12051 determines the collision risk, indicating the degree of danger of colliding with each obstacle. If the collision risk is equal to or exceeds a set value and there is a possibility of collision, microcomputer 12051 outputs a warning to the driver via audio speaker 12061 or display unit 12062 and performs forced deceleration or evasive steering via drive system control unit 12010. Therefore, microcomputer 12051 can assist driving to avoid collisions.

[0297] At least one of the camera units 12101 to 12104 can be an infrared camera for detecting infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the captured images of the camera units 12101 to 12104. This pedestrian identification is performed, for example, by extracting feature points from the captured images of the camera units 12101 to 12104, which are infrared cameras, and by performing pattern matching processing on a series of feature points representing the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the captured images of the camera units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 to display a rectangular outline for emphasis, superimposed on the identified pedestrian. The sound / image output unit 12052 can also control the display unit 12062 to display an icon or similar indicating the pedestrian at a desired location.

[0298] Examples of vehicle control systems to which the technology according to this disclosure is applicable have been described above. In the above configuration, the technology according to this disclosure can be applied, for example, to camera unit 12031. Applying the technology according to this disclosure to camera unit 12031 allows for easier viewing of captured images, helping to reduce driver fatigue.

[0299] Although this disclosure has been described with reference to embodiments, variations 1-3, applicable examples, application examples, and other examples, the content of this disclosure is not limited thereto, and can be modified in various ways. For example, the layered structure of the light receiving element according to the above embodiment is merely an example, and other layers may also be included. Furthermore, the materials and thicknesses of the layers are merely exemplary and are not limited to the values ​​described above. In the above embodiment, the semiconductor layer 10S includes a first contact layer 12, a photoelectric conversion layer 13, and a second contact layer 14. However, for example, the semiconductor layer 10S may include at least the photoelectric conversion layer 13. For example, the first contact layer 12 and the second contact layer 14 may not be provided. Other layers may also be included.

[0300] Furthermore, for convenience, holes are used as signal charges in the above embodiments. However, electrons can also be used as signal charges. For example, n-type impurities can be included in the diffusion region.

[0301] Furthermore, in the above embodiments, the light-receiving element represents a specific, but not limiting, example of a semiconductor element according to embodiments of the present technology. However, other elements besides the light-receiving element may represent semiconductor elements according to embodiments of the present technology. For example, a light-emitting element may represent a semiconductor element according to embodiments of the present technology.

[0302] It should be understood that the effects described herein are merely exemplary. The effects of this embodiment and other examples of this disclosure are not limited to those described herein. This disclosure may also include any effects other than those described herein.

[0303] Furthermore, for example, this disclosure can have the following configuration. According to the present technology having the following configuration, a through-wire is connected to an extension of the first electrode. The extension is disposed around an opening along an insulating layer. The extension is electrically connected to the semiconductor layer via this opening. Therefore, this configuration improves the ease of contact between the first electrode and the through-wire. Thus, electrical characteristics can be improved.

[0304] This disclosure may have the following structure. (1)

[0306] A semiconductor device comprising:

[0307] A component substrate comprising a stack of a wiring layer and a semiconductor layer, wherein the semiconductor layer comprises a compound semiconductor material;

[0308] A readout circuit board is positioned opposite the semiconductor layer via the wiring layer, and the readout circuit board is electrically connected to the semiconductor layer via the wiring layer.

[0309] An insulating film that covers at least one side of the semiconductor layer facing the wiring layer, the insulating film having an opening in which the semiconductor layer is partially exposed;

[0310] A first electrode has a connecting portion and an extension portion, the connecting portion being electrically connected to the semiconductor layer within the opening, and the extension portion extending on the insulating film; and

[0311] A through-wire has one end and another end, the one end being connected to the extension of the first electrode, and the other end being electrically connected to the wiring in the wiring layer. (2)

[0313] According to the semiconductor element described in (1), wherein,

[0314] In the plan view, the extension has a generally flat surface extending asymmetrically around the opening on the insulating film, the generally flat surface of the extension having a first region and a second region, the first region having a wider area than the second region, and

[0315] The through wiring is connected to a first region of the generally planar plane of the extension. (3)

[0317] According to the semiconductor element described in (1) or (2), wherein,

[0318] The wiring layer includes one or more first contact electrodes exposed on the opposing surface facing the readout circuit board, and

[0319] The through wiring is electrically connected to the one or more first contact electrodes. (4)

[0321] According to the semiconductor element described in (3), wherein,

[0322] The readout circuit board includes one or more second contact electrodes exposed on the opposing surface facing the component board, and

[0323] The component substrate and the readout circuit substrate are joined to each other via one or more first contact electrodes and one or more second contact electrodes. (5)

[0325] The semiconductor element according to any one of (1) to (4) wherein the insulating film extends from one side of the semiconductor layer to the side of the semiconductor layer. (6)

[0327] According to the semiconductor element of (5), a metal film is provided such that at least a portion of the side surface of the semiconductor layer is faced through the insulating film. (7)

[0329] The semiconductor element according to any one of (1) to (6) wherein the element substrate has an element region and a peripheral region, the wiring layer and the semiconductor layer are stacked on top of each other in the element region, and the peripheral region is located outside the element region and has a through hole extending to the readout circuit substrate. (8)

[0331] According to the semiconductor device of (7), the device substrate further includes a second electrode opposite to the first electrode across the semiconductor layer, the second electrode being electrically connected to the readout circuit substrate via the through-hole. (9)

[0333] The semiconductor element according to any one of (1) to (8) wherein the compound semiconductor material absorbs light of wavelengths in the infrared region. (10)

[0335] The semiconductor element according to any one of (1) to (9) wherein the semiconductor layer comprises a III-V group semiconductor material. (11)

[0337] The semiconductor element according to any one of (1) to (10), wherein the compound semiconductor material is any one of InGaAs, InAsSb, InAs, InSb and HgCdTe. (12)

[0339] An electronic device includes a semiconductor element, said semiconductor element comprising:

[0340] A component substrate comprising a stack of a wiring layer and a semiconductor layer, wherein the semiconductor layer comprises a compound semiconductor material;

[0341] A readout circuit board is positioned opposite the semiconductor layer via the wiring layer, and the readout circuit board is electrically connected to the semiconductor layer via the wiring layer.

[0342] An insulating film that covers at least one side of the semiconductor layer facing the wiring layer, the insulating film having an opening in which the semiconductor layer is partially exposed;

[0343] A first electrode has a connecting portion and an extension portion, the connecting portion being electrically connected to the semiconductor layer within the opening, and the extension portion extending on the insulating film; and

[0344] A through-wire has one end and another end, the one end being connected to the extension of the first electrode, and the other end being electrically connected to the wiring in the wiring layer. (13)

[0346] A light detection device, comprising:

[0347] The first substrate includes a first electrode, a semiconductor layer comprising a compound semiconductor material, a first insulating film, and a through-hole;

[0348] A second substrate faces the first substrate and is electrically connected to the semiconductor layer through the via;

[0349] The first electrode comprises a first part and a second part, and

[0350] The first portion of the first electrode is in contact with the semiconductor layer, and the second portion is in contact with the first insulating film and the through hole. (14)

[0352] According to the photodetector described in (13), the first electrode has a stepped shape. (15)

[0354] According to the photodetector of (13) or (14), the second portion of the first electrode overlaps with the through hole in a plan view. (16)

[0356] The photodetector according to any one of (13) to (15), wherein the first portion of the first electrode does not overlap with the through hole in the plan view. (17)

[0358] The light detection apparatus according to any one of (13) to (16), wherein the semiconductor layer includes a photoelectric conversion layer and the photoelectric conversion layer comprises the compound semiconductor material. (18)

[0360] The light detection apparatus according to any one of (13) to (17), wherein the semiconductor layer includes a diffusion region, and the first portion is in contact with the diffusion region. (19)

[0362] The light detection device according to any one of (13) to (18), wherein the diffusion region is configured to read the charge generated from the photoelectric conversion layer. (20)

[0364] The light detection device according to any one of (13) to (19), wherein the photoelectric conversion layer is configured to absorb light from the visible region to the short infrared region. (twenty one)

[0366] The photodetector according to any one of (13) to (20), wherein the compound semiconductor material includes at least one of indium gallium arsenide, indium antimony arsenide, indium arsenide, indium antimonide, and mercury cadmium telluride. (twenty two)

[0368] The photodetector according to any one of (13) to (21) further includes a second electrode facing the first electrode, wherein the semiconductor layer is disposed between the first electrode and the second electrode. (twenty three)

[0370] The photodetector according to any one of (13) to (22) further includes a second insulating film, wherein the second portion of the first electrode is sandwiched between the first insulating film and the second insulating film. (twenty four)

[0372] The light detection device according to any one of (13) to (23) further includes an on-chip lens located on the light incident surface of the first substrate. (25)

[0374] The photodetector according to any one of (13) to (24), wherein the first substrate includes a third electrode, the second substrate includes a fourth electrode, and wherein the first substrate and the second substrate are electrically connected through the third electrode and the fourth electrode. (26)

[0376] The photodetector according to any one of (13) to (25), wherein the third electrode and the fourth electrode each comprise copper pads. (27)

[0378] The photodetector according to any one of (13) to (26) wherein the third electrode overlaps with the first electrode in a plan view and the third electrode is in contact with the through hole. (28)

[0380] The photodetector according to any one of (13) to (27), wherein the first substrate and the second substrate are stacked on top of each other, and the third electrode is in contact with the fourth electrode. (29)

[0382] The photodetector according to any one of (13) to (28), wherein the via includes at least one of through silicon via and through wiring. (30)

[0384] The light detection device according to any one of (13) to (29), wherein the second substrate includes a readout circuit configured to read out a charge signal from the first substrate. (31)

[0386] A method for manufacturing an optical detection device, comprising:

[0387] A first substrate is formed, the first substrate including a first electrode, a semiconductor layer comprising a compound semiconductor material, a first insulating film, and a through hole;

[0388] A second substrate is formed, the second substrate facing the first substrate, and electrically connected to the semiconductor layer through the through-hole;

[0389] The first electrode comprises a first part and a second part, and

[0390] The first portion is in contact with the semiconductor layer, and the second portion is in contact with the first insulating film and the through hole. (32)

[0392] An electronic device includes a light detection device, the light detection device comprising:

[0393] The first substrate includes a first electrode, a semiconductor layer comprising a compound semiconductor material, a first insulating film, and a through-hole;

[0394] A second substrate faces the first substrate and is electrically connected to the semiconductor layer through the via;

[0395] The first electrode comprises a first part and a second part, and

[0396] The first portion is in contact with the semiconductor layer, and the second portion is in contact with the first insulating film and the through hole.

[0397] Those skilled in the art will understand that various modifications, combinations, sub-combinations and alterations can be made according to design requirements and other factors, as long as such modifications, combinations, sub-combinations and alterations are within the scope of the appended claims or their equivalents.

[0398] [List of reference numerals]

[0399] 1. Optical receiving element

[0400] 2. Camera device

[0401] 3 Electronic devices

[0402] 10 Component Substrate

[0403] 10S semiconductor layer

[0404] 10W wiring layer

[0405] 11 First Electrode

[0406] 11C concave part

[0407] 11X Connector

[0408] 11Y Extension Department

[0409] 12 First Contact Layer

[0410] 12A diffusion region

[0411] 13 Photoelectric conversion layer

[0412] 14 Second Contact Layer

[0413] 15 Second Electrode

[0414] 16A, 16B passivation films

[0415] 17A, 17B, 18A, 18B Insulating Film

[0416] 17H, 18H, 19H1, 19H2 opening

[0417] 18 Buried layer

[0418] 18V, 22V through electrodes

[0419] 19A, 19B, 22A, 2B Interlayer insulating film

[0420] 19E, 22E contact electrodes

[0421] 19ED, 22ED Dummy Electrodes

[0422] 20 Reading the circuit board

[0423] 21 Semiconductor substrate

[0424] 22CB wiring

[0425] 22P pad electrode

[0426] 31 Growth substrate

[0427] 32 Insulation layer

[0428] 33 Temporary substrate

[0429] 41 Color Filter Layers

[0430] 42 On-chip lens

[0431] 51S silicon layer

[0432] B Adhesive layer

[0433] H1, H2 through holes

[0434] P pixel

[0435] R1 component area

[0436] R2 surrounding area

[0437] S1 Light incident surface

[0438] S2 mating surface

Claims

1. A light detection device, comprising: The first substrate includes a first electrode, a semiconductor layer comprising a compound semiconductor material, a first insulating film, and a through-hole; A second substrate faces the first substrate and is electrically connected to the semiconductor layer through the via; The first electrode comprises a first part and a second part. In this configuration, the first portion of the first electrode is in contact with the semiconductor layer, and the second portion is in contact with the first insulating film and the through-hole. Wherein, the second portion of the first electrode overlaps with the through hole in the plan view, and Wherein, the first portion of the first electrode does not overlap with the through hole in the plan view.

2. The optical detection device according to claim 1, wherein, The first electrode has a stepped shape.

3. The optical detection device according to claim 1 or 2, wherein, The semiconductor layer includes a photoelectric conversion layer, and the photoelectric conversion layer contains the compound semiconductor material.

4. The optical detection device according to claim 3, wherein, The semiconductor layer includes a diffusion region, and the first portion is in contact with the diffusion region.

5. The optical detection device according to claim 4, wherein, The diffusion region is configured to read the charge generated from the photoelectric conversion layer.

6. The optical detection device according to claim 3, wherein, The photoelectric conversion layer is configured to absorb light from the visible region to the short infrared region.

7. The optical detection device according to claim 1 or 2, wherein, The compound semiconductor material includes at least one of indium gallium arsenide, indium antimony arsenide, indium arsenide, indium antimonide, and mercury cadmium telluride.

8. The photodetector according to claim 1 or 2, further comprising a second electrode facing the first electrode, wherein, The semiconductor layer is disposed between the first electrode and the second electrode.

9. The photodetector according to claim 1 or 2, further comprising a second insulating film, wherein, The second portion of the first electrode is sandwiched between the first insulating film and the second insulating film.

10. The optical detection device according to claim 1 or 2 further includes an on-chip lens, the on-chip lens being located on the light incident surface of the first substrate.

11. The optical detection device according to claim 1 or 2, wherein, The first substrate includes a third electrode, the second substrate includes a fourth electrode, and the first substrate and the second substrate are electrically connected through the third electrode and the fourth electrode.

12. The optical detection device according to claim 11, wherein, The third electrode and the fourth electrode each include copper pads.

13. The optical detection device according to claim 11, wherein, The third electrode overlaps with the first electrode in the plan view, and the third electrode is in contact with the through hole.

14. The optical detection device according to claim 11, wherein, The first substrate and the second substrate are stacked on top of each other, and the third electrode is in contact with the fourth electrode.

15. The optical detection device according to claim 1 or 2, wherein, The via includes at least one of through-silicon vias and through wiring.

16. The optical detection device according to claim 1 or 2, wherein, The second substrate includes a readout circuit configured to read out a charge signal from the first substrate.

17. A method for manufacturing a light detection device, comprising: A first substrate is formed, the first substrate including a first electrode, a semiconductor layer comprising a compound semiconductor material, a first insulating film, and a through hole; A second substrate is formed, the second substrate facing the first substrate, and electrically connected to the semiconductor layer through the through-hole; The first electrode comprises a first part and a second part. The first portion is in contact with the semiconductor layer, and the second portion is in contact with the first insulating film and the through-hole. Wherein, the second portion of the first electrode overlaps with the through hole in the plan view, and Wherein, the first portion of the first electrode does not overlap with the through hole in the plan view.

18. An electronic device comprising a light detection device, said light detection device being the light detection device according to any one of claims 1 to 16.

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