Built-in testing of display drivers

Abstract

A display driver includes image processing circuitry, driver circuitry, and test circuitry. The image processing circuitry is configured to generate first output data during a first display update period and second output data during a second display update period. The driver circuitry is configured to update a display panel based on the first output data during the first display update period and to update the display panel based on the second output data during the second display update period. The test circuitry is configured to test the image processing circuitry during a test period disposed between the first display update period and the second display update period.

Description

Technical Field

[0001] The disclosed technology generally relates to built-in testing of display drivers. Background Technology

[0002] Display devices can be tested before shipment and / or during startup to improve reliability. To perform pre-shipment and / or startup testing, the display driver configured to drive the display panel may include built-in test circuitry. Summary of the Invention

[0003] The present invention is provided to present, in a simplified form, the selection of concepts further described below in the detailed embodiments. The present invention is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0004] In one or more embodiments, a display driver is provided. The display driver includes image processing circuitry, driver circuitry, and test circuitry. The image processing circuitry is configured to generate first output data during a first display update period and second output data during a second display update period. The driver circuitry is configured to update a display panel based on the first output data during the first display update period and update the display panel based on the second output data during the second display update period. The test circuitry is configured to test the image processing circuitry during a test period defined between the first and second display update periods.

[0005] In one or more embodiments, a display system is provided. The display system includes a display panel and a display driver. The display driver includes image processing circuitry, driver circuitry, and test circuitry. The image processing circuitry is configured to generate first output data during a first display update period and second output data during a second display update period. The driver circuitry is configured to update the display panel based on the first output data during the first display update period and to update the display panel based on the second output data during the second display update period. The test circuitry is configured to test the image processing circuitry during a test period defined between the first and second display update periods.

[0006] In one or more embodiments, a method for driving a display panel is provided. The method includes: updating the display panel based on first output data generated by an image processing circuit during a first display update period; and updating the display panel based on second output data generated by the image processing circuit during a second display update period. The method further includes testing the image processing circuit during a test period disposed between the first and second display update periods.

[0007] Other aspects of the embodiments will become apparent from the following description and the appended claims. Attached Figure Description

[0008] To enable a more detailed understanding of the foregoing features of this disclosure, a more specific description of the disclosure briefly outlined above can be obtained by referring to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate exemplary embodiments only and should therefore not be considered as limiting the scope of the invention, as other equally effective embodiments are permissible with respect to this disclosure.

[0009] Figure 1 An example configuration of a display system according to one or more embodiments is illustrated.

[0010] Figure 2 An example test process according to one or more embodiments is illustrated.

[0011] Figure 3 The illustration shows an example configuration of a display panel and a display driver according to one or more embodiments.

[0012] Figure 4 An example test process according to one or more embodiments is illustrated.

[0013] Figure 5A An example configuration of an image processing circuit and a test circuit according to one or more embodiments is illustrated.

[0014] Figure 5B An example configuration of an image processing circuit and a test circuit according to other embodiments is illustrated.

[0015] Figure 6 The illustration shows an example operation of an image processing circuit according to one or more embodiments.

[0016] Figure 7 An example configuration and operation of an image processing circuit according to one or more embodiments is illustrated.

[0017] Figure 8A An example configuration of an image processing circuit according to one or more embodiments is illustrated.

[0018] Figure 8B An example configuration of an image processing circuit according to other embodiments is illustrated.

[0019] Figure 9A An example configuration of an image processing circuit according to one or more embodiments is illustrated.

[0020] Figure 9B An example configuration of an image processing circuit according to other embodiments is illustrated.

[0021] Figure 10A , Figure 10B , Figure 10C , Figure 10D ,and Figure 10E An example process for a boundary scan test according to one or more embodiments is illustrated.

[0022] Figure 11 An example configuration of a test circuit according to one or more embodiments is illustrated.

[0023] Figure 12 The illustration shows an example operation of the display system when a circuit fault is detected, according to one or more embodiments.

[0024] Figure 13 The illustration shows an example operation of the system when a circuit fault is detected, according to other embodiments.

[0025] Figure 14 An example configuration of an image processing circuit and a test circuit according to one or more embodiments is illustrated.

[0026] Figure 15 An example method for controlling a display panel is illustrated according to one or more embodiments.

[0027] For ease of understanding, where possible, the same reference numerals have been used to designate the same elements common to the figures. Elements disclosed in one embodiment are expected to be advantageously used in other embodiments without specific description. Suffixes may be attached to the reference numerals to distinguish the same elements from one another. The figures mentioned herein should not be construed as being drawn to scale unless specifically indicated. Furthermore, for clarity of presentation and explanation, the figures are generally simplified and details or parts are omitted. The figures and discussion are used to explain the principles discussed below, wherein the same reference numerals denote the same elements. Detailed Implementation

[0028] The following detailed descriptions are merely exemplary in nature and are not intended to limit this disclosure or its application and use. Furthermore, they are not intended to be construed as being bound by any express or implied theory presented in the foregoing background, summary of the invention, or the following detailed descriptions.

[0029] Some types of display devices may require higher reliability, for example, due to safety considerations. Examples of such display devices include automotive applications, such as front-view displays, speedometers, rearview displays, and side-view displays. To improve reliability, display devices are typically tested before shipment and / or during startup. However, pre-shipment testing and startup testing do not address circuit failures that occur during actual operation, such as when displaying images.

[0030] This disclosure provides various techniques for detecting circuit faults occurring during actual operation and providing measures to address these faults. In one or more embodiments, a display panel is updated based on first output data generated by an image processing circuit during a first display update period and second output data generated by the image processing circuit during a second display update period. The image processing circuit is tested during a test period set between the first and second display update periods. This operation enables the detection of circuit faults occurring during actual operation (e.g., while an image is being displayed on the display panel).

[0031] Figure 1 An example configuration of a display system 1000 according to one or more embodiments is illustrated. In the illustrated embodiment, the display system 1000 includes a display module 100, a host 200, and an output device 300. Examples of the host 200 may include an application processor, a central processing unit (CPU), or other processor. Examples of the output device 300 may include a speaker, an alarm light, or other device configured to output an alarm to a user.

[0032] Display module 100 includes display panel 10 and display driver 20. Display panel 10 may include liquid crystal display (LCD) panel, organic light-emitting diode (OLED) display panel, and other types of display panels. Display panel 10 includes pixel circuits 11 (four shown) that can be arranged in rows and columns. Display driver 20 is configured to update pixel circuits 11 to display an image on display panel 10 corresponding to image data D_in received from host 200. Examples of display driver 20 may include display driver integrated circuit (DDIC), touch display driver integrated circuit (TDDI), or other devices configured to drive display panel 10.

[0033] In the illustrated embodiment, the display driver 20 includes interface (I / F) circuitry 21, graphics random access memory (GRAM) 22, image processing circuitry 23, driver circuitry 24, timing controller (TCON) 25, and test circuitry 26. Interface circuitry 21 is configured to receive image data D_in from host 200 and forward the received image data D_in to GRAM 22. In other embodiments, interface circuitry 21 may be configured to process the received image data and send the processed image data to GRAM 22.

[0034] GRAM 22 is configured to temporarily store image data D_in and forward the stored image data D_in to image processing circuit 23. In other embodiments, GRAM 22 may be omitted and image data D_in may be supplied directly from interface circuit 21 to image processing circuit 23.

[0035] Image processing circuit 23 is configured to apply desired image processing (e.g., color adjustment, subpixel rendering, image scaling, and gamma transformation) to image data D_in received from GRAM 22 to generate output data D_out and provide it to driver circuit 24. Output data D_out can specify the voltage level of an output voltage, which the pixel circuit 11 in display panel 10 will use to update.

[0036] The driver circuit 24 is configured to drive or update the pixel circuit 11 based on the output data D_out. The driver circuit 24 can be configured to generate an output voltage with a voltage level specified by the output data D_out, and supply the generated output voltage to the corresponding pixel circuit 11.

[0037] The timing controller 25 is configured to provide timing control for the display driver 20. The timing control can define frame periods (or vertical synchronization periods), display update periods, and blanking periods. The timing controller 25 can also be configured to control the operation of the image processing circuitry 23.

[0038] Test circuit 26 is configured to perform built-in tests of image processing circuit 23. Test circuit 26 can also be configured to send test results to host 200 via interface circuit 21. Instead of host 200 or other systems, test circuit 26 can be configured to send test results to timing controller 25.

[0039] In one or more embodiments, the test circuit 26 is configured to test the image processing circuit 23 during actual operation (e.g., when the display driver 20 is in operation for displaying an image on the display panel 10). Figure 2 An example test procedure according to one or more embodiments is illustrated. In the illustrated embodiment, each frame period includes a display update period during which the pixel circuitry 11 of the display panel 10 is updated by the display driver 20. In one implementation, the entire pixel circuitry 11 of the display panel 10 is updated based on image data D_in defined for the frame image during the display update period of each frame period. Figure 2 The diagram illustrates first to third display update periods, denoted by numbers 2011 to 2013, respectively. A blanking period is set between two adjacent display update periods. In one or more embodiments, the image processing circuit 23 is configured to generate first output data during the first display update period 2011 and second output data during the second display update period 2012. In such an embodiment, the driver circuit 24 is configured to update the display panel 10 based on the first output data during the first display update period 2011 and based on the second output data during the second display update period 2012.

[0040] In the illustrated embodiment, test circuit 26 is configured to test image processing circuit 23 during a test period set between two adjacent display update periods 201 (e.g., in each blanking period). Figure 2 The diagram illustrates a first test period 2021 and a second test period 2022, wherein the first test period 2021 is set between the first display update period 2011 and the second display update period 2012, and the second test period 2022 is set between the second display update period 2012 and the third display update period 2013. Setting the test period 202 between two adjacent display update periods 201 allows the image processing circuit 23 to be tested to detect circuit faults that occur during actual operation while the display driver 20 continues to display images on the display panel 10.

[0041] In other embodiments, the display module 100 may be adapted for proximity sensing (e.g., touch sensing) to sense input provided by one or more input objects in a sensing area defined in the surface of the display panel 10. Example input objects include fingers and styluses. Figure 3 An example configuration of a display panel 10 and a display driver 20 according to such an embodiment is illustrated. In the illustrated embodiment, the display panel 10 further includes sensor elements 12 (four shown), and the display driver 20 further includes a proximity sensing module 30 configured to sense one or more input objects based on resulting signals received from the sensor elements 12. Each of the sensor elements 12 may include sensor electrodes. In some implementations, proximity sensing can be achieved using a self-capacitance (often also referred to as absolute capacitance) sensing method based on changes in capacitive coupling between the sensor elements 12 and the input object. In other implementations, proximity sensing can be achieved using a mutual capacitance (often also referred to as transcapacitance) sensing method based on changes in capacitive coupling between the sensor elements 12. In one implementation, the mutual capacitance sensing method operates by detecting capacitive coupling between one or more transmitter sensor electrodes and one or more receiver sensor electrodes.

[0042] In embodiments where the display module 100 is adapted for proximity sensing, the proximity sensing period can be set between two adjacent display update periods. In such embodiments, the proximity sensing module 30 can be configured to acquire a result signal from the sensor element 12 during the proximity sensing period and sense input provided by one or more input objects based on the result signal. The proximity sensing period may at least partially overlap with the test period.

[0043] Figure 4 The illustration shows one or more embodiments. Figure 3The example test procedure for the system configuration shown is illustrated. In one or more embodiments, each frame period includes multiple display update periods, and the pixel circuitry 11 of the entire display panel 10 is updated in a time-division manner. In one implementation, a first portion of the pixel circuitry 11 of the display panel 10 may be updated during a first display update period, and a second portion of the pixel circuitry 11 may be updated during a second display update period. In embodiments where each frame period includes three or more display update periods, similar operations may be performed for the remaining display update periods(s). Overall, the pixel circuitry 11 of the entire display panel 10 is updated based on image data D_in defined for the frame image during the multiple display update periods included in a frame period. In the illustrated embodiment, each frame period includes four display update periods. Figure 4 In the diagram, numbers 4011, 4012, 4013, and 4014 represent the first to fourth display update periods set within a frame period, and number 4015 represents the fifth display update period in the next frame period. A test period (during which the image processing circuit 23 is tested) is set between two adjacent display update periods. Figure 4 In the diagram, numbers 4021, 4022, 4023, and 4024 represent test periods. These test periods are respectively set between display update periods 4011 and 4012, between display update periods 4012 and 4013, between display update periods 4013 and 4014, and between display update periods 4014 and 4015. Additionally, the proximity sensing period is set between two adjacent display update periods. Figure 4 In the diagram, numbers 4031, 4032, and 4034 represent proximity sensing periods. In the illustrated embodiment, proximity sensing periods 4031 to 4034 overlap with test periods 4021 to 4024, respectively.

[0044] Figure 5A An example configuration of an image processing circuit 23 and a test circuit 26 according to one or more embodiments is illustrated. The image processing circuit 23 may include a plurality of image processing components 51 connected in series to process image data D_in. In the illustrated embodiment, the image processing circuit 23 includes first to fourth image processing components 511, 512, 513, and 514. The test circuit 26 may include a plurality of test components 52 configured to test corresponding image processing components 51. In the illustrated embodiment, four test components 521, 522, 523, and 524 are configured to test the first image processing component 511 to the fourth image processing component 514, respectively.

[0045] The test circuit 26 can be configured to generate one or more test patterns (which may include test images) and one or more test parameters to be provided to the image processing unit 51 under test. The test circuit 26 can also be configured to generate expected values ​​for the output of the corresponding image processing unit 51 and compare the output of the image processing unit 51 with the expected values. Expected values ​​can be defined for the corresponding test patterns or test images. The display driver 20 also includes, for example... Figure 5B In the embodiment of the processor 53 shown, the processor 53 may be configured to generate test patterns, test parameters, and / or expected values. The processor 53 may also be configured to compare the output of the image processing unit 51 with the expected values.

[0046] The image processing circuit 23 can be configured to be reconfigurable based on the test results obtained by the test circuit 26. Figure 6 The illustration shows an example operation of an image processing circuit 23 configured according to one or more embodiments. In one implementation, the image processing circuit 23 may be configured to respond to the detection of an image processing component 51 (e.g., such as...). Figure 6 The second image processing unit (512) shown in the diagram bypasses the faulty image processing unit 51 to generate output data D_out. Bypassing the faulty image processing unit can mitigate the impact of the fault on image display.

[0047] Figure 7 An example configuration and operation of an image processing circuit 23 according to other embodiments is illustrated. The image processing circuit 23 may also include a backup image processing unit 54 for the image processing unit 51 to maintain normal display in the event of a failure in the image processing unit 51. In the illustrated implementation, the backup image processing unit 54 is configured to perform the same image processing as the fourth image processing unit 514. Both the fourth image processing unit 514 and the backup image processing unit 54 may be configured to perform gamma transformations or different image processing that can significantly affect the displayed image. The image processing circuit 23 may be configured to deactivate the backup image processing unit 54 during normal operation. The image processing circuit 23 may also be configured to activate the backup image processing unit 54 and deactivate the fourth image processing unit 514 in response to detecting a failure in the fourth image processing unit 514. This can effectively prevent abnormal display. Although Figure 7 The fourth image processing unit is shown only as having a corresponding alternative image processing unit, but any of the image processing units may have an alternative image processing unit.

[0048] Figure 8AAn example configuration of an image processing circuit 23 according to other embodiments is illustrated. In the illustrated embodiment, the image processing circuit 23 includes storage circuits 551, 552, 553, and 554 respectively connected to first through fourth image processing units 511, 512, 513, and 514. In various embodiments, the first image processing unit 511 through fourth image processing unit 514 is configured to generate intermediate data when generating output data D_out. In some embodiments, the first image processing unit 511 through fourth image processing unit 514 may be configured to generate data for use during a first display update period (e.g., ...). Figure 2 Intermediate data for output data D_out is generated during the display update period 2012 shown, and the intermediate data generated during the first display update period (e.g., display update period 2013) is used to generate output data D_out during a second display update period following the first display update period. The first image processing unit 511 to the fourth image processing unit 514 can be tested by test units 521 to 524 during a test period (e.g., test period 2022) set between the first and second display update periods. In such an embodiment, the first image processing unit 511 to the fourth image processing unit 514 can be configured to store intermediate data in storage circuits 551 to 554 respectively before the test period, and to reload or retrieve the intermediate data from storage circuits 551 to 554 respectively after the test period. Storage and reloading can effectively prevent intermediate data from being corrupted by tests performed during the test period. The display driver 20 also includes, as shown in the example, Figure 8B In the embodiment of the processor 53 shown, the processor 53 may be configured to generate test images, test parameters, and / or expected values ​​and provide the test images, test parameters, and / or expected values ​​to test components 521 to 524. The processor 53 may also be configured to compare the output of the image processing component 51 with the expected values.

[0049] Figure 9AAn example configuration of an image processing circuit, indicated by numeral 23A, according to another embodiment is illustrated. In the illustrated embodiment, the first to fourth image processing units 511, 512, 513, and 514 respectively include scan chains 561, 562, 563, and 564 to perform boundary scan testing. Each of the scan chains 561 to 564 includes a series-connected scan flip-flop (or boundary scan unit) forming a shift register. The scan chains 561 to 564 are configured to provide a test pattern to the first to fourth image processing units 511 to 514 and capture combinational logic results from the first to fourth image processing units 511 to 514 against the test pattern. The captured combinational logic results are shifted out of the scan chains 561 to 564 and compared with expected values ​​by the test circuit 26 to detect circuit faults in the first to fourth image processing units 511 to 514. The display driver 20 also includes, as shown in the illustration, [further details about the display circuitry are needed for a complete translation]. Figure 9B In the embodiment of the processor 57 shown, the processor 57 may be configured to generate test patterns and / or expected values. The processor 57 may also be configured to compare the combined logic results captured from the first image processing unit 511 to the fourth image processing unit 514 with the expected values.

[0050] Figure 10A An example partial configuration of an image processing component (e.g., first image processing component 511 to fourth image processing component 514) disposed in an image processing circuit 23A according to one or more embodiments is illustrated. In the illustrated embodiment, the image processing component includes a plurality of scan triggers (or scan units) 611, 612, and 613 and a plurality of combination circuits 621, 622, and 623. In the illustrated embodiment, scan trigger 611 includes a data input configured to receive external input and a data output connected to an input of combination circuit 621. Scan trigger 612 includes a data input connected to an output of combination circuit 621 and a data output connected to an input of combination circuit 622. Scan trigger 613 includes a data input connected to an output of combination circuit 622 and a data output connected to an input of combination circuit 623. Scan triggers 611, 612, and 613 are connected in series via scan paths 631 and 632 to form a scan chain (e.g., scan chains 561 to 564).

[0051] In the illustrated embodiment, the image processing unit further includes data storage triggers 641, 642, and 643, respectively connected to scan triggers 611, 612, and 613. Data storage triggers 641 to 643 are configured to receive and store data from scan triggers 611 to 613, respectively, and are also configured to restore data to scan triggers 611 to 613, respectively. In one implementation, data storage triggers 641 to 643 are used to pause and restart actual operation and / or boundary scan testing of the relevant image processing unit to detect circuit faults in the relevant image processing unit.

[0052] Figures 10A to 10E The illustration depicts an example process for a boundary scan test according to one or more embodiments. In one implementation, during the first display update period (e.g., Figure 2 When image processing is completed during the display update period (2012) shown, scan triggers 611 to 613 store data generated during image processing, such as... Figure 10A As shown in the illustration. In the illustrated embodiment, scan triggers 611 to 613 store data “0”, “1”, and “1” respectively at the end of the first display update period.

[0053] A boundary scan test is performed during a test period (e.g., test period 2022) between the first display update period and a second display update period following the first display update period (e.g., display update period 2013). Prior to the start of the test period, data stored in scan triggers 611 to 613 is saved in data save triggers 641 to 643. In the illustrated embodiment, as... Figure 10B As shown, data save triggers 641 to 643 capture data “0”, “1”, and “1” from scan triggers 611 to 613. This is followed by setting a test pattern to scan triggers 611 to 613. In the illustrated embodiment, test data “1”, “0”, and “1” are set to scan triggers 611 to 613, respectively. In one implementation, display driver 20 is placed in scan shift mode, and the test pattern is then shifted via scan paths 631 and 632 into the scan chain containing scan triggers 611 to 613.

[0054] Once the test pattern is moved in, such as Figure 10CAs shown, the scan shift mode is disabled, and the resulting data (or combinational logic result) generated at the outputs of combinational circuits 621 and 622 is captured by scan flip-flops 612 and 613 to test combinational circuits 621 and 622. In the illustrated embodiment, the resulting data "1", "1", and "0" are captured by scan flip-flops 612 and 613. The resulting data is then shifted out of the scan chain via scan paths 631 to 633 and compared with expected values ​​to detect circuit faults, such as... Figure 10D As shown in the image.

[0055] Then, the intermediate data is restored from data save triggers 641 to 643 to scan triggers 611 to 613, such as... Figure 10E As shown in the illustration. In the illustrated embodiment, at the end of the first display update period, the data "0", "1", and "1" initially stored in scan triggers 611 to 613 are restored to scan triggers 611 to 613. Image processing is then performed using the restored data during the second display update period.

[0056] Figure 11 An example configuration of a test circuit, represented by numeral 26A, according to one or more embodiments is illustrated. Test circuit 26A is adapted to a parallel scanning scheme to reduce test time. In the illustrated embodiment, test circuit 26A is configured to accommodate multiple scan chains connected in parallel, represented by numeral 72. The multiple scan chains 72 may be integrated into an image processing circuit (e.g., Figure 9A or Figure 9B The image processing circuit 23A shown is included. The test circuit 26A may include a pattern generator circuit 71 configured to provide a test pattern to the scan chain 72 and a synthesis circuit 73 configured to synthesize the output of the scan chain 72 to generate a synthesized scan result. Circuit faults in the image processing circuit can be detected based on the synthesized scan result. The synthesis circuit 73 may be configured as an XOR circuit to calculate the XOR of the output of the scan chain 72 or a multiplier circuit to calculate the logical product of the output of the scan chain 72.

[0057] Test circuit 26A may further include cyclic redundancy check (CRC) decoding circuit 74, configured to generate cyclic redundancy codes for the synthesized scan results received from synthesis circuit 73. Cyclic redundancy codes can be generated for each test period. In some embodiments, the pattern generator circuit 71 generates the same test pattern in a first test period and a second test period following the first test period, and generates cyclic redundancy codes #1 and #2 for the first and second test periods, respectively. In such an embodiment, circuit faults can be detected based on the comparison of cyclic redundancy codes #1 and #2. This approach eliminates the need to generate expected values ​​for boundary scan testing, thereby facilitating the implementation of boundary scan testing.

[0058] Figure 12 The illustration shows an example operation of a display system 1000 when a circuit fault is detected, according to one or more embodiments. In the illustrated embodiment, a test circuit 26 is configured to send a fault notification to a timing controller 25 when a fault is detected in the image processing circuit 23. The fault notification may indicate an image processing component experiencing a fault. The timing controller 25 may provide a bypass instruction to the image processing circuit 23 based on the fault notification. The bypass instruction may instruct the image processing circuit 23 to bypass the image processing component experiencing the fault to generate output data D_out. The timing controller 25 may also provide alarm image data to the image processing circuit 23. The alarm image data may represent an alarm image notifying the user of the occurrence of a fault. The image processing circuit 23 generates output data D_out based on the alarm image data to display the alarm image on the display panel 10.

[0059] Figure 13 The illustration shows an example operation of the display system 1000 when a circuit fault is detected according to another embodiment. In the illustrated embodiment, the test circuit 26 is configured to send a fault notification to the host 200 when a fault is detected in the image processing circuit 23. The host 200 may provide a bypass instruction to the image processing circuit 23 via the interface circuit 21 based on the fault notification. The bypass instruction may instruct the image processing circuit 23 to bypass the image processing component experiencing the fault to generate output data D_out. The host 200 may also operate the output device 300 to output an alarm in response to the fault notification. In embodiments where the output device 300 includes a speaker, the host 200 may be configured to operate the speaker to generate an alarm sound in response to the fault notification. In embodiments where the output device 300 includes an alarm light, the host 200 may be configured to turn on the alarm light in response to the fault notification. Additionally or alternatively, the host 200 may also provide alarm image data to the display driver 20, and the alarm image data may be transmitted to the image processing circuit 23. The image processing circuit 23 generates output data D_out based on the alarm image data to display the alarm image on the display panel 10.

[0060] Figure 14Example configurations of image processing circuitry and test circuitry, respectively represented by digits 23B and 26B, according to other embodiments are illustrated. In one or more embodiments, image processing circuitry 23B is configured to process image data D_in of multiple pixels in parallel. In the illustrated embodiment, image processing circuitry 23B includes parallelizer circuitry 81, selector circuitry 82, multiple pixel tubes 83, serializer circuitry 84, and parameter registers 91 and 92, wherein pixel tubes 83 are configured to perform the same image processing. In the illustrated embodiment, the number of pixel tubes 83 is four to allow image processing circuitry 23B to process image data D_in of four pixels in parallel, but is not limited thereto. In other embodiments, the number of pixel tubes 83 may be two, three, five, or more.

[0061] Parallelizer circuit 81 is configured to parallelize image data D_in to provide the parallelized image data to pixel tubes 83 respectively. Selector circuit 82 is configured to select the parallelized image data and test data received from test circuit 26B, and provide the selected data to pixel tubes 83. Selector circuit 82 is configured to deliver the same test data to the corresponding pixel tube 83 when selecting test data. In the illustrated embodiment, selector circuit 82 includes four selectors 87, each selected by configuration to select the corresponding parallelized image data and test data and provide the selected data to the corresponding pixel tube 83.

[0062] Each pixel tube 83 is configured to process corresponding parallelized image data to generate processed image data. In the illustrated embodiment, pixel tube 83 is adapted for two types of image processing A and image processing B. In other embodiments, pixel tube 83 may each be configured to perform three or more types of image processing or perform one type of image processing. Each pixel tube 83 may include an image processing component 88 configured to perform image processing A and an image processing component 89 configured to perform image processing B. The image processing component 88 of the corresponding pixel tube 83 is configured to receive the same parameters from parameter register 91. This allows the image processing component 88 to perform the same image processing. Similarly, the image processing component 89 of the corresponding pixel tube 83 is configured to receive the same parameters from parameter register 92. The image processing performed by each pixel tube 83 may include subpixel rendering, color adjustment, image scaling, gamma transformation, and / or other types of image processing. Serializer circuit 84 is configured to serialize the processed image data received from pixel tube 83 to generate output data D_out to be provided to driver circuit 24.

[0063] Test circuit 26B includes test data generator circuit 85 and comparator circuit 86. Test data generator circuit 85 is configured to generate test data to be supplied to pixel tube 83. Comparator circuit 86 is configured to compare the output of pixel tube 83. Test circuit 26B is configured to detect faults in image processing circuit 23B based on the comparison of the output of pixel tube 83.

[0064] In one or more embodiments, the image processing circuit 23B is tested as follows: a test data generator circuit 85 generates test data, and a selector circuit 82 delivers the test data to pixel tubes 83. Pixel tubes 83 receive and process the same test data. Test circuit 26B detects faults in the image processing circuit 23B based on a comparison of the outputs of pixel tubes 83. In some embodiments, test circuit 26B may detect a fault in the image processing circuit 23B in response to one output from pixel tubes 83 differing from one or more of the remaining outputs from a plurality of pixel tubes 83. For example, when one output from pixel tubes 83 differs from a different output from pixel tubes 83, test circuit 26B may determine that a fault exists in the image processing circuit 23B. In other embodiments, when the outputs from pixel tubes 83 are the same, test circuit 26B may determine that no fault exists in the image processing circuit 23B.

[0065] Figure 15 Method 1500 illustrates a method for controlling a display panel (e.g., according to one or more embodiments) according to one or more embodiments. Figure 1 The steps of the display panel 10 shown are as follows. It should be noted that the order of the steps can be changed from the order shown.

[0066] At step 1501, based on the first display update period (e.g., Figure 2 The display update periods shown are 2011, 2012, and... Figure 4 The display update period shown (4011 to 4014) is handled by the image processing circuit (e.g., Figure 1 , 3 5A to 10D and Figure 14 The first output data generated by the image processing circuits 23, 23A, and 23B shown is used to update the display panel. At step 1502, then during the test period (e.g., Figure 2 The test periods shown are 2021 and 2022, and Figure 4 The image processing circuit is tested during test periods 4021 to 4024 as shown. At step 1503, the image processing circuit is tested based on the second display update period (e.g., Figure 2 The display shows update periods 2012, 2013, and... Figure 4The display panel is updated by second output data generated by the image processing circuit during the display update periods 4012 to 4015 shown. The test period is set between the first display update period and the second display update period.

[0067] While many embodiments have been described, those skilled in the art who benefit from this disclosure will understand that other embodiments can be devised without departing from the scope. Therefore, the scope of the invention should be limited only by the appended claims.

Claims

1. A display driver, comprising: The image processing circuit is configured as follows: The first output data is generated during the first display update period, and The second output data is generated during the second display update period. The image processing circuit includes: Storage circuits, and The first image processing unit is configured as follows: Intermediate data is generated for generating the first output data during the first display update period. The intermediate data is stored in the storage circuit before the test period. The intermediate data is retrieved from the storage circuit after the test period, and The intermediate data is used to generate the second output data during the second display update period; The driver circuit is configured as follows: During the first display update period, the display panel is updated based on the first output data, and The display panel is updated based on the second output data during the second display update period; and A test circuit is configured to test the image processing circuit during the test period set between the first display update period and the second display update period.

2. The display driver according to claim 1, wherein the image processing circuit comprises a plurality of image processing components, The image processing circuit is configured to bypass the first image processing unit to generate third output data in response to the test circuit detecting a fault in the first image processing unit among the plurality of image processing units.

3. The display driver according to claim 1, wherein the image processing circuit comprises: A first image processing unit is used to generate the first output data and the second output data; as well as A second image processing unit is configured to generate third output data in place of the first image processing unit in response to a fault detected by the test circuit. The driver circuitry is also configured to update the display panel based on the third output data.

4. The display driver of claim 3, wherein both the first image processing unit and the second image processing unit are configured to perform gamma transformation.

5. The display driver according to claim 1, wherein the image processing circuit comprises: A scan chain, which includes scan triggers; The data save trigger is configured as follows: Receive and store the first data from the scan trigger; as well as The first data is restored to the scan trigger.

6. The display driver of claim 5, wherein the data saving trigger is configured to: Receive the first data from the scan trigger at the end of the first display update period; and After testing the image processing circuit, the first data is restored to the scan trigger.

7. The display driver of claim 1, wherein the image processing circuitry comprises a plurality of pixel tubes configured to perform the same image processing in parallel. The image processing circuit is tested based on a comparison of the outputs from the plurality of pixel tubes.

8. The display driver of claim 7, wherein the image processing circuit is further configured to deliver the same test data to the plurality of pixel tubes in the test of the image processing circuit.

9. The display driver of claim 8, wherein testing the image processing circuitry includes detecting a fault in the image processing circuitry in response to one of the outputs from the plurality of pixel tubes being different from one or more of the remaining outputs from the plurality of pixel tubes.

10. The display driver of claim 8, wherein the test circuit is further configured to generate the test data.

11. The display driver according to claim 1, further comprising: The proximity sensing circuit is configured as follows: The result signal is acquired from a sensor element disposed in the sensing area during a proximity sensing period that at least partially overlaps with the test period; as well as The input object in the sensing area is detected based on the result signal.

12. The display driver of claim 1, wherein the test circuit is configured to notify a host, external to the display driver, of a detected fault in the image processing circuit.

13. A display system, comprising: Display panel; as well as Display drivers, including: The image processing circuit is configured as follows: The first output data is generated during the first display update period, and During a second display update period, second output data is generated, wherein the image processing circuit includes a storage circuit and a first image processing unit, the first image processing unit being configured to: Intermediate data is generated for generating the first output data during the first display update period. The intermediate data is stored in the storage circuit before the test period. The intermediate data is retrieved from the storage circuit after the test period, and The intermediate data is used to generate the second output data during the second display update period; The driver circuit is configured as follows: During the first display update period, the display panel is updated based on the first output data, and During the second display update period, the display panel is updated based on the second output data, and A test circuit is configured to test the image processing circuit during a test period set between the first display update period and the second display update period.

14. The display system according to claim 13, wherein the image processing circuit comprises: A scan chain, which includes scan triggers; The data save trigger is configured as follows: Receive and store the first data from the scan trigger; as well as The first data is restored to the scan trigger.

15. The display system of claim 13, wherein the image processing circuit comprises a plurality of pixel tubes configured to perform the same image processing in parallel. The image processing circuit is tested based on a comparison of the outputs from the plurality of pixel tubes.

16. The display system of claim 13, further comprising a host computer external to the display driver. The test circuit is configured to generate a fault notification to inform the host of a detected fault in the image processing circuit.

17. The display system of claim 16, wherein the host is configured to output an alarm indicating that the fault has been detected from an output device in response to the fault notification.

18. The display system of claim 17, wherein the host is configured to supply image data corresponding to an alarm image to the display driver in response to the fault notification, and The display driver is configured to display the alarm image.

19. A method for driving a display panel, comprising: The display panel is updated based on first output data generated by the image processing circuit during a first display update period, wherein the first output data is generated using intermediate data generated during the first display update period; The display panel is updated based on second output data generated by the image processing circuit during a second display update period, wherein the second output data is generated using the intermediate data; as well as The image processing circuit is tested during a test period set between the first display update period and the second display update period, wherein the intermediate data is stored in the storage circuit before the test period and is retrieved from the storage circuit after the test period.

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