Display device

Abstract

A display apparatus includes a display panel including a plurality of first pixels disposed in a first display area and a plurality of second pixels disposed in a second display area adjacent to the first display area, a gate driver disposed in the second display area of the display panel to overlap a portion of the second pixels and to drive the first pixels and the second pixels, a controller to receive image data and to convert the image data into image signals, and a data driver to convert the image signals into data signals and to output the data signals to the first pixels and the second pixels. The controller compensates for active data corresponding to the second pixels and reflects the compensated active data to the image signals.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to a display device. More specifically, the present invention relates to a display device having an enlarged display area. Background Technology

[0002] Various electronic devices for use in multimedia devices (such as televisions, mobile phones, tablets, navigation devices, or gaming devices) are under development.

[0003] In recent years, in line with market demand, research has been conducted to reduce the areas in electronic devices where images are not displayed. Furthermore, research has been conducted to expand the areas in electronic devices that provide images to users.

[0004] The information disclosed in this background section is only for understanding the concept of the present invention, and therefore, this background section may contain information that does not constitute prior art. Summary of the Invention

[0005] The present invention provides a display device that has an expanded display area by reducing the width of the border area.

[0006] Other features of the inventive concept will be set forth in the following description and will be apparent in part from the description or may be learned by practice of the inventive concept.

[0007] An embodiment of the present invention provides a display device, comprising: a display panel including a plurality of first pixels disposed in a first display area and a plurality of second pixels disposed in a second display area adjacent to the first display area; a gate driver disposed in the second display area of ​​the display panel to partially overlap with the second pixels, and driving the first and second pixels; a controller for receiving image data and converting the image data into an image signal; and a data driver for converting the image signal into a data signal and outputting the data signal to the first and second pixels. The controller compensates for valid data corresponding to the second pixels and reflects the compensated valid data in the image signal.

[0008] An embodiment of the present invention provides a display device, comprising: a display panel including a plurality of first pixels disposed in a first display area and a plurality of second pixels disposed in a second display area adjacent to the first display area; a gate driver disposed in the second display area of ​​the display panel to overlap a portion of the second pixels, and driving the first pixels and the second pixels; a controller that receives image data and converts the image data into a first image signal corresponding to the first pixels and a second image signal corresponding to the second pixels; and a data driver that converts the first image signal into a first data signal applied to the first pixels and converts the second image signal into a second data signal applied to the second pixels.

[0009] According to the embodiments described herein, the peripheral region of the first display area, where a gate driver is disposed, is used as a second display area for displaying an image. Therefore, the width of the bezel area in the display device is reduced.

[0010] Furthermore, the brightness difference between the second display area and the first display area is improved, thereby improving the overall display quality of the display device.

[0011] It will be understood that the foregoing general description and the subsequent detailed description are illustrative and explanatory, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0012] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate illustrative embodiments of the invention and, together with the description, serve to explain the inventive concept. In the drawings:

[0013] Figure 1A This is a perspective view illustrating a display device according to an embodiment of the concept of the present invention;

[0014] Figure 1B This is shown when viewed from the second direction. Figure 1A Side view of the display device shown;

[0015] Figure 1C This is shown when viewed in the first direction. Figure 1A Side view of the display device shown;

[0016] Figure 2A This is an exploded perspective view illustrating a display device according to an embodiment of the concept of the present invention;

[0017] Figure 2B This is a block diagram illustrating a display device according to an embodiment of the concept of the present invention;

[0018] Figure 2C and Figure 2DA plan view of a display panel according to an embodiment of the concept of the present invention is shown;

[0019] Figure 3A This illustrates an embodiment based on the concept of the present invention. Figure 2C An enlarged plan view of region A1 shown in the figure;

[0020] Figure 3B It is shown in Figure 3A A view showing the connection relationship between the emitting element and the pixel driving circuit in region A2;

[0021] Figure 3C It is shown in Figure 3A A view showing the connection relationship between the pixel driving circuit and the data lines;

[0022] Figure 3D This illustrates an embodiment of the concept according to the present invention. Figure 2C An enlarged plan view of region A3 shown in the diagram;

[0023] Figure 3E It is shown in Figure 3D A view showing the connection relationship between the pixel driving circuit and the data lines;

[0024] Figure 4A It is shown in Figure 2B The internal block diagram of the controller shown is shown below;

[0025] Figure 4B It is shown in Figure 2B The internal block diagram of the data driver shown is shown below;

[0026] Figures 5A to 5C It is an explanation applied to Figure 3A A conceptual diagram of the data compensation method for a pixel-structured data compensator;

[0027] Figure 6A This illustrates an embodiment of the concept according to the present invention. Figure 2C An enlarged plan view of region A1 shown in the figure;

[0028] Figure 6B It is shown in Figure 6A A view showing the connection relationship between the pixel driving circuit and the data lines;

[0029] Figure 7A and Figure 7B It is an explanation applied to Figure 6A A conceptual diagram of the data compensation method for a pixel-structured data compensator;

[0030] Figure 8A This illustrates an embodiment of the concept according to the present invention. Figure 2C An enlarged plan view of region A1 shown in the figure;

[0031] Figure 8B It is shown in Figure 8A A view showing the connection relationship between the pixel driving circuit and the emitting element in region A4;

[0032] Figure 9A This is a plan view illustrating a display panel according to an embodiment of the concept of the present invention;

[0033] Figure 9B It is shown in Figure 9A An enlarged plan view of region A5 shown in the diagram;

[0034] Figure 10A This is an internal block diagram illustrating an embodiment of a controller according to the present invention; and

[0035] Figure 10B It is shown in Figure 9B The diagram shows the internal block diagram of the driver chip. Detailed Implementation

[0036] In the following description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of various embodiments or implementations of the invention. As used herein, “embodiment” and “implementation” are interchangeable terms and are non-limiting examples of apparatus or methods using one or more inventive concepts disclosed herein. However, it will be apparent that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in the block diagrams to avoid unnecessarily obscuring the various embodiments. Furthermore, the various embodiments may be different, but are not necessarily exclusive. For example, a particular shape, configuration, and characteristic of an embodiment may be used or implemented in another embodiment without departing from the inventive concept.

[0037] Unless otherwise specifically stated, the embodiments shown are to be understood as illustrative features providing details of variations in how the inventive concept can be implemented in practice. Therefore, unless otherwise specifically stated, features, components, modules, layers, films, panels, regions, and / or aspects (hereinafter individually or collectively referred to as “elements”) of various embodiments may be additionally combined, separated, interchanged, and / or rearranged without departing from the inventive concept.

[0038] Crosshairs and / or shading used in the accompanying drawings are generally provided to clarify the boundaries between adjacent elements. Therefore, unless otherwise specified, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for a particular material, material properties, size, scale, commonalities between the elements shown, and / or any other characteristics, properties, etc., of the elements. Additionally, in the accompanying drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, a particular process sequence may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously, or in the reverse order of their description. Similarly, the same reference numerals denote the same elements.

[0039] When an element (such as a layer) is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or one or more intermediary elements or layers may be present. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, no intermediary element or layer is present. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection with or without an intermediary element. Furthermore, the D1, D2, and D3 axes are not limited to the three axes of a Cartesian coordinate system such as the x, y, and z axes, and can be interpreted in a broader sense. For example, the D1, D2, and D3 axes can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0040] Although the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element.

[0041] Spatial relative terms, such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side” (e.g., as in “sidewall”), may be used herein for descriptive purposes and thus describe the relationship of one element to another (or more elements) as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are intended to cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features will subsequently be oriented “above” other elements or features. Thus, the term “below” can cover both orientations above and below. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and similarly, the spatial relative terms used herein may be interpreted accordingly.

[0042] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms. Furthermore, the terms “comprising,” “including,” “containing,” and / or “having” as used in this specification indicate the presence of the stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than terms of degree, and thus, to explain the inherent biases in measured, calculated, and / or provided values ​​that would be recognized by those skilled in the art.

[0043] Various embodiments are described herein with reference to cross-sectional and / or exploded views as schematic diagrams of idealized embodiments and / or intermediate structures. Thus, variations in the shapes shown in the drawings are anticipated due to factors such as manufacturing techniques and / or tolerances. Therefore, the embodiments disclosed herein should not necessarily be construed as limited to the shapes of the specifically shown areas, but will include, for example, deviations in shape due to manufacturing processes. In this way, the areas shown in the drawings may be schematic in nature, and the shapes of these areas may not reflect the actual shapes of the areas of the device, and are thus not necessarily intended to be limiting.

[0044] As is customary in the art, some embodiments are described and illustrated in the accompanying drawings in terms of functional blocks, units, and / or modules. Those skilled in the art will understand that these functional blocks, units, and / or modules are physically implemented by electronic (or optical) circuits, such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, and wiring connections, which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where functional blocks, units, and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and optionally driven by firmware and / or software. It is also contemplated that each functional block, unit, and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware for performing some functions and processors (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions. Furthermore, without departing from the scope of the inventive concept, each functional block, unit, and / or module of some embodiments may be physically divided into two or more interacting and discrete functional blocks, units, and / or modules. Furthermore, without departing from the scope of the inventive concept, the functional blocks, units and / or modules of some embodiments can be physically combined into more complex functional blocks, units and / or modules.

[0045] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is part. Unless expressly defined herein, terms such as those defined in a general dictionary should be interpreted as having meanings consistent with their meanings in the context of the relevant field and should not be interpreted in an idealized or overly formalized sense.

[0046] In the present invention, it will be understood that when an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, the element or layer may be directly on, directly connected to or coupled to the other element or layer, or an intermediary element or layer may exist. Conversely, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, no intermediary element or layer exists.

[0047] The same numbers always refer to the same components. For the purpose of effectively describing the technical content, the thickness, scale, and dimensions of components are exaggerated. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0048] It will be understood that although the terms first, second, etc., may be used herein to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of the invention, the first element, first component, first area, first layer, or first portion discussed below may be defined as a second element, second component, second area, second layer, or second portion. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms.

[0049] Spatial relative terms, such as “below,” “under,” “down,” “above,” and “above,” are used herein for ease of description to describe the relationship of one element or feature to another element (or feature) or feature (or feature) as shown in the accompanying figures. It will be understood that, in addition to the orientation depicted in the figures, spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as “below” or “under” other elements or features will subsequently be oriented “above” other elements or features. Thus, the exemplary term “below” can cover both orientations above and below. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative terms used herein may be interpreted accordingly.

[0050] It will also be understood that the terms “may include” and / or “include” as used in this specification indicate the presence of the stated features, integers, steps, operations, elements, components and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0051] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Unless expressly defined herein, terms such as those defined in a general dictionary shall be interpreted as having meanings consistent with their meanings in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense.

[0052] The inventive concept will be explained in detail below with reference to the accompanying drawings.

[0053] Figure 1A This is a perspective view illustrating a display device DD according to an embodiment of the present invention. Figure 1B This is shown when viewed in the second direction DR2. Figure 1A The side view of the display device DD shown, and Figure 1C This is shown when viewed in the first direction DR1. Figure 1A The side view of the display device DD shown.

[0054] Figures 1A to 1C A smartphone is shown as a representative example of a display device DD; however, the display device DD is not limited to smartphones. That is, the display device DD of the present invention can also be applied to large electronic products, such as televisions or monitors, as well as small and medium-sized electronic products, such as mobile phones, tablets, car navigation devices, gaming devices, or smartwatches.

[0055] The display device DD may include active areas AA1 and AA2 in which an image IM is displayed, and a peripheral area NAA in which no image IM is displayed. Figure 1A In the example of an image IM, a date, time, and icon image are shown.

[0056] Active regions AA1 and AA2 may include a first active region AA1 having a planar shape and a second active region AA2 extending from the first active region AA1. The second active region AA2 may be curved from the first active region AA1 with a predetermined curvature; however, the shape of the second active region AA2 should not be limited thereto or thereby restricted. For example, the second active region AA2 may have a planar shape that is substantially parallel, inclined, or perpendicular to the first active region AA1. The first active region AA1 and the second active region AA2 are regions classified according to their shapes and may be practically implemented in a single display surface. The peripheral region NAA is the area in which no image IM is displayed. A border area may be defined in the display device DD by the peripheral region NAA.

[0057] The first active region AA1 can be substantially parallel to the plane defined by the first direction DR1 and the second direction DR2. The normal direction of the first active region AA1, i.e., the thickness direction of the display device DD, can be substantially parallel to the third direction DR3. The front (or upper) surface and rear (or lower) surface of each component of the display device DD can be defined relative to the third direction DR3. However, the first direction DR1, the second direction DR2, and the third direction DR3 can be interdependent and can be changed to other directions.

[0058] The second active region AA2 may be a region that curves and extends from the first active region AA1. The second active region AA2 may include edge active regions AA2_E1 to AA2_E4 that curve from the sides of the first active region AA1, and angular active regions AA2_C1 to AA2_C4 that curve from the corners of the first active region AA1. The second active region AA2 may include a first edge active region AA2_E1 that curves from a first side of the first active region AA1, a second edge active region AA2_E2 that curves from a second side of the first active region AA1, a third edge active region AA2_E3 that curves from a third side of the first active region AA1, and a fourth edge active region AA2_E4 that curves from a fourth side of the first active region AA1. Each of the first edge active regions AA2_E1 to the fourth edge active regions AA2_E4 may be curved with a predetermined curvature on a third-direction DR3. Each of the first edge active regions AA2_E1 to the fourth edge active regions AA2_E4 may have a single curved surface. Figure 1A The diagram shows the first edge active region AA2_E1 to the fourth edge active region AA2_E4 bent with the same curvature; however, the inventive concept should not be limited thereto or thereby restricted. As an example, the first edge active region AA2_E1 and the second edge active region AA2_E2 may be bent with a curvature different from that of the third edge active region AA2_E3 and the fourth edge active region AA2_E4.

[0059] The second active region AA2 may further include a first-angle active region AA2_C1 that bends from the first corner of the first active region AA1, a second-angle active region AA2_C2 that bends from the second corner of the first active region AA1, a third-angle active region AA2_C3 that bends from the third triangle of the first active region AA1, and a fourth-angle active region AA2_C4 that bends from the fourth corner of the first active region AA1.

[0060] The first corner active region AA2_C1 can be set between the first edge active region AA2_E1 and the third edge active region AA2_E3, and the second corner active region AA2_C2 can be set between the first edge active region AA2_E1 and the fourth edge active region AA2_E4. The third corner active region AA2_C3 can be set between the second edge active region AA2_E2 and the third edge active region AA2_E3, and the fourth corner active region AA2_C4 can be set between the second edge active region AA2_E2 and the fourth edge active region AA2_E4.

[0061] Each of the first-angle active regions AA2_C1 to the fourth-angle active regions AA2_C4 can be bent at a predetermined curvature on the third-direction DR3. Each of the first-angle active regions AA2_C1 to the fourth-angle active regions AA2_C4 can have a hyperboloid surface.

[0062] The number of edge active regions AA2_E1 to AA2_E4 and the number of corner active regions AA2_C1 to AA2_C4 should not be limited to or restricted by this. That is, the number of edge active regions AA2_E1 to AA2_E4 and the number of corner active regions AA2_C1 to AA2_C4 included in the second active region AA2 can be varied according to the shape of the first active region AA1. Furthermore, at least one of the edge active regions AA2_E1 to AA2_E4 and the corner active regions AA2_C1 to AA2_C4 can be omitted.

[0063] According to embodiments of the present invention, a first image displayed through a first active area AA1 and a second image displayed through a second active area AA2 can be interdependent. For example, a picture, a scene from a movie, or a UX / UI design can be formed by combining the first and second images. Since the second active area AA2 is curved at a predetermined curvature, the aesthetics of the display device DD can be improved, and the size of the user-perceived peripheral area NAA can be reduced.

[0064] However, the embodiments are not limited thereto. The first image displayed through the first active area AA1 and the second image displayed through the second active area AA2 can be independent of each other.

[0065] Figure 2A This is an exploded perspective view of a display device DD according to an embodiment of the present invention. Figure 2B This is a block diagram illustrating a display device DD according to an embodiment of the concept of the present invention. Figure 2C and Figure 2D This is a plan view illustrating a display panel DP according to an embodiment of the concept of the present invention.

[0066] Reference Figure 2A The display device DD may include a window WM, a display panel DP, and a housing HU. The window WM protects the upper surface of the display panel DP. The window WM may be optically transparent. Therefore, the user can perceive the image displayed through the display panel DP through the window WM. In other words, the window WM defines the display surface of the display device DD. The window WM may be made of glass, plastic, or film.

[0067] The window WM may have a curved structure. The window WM may include a front surface portion FS and one or more curved surface portions curved from the front surface portion FS. In this case, the front surface portion FS and the one or more curved surface portions may be referred to as a transmissive image or a transmissive portion of light. The front surface portion FS of the window WM may define a first active area AA1 of the display device DD (see reference). Figure 1A And one or more curved portions may define the second active area AA2 of the display device DD (refer to...). Figure 1A ).

[0068] As an example, the window WM may include four curved surface portions: a first curved surface portion ES1, a second curved surface portion ES2, a third curved surface portion ES3, and a fourth curved surface portion ES4. In this embodiment, the front surface portion FS may be a plane defined by a first direction DR1 and a second direction DR2. The front surface portion FS may be a plane substantially perpendicular to the third direction DR3. Each of the first curved surface portions ES1 to the fourth curved surface portion ES4 may be bent from the front surface portion FS. Each of the first curved surface portion ES1 and the second curved surface portion ES2 may be bent from the front surface portion FS. The first curved surface portion ES1 and the second curved surface portion ES2 may be bent from a first side surface and a second side surface of the front surface portion FS, respectively. The first side surface and the second side surface of the front surface portion FS may be substantially parallel to the first direction DR1. The first curved surface portion ES1 and the second curved surface portion ES2 may be arranged parallel to each other in the first direction DR1. Each of the third curved surface portion ES3 and the fourth curved surface portion ES4 may be bent from the front surface portion FS. In particular, the third curved surface portion ES3 and the fourth curved surface portion ES4 may be bent from the third side surface and the fourth side surface of the front surface portion FS, respectively. The third and fourth sides of the front surface portion FS can be substantially parallel to the second direction DR2. The third curved surface portion ES3 and the fourth curved surface portion ES4 can be set parallel to each other in the second direction DR2.

[0069] The first surface portion ES1 to the fourth surface portion ES4 can be bent from the front surface portion FS with a predetermined curvature. As an example, the first surface portion ES1 to the fourth surface portion ES4 can have the same curvature as each other. As another example, the first surface portion ES1 and the second surface portion ES2 can have the same curvature as each other, and the third surface portion ES3 and the fourth surface portion ES4 can have the same curvature as each other. However, the first surface portion ES1 and the second surface portion ES2 can have different curvatures than the third surface portion ES3 and the fourth surface portion ES4.

[0070] The window WM may also include at least one corner portion. As an example, the window WM may also include four corner portions, namely, a first corner portion CS1, a second corner portion CS2, a third corner portion CS3, and a fourth corner portion CS4. Each of the first corner portions CS1 to the fourth corner portion CS4 may include at least two curvatures. Each of the first corner portions CS1 to the fourth corner portion CS4 may have a shape in which surfaces having different curvatures from each other are continuously connected.

[0071] A first corner portion CS1 can be disposed between a first curved surface portion ES1 and a third curved surface portion ES3 to connect the first curved surface portion ES1 and the third curved surface portion ES3. A second corner portion CS2 can be disposed between a first curved surface portion ES1 and a fourth curved surface portion ES4 to connect the first curved surface portion ES1 and the fourth curved surface portion ES4. A third corner portion CS3 can be disposed between a second curved surface portion ES2 and a third curved surface portion ES3 to connect the second curved surface portion ES2 and the third curved surface portion ES3. A fourth corner portion CS4 can be disposed between a second curved surface portion ES2 and a fourth curved surface portion ES4 to connect the second curved surface portion ES2 and the fourth curved surface portion ES4. Each of the first corner portions CS1 to the fourth corner portion CS4 can be referred to as a transmitted image or a transmitted portion of light.

[0072] Reference Figure 2A and Figure 2C The display panel DP may include a display area for displaying images. As an example, the display area may include a first display area DA1 and a second display area DA2. The first display area DA1 may be parallel to the front surface portion FS of the window WM and may have a shape corresponding to the front surface portion FS. That is, the first display area DA1 may be a flat display area with a flat shape. The second display area DA2 may be configured to correspond to one or more curved surface portions and one or more corner portions. The second display area DA2 may have a curved shape corresponding to one or more curved surface portions and one or more corner portions. However, the shape of the second display area DA2 should not be limited to or constrained by this, and the second display area DA2 may also have a flat shape.

[0073] The second display area DA2 may include first edge display areas DA2_E1 to fourth edge display areas DA2_E4, respectively, which are respectively positioned to correspond to the first curved surface portion ES1 to the fourth curved surface portion ES4. The first edge display areas DA2_E1 and DA2_E2 can be curved from the first and second sides of the first display area DA1 and can be configured to correspond to the first curved surface portion ES1 and the second curved surface portion ES2 of the window WM, respectively. The first and second sides of the first display area DA1 can extend parallel to the first direction DR1. The first edge display areas DA2_E1 and DA2_E2 can be curved from the first display area DA1 with a predetermined curvature.

[0074] The third edge display area DA2_E3 and the fourth edge display area DA2_E4 can be curved from the third and fourth sides of the first display area DA1 and can be configured to correspond to the third curved surface portion ES3 and the fourth curved surface portion ES4 of the window WM, respectively. The third and fourth sides of the first display area DA1 can extend parallel to the second direction DR2. The third edge display area DA2_E3 and the fourth edge display area DA2_E4 can be curved from the first display area DA1 with a predetermined curvature.

[0075] In the above description of the display panel DP, a structure of the display panel DP in which the second display area DA2 includes four edge display areas DA2_E1 to DA2_E4 is described. However, the structure of the display panel DP conceived according to the present invention should not be limited to this or thus restricted. That is, the second display area DA2 of the display panel DP may include only one edge display area or may include only two edge display areas, which are provided at the first side and second side of the first display area DA1 or at the third side and fourth side of the first display area DA1.

[0076] The second display area DA2 may further include first corner display areas DA2_C1 to fourth corner display areas DA2_C4, respectively, corresponding to the first corner portions CS1 to the fourth corner portions CS4 of the window WM. The first corner display area DA2_C1 may be located between the first edge display area DA2_E1 and the third edge display area DA2_E3, and the second corner display area DA2_C2 may be located between the first edge display area DA2_E1 and the fourth edge display area DA2_E4. Furthermore, the third corner display area DA2_C3 may be located between the second edge display area DA2_E2 and the third edge display area DA2_E3, and the fourth corner display area DA2_C4 may be located between the second edge display area DA2_E2 and the fourth edge display area DA2_E4. The first corner display areas DA2_C1 to fourth corner display areas DA2_C4 may be areas in which an image is substantially displayed; however, the inventive concept should not be limited thereto or thereby restricted. In other words, as an example, the first corner display area DA2_C1 to the fourth corner display area DA2_C4 can be areas in which no image is displayed, and only a portion of the first corner display area DA2_C1 to the fourth corner display area DA2_C4 can display an image.

[0077] The display panel DP may include pixels disposed in a first display area DA1 and pixels disposed in a second display area DA2. In this case, the pixels disposed in the first display area DA1 will be referred to as first pixels, and the pixels disposed in the second display area DA2 will be referred to as second pixels. Each first pixel may include a first emitting element ED1 (see reference). Figure 3A and Figure 3B ) and the first pixel driving circuit PD1 connected to the first transmitting element (refer to Figure 3A and Figure 3B Each second pixel may include a second emitting element ED2 (see reference). Figure 3A and Figure 3B ) and the second pixel driving circuit PD2 connected to the second transmitting element (refer to Figure 3A and Figure 3B ).

[0078] Reference Figure 2B The display device DD also includes a controller 100, a gate driver 200, a data driver 300, a drive voltage generator 400, and an initialization voltage generator 500.

[0079] The controller 100 receives image data I_DATA and input control signal I_CS, and converts the data format of the image data I_DATA into a data format suitable for the interface between the controller 100 and the data driver 300 to generate an image signal IS. The controller 100 converts the input control signal I_CS into various control signals DCS, GCS, and VCS, as well as output control signals DCS, GCS, and VCS.

[0080] Gate driver 200 receives gate control signal GCS from controller 100. Gate control signal GCS includes a vertical start signal to initiate operation of gate driver 200 and a clock signal to determine the output timing of the signals. Gate driver 200 generates multiple scan signals and sequentially outputs the scan signals to multiple scan lines GIL1, GIL2, GIL3, ... to GILn, GWL1, GWL2, GWL3, ... to GWLn and GBL1, GBL2, GBL3, ... to GBLn, as described below. Furthermore, gate driver 200 generates multiple transmit control signals in response to gate control signal GCS and outputs the transmit control signals to multiple transmit control lines EL1, EL2, EL3, ... to ELn, as described below.

[0081] Figure 2BThe diagram illustrates a structure in which scan signals and transmit control signals are output from a gate driver 200; however, the inventive concept should not be limited thereto or thereby restricted. As an example, a scan drive circuit that generates and outputs multiple scan signals, and a transmit drive circuit that generates and outputs multiple transmit control signals, can be provided separately from each other. Furthermore, the gate driver 200 may be included in… Figure 2C The first gate driver GDC1 and the second gate driver GDC2 are shown in the figure. The first gate driver GDC1 and the second gate driver GDC2 can be electrically connected to the opposite ends of each scan line GIL1, GIL2, GIL3, ... to GILn, GWL1, GWL2, GWL3, ... to GWLn and GBL1, GBL2, GBL3, ... to GBLn.

[0082] The data driver 300 receives a data control signal DCS and an image signal IS from the controller 100. The data driver 300 converts the image signal IS into a data signal and outputs the data signal to multiple data lines DL1, DL2, ... to DLm, as described below. The data signal can be an analog voltage corresponding to the grayscale value of the image signal IS.

[0083] Drive voltage generator 400 receives a power supply voltage Vin from a power source (not shown). Drive voltage generator 400 converts the power supply voltage Vin to generate a first drive voltage ELVDD and a second drive voltage ELVSS having a voltage level different from the first drive voltage ELVDD. Drive voltage generator 400 may include a DC-DC converter. Drive voltage generator 400 may include a boost converter that boosts the power supply voltage Vin and generates the first drive voltage ELVDD. Additionally, drive voltage generator 400 may include a buck converter that reduces the power supply voltage Vin and generates the second drive voltage ELVSS. Drive voltage generator 400 receives a drive voltage control signal VCS from controller 100. Drive voltage generator 400 generates the first drive voltage ELVDD and the second drive voltage ELVSS in response to the drive voltage control signal VCS.

[0084] Initialization voltage generator 500 receives a first drive voltage ELVDD and a second drive voltage ELVSS from drive voltage generator 400. Initialization voltage generator 500 uses the first drive voltage ELVDD and the second drive voltage ELVSS to generate an initialization voltage Vint. The initialization voltage Vint has a voltage level different from the voltage level of the first drive voltage ELVDD and the voltage level of the second drive voltage ELVSS.

[0085] The display panel DP includes scan lines GIL1, GIL2, GIL3, ... to GILn, GWL1, GWL2, GWL3, ... to GWLn and GBL1, GBL2, GBL3, ... to GBLn; transmit control lines EL1, EL2, EL3, ... to ELn; data lines DL1, DL2, ... to DLm; and pixels PX. The scan lines GIL1, GIL2, GIL3, ... to GILn, GWL1, GWL2, GWL3, ... to GWLn and GBL1, GBL2, GBL3, ... to GBLn extend in a first direction DR1 and are arranged in a second direction DR2 perpendicular to the first direction DR1. Each transmit control line EL1, EL2, EL3, ... to ELn is arranged parallel to the corresponding scan lines in the scan lines GIL1, GIL2, GIL3, ... to GILn, GWL1, GWL2, GWL3, ... to GWLn and GBL1, GBL2, GBL3, ... to GBLn. Data lines DL1, DL2, ... to DLm are insulated from the scan lines GIL1, GIL2, GIL3, ... to GILn, GWL1, GWL2, GWL3, ... to GWLn to GBL1, GBL2, GBL3, ... to GBLn, while simultaneously crossing them.

[0086] Each pixel PX is connected to: the corresponding scan lines in scan lines GIL1, GIL2, GIL3, ... to GILn, GWL1, GWL2, GWL3, ... to GWLn and GBL1, GBL2, GBL3, ... to GBLn; the corresponding emission control lines in emission control lines EL1, EL2, EL3, ... to ELn; and the corresponding data lines in data lines DL1, DL2, ... to DLm. Figure 2B The diagram illustrates a structure in which each pixel PX is connected to three scan lines from GIL1, GIL2, GIL3, ... to GILn, GWL1, GWL2, GWL3, ... to GWLn, and GBL1, GBL2, GBL3, ... to GBLn. However, the inventive concept should not be limited thereto or thereby restricted. For example, each pixel PX may be connected to two scan lines from GIL1, GIL2, GIL3, ... to GILn, GWL1, GWL2, GWL3, ... to GWLn, and GBL1, GBL2, GBL3, ... to GBLn.

[0087] The display panel DP receives a first driving voltage ELVDD and a second driving voltage ELVSS. The first driving voltage ELVDD is applied to the pixel PX through a first power line. The second driving voltage ELVSS is applied to the pixel PX through an electrode (not shown) formed in the display panel DP or the second power line. The display panel DP receives an initialization voltage Vint. The initialization voltage Vint can be applied to the pixel PX through the initialization voltage line VIL.

[0088] exist Figure 2B The display panel DP shown may include, for example: Figure 2C The first display area DA1 and the second display area DA2 shown in the figure, and the pixel PX may include a first pixel set in the first display area DA1 and a second pixel set in the second display area DA2.

[0089] The gate driver 200 may include a first gate driver GDC1 and a second gate driver GDC2. The first gate driver GDC1 and the second gate driver GDC2 can generate scan signals and transmit control signals, and can output the generated signals to the corresponding pixels. The first gate driver GDC1 and the second gate driver GDC2 can be integrated into the display panel DP. That is, the first gate driver GDC1 and the second gate driver GDC2 can be directly formed in the display panel DP using a thin-film process for forming pixels PX.

[0090] The display panel DP may also include a non-display area surrounding the second display area DA2. The non-display area may be an area in which no image is displayed. The non-display area may surround the second display area DA2.

[0091] Each of the first gate driver GDC1 and the second gate driver GDC2 can be disposed in the second display area DA2 or can be disposed to partially overlap with the second display area DA2 including the second pixel PX2. Because each of the first gate driver GDC1 and the second gate driver GDC2 is disposed in the second display area DA2, an increase in the width of the non-display area due to the first gate driver GDC1 and the second gate driver GDC2 can be prevented. Therefore, the size of the non-display area of ​​the display device DD perceived by the user can be reduced by the second display area DA2.

[0092] exist Figure 2CIn this configuration, a first gate driver GDC1 is disposed adjacent to the outer side of the third edge display area DA2_E3, and a second gate driver GDC2 is disposed adjacent to the outer side of the fourth edge display area DA2_E4. Furthermore, the first gate driver GDC1 is disposed adjacent to the outer side of the first corner display area DA2_C1 and the third corner display area DA2_C3, and the second gate driver GDC2 is disposed adjacent to the outer side of the second corner display area DA2_C2 and the fourth corner display area DA2_C4. However, the positions of the first gate driver GDC1 and the second gate driver GDC2 should not be limited to or restricted by these conditions.

[0093] like Figure 2D As shown, a first gate driver GDC1 is disposed adjacent to the boundary of the first display area DA1 in the first corner display area DA2_C1 and the third corner display area DA2_C3, and a second gate driver GDC2 is disposed adjacent to the boundary of the first display area DA1 in the second corner display area DA2_C2 and the fourth corner display area DA2_C4. In the first corner display area DA2_C1 to the fourth corner display area DA2_C4, bending stress can increase further outward relative to the first display area DA1. When the first gate driver GDC1 and the second gate driver GDC2 are disposed adjacent to the outer side of the first corner display area DA2_C1 to the fourth corner display area DA2_C4, bending stress may affect the operation of the first gate driver GDC1 and the second gate driver GDC2. Therefore, because the first gate driver GDC1 and the second gate driver GDC2 are disposed adjacent to the first display area DA1 in the first corner display area DA2_C1 to the fourth corner display area DA2_C4, reliability degradation of the first gate driver GDC1 and the second gate driver GDC2 due to bending stress can be prevented.

[0094] In embodiments of the inventive concept, a first image displayed in a first display area DA1 and a second image displayed in a second display area DA2 may be interdependent. As an example, a picture, a scene from a movie, or a UX / UI design can be formed by combining the first and second images; however, the inventive concept should not be limited thereto or thereby restricted. For example, a portion of the second display area DA2 (e.g., the first corner display areas DA2_C1 to the fourth corner display areas DA2_C4) may display a black and white image or an image with a specific pattern that is independent of the first image.

[0095] As an example, the display panel DP can be an organic light-emitting display panel, an electrophoretic display panel, or an electrowetting display panel. Furthermore, the display panel DP can be a flexible display panel that bends along the shape of the window WM.

[0096] Refer again Figure 2AThe display panel DP may also include a pad area PP extending from the second display area DA2. The driver chip D-IC and pads may be disposed in the pad area PP of the display panel DP. The driver chip D-IC may include a data driver 300 (see reference). Figure 2B The driver chip D-IC, which incorporates a data driver 300, can apply data signals to the first display area DA1 and the second display area DA2 of the display panel DP. The driver chip D-IC may also include a drive voltage generator 400 (see reference). Figure 2B ) and initialization voltage generator 500 (refer to Figure 2B In this case, the driver chip D-IC can provide the first driving voltage ELVDD, the second driving voltage ELVSS, and the initialization voltage Vint to the first display area DA1 and the second display area DA2.

[0097] As an example, the driver chip D-IC can be mounted on the display panel DP. The display panel DP can be electrically connected to the flexible circuit film FCB via pads. According to an embodiment of the present invention, the driver chip D-IC can be mounted on the flexible circuit film FCB.

[0098] The housing HU may include a bottom BP and side walls SW. The side walls SW may extend from the bottom BP. The display panel DP may be accommodated within the receiving space defined by the bottom BP and side walls SW of the housing HU. The window WM may be coupled to the side walls SW of the housing HU. The side walls SW of the housing HU may support the edges of the window WM.

[0099] The housing HU may comprise a material with relatively high strength. For example, the housing HU may comprise glass, plastic, or metal, or multiple frames and / or plates formed by a combination of glass, plastic, and metal. The housing HU can stably protect the components of the display device DD housed within it from external impacts.

[0100] Figure 3A This illustrates an embodiment based on the concept of the present invention. Figure 2C An enlarged plan view of region A1 shown, and Figure 3B It is shown in Figure 3A The view shows the connection relationship between the emitting element and the pixel driving circuit in region A2. Figure 3C It is shown in Figure 3A The diagram shows the connection relationship between the pixel driving circuit and the data lines. Figure 3D This illustrates an embodiment of the concept according to the present invention. Figure 2C An enlarged plan view of region A3 shown, and Figure 3E It is shown in Figure 3D The diagram shows the connection relationship between the pixel driving circuit and the data lines.

[0101] Reference Figure 3A and Figure 3B A first pixel PX1 can be disposed in the first display area DA of the display panel DP. The first pixel PX1 may include multiple first red pixels, multiple first green pixels, and multiple first blue pixels. Each first pixel PX1 may include a first pixel driving circuit PD1 and a first emitting element ED1. A rectangular portion may represent the first pixel driving circuit PD1, and a shaded portion may represent a color emitting area. The first pixel driving circuit PD1 may be electrically connected to the corresponding first emitting element ED1 and can control the driving of the first emitting element ED1. In the first display area DA1, the first pixel driving circuit PD1 may be configured to overlap with the first emitting element ED1 electrically connected to the first pixel driving circuit PD1.

[0102] The fourth edge display area DA2_E4 of the second display area DA2 may include the first sub-area SA1 and the second sub-area SA2. Figures 3A to 3C The diagram shows only the fourth edge display area DA2_E4 of the second display area DA2. However, the first edge display areas DA2_E1 to the third edge display areas DA2_E3 and the first corner display areas DA2_C1 to the fourth corner display areas DA2_C4 of the second display area DA2 can have a similar structure to the fourth edge display area DA2_E4. Therefore, reference will be made to... Figures 3A to 3C The fourth edge display area DA2_E4 is described, and descriptions of other areas of the second display area DA2 will be omitted. However, for ease of explanation, the fourth edge display area DA2_E4 will be referred to as the second display area DA2 as a superordinate concept that includes the fourth edge display area DA2_E4.

[0103] The second pixel PX2 can be disposed in the second display area DA2 of the display panel DP. The second pixel PX2 may include multiple second red pixels, multiple second green pixels, and multiple second blue pixels. Each second pixel PX2 may include a second pixel driving circuit PD2 and a second emitting element ED2. The second pixel driving circuit PD2 can be electrically connected to the corresponding second emitting element ED2 and can control the driving of the second emitting element ED2. In the second display area DA2, the second pixel driving circuit PD2 can be configured not to overlap with the second emitting element ED2 electrically connected to it.

[0104] The second display area DA2 may include a first sub-area SA1 and a second sub-area SA2. Specifically, the fourth edge display area DA2_E4 of the second display area DA2 can be divided into a first sub-area SA1 and a second sub-area SA2. The third edge display area DA2_E3 of the second display area DA2 can also be divided into a first sub-area SA1 and a second sub-area SA2.

[0105] The second pixel driving circuit PD2 of the second pixel PX2 can be disposed in the first sub-region SA1, and the second emitting element ED2 of the second pixel PX2 can be disposed in the first sub-region SA1 and the second sub-region SA2. The second pixel driving circuit PD2 of the second pixel PX2 can be disposed in the first sub-region SA1, and the second gate driver GDC2 or the first gate driver GDC1 (refer to...) Figure 2C The second pixel driver circuit PD2 can be located in the second sub-region SA2. Therefore, the second pixel driver circuit PD2 may not overlap with the second gate driver GDC2 or the first gate driver GDC1.

[0106] Some second emitting elements ED2 in the second pixel PX2 are disposed in the first sub-region SA1, and other second emitting elements ED2 in the second pixel PX2 are disposed in the second sub-region SA2. Hereinafter, the second emitting elements ED2 disposed in the first sub-region SA1 are referred to as the first group of second emitting elements ED2, and the second emitting elements ED2 disposed in the second sub-region SA2 are referred to as the second group of second emitting elements ED2. The first group of second emitting elements ED2 is disposed on the second pixel driving circuit PD2 in the first sub-region SA1, and the second group of second emitting elements ED2 is disposed on the second gate driver GDC2 or the first gate driver GDC1 in the second sub-region SA2. Therefore, each of the second group of second emitting elements ED2 in the second sub-region SA2 may not overlap with the corresponding second pixel driving circuit PD2 electrically connected to each of the second group of second emitting elements ED2.

[0107] like Figure 3A and Figure 3B As shown, when comparing the first emitting element ED1 with a second emitting element ED2 that emits the same color as the first emitting element ED1, the first emitting element ED1 and the second emitting element ED2 can have the same size and shape. However, the number of second pixels PX2 arranged per unit area in the second display area DA2 can be equal to or less than the number of first pixels PX1 arranged per unit area in the first display area DA1. In this case, the term "unit area" can correspond to a size sufficient to cover at least four first pixels PX1. As an example, Figure 3AThe diagram illustrates a structure in which the number of second pixels PX2 arranged per unit area in the second display area DA2 is reduced to half (1 / 2) the number of first pixels PX1 arranged per unit area in the first display area DA1. However, the inventive concept should not be limited thereto or thereby restricted. As an example, the number of second pixels PX2 arranged per unit area in the second display area DA2 can be reduced to one-quarter (1 / 4) or one-eighth (1 / 8) of the number of first pixels PX1 arranged per unit area in the first display area DA1. In this case, the term "unit area" can correspond to a size sufficient to cover at least eight or sixteen first pixels PX1. In this respect, a portion of the first sub-region SA1 will remain unoccupied by the second emitting element ED2, and so will a portion of the second sub-region SA2.

[0108] Reference Figure 3C A first data line group DG1, including data lines DL1_1, DL1_2, DL1_3, DL1_4, DL1_5, DL1_6, DL1_7, and DL1_8 respectively connected to the first pixel PX1, can be disposed in the first display area DA1, and a second data line group DG2, including data lines DL2_1, DL2_2, DL2_3, DL2_4, DL2_5, DL2_6, DL2_7, and DL2_8 respectively connected to the second pixel PX2, can be disposed in the second display area DA2. For ease of explanation, Figure 3C The diagram shows eight data lines DL1_1, DL1_2, DL1_3, DL1_4, DL1_5, DL1_6, DL1_7, and DL1_8 included in the first data line group DG1, and eight data lines DL2_1, DL2_2, DL2_3, DL2_4, DL2_5, DL2_6, DL2_7, and DL2_8 included in the second data line group DG2. However, the number of data lines included in each of the first data line group DG1 and the second data line group DG2 should not be limited to or restricted by this.

[0109] Figure 3C The sixteen data lines shown, DL1_1, DL1_2, DL1_3, DL1_4, DL1_5, DL1_6, DL1_7, and DL1_8, and DL2_1, DL2_2, DL2_3, DL2_4, DL2_5, DL2_6, DL2_7, and DL2_8, are selected from... Figure 2B The data lines shown are DL1, DL2, ... to DLm.

[0110] The data lines DL1_1, DL1_2, DL1_3, DL1_4, DL1_5, DL1_6, DL1_7, and DL1_8 of the first data line group DG1 can be connected to the first pixel driving circuit PD1, and the data lines DL2_1, DL2_2, DL2_3, DL2_4, DL2_5, DL2_6, DL2_7, and DL2_8 of the second data line group DG2 can be connected to the second pixel driving circuit PD2.

[0111] like Figure 3D and Figure 3E As shown, at least a portion of the data lines DL1_1, DL1_2, DL1_3, DL1_4, DL1_5, DL1_6, DL1_7, and DL1_8 included in the first data line group DG1 can be connected to the second pixel driving circuit PD2. For example, with the first edge display area DA2_E1 and the second edge display area DA2_E2 (see reference). Figure 2C The overlapping data lines of the first corner display area DA2_C1 to the fourth corner display area DA2_C4 can be connected to the second pixel driving circuit PD2 and the first pixel driving circuit PD1.

[0112] Figure 4A It is shown in Figure 2B The internal block diagram of the controller 100 shown is as follows: Figure 4B It is shown in Figure 2B The internal block diagram of the data driver 300 shown is shown. Figures 5A to 5C It is an explanation applied to Figure 3A A conceptual diagram of the data compensation method for the pixel structure data compensator 110.

[0113] Reference Figure 3A and Figure 4A The controller 100 may include a data compensator 110 and a memory 120. The data compensator 110 may include an image analyzer 111, a data processor 112, and a synthesizer 113. The memory 120 may store information I_DA2 about the second display area DA2. As an example, the information I_DA2 may include information about the number of second pixels PX2 arranged in the second display area DA2, the size of each second pixel PX2, the width of the second display area DA2, and the position of the second pixel PX2.

[0114] Image analyzer 111 can receive image data I_DATA and divide the image data I_DATA into first image data ID1 corresponding to the first display area DA1 and second image data ID2 corresponding to the second display area DA2 based on information I_DA2. Data processor 112 can analyze the second image data ID2 and process the second image data ID2 based on the analysis results.

[0115] like Figure 4A , Figure 5A and Figure 5B As shown, the second image data ID2 may include valid data A_ID2 that substantially corresponds to the second pixel PX2 and invalid data NA_ID2 that substantially does not correspond to the second pixel PX2. The invalid data NA_ID2 is due to the display panel DP (refer to...). Figure 2A The data in the data set does not contain the second pixel PX2 corresponding to the invalid data NA_ID2, which is discarded. Each of the valid data A_ID2 and the invalid data NA_ID2 may include red image data R_D, blue image data B_D, first green image data G1_D, and second green image data G2_D.

[0116] The data processor 112 can use invalid data NA_ID2 from the second image data ID2 to compensate for valid data A_ID2, and can output compensated data C_ID2. Specifically, the data processor 112 can set a reference valid data R_A_ID2 from the valid data A_ID2, and can set peripheral data adjacent to the reference valid data R_A_ID2 from the invalid data NA_ID2. For example... Figure 5B As shown, when a valid data A_ID2 is set as a reference valid data R_A_ID2, six surrounding data adjacent to the reference valid data R_A_ID2 can be set. These six surrounding data can include two invalid data P_NA_ID2 and four valid data P_A_ID2. The number of surrounding data should not be limited by this or this restriction, and the number of invalid data P_NA_ID2 and valid data P_A_ID2 included in the surrounding data should not be specifically limited. Figure 5C As shown, eight peripheral data points can be set adjacent to the reference valid data R_A_ID2. These eight peripheral data points can include six invalid data points P_NA_ID2 and two valid data points P_A_ID2. Furthermore, the number of invalid and valid data points included in the peripheral data can be varied based on the position of the second pixel PX2 corresponding to the reference valid data R_A_ID2.

[0117] When the reference valid data R_A_ID2 is set to red image data R_D, the surrounding data can also be set to red image data R_D. That is, data of pixels with a different color than the pixel corresponding to the reference valid data R_A_ID2 can be excluded from being set as the surrounding data of the reference valid data R_A_ID2.

[0118] Data processor 112 can compensate reference valid data R_A_ID2 based on surrounding data to generate compensated data C_ID2. Furthermore, data processor 112 can set each valid data A_ID2 as reference valid data R_A_ID2 to perform a compensation operation on each valid data A_ID2. The compensated data C_ID2 generated by compensating valid data A_ID2 can be provided to synthesizer 113.

[0119] Synthesizer 113 can synthesize first image data ID1 and compensation data C_ID2, and can generate image signal IS. Image signal IS can be output from controller 100 and can be provided to data driver 300.

[0120] When one of the blue image data B_D, the first green image data G1_D, and the second green image data G2_D is set as the reference valid data R_A_ID2, the compensation process described above can be performed in the same manner. However, depending on the color of the pixel corresponding to the reference valid data R_A_ID2, the number of valid data and the number of invalid data included in the surrounding data can differ from each other.

[0121] like Figure 4B As shown, the data driver 300 may include a D / A converter 310 and an output buffer 320. The D / A converter 310 can receive an image signal IS and convert the image signal IS into an analog data signal DS. The D / A converter 310 can receive a reference gamma voltage R_GM from an external source (not shown). The D / A converter 310 can generate a data signal DS corresponding to the digital image signal IS based on the reference gamma voltage R_GM.

[0122] The data signal DS generated by the D / A converter 310 can be provided to the output buffer 320. The output buffer 320 can be connected to data lines DL1, DL2, ... to DLm (see reference). Figure 2B It can also provide the data signal DS to the data lines DL1, DL2, ... to DLm. The output buffer 320 can control the output timing of the data signal DS provided to the data lines DL1, DL2, ... to DLm.

[0123] according to Figures 4A to 5C Because the data compensator 110 uses invalid data NA_ID2 discarded between the first pixel PX1 and the second pixel PX2 to compensate for the valid data A_ID2 that is essentially provided to the second pixel PX2, the phenomenon that the boundary between the first display area DA1 and the second display area DA2 is observed can be prevented or reduced.

[0124] Figure 6AThis illustrates an embodiment of the concept according to the present invention. Figure 2C An enlarged plan view of region A1 shown, and Figure 6B It is shown in Figure 6A The diagram shows the connection relationship between the pixel driving circuit and the data lines. Figure 7A and Figure 7B It is an explanation applied to Figure 6A A conceptual diagram of the data compensation method for the pixel structure data compensator 110.

[0125] Reference Figure 6A The illustrated structure reduces the number of second pixels PX2 per unit area in the second display area DA2 to one-quarter (1 / 4) of the number of first pixels PX1 per unit area in the first display area DA1. However, the inventive concept should not be limited thereto. For example, the number of second pixels PX2 per unit area in the second display area DA2 can be reduced to one-eighth (1 / 8) or one-sixteenth (1 / 16) of the number of first pixels PX1 per unit area in the first display area DA1. In this case, the term "unit area" can correspond to a size sufficient to cover at least eight or sixteen first pixels PX1.

[0126] However, when the first emitting element ED1 is compared with the second emitting element ED2 which emits the same color as the first emitting element ED1, the first emitting element ED1 and the second emitting element ED2 can have the same size and shape.

[0127] Reference Figure 6B A first data line group DG1, including data lines DL1_1, DL1_2, DL1_3, DL1_4, DL1_5, DL1_6, DL1_7, and DL1_8 respectively connected to the first pixel PX1, can be disposed in the first display area DA1, and a second data line group DG2, including data lines DL2_1, DL2_2, DL2_3, DL2_4, DL2_5, DL2_6, DL2_7, and DL2_8 respectively connected to the second pixel PX2, can be disposed in the second display area DA2. For ease of explanation, Figure 6B The diagram shows eight data lines DL1_1, DL1_2, DL1_3, DL1_4, DL1_5, DL1_6, DL1_7, and DL1_8 included in the first data line group DG1, and eight data lines DL2_1, DL2_2, DL2_3, DL2_4, DL2_5, DL2_6, DL2_7, and DL2_8 included in the second data line group DG2. However, the number of data lines included in each of the first data line group DG1 and the second data line group DG2 should not be limited to or restricted by this.

[0128] Figure 6B The sixteen data lines shown, DL1_1, DL1_2, DL1_3, DL1_4, DL1_5, DL1_6, DL1_7, and DL1_8, and DL2_1, DL2_2, DL2_3, DL2_4, DL2_5, DL2_6, DL2_7, and DL2_8, are from... Figure 2B The data lines DL1, DL2, ... to DLm shown are the selected data lines.

[0129] The data lines DL1_1, DL1_2, DL1_3, DL1_4, DL1_5, DL1_6, DL1_7, and DL1_8 of the first data line group DG1 can be connected to the first pixel driving circuit PD1, and the data lines DL2_1, DL2_2, DL2_3, DL2_4, DL2_5, DL2_6, DL2_7, and DL2_8 of the second data line group DG2 can be connected to the second pixel driving circuit PD2. The number of first pixel driving circuits PD1 connected to the data lines DL1_1, DL1_2, DL1_3, DL1_4, DL1_5, DL1_6, DL1_7, and DL1_8 of the first data line group DG1 can be equal to or greater than the number of second pixel driving circuits PD2 connected to the data lines DL2_1, DL2_2, DL2_3, DL2_4, DL2_5, DL2_6, DL2_7, and DL2_8 of the second data line group DG2. Based on the number of driving circuits connected to a data line, the number of second pixel driving circuits PD2 can be 1 / 2 times smaller than the number of first pixel driving circuits PD1.

[0130] Reference Figure 4A , Figure 7A and Figure 7B The second image data ID2 may include valid data A_ID2 that substantially corresponds to the second pixel PX2 and invalid data NA_ID2 that substantially does not correspond to the second pixel PX2. The invalid data NA_ID2 is due to the display panel DP (refer to...). Figure 2A The data for the second pixel PX2 corresponding to the invalid data NA_ID2 is not present in the data set and should be discarded. Figure 7A and Figure 5A In comparison, if the number of second pixels PX2 arranged in the second display area DA2 is reduced, the amount of discarded invalid data NA_ID2 may increase. Because the amount of invalid data NA_ID2 increases, the phenomenon observed at the boundary between the first display area DA1 and the second display area DA2 may be exacerbated.

[0131] The data processor 112 can use invalid data NA_ID2 from the second image data ID2 to compensate for valid data A_ID2, and can output compensated data C_ID2. Specifically, the data processor 112 can set a reference valid data R_A_ID2 from the valid data A_ID2, and can set surrounding data adjacent to the reference valid data R_A_ID2. The surrounding data may include at least one invalid data NA_ID2. Figure 7B As shown, when valid data A_ID2 is set as reference valid data R_A_ID2, six surrounding data adjacent to the reference valid data R_A_ID2 can be set. These six surrounding data can include four invalid data P_NA_ID2 and two valid data P_A_ID2. The number of surrounding data should not be limited by this or any other constraint, and the number of invalid data P_NA_ID2 and valid data P_A_ID2 included in the surrounding data should not be specifically limited.

[0132] When the reference valid data R_A_ID2 is set to red image data R_D, the surrounding data can also be set to red image data R_D. That is, the data of pixels with a color different from the color of the pixel corresponding to the reference valid data R_A_ID2 does not need to be set as the surrounding data of the reference valid data R_A_ID2.

[0133] Based on surrounding data, data processor 112 can compensate reference valid data R_A_ID2 to generate compensated data C_ID2. Furthermore, data processor 112 can set each valid data A_ID2 as reference valid data R_A_ID2 to perform a compensation operation on each valid data A_ID2. Because the operation after the compensation operation is related to the reference... Figure 4A , Figure 4B and Figures 5A to 5C The operations described are the same, so their descriptions will be omitted.

[0134] Figure 8A This illustrates an embodiment of the concept according to the present invention. Figure 2C An enlarged plan view of region A1 shown, and Figure 8B It is shown in Figure 8A The view shows the connection relationship between the pixel driving circuit and the emission element in region A4.

[0135] Reference Figure 8A and Figure 8BThe illustrated structure reduces the number of second pixels PX2 arranged per unit area in the second display area DA2 to one-quarter (1 / 4) of the number of first pixels PX1 arranged per unit area in the first display area DA1. However, the inventive concept should not be limited thereto or thereby restricted. For example, the number of second pixels PX2 arranged per unit area in the second display area DA2 can be reduced to one-eighth (1 / 8) or one-sixteenth (1 / 16) of the number of first pixels PX1 arranged per unit area in the first display area DA1. In this case, the term "unit area" can correspond to a size sufficient to cover at least eight or sixteen first pixels PX1.

[0136] However, when comparing the first emitting element ED1 with a second emitting element ED2 that emits the same color as the first emitting element ED1, the first emitting element ED1 and the second emitting element ED2 can have different sizes and shapes from each other. The second emitting element ED2 can have a size four times that of the first emitting element ED1; however, the inventive concept should not be limited thereto or thereby restricted. For example, the second emitting element ED2 can have a size two or three times that of the first emitting element ED1.

[0137] When Figure 8A and Figure 6A During the comparison, the size of the second pixel PX2 is changed, but the connection relationship between the second pixel PX2 in the second display area DA2 and the data lines DL2_1, DL2_2, DL2_3, DL2_4, DL2_5, DL2_6, DL2_7 and DL2_8 remains the same. Figure 6B Similar to that in [the text]. Therefore, although the second pixel PX2 is as [the text is incomplete and likely refers to a different Figure 8A The arrangement shown is possible, but can also be compared with the reference. Figure 7A and Figure 7B The method described is similar to the method used to compensate for the valid data A_ID2 corresponding to the second pixel PX2.

[0138] Figure 9A This is a plan view illustrating a display panel DP according to an embodiment of the concept of the present invention, and Figure 9B It is shown in Figure 9A The enlarged plan view of region A5 shown.

[0139] Reference Figure 9A The display panel DP may include a display area for displaying images. As an example, the display area may include a first display area DA1 and a second display area DA2. The first display area DA1 may be set to be the same as the window WM (see reference). Figure 2AThe front surface portion FS of the first display area DA1 is parallel and may have a shape corresponding to the front surface portion FS. That is, the first display area DA1 may be a flat display area with a flat shape. The second display area DA2 may be configured to correspond to one or more curved portions and one or more corner portions. The second display area DA2 may have a curved shape corresponding to one or more curved portions and one or more corner portions. However, the shape of the second display area DA2 should not be limited to or restricted by this, and the second display area DA2 may also have a flat surface shape.

[0140] The second display area DA2 may include a first edge display area DA2_E5 and a second edge display area DA2_E6. The first edge display area DA2_E5 and the second edge display area DA2_E6 may be curved from a first side and a second side of the first display area DA1. The first edge display area DA2_E5 and the second edge display area DA2_E6 may be curved from the first display area DA1 with a predetermined curvature. The first side and the second side of the first display area DA1 may extend substantially parallel to the first direction DR1.

[0141] The display panel DP may also include a non-display area NDA surrounding the second display area DA2. The non-display area NDA may be an area in which no image is displayed. The non-display area NDA may be defined on the third and fourth sides of the first display area DA1.

[0142] Each of the first gate driver GDC1 and the second gate driver GDC2 may be disposed within the second display area DA2 or may be disposed to partially overlap with the second display area DA2 and the second transmitting element ED2. The partially overlapping area may refer to a portion of the second display area DA2 and the second transmitting element ED2 herein. The first gate driver GDC1 and the second gate driver GDC2 may be disposed to overlap with the first edge display area DA2_E5 and the second edge display area DA2_E6, respectively. As an example, the first gate driver GDC1 may be disposed within the first edge display area DA2_E5, and the second gate driver GDC2 may be disposed within the second edge display area DA2_E6.

[0143] This prevents an increase in the width of the non-display area NDA due to the first gate driver GDC1 and the second gate driver GDC2, or the arrangement of the non-display area around the display area. Therefore, due to the second display area DA2, the size of the non-display area NDA observed by the user in the display device DD can be reduced.

[0144] The above description describes a structure in which the second display area DA2 in the display panel DP includes two edge display areas DA2_E5 and DA2_E6. However, the structure of the display panel DP according to the present invention should not be limited to this or restricted by it. That is, the second display area DA2 of the display panel DP may include only one edge display area.

[0145] Reference Figure 9A and Figure 9B The first data cable group DG1_1 can be located in the first display area DA1 of the display panel DP, and the second data cable group DG2_1 can be located in the second display area DA2 of the display panel DP. The first data cable group DG1_1 may include data cables DL1, DL2, ... to DLm (refer to...). Figure 2B Some of them, and the second data line group DG2_1 may include other data lines DL1, DL2, ... to DLm.

[0146] When the total number of data lines DL1, DL2, ... to DLm arranged in the display panel DP is 1440, the first data line group DG1_1 can include 1428 data lines, and the second data line group DG2_1 can include 12 data lines. The second data line group DG2_1 can include a first sub-data line group DG2_S1 located in the first edge display area DA2_E5, and a second sub-data line group DG2_S2 located in the second edge display area DA2_E6. Each of the first sub-data line group DG2_S1 and the second sub-data line group DG2_S2 can include six data lines. The number of data lines contained in each of the data line groups DG1_1, DG2_S1, and DG2_S2 should not be specifically limited.

[0147] The driver chip D-IC can be mounted on the display panel DP. A panel pad portion PD_P can be provided adjacent to the driver chip D-IC in the display panel DP. The panel pad portion PD_P may include a first pad portion PP1 and a second pad portion PP2. The first pad portion PP1 can receive a first pixel PX1 (refer to...) disposed in the first display area DA1. Figure 3A The signal is applied to the second pixel PX2 (see reference ) and the second pad portion PP2 can receive the signal applied to the second pixel PX2 arranged in the second display area DA2. Figure 3A () signal.

[0148] The second pad portion PP2 may include a first sub-pad portion PP2_1 and a second sub-pad portion PP2_2. The first sub-pad portion PP2_1 may receive a signal applied to a second pixel PX2 disposed in the first edge display area DA2_E5, and the second sub-pad portion PP2_2 may receive a signal applied to a second pixel PX2 disposed in the second edge display area DA2_E6.

[0149] The driver chip D-IC can be connected to the panel pad portion PD_P. The driver chip D-IC may include a data driver 300 (see reference). Figure 2B The data driver 300 may include a first driver electrically connected to a first pad portion PP1 and a second driver electrically connected to a second pad portion PP2. (See reference...) Figure 10B A detailed description of the driver chip D-IC.

[0150] Figure 10A This is an internal block diagram illustrating an embodiment of the controller 101 according to the present invention, and Figure 10B It is shown in Figure 9B The diagram shows the internal block diagram of the driver chip D-IC.

[0151] Reference Figure 10A and Figure 10B The controller 101 may include a data converter 130 and a memory 120. The data converter 130 may include an image analyzer 131 and a converter 132. The memory 120 may store information I_DA2 about the second display area DA2. As an example, the information I_DA2 may include information about the number of second pixels PX2 arranged in the second display area DA2, the size of each second pixel PX2, the width of the second display area DA2, and the position of the second pixels PX2.

[0152] Image analyzer 131 can receive image data I_DATA and, based on information I_DA2, can divide the image data I_DATA into first image data ID1 corresponding to the first display area DA1 and second image data ID2 corresponding to the second display area DA2. In this case, the second image data ID2 can be divided into first sub-image data ID2_1 and second sub-image data ID2_2. The first sub-image data ID2_1 may be data corresponding to the first edge display area DA2_E5 of the second display area DA2, and the second sub-image data ID2_2 may be data corresponding to the second edge display area DA2_E6 of the second display area DA2.

[0153] Converter 132 can receive first image data ID1 and second image data ID2 from image analyzer 131. Converter 132 can convert the first image data ID1 into a first image signal IS1 corresponding to the first pixel PX1, and can convert the second image data ID2 into a second image signal IS2 corresponding to the second pixel PX2. The second image signal IS2 may include a first sub-image signal IS2_1 obtained by converting the first sub-image data ID2_1 and a second sub-image signal IS2_2 obtained by converting the second sub-image data ID2_2. The first image signal IS1 and the second image signal IS2 can be provided to the driver chip D-IC.

[0154] The driver chip D-IC can receive a first image signal IS1 and a second image signal IS2 from the controller 101. The driver chip D-IC may include a first D / A converter 330 for receiving the first image signal IS1, a second D / A converter 341 for receiving the first sub-image signal IS2_1, and a third D / A converter 342 for receiving the second sub-image signal IS2_2. The first driver may include the first D / A converter 330, and the second driver 340 may include the second D / A converter 341 and the third D / A converter 342.

[0155] The first D / A converter 330 can receive a first image signal IS1 and convert the first image signal IS1 into a first data signal DS1 based on a predetermined first reference gamma voltage R_GM1. The second D / A converter 341 can receive a first sub-image signal IS2_1 and convert the first sub-image signal IS2_1 into a first sub-data signal DS2_1 based on a predetermined second reference gamma voltage R_GM2. The third D / A converter 342 can receive a second sub-image signal IS2_2 and convert the second sub-image signal IS2_2 into a second sub-data signal DS2_2 based on a predetermined third reference gamma voltage R_GM3.

[0156] The first reference gamma voltage R_GM1 can be different from the second reference gamma voltage R_GM2 and the third reference gamma voltage R_GM3, and the second reference gamma voltage R_GM2 and the third reference gamma voltage R_GM3 can be the same as each other or can be different from each other. The second D / A converter 341 and the third D / A converter 342 can convert the image signal based on a reference gamma voltage different from the reference gamma voltage of the first D / A converter 330. Therefore, although the first D / A converter 330, the second D / A converter 341, and the third D / A converter 342 receive image signals with the same grayscale, the second D / A converter 341 and the third D / A converter 342 can output data signals with voltage levels different from the voltage level of the data signal output by the first D / A converter 330. For example, at the same grayscale, the second D / A converter 341 and the third D / A converter 342 can output data signals with voltage levels higher than the voltage level of the data signal output from the first D / A converter 330. Therefore, the brightness difference between the first display area DA1 and the second display area DA2 can be compensated.

[0157] The driver chip D-IC may also include an output buffer 321. The output buffer 321 can be connected to a first D / A converter 330, a second D / A converter 341, and a third D / A converter 342. The output buffer 321 can control the output timing of the first data signal DS1 and the second data signal DS2 output from the first D / A converter 330, the second D / A converter 341, and the third D / A converter 342, and can output the first data signal DS1 and the second data signal DS2 substantially simultaneously. The first data signal DS1 output from the output buffer 321 can be applied to... Figure 9B The first data line group DG1_1 is shown. The second sub-data signal DS2_1 output from the output buffer 321 can be applied to... Figure 9B The first sub-data line group DG2_S1 shown, and the third sub-data signal DS2_2 output from the output buffer 321 can be applied to Figure 9B The second sub-data line group DG2_S2 is shown in the diagram.

[0158] While specific embodiments and implementations have been described herein, other embodiments and modifications will become apparent from this specification. Therefore, the inventive concept is not limited to these embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements that will be apparent to those skilled in the art.

Claims

1. A display device, wherein, The display device includes: The display panel includes a plurality of first pixels disposed in a first display area and a plurality of second pixels disposed in a second display area adjacent to the first display area; A gate driver is disposed in the second display area of ​​the display panel to overlap with a portion of the second pixel, and is configured to drive the first pixel and the second pixel; The controller is configured to receive image data and convert the image data into an image signal; and A data driver is configured to convert the image signal into a data signal and output the data signal to the first pixel and the second pixel, wherein the controller compensates for valid data corresponding to the second pixel and reflects the compensated valid data back into the image signal, wherein the controller includes: A data compensator is configured to extract image data about the second display area from the image data, and to compensate the valid data corresponding to the second pixel in the extracted image data using invalid data in the extracted image data that does not correspond to the second pixel, to generate compensated data, wherein the data compensator includes: An image analyzer is configured to extract first image data about the first display area and second image data about the second display area from the image data; and A data processor is configured to receive the second image data, set reference valid data from the valid data, set surrounding data adjacent to the reference valid data, and compensate the reference valid data based on the surrounding data to generate the compensated data, wherein the surrounding data includes at least one invalid data adjacent to the reference valid data. The surrounding data also includes valid data adjacent to the reference valid data.

2. The display device according to claim 1, wherein, The data compensator also includes: A synthesizer is configured to synthesize the compensation data and the first image data to output the image signal.

3. The display device according to claim 1, wherein, The controller also includes: The memory stores information about the second display area. The image analyzer extracts the first image data and the second image data from the image data based on the information.

4. The display device according to claim 1, wherein, Each of the second pixels includes: The second emitting element emits light; and The second pixel driving circuit drives the second emitting element, and the second display area includes: A first sub-region, wherein a second pixel driving circuit for the second pixel is arranged; and The second sub-region contains the gate driver.

5. The display device according to claim 4, wherein, The first group of second emitting elements in the second pixel is disposed on the second pixel driving circuit in the first sub-region, and the second group of second emitting elements in the second pixel is disposed on the gate driver in the second sub-region.

6. The display device according to claim 4, wherein, The number of second pixels per unit area in the second display area is less than the number of first pixels per unit area in the first display area.

7. The display device according to claim 6, wherein, Each of the second emitting elements has a size equal to or greater than the size of the first emitting element included in each of the first pixels.

8. The display device according to claim 1, wherein, The number of invalid data and the number of valid data in the surrounding data change according to the position of the second pixel corresponding to the reference valid data.

9. The display device according to claim 1, wherein, The controller includes: The converter is configured to convert the first image data into a first image signal and the second image data into a second image signal. The data driver is further configured to convert the first image signal into a first data signal applied to the first pixel and to convert the second image signal into a second data signal applied to the second pixel.

10. The display device according to claim 9, wherein, The data driver includes: A first D / A converter receives the first image signal and converts the first image signal into the first data signal based on a predetermined first reference gamma voltage.

11. The display device according to claim 10, wherein, The second display area includes: A first edge display area is disposed on a first side of the first display area; and A second edge display area is disposed on a second side of the first display area, and the second image data includes: First sub-image data, corresponding to the first edge display area; and The second sub-image data corresponds to the second edge display area.

12. The display device according to claim 11, wherein, The second image signal includes: The first sub-image signal is obtained by converting the first sub-image data, and The second sub-image signal is obtained by converting the second sub-image data.

13. The display device according to claim 12, wherein, The data driver also includes: A second D / A converter is configured to receive the first sub-image signal and convert the first sub-image signal into a first sub-data signal based on a predetermined second reference gamma voltage; and A third D / A converter is configured to receive the second sub-image signal and convert the second sub-image signal into a second sub-data signal based on a predetermined third reference gamma voltage.

14. The display device according to claim 13, wherein, The first reference gamma voltage is different from the second reference gamma voltage and the third reference gamma voltage, and the second reference gamma voltage and the third reference gamma voltage are either equal to each other or different from each other.

15. The display device according to claim 13, wherein, The second data signal includes the first sub-data signal and the second sub-data signal.

16. The display device according to claim 9, wherein, The controller also includes: The memory stores information about the second display area, and based on the information, the image analyzer extracts the first image data and the second image data from the image data.

17. The display device according to claim 1, wherein, Each of the second pixels includes: The second emitting element emits light; and The second pixel driving circuit drives the second emitting element, and the second display area includes: A first sub-region, wherein a second pixel driving circuit for the second pixel is arranged; and The second sub-region is provided with the gate driver, the second emission element of the first group of pixels in the second pixel is provided on the second pixel driving circuit in the first sub-region, and the second emission element of the second group of pixels in the second pixel is provided on the gate driver in the second sub-region.

Images