Word line drive circuit and dynamic random access memory

Abstract

The application provides a word line driving circuit and a dynamic random access memory. The word line driving circuit comprises a first transistor, a second transistor, a third transistor and a fourth transistor. The gate of the first transistor is connected with a word line gate voltage, and the drain is connected with a word line. The gate of the second transistor is connected with a first driving voltage of the word line, and the drain is connected with the word line. The source of the first transistor and the source of the second transistor are connected with a negative bias voltage through the third transistor. That is, the source of the first transistor and the source of the second transistor are not directly connected with the negative bias voltage, but are connected with the negative bias voltage through the third transistor. Thus, when the word line driving circuit is in an active mode, the leakage current generated by the first transistor and the second transistor can be effectively reduced, so that the power consumption of the dynamic random access memory is reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a word line driving circuit and a dynamic random access memory. Background Technology

[0002] Currently, Dynamic Random Access Memory (DRAM) is widely used in various electronic products due to its advantages of low cost and high density.

[0003] Existing DRAM typically consists of multiple memory cells, each corresponding to and coupled to a word line, and the voltage of each word line is controlled by the word line driver circuit corresponding to each word line.

[0004] The word line driving circuit mentioned above typically includes two transistors. When the word line driving circuit is in active mode, leakage current is inevitably generated, which increases the power consumption of the DRAM. Summary of the Invention

[0005] This application provides a word line driving circuit and a dynamic random access memory, which can reduce leakage current generated in the word line driving circuit and reduce the power consumption of DRAM.

[0006] In a first aspect, embodiments of this application provide a word line driving circuit, including a first transistor, a second transistor, a third transistor, and a fourth transistor;

[0007] The gate of the first transistor is connected to the word line open-gate voltage, and the drain of the first transistor is connected to the word line.

[0008] The gate of the second transistor is connected to the first driving voltage of the word line, and the drain of the second transistor is connected to the word line;

[0009] The source of the first transistor and the source of the second transistor are both connected to a negative bias voltage through the third transistor;

[0010] The drain of the fourth transistor is connected to the word line, the source of the fourth transistor is connected to the second driving voltage of the word line, and the gate of the fourth transistor is connected to the gate-opening voltage of the word line.

[0011] In one possible design, the source of the first transistor and the source of the second transistor are both connected to the drain of the third transistor; the source of the third transistor is connected to a negative bias voltage.

[0012] In one possible design, the gate of the third transistor is connected to a power supply.

[0013] In one possible design, the gate of the third transistor is connected to the first driving voltage.

[0014] In one possible design, when the word line driving circuit is in active mode, the word line gate-opening voltage and the first driving voltage are at a low potential, and the second driving voltage and the word line output voltage are at a high potential.

[0015] In one possible design, the gate of the third transistor is connected to a power supply, and when the word line driving circuit is in active mode, the first transistor, the second transistor, and the third transistor respectively form a drain-source stacked structure.

[0016] In one possible design, the gate of the third transistor is connected to the first driving voltage, and when the word line driving circuit is in active mode, the third transistor is in a turned-off state, while the first transistor and the second transistor are in a floating state.

[0017] In one possible design, the first transistor, the second transistor, and the third transistor are all N-metal-oxide-semiconductor (NMOS) transistors, and the fourth transistor is a P-type metal-oxide-semiconductor (PMOS) transistor.

[0018] Secondly, embodiments of this application provide a dynamic random access memory, including word lines and word line driving circuits. The word line driving circuit is the word line driving circuit provided in the first aspect of this application, wherein the word line driving circuit is connected to the aforementioned word lines.

[0019] In the word line driving circuit and dynamic random access memory provided in this application embodiment, the word line driving circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The gate of the first transistor is connected to the word line turn-on voltage, and its drain is connected to the word line. The gate of the second transistor is connected to the first driving voltage of the word line, and its drain is connected to the word line. The sources of both the first and second transistors are connected to a negative bias voltage through the third transistor. That is, in this application, the sources of the first and second transistors are not directly connected to the negative bias voltage, but rather through the third transistor. This effectively reduces the leakage current generated by the first and second transistors when the word line driving circuit is in active mode, thereby reducing the power consumption of the dynamic random access memory. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments of this application or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the structure of a word line driving circuit in an embodiment of this application;

[0022] Figure 2 The leakage current I generated in the embodiments of this application OFF A schematic diagram of the path;

[0023] Figure 3 This is a schematic diagram of the structure of a novel word line driving circuit provided in the embodiments of this application;

[0024] Figure 4 This is a schematic diagram of another novel word line driving circuit provided in the embodiments of this application. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] In existing transistor manufacturing technologies, taking NMOS transistors as an example, a gate oxide layer is typically formed on a semiconductor substrate first, and a gate conductive layer (also called a gate electrode layer) is formed on the gate oxide layer. Then, the gate is formed by etching the gate conductive layer and the gate oxide layer. Next, the source region and drain region are formed in the substrate on both sides of the gate by ion implantation, thereby forming an NMOS transistor.

[0027] When a voltage is applied to the gate of an NMOS transistor, a conductive channel is formed between the source and drain regions, creating a potential difference between them, which in turn generates a current. The gate oxide layer acts as an insulating layer, preventing leakage current between the gate and source regions, and between the gate and drain regions.

[0028] However, with the rapid development of semiconductor manufacturing technology, semiconductor wafers are moving towards higher integration. The critical size of the gate of NMOS transistors is gradually shrinking, and the gate is becoming shorter and narrower. The conductive channel between the source and drain regions in the semiconductor substrate under the gate is also becoming shorter and narrower. This leads to a gradual increase in leakage current from the drain region to the semiconductor substrate or the source region, which affects the performance of semiconductor devices.

[0029] Existing dynamic random access memory (DRAM) typically includes multiple memory cells arranged in a matrix, several word lines arranged horizontally, and several bit lines arranged vertically. Each memory cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the transistor to turn on or off, thereby reading data information stored in the capacitor through the bit line, or writing data information into the capacitor for storage through the bit line.

[0030] In this system, the control gate of each memory cell is electrically connected to the word line driving circuit via a word line. The other end of the word line driving circuit is connected to the word line selection circuit, and the voltage of each word line is controlled by the word line driving circuit corresponding to each word line.

[0031] During a read operation, a word line select circuit is typically used to activate the channel region of the corresponding memory cell on a bit line. The memory cell then raises or lowers the bit line voltage to a specific value, where the bit line voltage corresponds to the stored information in the memory cell. This specific voltage value is compared with a reference voltage to determine whether the corresponding memory cell is a logic "1" or a logic "0".

[0032] The voltage signal on the word line can control the transistor to turn on or off, thereby reading data information stored in the capacitor through the bit line, or writing data information into the capacitor for storage through the bit line.

[0033] When the word line driving circuit is in active mode, the aforementioned transistors will inevitably generate leakage current, thereby increasing the power consumption of the DRAM.

[0034] Reference Figure 1 , Figure 1 This is a schematic diagram of a word line driving circuit according to an embodiment of this application. In the prior art, a word line driving circuit includes two NMOS transistors, namely a first NMOS transistor N1 and a second NMOS transistor N2, and a PMOS transistor P1. Wherein:

[0035] The drain of PMOS transistor P1 is connected to the word line (WL) and can drive the memory array connected to WL; the source of PMOS transistor P1 is connected to the second driving voltage PXID of WL; the gate of PMOS transistor P1 is connected to the word line turn-on voltage bMWL and uses the word line turn-on voltage bMWL as the control voltage of its gate. By controlling whether the second driving voltage PXID is passed, the conduction of WL is controlled.

[0036] The gate of the first NMOS transistor N1 is connected to the word line turn-on voltage bMWL, and the word line turn-on voltage bMWL is used as the control voltage for its gate; the drain of the first NMOS transistor N1 is connected to WL, and the source is connected to the negative bias voltage V. SS (or negative potential) connection, negative bias voltage V SS The output from the source and drain of the first NMOS transistor N1 is sent to WL, which can be used to turn off WL.

[0037] The gate of the second NMOS transistor N2 is connected to the first driving voltage PXIB of WL. This first driving voltage PXIB is a word line shutdown switch that can control the gate of the second NMOS transistor N2. The drain of the second NMOS transistor N2 is connected to WL, and the source is connected to the negative bias voltage V. SS Connection, negative bias V SS The output from the source and drain of the second NMOS transistor N2 is sent to WL, which can be used to turn off WL.

[0038] The aforementioned word line driving circuit typically operates in three modes: active mode, sleep mode, and power-down mode. When the word line driving circuit is in active mode, the second driving voltage PXID is at a high potential, the word line gate opening voltage bMWL is at a low potential, and the PMOS transistor P1 is in the on state. At this time, the first NMOS transistor N1 and the second NMOS transistor N2 are in the off state. A voltage difference is generated between the source and drain regions of the first NMOS transistor N1 and the second NMOS transistor N2, resulting in a leakage current I from the drain region to the source region. OFF .

[0039] Reference Figure 2 , Figure 2 The leakage current I generated in the embodiments of this application OFF A schematic diagram of the path.

[0040] exist Figure 2 In this context, for any transistor, when the gate (G) and source (S) are grounded and the drain (D) is connected to the operating voltage VDD, a leakage current I will be generated in the transistor. OFFFurthermore, as the channel length of the transistor device decreases, the leakage current I... OFF It will get worse.

[0041] To address the aforementioned technical problems, this application provides a novel word line driving circuit that can be applied to dynamic random access memory (DRAM). By adding a third transistor to an existing word line driving circuit, the source of the third transistor is connected to a negative bias voltage, and its drain is connected to the sources of the first transistor and the second transistor, respectively. That is, the sources of the first and second transistors are not directly connected to the negative bias voltage, but are connected to the negative bias voltage through the third transistor. This effectively reduces the leakage current generated by the first and second transistors when the word line driving circuit is in active mode, thereby reducing the power consumption of the DRAM.

[0042] For details, see Figure 3 , Figure 3 This is a schematic diagram of a novel word line driving circuit provided in an embodiment of this application. In one feasible implementation, the word line driving circuit includes a first transistor N1, a second transistor N2, a third transistor N3, and a fourth transistor P1. Wherein:

[0043] The gate of the first transistor N1 is connected to the word line gate-opening voltage bMWL, and the word line gate-opening voltage bMWL is used as the control voltage of its gate; the drain of the first transistor N1 is connected to WL, and the source is connected to the drain of the third transistor N3.

[0044] The gate of the second transistor N2 is connected to the first driving voltage PXIB of the word line WL. The first driving voltage PXIB is a word line shutdown switch that can control the gate of the second transistor N2. The drain of the second transistor N2 is connected to WL, and the source is connected to the drain of the third transistor N3.

[0045] The source of the third transistor N3 is connected to a negative bias voltage V. SS The gate is connected to the power supply VDD.

[0046] Among them, negative bias voltage V SS The voltage is introduced to the source of the first transistor N1 through the third transistor N3, and then output to WL through the source and drain of the first transistor N1. Negative bias V SS The signal is fed into the source of the second transistor N2 through the third transistor N3, and then output to WL through the source and drain of the second transistor N2.

[0047] The drain of the fourth transistor P1 is connected to WL, which can drive the memory array connected to WL; the source of the fourth transistor P1 is connected to the second driving voltage PXID of WL; the gate of the fourth transistor P1 is connected to the word line open voltage bMWL, and the word line open voltage bMWL is used as the control voltage of its gate. By controlling whether the second driving voltage PXID is passed, the conduction of WL is controlled.

[0048] In this embodiment, when the word line driving circuit is in active mode, under normal circumstances, the word line opening voltage bMWL is low, the second driving voltage PXID is high, the first driving voltage PXIB is low, and the word line WL output is high.

[0049] Since the sources of the first transistor N1 and the second transistor N2 are both connected to the drain of the third transistor N3, and the source of the third transistor N3 is connected to a negative bias voltage V... SS Therefore, in active mode, both the first transistor N1 and the second transistor N2 can form a cascade structure with the third transistor N3. At this time, the third transistor N3 is equivalent to a resistor, thereby reducing the leakage current of the first transistor N1 and the second transistor N2.

[0050] Optionally, the first transistor N1, the second transistor N2, and the third transistor N3 are all NMOS transistors, and the fourth transistor P1 is a PMOS transistor.

[0051] In the word line driving circuit provided in this application embodiment, the source of the first transistor N1 and the source of the second transistor N2 are not directly connected to the negative bias voltage, but are connected to the negative bias voltage through the third transistor N3. The gate of the third transistor is connected to the power supply. In active mode, both the first transistor N1 and the second transistor N2 can form a cascade structure with the third transistor N3, which effectively reduces the leakage current generated by the first transistor N1 and the second transistor N2, thereby reducing the power consumption of the dynamic random access memory.

[0052] Based on the content described in the above embodiments, see Figure 4 , Figure 4 This is a schematic diagram of another novel word line driving circuit provided in an embodiment of this application. In one feasible implementation, the word line driving circuit includes a first transistor N1, a second transistor N2, a third transistor N3, and a fourth transistor P1. Wherein:

[0053] The gate of the first transistor N1 is connected to the word line gate-opening voltage bMWL, and the word line gate-opening voltage bMWL is used as the control voltage of its gate; the drain of the first transistor N1 is connected to WL, and the source is connected to the drain of the third transistor N3.

[0054] The gate of the second transistor N2 is connected to the first driving voltage PXIB of the word line WL. The first driving voltage PXIB is a word line shutdown switch that can control the gate of the second transistor N2. The drain of the second transistor N2 is connected to WL, and the source is connected to the drain of the third transistor N3.

[0055] The source of the third transistor N3 is connected to a negative bias voltage V. SS The gate is connected to the first drive voltage PXIB.

[0056] Among them, negative bias voltage V SS The voltage is introduced to the source of the first transistor N1 through the third transistor N3, and then output to WL through the source and drain of the first transistor N1. Negative bias V SS The signal is fed into the source of the second transistor N2 through the third transistor N3, and then output to WL through the source and drain of the second transistor N2.

[0057] The drain of the fourth transistor P1 is connected to WL, which can drive the memory array connected to WL; the source of the fourth transistor P1 is connected to the second driving voltage PXID of WL; the gate of the fourth transistor P1 is connected to the word line open voltage bMWL, and the word line open voltage bMWL is used as the control voltage of its gate. By controlling whether the second driving voltage PXID is passed, the conduction of WL is controlled.

[0058] In this embodiment, when the word line driving circuit is in active mode, under normal circumstances, the word line opening voltage bMWL is low, the second driving voltage PXID is high, the first driving voltage PXIB is low, and the word line WL output is high.

[0059] Since the sources of the first transistor N1 and the second transistor N2 are both connected to the drain of the third transistor N3, and the source of the third transistor N3 is connected to a negative bias voltage V... SS The gate is connected to the first driving voltage PXIB, that is, the first transistor N1 and the second transistor N2 are connected to the negative bias voltage V. SS A third transistor N3 is also connected in front. Therefore, in active mode, the third transistor N3 is turned off, causing the first transistor N1 and the second transistor N2 to be in a floating state, thereby reducing the leakage current of the first transistor N1 and the second transistor N2.

[0060] Optionally, the first transistor N1, the second transistor N2, and the third transistor N3 are all NMOS transistors, and the fourth transistor P1 is a PMOS transistor.

[0061] In the word line driving circuit provided in this application embodiment, the source of the first transistor N1 and the source of the second transistor N2 are not directly connected to the negative bias voltage, but are connected to the negative bias voltage through the third transistor N3. The gate of the third transistor is connected to the first driving voltage PXIB. In active mode, the third transistor N3 is turned off, so that the first transistor N1 and the second transistor N2 are in a floating state, which can effectively reduce the leakage current generated by the first transistor N1 and the second transistor N2, thereby reducing the power consumption of the dynamic random access memory.

[0062] Furthermore, based on the content described in the above embodiments, this application also provides a dynamic random access memory, which includes word lines and word line driving circuits.

[0063] The word line driving circuit mentioned above is connected to the word line and is used to control the voltage of the word line.

[0064] Specifically, the word line driving circuit described above is the word line driving circuit described in the above embodiments. Its specific circuit structure can be referred to the description in the above embodiments, and will not be repeated here.

[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A word line drive circuit characterized by comprising: It includes a first transistor, a second transistor, a third transistor, and a fourth transistor; The gate of the first transistor is connected to the word line open-gate voltage, and the drain of the first transistor is connected to the word line. The gate of the second transistor is connected to the first driving voltage of the word line, and the drain of the second transistor is connected to the word line; The source of the first transistor and the source of the second transistor are both connected to a negative bias voltage through the third transistor; The drain of the fourth transistor is connected to the word line, the source of the fourth transistor is connected to the second driving voltage of the word line, and the gate of the fourth transistor is connected to the gate-opening voltage of the word line. The source of the first transistor and the source of the second transistor are both connected to the drain of the third transistor; the source of the third transistor is connected to the negative bias voltage. The gate of the third transistor is connected to the first driving voltage.

2. The word line drive circuit according to claim 1, characterized by When the word line driving circuit is in active mode, the word line opening voltage and the first driving voltage are at a low potential, and the second driving voltage and the word line output voltage are at a high potential.

3. The word line drive circuit according to claim 2, characterized by When the gate of the third transistor is connected to a power supply and the word line driving circuit is in active mode, the first transistor, the second transistor, and the third transistor respectively form a drain-source stacked structure.

4. The word line drive circuit of claim 2, wherein When the gate of the third transistor is connected to the first driving voltage, and the word line driving circuit is in active mode, the third transistor is in a turned-off state, and the first transistor and the second transistor are in a floating state.

5. The word line drive circuit of claim 1, wherein The first transistor, the second transistor, and the third transistor are all N-type metal-oxide-semiconductor (NMOS) transistors; the fourth transistor is a P-type metal-oxide-semiconductor (PMOS) transistor.

6. A dynamic random access memory, characterized by It includes word lines and the word line driving circuit according to any one of claims 1-5, wherein the word line driving circuit is connected to the word lines.

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