Method of testing a semiconductor device and testing apparatus

Abstract

The application provides a semiconductor device testing method and testing device, the testing method comprises the following steps: connecting the semiconductor device to the testing device, then taking one of the operating voltages in the incremental step pulse operation as a preset operating voltage, calculating a preset pulse number according to the operating pulse number of the incremental step pulse operation, the operating voltage multiple factor and the operating temperature multiple factor, and finally programming and erasing the semiconductor device for a preset number of times with the preset operating voltage of the preset pulse number, so that the peripheral high-voltage circuit of the semiconductor device can receive sufficient voltage stress, thus the stress characterization of the semiconductor device after testing is more accurate, and the accuracy of the testing result is improved.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a testing method and testing apparatus for semiconductor devices. Background Technology

[0002] High Temperature Operating Life (HTOL) testing is a high-temperature, long-term accelerated stress test for reliability, used to predict the lifespan of integrated circuit (IC) chips.

[0003] The existing high-temperature life test involves applying a reading voltage to the semiconductor device and then evaluating its lifespan by determining whether the post-stress characterization of the semiconductor device is qualified.

[0004] However, because the reading voltage is relatively low, using the reading voltage to perform high-temperature life tests on semiconductor devices will result in insufficient stress on the high-voltage circuitry surrounding the semiconductor device, leading to inaccurate test results. Summary of the Invention

[0005] This invention provides a testing method and apparatus for semiconductor devices, which effectively solves the problem that the high-voltage circuits surrounding the semiconductor device do not receive sufficient stress when using reading voltage to perform high-temperature life testing, resulting in inaccurate test results.

[0006] To address the above problems, the present invention provides a testing method for semiconductor devices, the testing method comprising:

[0007] Connect the semiconductor device to the testing apparatus;

[0008] One of the operating voltages in the incremental step pulse operation is used as the preset operating voltage, and the preset number of pulses is calculated based on the number of operating pulses, the operating voltage multiplier factor, and the operating temperature multiplier factor of the incremental step pulse operation.

[0009] The semiconductor device is programmed and erased a preset number of times using the preset operating voltage with the preset number of preset pulses.

[0010] According to a test method of an embodiment of the present invention, before the step of calculating the preset number of pulses based on the number of pulses in the incremental step pulse operation, the operating voltage multiplier factor, and the operating temperature multiplier factor, the method further includes:

[0011] The voltage acceleration factor was calculated based on the Allen model, and the temperature acceleration factor was calculated based on the Arrhenius model.

[0012] Based on the voltage acceleration factor and the temperature acceleration factor, the number of voltage equivalent pulses and the number of temperature equivalent pulses required to convert all the operating voltages of the incremental step pulse operation to the preset operating voltage under the influence of voltage or temperature are calculated respectively.

[0013] The number of voltage equivalent pulses, the number of temperature equivalent pulses, and the number of operating pulses of the incremental step pulse operation are calculated according to a preset formula to obtain the operating voltage multiplier factor and the operating temperature multiplier factor.

[0014] According to a test method of an embodiment of the present invention, the preset operating voltage is the maximum operating voltage in the incremental step pulse operation.

[0015] According to a test method of an embodiment of the present invention, the incremental step pulse operation includes incremental step pulse programming and incremental step pulse erasure.

[0016] According to a test method of an embodiment of the present invention, programming verification and erasure verification are not performed during the process of programming and erasing the semiconductor device a preset number of times.

[0017] According to a test method of an embodiment of the present invention, during the programming process of the semiconductor device a preset number of times, the memory cell array of the semiconductor device is written to an erase state.

[0018] According to a test method of an embodiment of the present invention, during the process of erasing the semiconductor device a preset number of times, the word lines of the semiconductor device are not selected.

[0019] According to a test method of an embodiment of the present invention, during the programming of the semiconductor device a preset number of times, a high-level voltage is written to the latch in the page buffer of the semiconductor device.

[0020] According to a test method of an embodiment of the present invention, before and after the step of programming and erasing the semiconductor device a preset number of times with the preset operating voltage of the preset number of preset pulses, the method further includes:

[0021] Record the initial characterization data and post-stress characterization data of the semiconductor device respectively;

[0022] The initial characterization data includes the initial static current, initial dynamic current, and initial timing of the semiconductor device, and the post-stress characterization data includes the post-stress static current, post-stress dynamic current, and post-stress timing of the semiconductor device.

[0023] According to a test method of an embodiment of the present invention, the semiconductor device is a 3D NAND flash memory.

[0024] According to a test method of an embodiment of the present invention, the test method covers the high-temperature life test of the peripheral high-voltage circuit of the 3D NAND flash memory.

[0025] On the other hand, the present invention also provides a testing apparatus for semiconductor devices, the testing apparatus comprising:

[0026] An enable module for connecting the semiconductor device to the test apparatus;

[0027] The setting module is used to take one of the first-level operating voltages in the incremental step pulse operation as the preset operating voltage, and calculate the preset number of pulses based on the number of operating pulses, the operating voltage multiplier factor, and the operating temperature multiplier factor of the incremental step pulse operation.

[0028] An operation module is used to program and erase the semiconductor device a preset number of times using the preset operating voltage with the preset number of preset pulses.

[0029] This invention provides a method for testing semiconductor devices, comprising: connecting the semiconductor device to a testing device; then, using one of the operating voltages in an incremental step pulse operation as a preset operating voltage; calculating a preset number of pulses based on the number of operating pulses in the incremental step pulse operation, an operating voltage multiplier factor, and an operating temperature multiplier factor; and finally, programming and erasing the semiconductor device a preset number of times using the preset operating voltage and the preset number of pulses. This method, by programming and erasing the semiconductor device with a preset operating voltage, allows the peripheral high-voltage circuitry of the semiconductor device to receive sufficient voltage stress, thereby resulting in a more accurate stress characterization of the semiconductor device after testing and improving the accuracy of the test results. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the present invention, the drawings used in the description of the various embodiments made according to the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0031] Figure 1 This is a schematic flowchart of a semiconductor device testing method provided by an embodiment of the present invention.

[0032] Figure 2This is a further schematic flowchart of a testing method for semiconductor devices provided according to an embodiment of the present invention.

[0033] Figure 3 This is a schematic diagram illustrating how, in a semiconductor device testing method provided by an embodiment of the present invention, all operating voltages in an incremental step pulse operation are equivalent to a preset operating voltage.

[0034] Figure 4 This is a schematic diagram of the structure of a test apparatus for a semiconductor device provided according to an embodiment of the present invention.

[0035] Figure 5 This is a schematic diagram of the structure of a semiconductor device provided according to an embodiment of the present invention. Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0037] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0038] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows for communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0039] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0040] The following disclosure provides many different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0041] Please see Figure 1 , Figure 1 A schematic flowchart of a testing method for a semiconductor device provided according to an embodiment of the present invention is shown. The testing method may specifically include the following steps:

[0042] Enable step S101: Connect the semiconductor device to the test apparatus;

[0043] Setting step S102: Take one of the first-level operating voltages in the incremental step pulse operation as the preset operating voltage, and calculate the preset number of pulses based on the number of operating pulses, the operating voltage multiplier factor, and the operating temperature multiplier factor of the incremental step pulse operation.

[0044] Operation step S103: Program and erase the semiconductor device a preset number of times using a preset operating voltage with a preset number of pulses.

[0045] It is easy to understand that the above enabling step S101 is to enable the test equipment to power the semiconductor.

[0046] It should be noted that incremental step pulse operation refers to using a pulse with a preset operating voltage V0 as the first-level operating pulse. As the number of operations increases, a preset voltage increment h is added to the preset operating voltage V0 each time. The i-th level operating voltage corresponding to the i-th level operating pulse can be expressed as Vi = V0 + (i-1) * h. The entire incremental step pulse operation has N levels of operating pulses, each corresponding to an N-level operating voltage. The "one-level operating voltage" mentioned above can be any one of these N levels of operating voltages.

[0047] It should be noted that, in this embodiment, the semiconductor device is a 3D NAND flash memory, and its peripheral circuitry includes: a charge pump circuit for providing operating voltage to each working module of the 3D NAND flash memory, a word line (X-path) high-voltage transmission circuit, a bit line (Y-path) high-voltage transmission circuit, a page buffer electrically connected to the bit line, and input / output ports (I / O ports). The test method provided in this embodiment can cover the high-temperature operating life (HTOL) test of the peripheral high-voltage circuitry (such as the charge pump circuit, word line high-voltage transmission circuit, and bit line high-voltage transmission circuit) of the 3D NAND flash memory.

[0048] In one embodiment, a high-temperature life test of a 3D NAND flash memory involves operating the 3D NAND flash memory for 1000 hours in a preset stress environment, during which read operations are performed on the 3D NAND flash memory. This preset environment may involve subjecting the 3D NAND flash memory to a test voltage greater than its power supply voltage and an environment with a temperature greater than 125 degrees Celsius. However, the voltage used for reading operations on the 3D NAND flash memory is lower than the voltage used for programming or erasing operations. Therefore, the high-temperature life test of the 3D NAND flash memory in this embodiment may result in inaccurate test results due to issues such as insufficient electrical stress received by its peripheral high-voltage circuitry (e.g., the word line high-voltage transmission circuit mentioned above), and the inability of the test to cover the charge pump circuitry and high-voltage circuitry associated with programming or erasing operations. The testing method provided in this embodiment programs and erases the 3D NAND flash memory with a preset operating voltage, allowing its peripheral high-voltage circuit to receive sufficient voltage stress. As a result, the stress characterization exhibited by the 3D NAND flash memory after testing is more accurate, and the accuracy of the test results is thus improved.

[0049] It should be noted that the aforementioned preset operating voltage is one of the operating voltages in incremental step pulse operation. Specifically, incremental step pulse operation includes incremental step pulse programming (ISPP) and incremental step pulse erasure (ISPE). Taking the programming operation of a semiconductor device using the incremental step pulse programming method as an example, this programming method involves using N-level programming pulses corresponding to N-level programming voltages to sequentially program and verify the memory cells of the semiconductor device until the number of verified memory cells reaches a set value. Similarly, the erasure operation of a semiconductor device using the incremental step pulse erasure method involves using N-level erasure pulses corresponding to N-level erasure voltages to sequentially erase and verify the memory cells of the semiconductor device until the number of verified memory cells reaches a set value.

[0050] Furthermore, since in this embodiment, the voltage values ​​of the preset operating voltage for the preset number of pulses are equal during a single operation on the semiconductor device, instead of increasing progressively as in the incremental step pulse operation with multiple programming voltage pulses, it is necessary to calculate the number of preset pulses required to produce the same electrical stress effect on the semiconductor device as the incremental step pulse operation when one of the operating voltage levels in the incremental step pulse operation is used as the preset operating voltage. Figure 3 As shown.

[0051] Because the calculated number of preset pulses is affected by both voltage and temperature when all operating voltages in the incremental step pulse operation are equivalent to the preset operating voltage, therefore, as Figure 2 As shown, the above setting step S102 may specifically include:

[0052] Acceleration factor calculation step S1021: Take one of the first-level operating voltages in the incremental step pulse operation as the preset operating voltage, and calculate the voltage acceleration factor and temperature acceleration factor according to the Ellen model and the Arrhenius model respectively.

[0053] Equivalent Step S1022: Based on the voltage acceleration factor and the temperature acceleration factor, calculate the number of voltage equivalent pulses and the number of temperature equivalent pulses required to convert all the operating voltages of the incremental step pulse operation to the preset operating voltage under the influence of voltage or temperature.

[0054] Multiplier factor calculation step S1023: Calculate the number of voltage equivalent pulses and temperature equivalent pulses with the number of operation pulses of incremental step pulse operation according to the preset formula to obtain the operation voltage multiplier factor and the operation temperature multiplier factor.

[0055] Equivalent calculation step S1024: Calculate the preset number of pulses based on the number of operating pulses, operating voltage multiplier factor, and operating temperature multiplier factor of the incremental step pulse operation.

[0056] It should be noted that in the acceleration factor calculation step S1021 described above, the acceleration factor is the ratio of the lifetime of a semiconductor device under normal stress to the lifetime under accelerated stress. Normal stress refers to the semiconductor device operating at normal voltage and normal temperature, while accelerated stress refers to the semiconductor device operating at stress voltage and stress temperature. Generally speaking, the stress voltage is higher than the normal voltage, and the stress temperature is higher than the normal temperature.

[0057] Specifically, the Eyring model is:

[0058] V AF =exp[a*(Vstress-Vnormal)]

[0059] Among them, V AFis the voltage acceleration factor, a is the voltage acceleration constant (typically, 0.5<a<1), Vstress is the stress voltage, and in this embodiment, Vstress is any one of N-level operating voltages, that is, Vstress=Vi=V0+(i-1)*h (where 0≤i≤N), and Vstress is the voltage at which the semiconductor device operates normally.

[0060] Specifically, the Arrhenius model is:

[0061] T AF =Lnormal / Lstress=exp[(Ea / k)*(1 / Tnormal-1 / Tstress)]

[0062] wherein, T AF is the temperature acceleration factor, Lnormal is the lifetime of the semiconductor device at normal temperature, Lstress is the lifetime of the semiconductor device at stress temperature, Ea is the activation energy of failure reaction (typically, 0.3eV<Ea<1.2eV), k is the Boltzmann constant (k=8.62×10–5eV / K), Tnormal is the normal temperature, and Tstress is the stress temperature.

[0063] It should be noted that in the respective equivalent step S1022 described above, the step of "the number of voltage-equivalent pulses and the number of temperature-equivalent pulses required to equivalently convert all levels of operating voltages in the incremental step pulse operation to a preset operating voltage" can be calculated by the following method:

[0064]

[0065]

[0066] wherein, J is the number of voltage-equivalent pulses required to equivalently convert all levels of operating voltages in the incremental step pulse operation to a preset operating voltage (specifically, the i-th level operating voltage), and K is the number of temperature-equivalent pulses required to equivalently convert all levels of operating voltages in the incremental step pulse operation to a preset operating voltage (specifically, the i-th level operating voltage).

[0067] It should be noted that in the multiple factor calculation step S1023 described above, the operating voltage multiple factor AF_V and the operating temperature multiple factor AF_T can be calculated according to the following calculation formulas:

[0068] AF_V=N / J

[0069] AF_T=N / K

[0070] wherein, N is the number of operating pulses of the incremental step pulse operation.

[0071] It should be noted that in the equivalent calculation step S1024 described above, the preset number of pulses T can be calculated according to the following formula:

[0072] T = N / (AF_V*AF_T)

[0073] It is easy to understand that the number of preset pulses required when selecting a higher-level operating voltage in incremental step pulse operation as the preset operating voltage is less than the number of preset pulses required when selecting a lower-level operating voltage in incremental step pulse operation as the preset operating voltage. Therefore, in order to shorten the testing time of semiconductor devices, in this embodiment, the preset operating voltage is the maximum operating voltage in incremental step pulse operation, i.e., V0+(N-1)*h.

[0074] Further, in the setting step S102, the first preset number of pulses required when using one of the programming voltages in incremental step pulse programming as the preset programming voltage, and the second preset number of pulses required when using one of the erase voltages in incremental step pulse erasure as the preset erase voltage, are calculated respectively. Then, in the operation step S103, the semiconductor device is programmed and erased for a preset number of times using the preset programming voltage of the first preset number of pulses and the preset erase voltage of the second preset number of pulses.

[0075] It is easy to understand that since the test method provided in this embodiment is for testing the peripheral high-voltage circuit of the semiconductor device, the memory cell of the semiconductor device does not need to undergo programming verification (PGM Verify) and erase verification (ERS Verify) during the preset number of programming and erasing cycles. Furthermore, it is also necessary to avoid prolonged testing time due to data input and output in the memory cell of the semiconductor device. For example, all latches in the page buffer of the semiconductor device can be written to a high-level voltage to prevent data input, and subsequent read operations should be avoided to prevent data output. Specifically, the above-mentioned setting steps can be between the enable step S101 and the operation step S103 described above.

[0076] Furthermore, to avoid performance degradation of the semiconductor device's memory cells due to the aforementioned high preset operating voltage, an erase state can be written to the semiconductor device's memory cell array during programming with a preset programming voltage of a first preset number of pulses. This allows the semiconductor device's memory cells to reduce the voltage difference between their gate and channel through a self-boosting program inhibit (SBPI) mechanism. Simultaneously, during erasing of the semiconductor device with a preset erase voltage of a second preset number of pulses, word lines of the semiconductor device are not selected. This allows the semiconductor device's memory cells to reduce the voltage difference between their gate and channel through a self-boosting erase inhibit (SBEI) mechanism. Specifically, the above-mentioned setting steps can be positioned between the enable step S101 and the operation step S103 described above.

[0077] It is easy to understand that, before and after the above-mentioned operation step S103, the following steps may also be included:

[0078] Record the initial characterization data and post-stress characterization data of the semiconductor device respectively;

[0079] The initial characterization data includes the initial static current, initial dynamic current, and initial timing of the semiconductor device, while the post-stress characterization data includes the post-stress static current, post-stress dynamic current, and post-stress timing of the semiconductor device.

[0080] It should be noted that when a semiconductor device is tested using a preset operating voltage, the various data characteristics of the semiconductor device will change. Therefore, it is necessary to record the corresponding data of each characteristic before and after testing the semiconductor device, such as static current, dynamic current, and timing. Furthermore, the characteristics of each function of the semiconductor device before and after testing can also be recorded. After the test is completed, the lifespan of the semiconductor device can be evaluated by judging whether the data corresponding to each characteristic of the semiconductor device is qualified.

[0081] According to the foregoing embodiments, the present invention provides a method for testing semiconductor devices, comprising: connecting the semiconductor device to a testing device; then, using one of the operating voltages in incremental step pulse operation as a preset operating voltage; calculating a preset number of pulses based on the number of operating pulses in the incremental step pulse operation, an operating voltage multiplier factor, and an operating temperature multiplier factor; and finally, programming and erasing the semiconductor device a preset number of times using the preset operating voltage with the preset number of pulses. The semiconductor device testing method provided by the present invention, by programming and erasing the semiconductor device with a preset operating voltage, allows the peripheral high-voltage circuit of the semiconductor device to receive sufficient voltage stress, thereby making the stress characterization exhibited by the semiconductor device after testing more accurate and improving the accuracy of the test results.

[0082] Please see Figure 4 , Figure 4 A schematic diagram of the structure of a test apparatus 100 for a semiconductor device 200 provided according to an embodiment of the present invention is shown. The components of the embodiment of the present invention and their relative positions can be seen intuitively from the figure.

[0083] like Figure 4 As shown, the testing device 100 may specifically include the following modules:

[0084] Enable module 110 is used to connect semiconductor device 200 to test device 100;

[0085] The setting module 120 is used to take one of the first-level operating voltages in the incremental step pulse operation as the preset operating voltage, and calculate the preset number of pulses based on the number of operating pulses, the operating voltage multiplier factor, and the operating temperature multiplier factor of the incremental step pulse operation.

[0086] The operation module 130 is used to program and erase the semiconductor device 200 a preset number of times with a preset operating voltage and a preset number of pulses.

[0087] It should be noted that in one embodiment of the testing device, the semiconductor device 200 is tested using a read voltage. This may result in insufficient electrical stress received by the high-voltage circuit surrounding the semiconductor device 200, ultimately leading to inaccurate test results. The testing device 100 provided in this embodiment has an operation module 130 that can program and erase the semiconductor device 200 using a preset operation voltage higher than the read voltage. This allows the high-voltage circuit surrounding the semiconductor device to receive sufficient voltage stress, thereby making the stress characterization of the semiconductor device 200 after testing more accurate, and thus improving the accuracy of the test results.

[0088] Further, please refer to Figure 5 , Figure 5 A schematic diagram of the structure of a semiconductor device 200 provided according to an embodiment of the present invention is shown.

[0089] like Figure 5 As shown, the semiconductor device 200 includes a memory cell array 210 and peripheral circuitry 220 coupled to the memory cell array 210.

[0090] Specifically, the enable module 110 of the test device 100 is electrically connected to the peripheral circuit 220 of the semiconductor device 200, and the memory cell array 210 of the semiconductor device 200 is a 3D NAND memory cell array.

[0091] According to the foregoing embodiments, the present invention provides a testing apparatus 100 for a semiconductor device 200, comprising: an enabling module 110 for connecting the semiconductor device 200 to the testing apparatus 100; a setting module 120 for using one of the first-level operating voltages in incremental step pulse operation as a preset operating voltage and calculating the preset number of pulses based on the number of operating pulses, the operating voltage multiplier factor, and the operating temperature multiplier factor of the incremental step pulse operation; and an operation module 130 for programming and erasing the semiconductor device 200 a preset number of times with the preset operating voltage and the preset number of pulses. The testing apparatus 100 for a semiconductor device 200 provided by the present invention, wherein the operation module 130 programs and erases the semiconductor device 200 with the preset operating voltage, allows the peripheral high-voltage circuit of the semiconductor device 200 to receive sufficient voltage stress, thereby making the stress characterization exhibited by the semiconductor device 200 after testing more accurate and improving the accuracy of the test results.

[0092] In addition to the embodiments described above, the present invention may have other implementations. All technical solutions formed by equivalent substitutions or equivalent replacements fall within the protection scope claimed by the present invention.

[0093] In summary, although the preferred embodiments of the present invention have been disclosed above, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A method for testing semiconductor devices, characterized in that, The testing method includes: Connect the semiconductor device to the testing apparatus; One of the operating voltages in the incremental step pulse operation is used as the preset operating voltage, and the preset number of pulses is calculated based on the number of operating pulses, the operating voltage multiplier factor, and the operating temperature multiplier factor of the incremental step pulse operation. The semiconductor device is programmed and erased a predetermined number of times using the predetermined number of predetermined operating voltage pulses; wherein each programming operation includes the predetermined number of predetermined operating voltage pulses, and each programming operation does not include a programming verification pulse; each erasing operation includes the predetermined number of predetermined operating voltage pulses, and each erasing operation does not include an erasure verification pulse. The incremental step pulse operation includes incremental step pulse programming and incremental step pulse erasing; the semiconductor device is programmed using the incremental step pulse programming method, and the semiconductor device is erased using the incremental step pulse erasing method. Before the step of calculating the preset number of pulses based on the number of pulses in the incremental step pulse operation, the operating voltage multiplier factor, and the operating temperature multiplier factor, the method further includes: The voltage acceleration factor was calculated based on the Allen model, and the temperature acceleration factor was calculated based on the Arrhenius model. Based on the voltage acceleration factor and the temperature acceleration factor, the number of voltage equivalent pulses and the number of temperature equivalent pulses required to convert all the operating voltages of the incremental step pulse operation to the preset operating voltage under the influence of voltage or temperature are calculated respectively. The number of voltage equivalent pulses, the number of temperature equivalent pulses, and the number of operating pulses of the incremental step pulse operation are calculated according to a preset formula to obtain the operating voltage multiplier factor and the operating temperature multiplier factor.

2. The test method according to claim 1, characterized in that, The preset operating voltage is the maximum operating voltage in the incremental step pulse operation.

3. The test method according to claim 1, characterized in that, During the process of programming and erasing the semiconductor device a preset number of times, no programming verification or erasure verification is performed.

4. The test method according to claim 1, characterized in that, During the programming process of the semiconductor device a preset number of times, the memory cell array of the semiconductor device is written to an erase state.

5. The test method according to claim 1, characterized in that, During the erase process of the semiconductor device a preset number of times, the word lines of the semiconductor device are not selected.

6. The test method according to claim 1, characterized in that, During the programming process of the semiconductor device a preset number of times, a high-level voltage is written to the latch in the page buffer of the semiconductor device.

7. The test method according to claim 1, characterized in that, Before and after the step of programming and erasing the semiconductor device a preset number of times with the preset operating voltage and the preset number of preset pulses, the method further includes: Record the initial characterization data and post-stress characterization data of the semiconductor device respectively; The initial characterization data includes the initial static current, initial dynamic current, and initial timing of the semiconductor device, and the post-stress characterization data includes the post-stress static current, post-stress dynamic current, and post-stress timing of the semiconductor device.

8. The test method according to claim 1, characterized in that, The semiconductor device is a 3D NAND flash memory.

9. The test method according to claim 8, wherein the test method covers the high-temperature life test of the peripheral high-voltage circuit of the 3D NAND flash memory.

10. A testing apparatus for a semiconductor device, characterized in that, The testing apparatus includes: An enable module for connecting the semiconductor device to the test apparatus; The setting module is used to take one of the first-level operating voltages in the incremental step pulse operation as the preset operating voltage, and calculate the preset number of pulses based on the number of operating pulses, the operating voltage multiplier factor, and the operating temperature multiplier factor of the incremental step pulse operation. An operation module is configured to program and erase the semiconductor device a preset number of times using the preset operating voltage with the preset number of preset pulses; wherein each programming operation includes the preset number of preset operating voltage pulses, and each programming operation does not include a programming verification pulse; each erasing operation includes the preset number of preset operating voltage pulses, and each erasing operation does not include an erasure verification pulse. The incremental step pulse operation includes incremental step pulse programming and incremental step pulse erasing; the semiconductor device is programmed using the incremental step pulse programming method, and the semiconductor device is erased using the incremental step pulse erasing method. Before the step of calculating the preset number of pulses based on the number of pulses in the incremental step pulse operation, the operating voltage multiplier factor, and the operating temperature multiplier factor, the method further includes: The voltage acceleration factor was calculated based on the Allen model, and the temperature acceleration factor was calculated based on the Arrhenius model. Based on the voltage acceleration factor and the temperature acceleration factor, the number of voltage equivalent pulses and the number of temperature equivalent pulses required to convert all the operating voltages of the incremental step pulse operation to the preset operating voltage under the influence of voltage or temperature are calculated respectively. The number of voltage equivalent pulses, the number of temperature equivalent pulses, and the number of operating pulses of the incremental step pulse operation are calculated according to a preset formula to obtain the operating voltage multiplier factor and the operating temperature multiplier factor.

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