Semiconductor device and method of manufacturing the same
By etching and oxidation processes during the fabrication of LDMOS devices, the sharp corners at the junction of the field oxide layer and the shallow trench isolation region are reduced, solving the problems of reduced breakdown voltage and charge accumulation in the prior art and improving device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SILERGY SEMICON TECH (HANGZHOU) CO LTD
- Filing Date
- 2021-12-28
- Publication Date
- 2026-06-16
AI Technical Summary
In the prior art, the sharp corners at the junction of the field oxide layer and the shallow trench isolation region of LDMOS devices lead to a decrease in breakdown voltage and a risk of charge accumulation, affecting device performance.
A vertical oxide layer structure is formed by etching grooves and depositing oxides on a semiconductor substrate. The vertical oxide layer structure is etched below the surface of the semiconductor substrate to expose the sharp corner structure at the junction. In the subsequent oxidation process, the upper surface and side surface at the junction are oxidized to reduce the sharp corner and form a smooth junction structure.
It improves the uniformity of field oxide thickness, reduces the risk of breakdown, and enhances the performance of semiconductor devices.
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Figure CN114496794B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more specifically, to semiconductor devices and methods for manufacturing the same. Background Technology
[0002] Power switches can be semiconductor devices, including metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated-gate bipolar transistors (IGBTs). Laterally diffused metal-oxide-semiconductor (LDMOS) is widely used in switching regulators.
[0003] Figure 1 A schematic diagram of the structure of an LDMOS device according to the prior art is shown, such as... Figure 1 As shown, the LDMOS device 100 has a body region 120 and a drift region 130 in a semiconductor substrate 110. The body region 120 has a first doped region 121 and a second doped region 122. The drift region 130 has a drain region 131. A shallow trench isolation (STI) region 140 is also provided in the drift region 130 between the drain region 131 and the body region 120. A field oxide layer 150 is also provided on the upper surface of the shallow trench isolation region 140. A gate structure 160 is provided from the second doped region 122 to the drift region 130. A gate oxide layer 162 is provided at the bottom of the gate structure 160, and a polysilicon layer 161 is provided on the top layer. The polysilicon layer 161 also covers the junction of the field oxide layer 150 and the shallow trench isolation region 140.
[0004] In the existing LDMOS device 100, a sharp corner 10 is formed at the junction of the field oxide layer 150 and the shallow trench isolation region 140. The sharp corner 10 reduces the thickness of the field oxide layer 150 in that part, reduces its breakdown voltage, and the sharp corner 10 is prone to charge accumulation, increasing the risk of breakdown of the field oxide layer 150 and reducing the performance of the LDMOS device 100. Summary of the Invention
[0005] In view of the above problems, the purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, thereby reducing the sharp corners at the junction of the horizontal oxide layer structure and the vertical oxide layer structure and ensuring device performance.
[0006] According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided, for manufacturing a combined structure of a horizontal oxide layer structure and a vertical oxide layer structure of the semiconductor device, comprising:
[0007] Grooves are etched into a semiconductor substrate;
[0008] An oxide is deposited in the groove to obtain the vertical oxide layer structure;
[0009] The vertical oxide layer structure is etched to lower the upper surface of the vertical oxide layer structure below the upper surface of the semiconductor substrate, and a sharp corner structure exposing the upper surface and sidewalls is formed at the top edge of the groove;
[0010] The horizontal oxide layer structure is fabricated on the upper surface of the semiconductor substrate and on the upper surface of the vertical oxide layer structure, wherein,
[0011] The sharp corner structure corresponds to the junction of the horizontal oxide layer structure and the vertical oxide layer structure. During the manufacturing step of the horizontal oxide layer structure, the upper surface and sidewall of the sharp corner structure are oxidized simultaneously to reduce the sharp corner structure.
[0012] Optionally, the sidewalls of the groove are inclined outwards at an angle of less than or equal to 90 degrees.
[0013] Optionally, the vertical cross-section of the groove is inverted trapezoidal in shape, and the inclination angle of its sidewalls is 65 to 70 degrees.
[0014] Optionally, in the step of etching the vertical oxide layer structure, the vertical oxide layer structure is etched according to a wet etching process.
[0015] Optionally, in the step of etching the vertical oxide layer structure, the upper surface of the etched vertical oxide layer structure is 100 to 400 angstroms lower than the upper surface of the semiconductor substrate.
[0016] Optionally, in the step of manufacturing the horizontal oxide layer structure, the horizontal oxide layer structure is manufactured according to a local silicon oxide isolation process.
[0017] According to another aspect of the present invention, a semiconductor device is provided, comprising:
[0018] The semiconductor device manufacturing method provided by the present invention produces a combined structure of horizontal oxide layer structure and vertical oxide layer structure.
[0019] Optionally, the semiconductor device includes an LDMOS device;
[0020] The vertical oxide layer structure includes a shallow trench isolation structure;
[0021] The horizontal oxide layer structure includes a field oxide layer structure.
[0022] Optionally, a gate structure may be further covered over the boundary region between the field oxide layer structure and the shallow trench isolation structure.
[0023] The semiconductor device manufacturing method provided by this invention further etches the vertical oxide layer structure to lower its upper surface below the upper surface of the semiconductor substrate after deposition, thereby simultaneously exposing the upper surface and side surface of the sharp corner structure at the junction of the horizontal and vertical oxide layer structures. In subsequent oxidation, the upper surface and side surface at the junction of the horizontal and vertical oxide layer structures can be oxidized simultaneously, reducing the sharp corners at the junction and minimizing the impact of incomplete oxidation of the boundary structure on the thickness of the horizontal oxide layer structure. This ensures the uniformity of the horizontal oxide layer structure's thickness, guarantees the breakdown protection effect of the horizontal oxide layer structure, and improves the performance of the semiconductor device.
[0024] The semiconductor device provided by this invention is manufactured according to the semiconductor device manufacturing method provided by this invention, which reduces the sharp corners at the junction of the horizontal oxide layer structure and the vertical oxide layer structure, reduces the influence of the sharp corners caused by the incomplete oxidation of the boundary structure on the thickness of the horizontal oxide layer structure, thereby ensuring the thickness uniformity of the horizontal oxide layer structure, ensuring the breakdown protection effect of the horizontal oxide layer structure, and improving the performance of the semiconductor device. Attached Figure Description
[0025] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:
[0026] Figure 1 A schematic diagram of the structure of an LDMOS device according to the prior art is shown;
[0027] Figures 2A to 2C A partial process diagram of a manufacturing method for an LDMOS device according to the prior art is shown;
[0028] Figure 3 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown;
[0029] Figures 4A to 4D A partial process diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown;
[0030] Figure 5 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention is shown. Detailed Implementation
[0031] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.
[0032] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.
[0033] Figures 2A to 2C A partial process diagram of a manufacturing method for an LDMOS device according to the prior art is shown.
[0034] Reference Figure 2A In the prior art, a groove is etched in the shallow trench isolation area, and oxide is deposited in the groove to obtain a vertical oxide layer structure 141. To ensure the isolation effect, the height of the vertical oxide layer structure 141 exceeds the upper surface of the semiconductor substrate 110.
[0035] Reference Figure 2B A horizontal oxide layer structure is fabricated on a semiconductor having a vertical oxide layer structure 141 using a LOCOS (Local Oxidation of Silicon) oxidation process to obtain a field oxide layer 150. The horizontal oxide layer obtained by this oxidation process is oxidized from the upper surface of the semiconductor substrate 110 inward. The oxidation process has insufficient oxidation degree at the edge portion, which easily forms sharp corners 10 at the boundary between the field oxide layer 150 and the shallow trench isolation region 140.
[0036] Reference Figure 2C After the field oxide layer 150 and the shallow trench isolation region 140 are formed, source and drain regions are doped and implanted, and then the gate structure 160 is fabricated to complete the fabrication of the main structure of the LDMOS device 100. Subsequent processes include electrode fabrication and packaging. The sharp corner 10 at the boundary between the field oxide layer 150 and the shallow trench isolation region 140 is difficult to reduce, affecting the breakdown voltage of the LDMOS device.
[0037] Figure 3 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown. Figures 4A to 4D A partial process diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.
[0038] Reference Figure 3 ,as well as Figures 4A to 4D The method for manufacturing a semiconductor device according to embodiments of the present invention mainly includes:
[0039] Step S10: Form a bulk region and a drift region on a semiconductor substrate.
[0040] Taking N-type LDMOS as an example, the semiconductor substrate is, for example, a silicon substrate or a gallium substrate. The substrate is a P-type substrate, the body region is a P-type doped well region, and the drift region is an N-type deep well.
[0041] Step S11: Etching to form STI grooves. That is, etching STI grooves at the shallow trench isolation area.
[0042] In step S11, the sidewall of the STI groove is inclined outward, and the inclination angle is less than or equal to 90 degrees. In this embodiment, the STI groove is an inverted trapezoid, and the inclination angle of its sidewall is 65 to 70 degrees.
[0043] Step S12: Deposit oxide in the STI groove.
[0044] In step S12, refer to Figure 4A The height of the vertical oxide layer structure 241 obtained by deposition exceeds the upper surface of the semiconductor substrate 110, and its outward tilt angle A is 65 degrees to 70 degrees.
[0045] Step S13: Etch to reduce the height of the deposited oxide below the surface of the semiconductor substrate.
[0046] In step S13, as Figure 4B As shown, the etching process is a wet etching process, which reduces the height of the vertical oxide layer structure 241 to below the height of the upper surface of the semiconductor substrate 110. Wet etching helps to maintain the tilt angle of its sidewalls.
[0047] In this embodiment, the height of the upper surface of the vertical oxide layer structure 241 is reduced to a distance of 100 to 400 angstroms below the height of the upper surface of the semiconductor substrate 110, in order to ensure the reduction effect of the sharp corner structure at the boundary position in subsequent oxidation, ensure the smoothness of the smooth boundary structure 20, increase the minimum thickness of the field oxide layer 250 (the thickness at the location of the boundary structure 20, without considering the thickness influence of its edge beak structure), and improve the reliability of breakdown protection.
[0048] In ideal circumstances, such as Figure 4C As shown, the sharp corner 10 can be completely eliminated, and the highest point of the obtained boundary structure 20 is horizontally aligned with the lower surface of the field oxide layer 250. The boundary structure 20 extends smoothly downward from the highest point, and the thickness of the field oxide layer 250 corresponding to the position of the boundary structure 20 gradually increases without rebound, ensuring the thickness.
[0049] When the distance between the upper surface of the vertical oxide layer structure 241 and the upper surface of the semiconductor substrate 110 is small, it is not easy to completely eliminate the sharp corner 10 at the junction of the horizontal oxide layer structure and the vertical oxide layer structure. However, it can still reduce the prominence of the sharp corner 10 to a certain extent, reduce the risk of field oxide breakdown caused by the sharp corner 10, and improve the breakdown voltage of the semiconductor device and improve performance to a certain extent compared with the existing technology.
[0050] Step S14: Mid-section process.
[0051] In step S14, the intermediate process includes, for example, source / drain region doping implantation to form a source region in the bulk region and a drain region in the drift region.
[0052] Step S15: Fabricate a field oxide layer according to the local silicon oxide isolation process.
[0053] In step S15, a silicon nitride layer is deposited on the semiconductor substrate 110 (including structures such as source region, drain region, drift region and body region formed on the semiconductor substrate 110) and the upper surface of the vertical oxide layer 241. The silicon nitride layer is etched, and the window area of the etched silicon nitride layer corresponds to the field oxide layer area. The window area covers the area of the vertical oxide layer structure 241. Then, according to the LOCOS process, using the silicon nitride layer as a mask, a horizontal oxide layer structure is obtained by oxidation, and a field oxide layer structure 250 is obtained at the position of the vertical oxide layer structure 241.
[0054] In step S15, because the preceding process reduces the height of the vertical oxide layer structure 241, both the upper surface and the side surface (sharp corner structure at the junction) of the silicon material at its boundary are exposed. During the high-pressure gate oxide furnace oxidation, oxidation can be performed simultaneously on both the upper surface and the side surface. This reduces the sharp corner at the junction of the field oxide layer 250 and the shallow trench isolation region 240, resulting in a... Figure 4C The smooth junction structure 20 shown effectively increases the thickness of the field oxide layer 250 and reduces the risk of breakdown caused by charge accumulation.
[0055] Step S16: Fabricate the gate structure.
[0056] like Figure 4D As shown, a gate structure 160 is fabricated on a semiconductor substrate on which a field oxide layer 250 and a shallow trench isolation region 240 are formed. In this embodiment, the thickness of the gate oxide layer 162 of the gate structure 160 is less than the thickness of the field oxide layer 250, and the polysilicon layer 161 also covers the area above the junction of the field oxide layer 250 and the shallow trench isolation region 240.
[0057] In step S15, before depositing the silicon nitride layer, a thin oxide layer with the same thickness as the gate oxide layer 162 can be deposited on the semiconductor substrate 110. The etched silicon nitride layer also covers the gate oxide layer 162. Subsequently, using the silicon nitride layer as a mask, the thickness of a portion of the thin oxide layer is increased by oxidation to obtain a field oxide layer 250 of the target thickness. Then, the silicon nitride layer is removed, and the thin oxide layer is etched to expose other areas on the upper surface of the semiconductor substrate 110, such as the source and drain doped regions, so as to subsequently manufacture source and drain electrodes that connect the source and drain doped regions.
[0058] It should be noted that the main inventive point of this invention lies in the fabrication of the connection structure between the horizontal oxide layer structure and the vertical oxide layer structure. The fabrication process of other layer structures in LDMOS devices or other semiconductor devices is not particularly limited, and it is not limited to high-voltage LDMOS devices, but can also be used in other low-voltage MOS devices. Correspondingly, it can ensure the thickness reliability of field oxide layers of various thicknesses and ensure the design reliability of breakdown voltage. The horizontal oxide layer structure is not limited to high-thickness high-voltage field oxide layers, and can be applied to horizontal oxide layers such as field oxide layers or gate oxide layers of any thickness.
[0059] Figure 5 A schematic diagram of a semiconductor device according to an embodiment of the present invention is shown. The semiconductor device 200 of this embodiment has the same main structure as the prior art semiconductor device 100, and the identical parts will not be described again here.
[0060] Reference Figure 5 The semiconductor device 200 obtained by the manufacturing method of the semiconductor device of the present invention has a smooth interface structure 20 between the field oxide layer 250 and the shallow trench isolation region 240. The thickness of the field oxide layer 250 is guaranteed, and the smooth structure is not easy to accumulate charge, which can further reduce the breakdown risk of the field oxide layer 250 and improve the breakdown voltage of the semiconductor device 200.
[0061] Taking an N-type LDMOS device as an example, the semiconductor substrate 110 of the semiconductor device 200 is a P-type substrate, the body region 120 is a P-type well region, the drift region 130 is an N-type doped well region, the base region 121 is P-type doped, the source region 122 is N-type doped, and the drain region 131 is N-type doped.
[0062] The semiconductor device manufacturing method provided by this invention, after depositing a vertical oxide layer structure, further etches to lower the upper surface of the vertical oxide layer structure below the upper surface of the semiconductor substrate. In subsequent oxidation, the upper surface and side surface at the junction of the horizontal oxide layer structure and the vertical oxide layer structure can be oxidized simultaneously, smoothing the sharp corners at the junction, reducing the impact of sharp corners caused by incomplete oxidation of the boundary structure on the thickness of the horizontal oxide layer structure, thereby improving the thickness uniformity of the horizontal oxide layer structure, improving the breakdown protection effect of the horizontal oxide layer structure, and improving the performance of the semiconductor device.
[0063] The semiconductor device provided by this invention is manufactured according to the semiconductor device manufacturing method provided by this invention, which reduces the sharp corners at the junction of the horizontal oxide layer structure and the vertical oxide layer structure, reduces the influence of the sharp corners caused by the incomplete oxidation of the boundary structure on the thickness of the horizontal oxide layer structure, thereby ensuring the thickness uniformity of the horizontal oxide layer structure, ensuring the breakdown protection effect of the horizontal oxide layer structure, and improving the performance of the semiconductor device.
[0064] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.
Claims
1. A method for manufacturing a semiconductor device, comprising manufacturing a combined structure of a horizontal oxide layer structure and a vertical oxide layer structure of the semiconductor device, comprising: Grooves are etched into a semiconductor substrate; An oxide is deposited in the groove to obtain the vertical oxide layer structure; The vertical oxide layer structure is etched to lower the upper surface of the vertical oxide layer structure below the upper surface of the semiconductor substrate, and a sharp corner structure exposing the upper surface and sidewalls is formed at the top edge of the groove; The horizontal oxide layer structure is fabricated on the upper surface of the semiconductor substrate and on the upper surface of the vertical oxide layer structure, wherein, The sharp corner structure corresponds to the boundary between the horizontal oxide layer structure and the vertical oxide layer structure. During the manufacturing step of the horizontal oxide layer structure, the upper surface and sidewalls of the sharp corner structure are simultaneously oxidized to reduce the sharp corner structure. In the step of etching the vertical oxide layer structure, the upper surface of the etched vertical oxide layer structure is 100 to 400 angstroms lower than the upper surface of the semiconductor substrate.
2. The method for manufacturing a semiconductor device according to claim 1, wherein, The sidewalls of the groove are inclined outwards at an angle of less than or equal to 90 degrees.
3. The method for manufacturing a semiconductor device according to claim 2, wherein, The groove has an inverted trapezoidal vertical cross-section and its sidewalls have an inclination angle of 65 to 70 degrees.
4. The method for manufacturing a semiconductor device according to claim 1, wherein, In the step of etching the vertical oxide layer structure, the vertical oxide layer structure is etched according to a wet etching process.
5. The method for manufacturing a semiconductor device according to claim 1, wherein, In the step of manufacturing the horizontal oxide layer structure, the horizontal oxide layer structure is manufactured according to a local silicon oxide isolation process.
6. A semiconductor device, comprising: The combined structure of horizontal oxide layer structure and vertical oxide layer structure manufactured by the semiconductor device manufacturing method according to any one of claims 1 to 5.
7. The semiconductor device according to claim 6, wherein, The semiconductor device includes an LDMOS device; The vertical oxide layer structure includes a shallow trench isolation structure; The horizontal oxide layer structure includes a field oxide layer structure.
8. The semiconductor device according to claim 7, wherein, A gate structure is also covered above the boundary region between the field oxide layer structure and the shallow trench isolation structure.