Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a substrate, the substrate including a first region and a second region spaced apart from each other, a stacked structure located in the first region as a first stacked structure, and a stacked structure located in the second region as a second stacked structure; forming a first dielectric layer conformally covering the first stacked structure and the second stacked structure, and surrounding the spaced region between the first stacked structure and the second stacked structure; forming an air wall between the first stacked structure and the second stacked structure; and forming a second dielectric layer on the side of the first stacked structure and the second stacked structure away from the air wall. In this embodiment, during the formation of the dielectric wall, the first dielectric layer and the second dielectric layer on the side of the first stacked structure and the second stacked structure away from the dielectric wall provide support for the first stacked structure and the second stacked structure, resulting in good morphological quality of the first stacked structure and the second stacked structure, which is beneficial to improving the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits, the feature size of integrated circuits continues to shrink. In order to adapt to the smaller feature size, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also continuously shortened.

[0003] Therefore, to better adapt to the requirements of proportionally shrinking device dimensions, semiconductor technology has gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as nanowire transistors. In nanowire transistors, the gate surrounds the area where the channel is located. Compared with planar transistors, nanowire transistors have stronger control over the channel by the gate and can better suppress short-channel effects.

[0004] To further improve the integration of semiconductor structures, the forksheet transistor was proposed as an alternative to FinFET and nanowire transistors. It is characterized by a complex double-sided fin structure separated by dielectric walls. Summary of the Invention

[0005] The problem addressed by the embodiments of this application is to provide a semiconductor structure and a method for forming the same, thereby optimizing the electrical performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of this application provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and a second region spaced apart, the substrate including a substrate and a plurality of stacked structures discretely disposed on the substrate, the stacked structure located in the first region serving as a first stacked structure, and the stacked structure located in the second region serving as a second stacked structure; forming a first dielectric layer conformally covering the first stacked structure and the second stacked structure, and surrounding the spacer region between the first stacked structure and the second stacked structure, forming an air wall between the first stacked structure and the second stacked structure; after forming the air wall, forming a second dielectric layer on the side of the first stacked structure and the second stacked structure facing away from the air wall; removing the first dielectric layer at the top of the air wall; and after removing the first dielectric layer at the top of the air wall, forming a dielectric wall in the spacer region between the first stacked structure and the second stacked structure.

[0007] Optionally, the first dielectric layer is formed using a plasma chemical vapor deposition process.

[0008] Optionally, in the step of forming the first dielectric layer, the thickness of the first dielectric layer is 2 nanometers to 100 nanometers.

[0009] Optionally, the material of the first dielectric layer includes silicon oxide.

[0010] Optionally, in the step of providing a substrate with the lateral dimension of the spacer region between the first stacked structure and the second stacked structure being parallel to the substrate surface and perpendicular to the extension direction of the stacked structure, the lateral dimension is 3 nanometers to 30 nanometers.

[0011] Optionally, the second dielectric layer is formed using a flowable chemical vapor deposition process.

[0012] Optionally, the material of the second dielectric layer includes silicon oxide.

[0013] Optionally, the step of removing the first dielectric layer at the top of the air wall includes: planarizing the first dielectric layer at the top of the air wall.

[0014] Optionally, the planarization process includes a chemical mechanical polishing process.

[0015] Optionally, the step of removing the first dielectric layer at the top of the air wall includes: etching the first dielectric layer at the top of the air wall using a dry etching process.

[0016] Optionally, the dielectric wall material includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron carbide.

[0017] Optionally, the step of forming a dielectric wall in the gap region between the first stacked structure and the second stacked structure includes: forming a dielectric material film in the gap region between the first stacked structure and the second stacked structure, as well as on the first stacked structure and the second stacked structure; removing the dielectric material film above the first stacked structure and the second stacked structure, with the remaining dielectric material film in the gap region between the first stacked structure and the second stacked structure serving as the dielectric wall.

[0018] Optionally, in the step of providing the substrate, the stacked structure includes: a fin, a plurality of channel stacks located on the fin, the channel stacks including a first sacrificial layer and a channel layer located on the first sacrificial layer; the stacked structure further includes: a second sacrificial layer located between the fin and the channel stacks.

[0019] Optionally, in the step of forming the first dielectric layer, the first stacked structure, the second stacked structure, the first dielectric layer, and the substrate form an air wall; the method for forming the semiconductor structure further includes: etching the first dielectric layer and the second dielectric layer to form an isolation layer, wherein the top surface of the isolation layer is lower than the bottom surface of the second sacrificial layer.

[0020] Optionally, in the step of providing the substrate, an isolation structure is formed on the substrate between the stacked structures, the top surface of the isolation structure being lower than the bottom surface of the second sacrificial layer; in the step of forming the first dielectric layer, the first dielectric layer is formed on the isolation structure, and the air wall is surrounded by the isolation structure, the first stacked structure, the second stacked structure, and the first dielectric layer.

[0021] Accordingly, this application also provides a semiconductor structure, including: a substrate, the substrate including a first region and a second region; a stacked structure, disposed on the substrate, the stacked structure located in the first region being a first stacked structure, the stacked structure located in the second region being a second stacked structure, and a gap region being formed between the first stacked structure and the second stacked structure; a first dielectric structure located on a sidewall of the first stacked structure and the second stacked structure away from the gap region; and a second dielectric structure located on the sidewall of the first dielectric structure.

[0022] Optionally, the lateral dimension of the gap region between the first stacked structure and the second stacked structure is 3 nanometers to 30 nanometers, with the lateral direction being parallel to the substrate surface and perpendicular to the extension direction of the stacked structure.

[0023] Optionally, the thickness of the first dielectric structure is 2 nanometers to 100 nanometers.

[0024] Optionally, the material of the first dielectric structure includes silicon oxide.

[0025] Optionally, the material of the second dielectric structure includes silicon oxide.

[0026] Compared with the prior art, the technical solution of this application has the following advantages:

[0027] In the semiconductor structure formation method provided in this application embodiment, a first dielectric layer is formed that conformally covers the first stacked structure and the second stacked structure, and surrounds the gap region between the first stacked structure and the second stacked structure. An air wall is formed between the first stacked structure and the second stacked structure. After forming the air wall, a second dielectric layer is formed on the side of the first stacked structure and the second stacked structure. The first dielectric layer and the second dielectric layer exert relatively low stress on the first stacked structure and the second stacked structure, making the first stacked structure and the second stacked structure less prone to bending or misalignment. In this application embodiment, even if the dielectric wall exerts significant stress on the first stacked structure and the second stacked structure during the formation of the dielectric wall, the first dielectric layer and the second dielectric layer on the side of the first stacked structure and the second stacked structure away from the dielectric wall can provide support for the first stacked structure and the second stacked structure, making the first stacked structure and the second stacked structure less prone to bending or misalignment under the stress of the dielectric wall. The morphological quality of the first stacked structure and the second stacked structure is better, which is beneficial to improving the electrical performance of the semiconductor structure. Attached Figure Description

[0028] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0029] Figures 5 to 11 This is a schematic diagram of the structure corresponding to each step in the first embodiment of the method for forming a semiconductor structure according to the present application;

[0030] Figure 12 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0031] As the background technology shows, the devices currently being fabricated still suffer from poor performance. This paper analyzes the reasons for this poor performance by examining a semiconductor structure fabrication method.

[0032] refer to Figures 1 to 4 The diagram shows a schematic representation of each step in a method for forming a semiconductor structure.

[0033] like Figure 1 As shown, a substrate is provided, the substrate including a plurality of discrete stacked structures 1 and an isolation layer 4 located between the stacked structures 1. The stacked structures 1 include fins 2 and channel stacks 3 located on the fins 2. The channel stacks 3 include a sacrificial layer 31 and a channel layer 32 located on the sacrificial layer 31. The substrate includes adjacent first regions I and second regions II, the first regions I being used to form first-type transistors and the second regions being used to form second-type transistors.

[0034] like Figure 2 As shown, a dielectric material layer 5 is formed to conformally cover the stacked structure 1 and the isolation layer 4. The thickness of the dielectric material layer 5 is twice greater than the lateral dimension d of the gap between the stacked structure 1 in the first region I and the stacked structure 1 in the second region II. The area between the stacked structures 1 in the first region I and the second region II is filled by the dielectric material layer 5.

[0035] Typically, the dielectric material layer 5 is made of silicon nitride.

[0036] like Figure 3 As shown, the dielectric material layer 5 is etched using an isotropic dry etching process, and the remaining dielectric material layer 5 located between the first region I and the second region II serves as a dielectric wall 6.

[0037] like Figure 4 As shown, an isolation structure 7 is formed on the isolation layer 4 between the stacked structures 1, and the top surface of the isolation structure 7 is lower than or flush with the top surface of the fin 1.

[0038] The dielectric material layer 5 is made of silicon nitride, the channel layer 32 is typically made of silicon, and the sacrificial layer 31 is made of silicon germanide. The dielectric wall 6 is located between the stacked structure 1 in the first region I and the stacked structure 1 in the second region II. That is, the dielectric wall 6 is formed on one sidewall of the stacked structure 1, while the other sidewall does not have a dielectric wall 6. Because silicon nitride is a high-stress material, both the stacked structure 1 in the first region I and the stacked structure 1 in the second region II are subjected to stress provided by the dielectric wall 6 on one side. The stacked structure 1 is prone to bending or misalignment. Subsequent semiconductor processes are based on the stacked structure 1, and the poor morphology of the stacked structure 1 leads to poor performance of the semiconductor structure.

[0039] To address the technical problem, the semiconductor structure formation method provided in this application involves forming a first dielectric layer that conformally covers the first and second stacked structures and surrounds the gap between them, while forming an air wall between them. After forming the air wall, a second dielectric layer is formed on the sides of the first and second stacked structures. The first and second dielectric layers exert relatively low stress on the first and second stacked structures, making them less prone to bending or misalignment. In this application embodiment, even if the dielectric wall exerts significant stress on the first and second stacked structures during the formation of the dielectric wall, the first and second dielectric layers on the sides of the first and second stacked structures facing away from the dielectric wall provide support, making them less prone to bending or misalignment under the stress of the dielectric wall. This results in better morphological quality of the first and second stacked structures, which is beneficial for improving the electrical performance of the semiconductor structure.

[0040] To make the above-mentioned objectives, features and advantages of the embodiments of this application more apparent and understandable, the specific embodiments of the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0041] Figures 5 to 11 This is a schematic diagram of the structure corresponding to each step in the first embodiment of the method for forming a semiconductor structure according to the present application.

[0042] refer to Figure 5 A substrate is provided, the substrate including an adjacent first region I and a second region II, the substrate including a substrate 100 and a plurality of stacked structures discrete on the substrate 100, the stacked structure located in the first region I serving as a first stacked structure 102, and the stacked structure located in the second region II serving as a second stacked structure 103.

[0043] In this embodiment, the first region I is used to form a first-type transistor, and the second region II is used to form a second-type transistor. The first-type transistor and the second-type transistor have different conductivity types. Specifically, the first-type transistor is a PMOS (Positive Channel Metal Oxide Semiconductor), and the second-type transistor is an NMOS (Negative Channel Metal Oxide Semiconductor).

[0044] The substrate 100 is used to provide a process platform for the subsequent formation of the gate structure, preparing for the subsequent formation of the forksheet.

[0045] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0046] It should be noted that the first region I and the second region II are located in the device region, and the substrate 100 includes a plurality of phase-spaced device regions.

[0047] The stacked structure includes: a fin 105, and a plurality of channel stacks 101 located on the fin 105, wherein the channel stacks 101 include a first sacrificial layer 1011 and a channel layer 1012 located on the first sacrificial layer 1011.

[0048] The first sacrificial layer 1011 is then removed to form a gate structure that fully surrounds the channel layer 1012. The fin 105 is used to space the channel stack 101 from the substrate 100, in preparation for the subsequent formation of an isolation layer between the substrate 100 and the gate structure.

[0049] In this embodiment, the material of the fin 105 is the same as the material of the substrate 100. In other embodiments, the material of the fin may be different from the material of the substrate.

[0050] The channel stack 101 provides a process basis for the subsequent channel layer 1012 to be suspended. The first sacrificial layer 1011 supports the channel layer 1012, provides process conditions for the subsequent channel layer 1012 to be suspended, and also occupies space for the gate structure to be formed later.

[0051] When the semiconductor structure is in operation, the channel layer 1012 serves as the channel region.

[0052] In this embodiment, the channel layer 1012 is more difficult to etch than the first sacrificial layer 1011, so the channel layer 1012 is less likely to be damaged when the first sacrificial layer 1011 is removed.

[0053] In this embodiment, the channel layer 1012 is made of silicon; the first sacrificial layer 1011 is made of silicon germanide. In other embodiments, the channel layer can also be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ide, and the first sacrificial layer can also be made of silicon.

[0054] It should be noted that, in the step of providing the substrate with the lateral direction parallel to the surface of the substrate 100 and perpendicular to the extension direction of the stacked structure, the lateral dimension D of the gap region between the first stacked structure 102 and the second stacked structure 103 should not be too large or too small. If the lateral dimension D of the gap region between the first stacked structure 102 and the second stacked structure 103 is too large, during the subsequent formation of the first dielectric layer that conformally covers the first stacked structure 102 and the second stacked structure 103 and surrounds the gap region between the first stacked structure 102 and the second stacked structure 103, it will be difficult for the first dielectric layer to surround the gap region between the first stacked structure 102 and the second stacked structure 103. In other words, it will be difficult to form an air wall between the first stacked structure 102 and the second stacked structure 103, and the first dielectric layer will easily be formed in the gap region between the first stacked structure 102 and the second stacked structure 103. The first dielectric layer formed in the gap region will occupy the space used to form the dielectric wall later. The electrical isolation effect between the channel layer 1012 in the first stacked structure 102 and the channel layer 1012 in the second stacked structure 103 will be poor, resulting in poor electrical performance of the semiconductor structure. If the lateral dimension D of the gap region between the first stacked structure 102 and the second stacked structure 103 is too small, the lateral dimension of the dielectric wall subsequently formed between the first stacked structure 102 and the second stacked structure 103 will be small. This dielectric wall will not effectively electrically isolate the channel layer 1012 in the first stacked structure 102 and the channel layer 1012 in the second stacked structure 103, resulting in poor electrical performance of the semiconductor structure. In this embodiment, during the step of providing the substrate, the lateral dimension D of the gap region between the first stacked structure 102 and the second stacked structure 103 is 3 nanometers to 30 nanometers.

[0055] It should be noted that the stacked structure further includes a second sacrificial layer 104, located between the fin 105 and the channel stack 101.

[0056] The second sacrificial layer 104 has a lower etch resistance than the first sacrificial layer 1011. During the subsequent removal of the first sacrificial layer 1011, the second sacrificial layer 104 is less likely to remain. After removing the first sacrificial layer 1011 and the second sacrificial layer 104, preparation is made for the formation of the gate structure.

[0057] The process space for forming the gate structure between the fin 105 and the bottommost channel layer 1012 is relatively large. Therefore, when the semiconductor structure is working, the gate structure has a strong control over the bottommost channel layer 1012, and at the same time, the gate structure has a strong control over the fin 101, which is beneficial to improving the electrical performance of the semiconductor structure.

[0058] In this embodiment, a mask layer 110 is also formed on the top of the channel stack 101.

[0059] During the formation of the semiconductor structure, the mask layer 110 is used to protect the top of the stacked structure from damage.

[0060] Specifically, the material of the mask layer 110 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, boron silicon nitride, and boron silicon carbide. In this embodiment, the material of the mask layer 110 includes silicon nitride.

[0061] It should be noted that, in other embodiments, during the step of providing the substrate, an isolation structure is formed on the substrate between the stacked structures, and the top surface of the isolation structure is lower than the bottom surface of the second sacrificial layer.

[0062] refer to Figure 6 A first dielectric layer 106 is formed to conformally cover the first stacked structure 102 and the second stacked structure 103 and surround the spaced area between the first stacked structure 102 and the second stacked structure 103, and an air wall 107 is formed between the first stacked structure 102 and the second stacked structure 103.

[0063] The first dielectric layer 106 exerts less stress on the first stacked structure 102 and the second stacked structure 103, making the first stacked structure 102 and the second stacked structure 103 less prone to bending or misalignment. Subsequently, a second dielectric layer is formed on the side of the first stacked structure 102 and the second stacked structure 103 away from the air wall 107. After removing the first dielectric layer 106 from the top of the air wall 107, a dielectric wall is formed in the gap region between the first stacked structure 102 and the second stacked structure 103. The air wall 107 reserves process space for the subsequent formation of the dielectric wall. Furthermore, compared to the case where a dielectric wall is directly formed between the first stacked structure 102 and the second stacked structure 103, the first dielectric layer 106 and the second dielectric layer on the side of the first stacked structure 102 and the second stacked structure 103 away from the dielectric wall can provide support for the first stacked structure 102 and the second stacked structure 103, making the first stacked structure 102 and the second stacked structure 103 less prone to bending or misalignment under the stress of the dielectric wall. The morphological quality of the first stacked structure 102 and the second stacked structure 103 is better, which is beneficial to improving the electrical performance of the semiconductor structure.

[0064] During the subsequent formation of the second dielectric layer on the side of the first stacked structure 102 and the second stacked structure 103 away from the air wall 107, the second dielectric layer is not easily formed in the air wall 107.

[0065] Subsequently, the first sacrificial layer 1011 and the second sacrificial layer 104 are removed, and the channel layer 1012 is used as a channel. The first stacked structure 102 and the second stacked structure 103 are not easily bent or misaligned. Correspondingly, the channel layer 1012 in the first region I and the channel layer 1012 in the second region II have a larger spacing, which reduces the probability of leakage current between the first transistor and the second transistor and is beneficial to improving the electrical performance of the semiconductor structure.

[0066] The first dielectric layer 106 is made of a material with low stress. Even if the first dielectric layer 106 is only formed on one sidewall of the first stacked structure 102 and the second stacked structure 103, the stress exerted by the first dielectric layer 106 on the stacked structure is less than the stress exerted by the subsequently formed dielectric wall on the stacked structure. The first stacked structure 102 and the second stacked structure 103 are subjected to less stress from the first dielectric layer 106, and are not easily bent or misaligned. The morphology of the first stacked structure 102 and the second stacked structure 103 is better, the semiconductor process control is better, and the electrical performance of the final semiconductor structure is better.

[0067] In this embodiment, the material of the first dielectric layer 106 includes silicon oxide. Silicon oxide has low stress, is a commonly used and low-cost dielectric material, and has high process compatibility, which helps to reduce the process difficulty and cost of forming the first dielectric layer 106.

[0068] In this embodiment, during the step of forming the first dielectric layer 106, the first stacked structure 102, the second stacked structure 103, the first dielectric layer 106, and the substrate 100 form an air wall 107.

[0069] In this embodiment, the first dielectric layer 106 is formed using plasma chemical vapor deposition (PCVD). PCVD is a method of generating a thin film by chemically reacting one or more gaseous compounds or elements containing thin film elements. By adjusting parameters such as bias voltage and pressure, the step coverage of the first dielectric layer 106 can be reduced, allowing the thin films at the top of the first stacked structure 102 and the second stacked structure 103 to contact earlier and close. Consequently, the first dielectric layer 106 is less likely to form between the first stacked structure 102 and the second stacked structure 103, resulting in better formation quality of the air wall 107. This provides better process space for the subsequent formation of the dielectric wall between the first stacked structure 102 and the second stacked structure 103.

[0070] It should be noted that during the step of forming the first dielectric layer 106, the first dielectric layer 106 should not be too thick or too thin. If the first dielectric layer 106 is too thick, that is, if an excessively thick first dielectric layer 106 is formed on one sidewall of the first stacked structure 102 and the second stacked structure 103, even if the stress of the material of the first dielectric layer 106 is small, the first stacked structure 102 and the second stacked structure 103 are still prone to bending or tilting under the action of the excessively thick first dielectric layer 106. The morphology of the first stacked structure 102 and the second stacked structure 103 is poor, the semiconductor process control is poor, and the electrical performance of the final semiconductor structure is poor. If the first dielectric layer 106 is too thin, during the formation of the first dielectric layer 106, it will be difficult for the first dielectric layer 106 to surround the gap region between the first stacked structure 102 and the second stacked structure 103. This makes it difficult to form an air wall 107 between the first stacked structure 102 and the second stacked structure 103. In the subsequent step of forming the second dielectric layer, the second dielectric layer is likely to be formed in the gap region, occupying the space for the formation of the dielectric wall. The electrical isolation effect between the channel layer 1012 in the first stacked structure 102 and the channel layer 1012 in the second stacked structure 103 will be poor, resulting in poor electrical performance of the semiconductor structure. In this embodiment, the thickness of the first dielectric layer 106 is 2 nanometers to 100 nanometers during the formation of the first dielectric layer 106.

[0071] It should be noted that, in the step of forming the first dielectric layer 106, the first dielectric layer 106 is also formed on the substrate 100 between adjacent device regions, and the first dielectric layer 106 between adjacent device regions forms an opening 109.

[0072] It should also be noted that, in other embodiments, during the step of providing the substrate, an isolation structure is formed on the substrate between the stacked structures, and the top surface of the isolation structure is lower than the bottom surface of the second sacrificial layer. Correspondingly, during the step of forming the first dielectric layer, the first dielectric layer is formed on the isolation structure, and the air wall is surrounded by the isolation structure, the first stacked structure, the second stacked structure, and the first dielectric layer.

[0073] The shallow depth of the air wall makes it easier to remove the first dielectric layer at the top of the air wall. This reduces the likelihood of voids or other problems in the dielectric wall during the subsequent formation of the dielectric wall in the gap region between the first and second stacked structures, resulting in higher quality dielectric wall formation.

[0074] refer to Figure 7After the air wall 107 is formed, a second dielectric layer 108 is formed on the side of the first stacked structure 102 and the second stacked structure 103 away from the air wall 107.

[0075] The second dielectric layer 108 and the first dielectric layer 106 together prepare for the subsequent formation of the isolation layer. Furthermore, the first dielectric layer 106 and the second dielectric layer 108 exert relatively low stress on the first stacked structure 102 and the second stacked structure 103, making the first stacked structure 102 and the second stacked structure 103 less prone to bending or misalignment. This ensures that, even if the dielectric wall exerts significant stress on the first stacked structure 102 and the second stacked structure 103, the first dielectric layer 106 and the second dielectric layer 108 on the side of the first stacked structure 102 and the second stacked structure 103 facing away from the dielectric wall can provide support for the first stacked structure 102 and the second stacked structure 103. This makes the first stacked structure 102 and the second stacked structure 103 less prone to bending or misalignment under the stress of the dielectric wall, resulting in better morphological quality and improved electrical performance of the semiconductor structure.

[0076] The material of the second dielectric layer 108 is a material with low stress. The stress exerted by the second dielectric layer 108 on the stacked structure is less than the stress exerted by the subsequently formed dielectric walls on the stacked structure. Even if the second dielectric layer 108 is only formed on one side of the first stacked structure 102 and the second stacked structure 103, the stress it receives from the first dielectric layer 106 and the second dielectric layer 108 is small. The first stacked structure 102 and the second stacked structure 103 are not easily bent or misaligned, the morphology of the first stacked structure 102 and the second stacked structure 103 is better, the semiconductor process control is better, and the electrical performance of the final semiconductor structure is better.

[0077] In this embodiment, the material of the second dielectric layer 108 includes silicon oxide. Silicon oxide has low stress, is a commonly used and low-cost dielectric material, and has high process compatibility, which helps to reduce the process difficulty and cost of forming the second dielectric layer 108.

[0078] In this embodiment, the second dielectric layer 108 is formed using a flowable chemical vapor deposition (FCVD) process. The FCVD process has excellent filling capabilities and is suitable for filling the high aspect ratio opening 109 formed by the first dielectric layer 106. This helps reduce the probability of voids and other defects forming within the second dielectric layer 108, thereby improving the film quality of the second dielectric layer 108.

[0079] It should be noted that during the process of forming the second dielectric layer 108 on the side of the first stacked structure 102 and the second stacked structure 103, the second dielectric layer 108 is also formed on the top of the first dielectric layer 106.

[0080] It should also be noted that the first stacked structure 102 and the second stacked structure 103 are on the side opposite to the air wall 107, that is, the opening 109. Correspondingly, in the step of forming the second dielectric layer 108, the second dielectric layer 108 is formed in the opening 109.

[0081] refer to Figure 8 Remove the first dielectric layer 106 on top of the air wall 107.

[0082] Remove the first dielectric layer 106 on top of the air wall 107 to expose the gap region between the first stacked structure 102 and the second stacked structure 103, in preparation for the subsequent formation of a dielectric wall in the gap region.

[0083] In this embodiment, during the process of removing the first dielectric layer 106 on top of the air wall 107, the second dielectric layer 108 on top of the air wall 107 is also removed.

[0084] The step of removing the first dielectric layer 106 on top of the air wall 107 includes: planarizing the first dielectric layer 106 on top of the air wall 107.

[0085] During the planarization process of the first dielectric layer 106 at the top of the air wall 107, the top of the mask layer 110 can be used as the stopping position to reduce damage to the channel stack 101.

[0086] Specifically, the planarization process includes chemical mechanical planarization (CMP). CMP is a global surface planarization technique that can uniformly remove the first dielectric layer 106 and the second dielectric layer 108 on top of the first stacked structure 102 and the second stacked structure 103 during semiconductor manufacturing.

[0087] It should be noted that the step of removing the first dielectric layer 106 on the top of the air wall 107 includes: etching the first dielectric layer 106 on the top of the air wall 107 using a dry etching process.

[0088] During the dry etching process, the top of the mask layer 110 can be used as the etching stop position to reduce damage to other film layers.

[0089] Specifically, the dry etching process is a maskless dry etching process. The maskless dry etching process has anisotropic etching characteristics, which can eliminate the need for a photomask and reduce the process cost of removing the first dielectric layer 106 on the top of the air wall 107.

[0090] Specifically, it should be noted that in the step of removing the first dielectric layer 106 at the top of the air wall 107, the remaining first dielectric layer 106 serves as the first dielectric structure 113, and the remaining second dielectric layer 108 serves as the second dielectric structure 114.

[0091] Specifically, the first dielectric layer 106 and the second dielectric layer 108 on the side of the first stacked structure 102 and the second stacked structure 103 away from the dielectric wall can provide support for the first stacked structure 102 and the second stacked structure 103, which means that the first dielectric structure 113 and the second dielectric structure 114 provide support for the first stacked structure 102 and the second stacked structure 103.

[0092] refer to Figure 9 and Figure 10 After removing the first dielectric layer 106 on top of the air wall 107, a dielectric wall 111 is formed between the first stacked structure 102 and the second stacked structure 103.

[0093] In this embodiment of the application, during the formation of the dielectric wall 111 between the first stacked structure 102 and the second stacked structure 103, even if the dielectric wall 111 exerts significant stress on the first stacked structure 102 and the second stacked structure 103, the first dielectric structure 113 and the second dielectric structure 114 on the side of the first stacked structure 102 and the second stacked structure 103 away from the dielectric wall 111 can provide support for the first stacked structure 102 and the second stacked structure 103. This makes the first stacked structure 102 and the second stacked structure 103 less prone to bending or misalignment under the stress of the dielectric wall 111, resulting in better morphological quality of the first stacked structure 102 and the second stacked structure 103, which is beneficial to improving the electrical performance of the semiconductor structure.

[0094] The dielectric wall 111 is used to electrically isolate the first stacked structure 102 and the second stacked structure 103. Subsequently, after a first transistor is formed in the first region I and a second transistor is formed in the second region II, the dielectric wall 111 is used to electrically isolate the first transistor and the second transistor.

[0095] Specifically, the dielectric wall 111 is made of one or more of the following: silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron carbide. In this embodiment, the dielectric wall 111 is made of silicon nitride.

[0096] The step of forming a dielectric wall 111 in the gap region between the first stacked structure 102 and the second stacked structure 103 includes: forming a dielectric material film in the gap region between the first stacked structure 102 and the second stacked structure 103 and on the first stacked structure 102 and the second stacked structure 103; removing the dielectric material film above the first stacked structure 102 and the second stacked structure 103, and the remaining dielectric material film located in the gap region between the first stacked structure 102 and the second stacked structure 103 as the dielectric wall 111.

[0097] In this embodiment, the dielectric material film 112 is formed using atomic layer deposition (ALD). ALD involves multiple ALD cycles, resulting in a dielectric material film 112 with strong conformal coverage. The dielectric material film 112 conformally covers the sidewalls of the first stacked structure 102 and the second stacked structure 103. Pores are less likely to exist in the dielectric material film 112 between the first stacked structure 102 and the second stacked structure 103. Subsequently, the portion of the dielectric material film 112 above the first stacked structure 102 and the second stacked structure 103 is removed, leaving the remaining dielectric material film 112 between the first stacked structure 102 and the second stacked structure 103 as a dielectric wall. In other embodiments, the dielectric wall 111 can also be formed using chemical vapor deposition (CVD).

[0098] In this embodiment, a dry etching process is used to remove the dielectric material film 112 that is higher than the first stacked structure 102 and the second stacked structure 103. The dry etching process has anisotropic etching characteristics. During the removal of the dielectric material film 112 using the dry etching process, the top of the first dielectric structure 113 and the second dielectric structure 114 can be used as the etching stop position, thereby reducing damage to other film layers.

[0099] It should be noted that after removing the dielectric material film 112 that is higher than the first stacked structure 102 and the second stacked structure 103, the mask layer 110 is also removed.

[0100] In this embodiment, a dry etching process is used to remove the mask layer 110. During the removal of the mask layer 110 using the dry etching process, the top of the trench stack 101 can be used as the etching stop position, reducing damage to other film layers.

[0101] It should be noted that the dielectric material film 112 is made of silicon nitride, and the mask layer 110 is made of silicon nitride. Therefore, the dielectric material film 112 and the mask layer 110, which are higher than the first stacked structure 102 and the second stacked structure 103, can be removed in a one-step dry etching process, which helps to simplify the process steps and improve the formation efficiency of the semiconductor structure.

[0102] refer to Figure 11 The method for forming the semiconductor structure further includes: etching the first dielectric layer 106 and the second dielectric layer 108 to form an isolation layer 112. Specifically, etching the first dielectric structure 113 and the second dielectric structure 114 to form the isolation layer 112.

[0103] The isolation layer 112 is used for the electrically isolated substrate 100 and the subsequently formed gate structure.

[0104] The top surface of the isolation layer 112 is lower than the bottom surface of the second sacrificial layer 104, so that the second sacrificial layer 104 is not easy to remain during the subsequent removal process.

[0105] The method for forming the semiconductor structure further includes: forming a dummy gate structure on the isolation layer 112 that spans the stacked structure and the dielectric wall 111, the dummy gate structure covering part of the top wall and part of the side wall of the stacked structure; source and drain doped layers in the first stacked structure 102 and the second stacked structure 103 on both sides of the dummy gate structure; forming an interlayer dielectric layer covering the source and drain doped layers, the interlayer dielectric layer exposing the top of the dummy gate structure; removing the dummy gate structure, the first sacrificial layer 1011 and the second sacrificial layer 104, forming a gate opening in the interlayer dielectric layer; and forming a gate structure in the gate opening.

[0106] Accordingly, embodiments of this application also provide a semiconductor structure. (See reference...) Figure 12 The diagram shows a schematic representation of an embodiment of the semiconductor structure of the present invention.

[0107] The semiconductor structure includes: a substrate 200, the substrate 200 including a first region I and a second region II; a stacked structure, disposed on the substrate 200, the stacked structure located in the first region I being a first stacked structure 202, the stacked structure located in the second region II being a second stacked structure 203, a spacer region 207 being formed between the first stacked structure 202 and the second stacked structure 203; a first dielectric structure 213 located on a sidewall of the first stacked structure 202 and the second stacked structure 203 away from the spacer region 207; and a second dielectric structure 214 located on a sidewall of the first dielectric structure 213.

[0108] In the semiconductor structure provided in this application embodiment, the first dielectric structure 213 and the second dielectric structure 214 exert relatively low stress on the first stacked structure 202 and the second stacked structure 203, making the first stacked structure 202 and the second stacked structure 203 less prone to bending or misalignment. Subsequently, a dielectric wall is formed in the gap region 207 between the first stacked structure 202 and the second stacked structure 203. During the formation of the dielectric wall in the gap region 207 between the first stacked structure 202 and the second stacked structure 203, even if the dielectric wall exerts significant stress on the first stacked structure 202 and the second stacked structure 203, the first dielectric structure 213 and the second dielectric structure 214 on the side of the first stacked structure 202 and the second stacked structure 203 away from the gap region 207 can provide support for the first stacked structure 202 and the second stacked structure 203, making the first stacked structure 202 and the second stacked structure 203 less prone to bending or misalignment under the stress of the dielectric wall. The morphological quality of the first stacked structure 202 and the second stacked structure 203 is better, which is beneficial to improving the electrical performance of the semiconductor structure.

[0109] In this embodiment, the first region I is used to form a first-type transistor, and the second region II is used to form a second-type transistor. The first-type transistor and the second-type transistor have different conduction types. Specifically, the first-type transistor is a PMOS (Positive Channel Metal Oxide Semiconductor), and the second-type transistor is an NMOS (Negative Channel Metal Oxide Semiconductor).

[0110] The substrate 200 is used to provide a process platform for the subsequent formation of the gate structure, preparing for the subsequent formation of the forksheet.

[0111] In this embodiment, the substrate 200 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth, etc., and the substrate may also be other types of substrates such as silicon on insulator or germanium on insulator.

[0112] It should be noted that the first region I and the second region II are located in the device region, and the substrate 200 includes a plurality of phase-spaced device regions.

[0113] The stacked structure includes: a fin 205, and a plurality of channel stacks 201 located on the fin 205, wherein the channel stacks 201 include a first sacrificial layer 2011 and a channel layer 2012 located on the first sacrificial layer 2011.

[0114] The first sacrificial layer 2011 is then removed to form a gate structure that fully surrounds the channel layer 2012. The fin 205 is used to space the channel stack 201 from the substrate 200, in preparation for the subsequent formation of an isolation layer between the substrate 200 and the gate structure.

[0115] In this embodiment, the material of the fin 205 is the same as the material of the substrate 200. In other embodiments, the material of the fin may be different from the material of the substrate.

[0116] The channel stack 201 provides a process basis for the subsequent channel layer 2012 to be suspended. The first sacrificial layer 2011 supports the channel layer 2012, provides process conditions for the subsequent channel layer 2012 to be suspended, and also occupies space for the gate structure to be formed later.

[0117] When the semiconductor structure is in operation, the channel layer 2012 serves as the channel region.

[0118] In this embodiment, the channel layer 2012 is more difficult to etch than the first sacrificial layer 2011, so the channel layer 2012 is less likely to be damaged when the first sacrificial layer 2011 is removed.

[0119] In this embodiment, the channel layer 2012 is made of silicon; the first sacrificial layer 2011 is made of silicon germanide. In other embodiments, the channel layer may also be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ide, and the first sacrificial layer may also be made of silicon.

[0120] It should be noted that, in the step of providing the substrate with the lateral direction parallel to the surface of the substrate 200 and perpendicular to the extension direction of the stacked structure, the lateral dimension D of the gap region 207 between the first stacked structure 202 and the second stacked structure 203 should not be too large or too small. The first dielectric structure 213 and the second dielectric structure 214 are formed after the first stacked structure 202 and the second stacked structure 203. The step of forming the first dielectric structure 213 and the second dielectric structure 214 includes: forming a first dielectric layer that conformally covers the first stacked structure 202 and the second stacked structure 203 and surrounds the gap region 207 between the first stacked structure 202 and the second stacked structure 203; forming a second dielectric layer on the first dielectric layer; removing the first dielectric layer that is higher than the first stacked structure 202 and the second stacked structure 203; the remaining first dielectric layer serves as the first dielectric structure 213; and the remaining second dielectric layer serves as the second dielectric structure 214. If the lateral dimension D of the gap region 207 between the first stacked structure 202 and the second stacked structure 203 is too large, during the formation of the first dielectric layer, the first dielectric layer will be unable to surround the first stacked structure 202 and the second stacked structure 203. The first dielectric layer formed in the gap region 207 will occupy the space subsequently used to form dielectric walls, resulting in poor electrical isolation between the channel layer 2012 in the first stacked structure 202 and the channel layer 2012 in the second stacked structure 203, leading to poor electrical performance of the semiconductor structure. Conversely, if the lateral dimension D of the gap region 207 between the first stacked structure 202 and the second stacked structure 203 is too small, the lateral dimension of the dielectric wall subsequently formed between the first stacked structure 202 and the second stacked structure 203 will be small. The dielectric wall will not effectively electrically isolate the channel layer 2012 in the first stacked structure 202 and the channel layer 2012 in the second stacked structure 203, resulting in poor electrical performance of the semiconductor structure. In this embodiment, the lateral dimension D of the spacing region 207 between the first stacked structure 202 and the second stacked structure 203 is 3 nanometers to 30 nanometers.

[0121] The stacked structure further includes a second sacrificial layer 204 located between the fin 205 and the channel stack 201.

[0122] The etching resistance of the second sacrificial layer 204 is less than that of the first sacrificial layer 2011. During the subsequent removal of the first sacrificial layer 2011, the second sacrificial layer 204 is less likely to remain. After removing the first sacrificial layer 2011 and the second sacrificial layer 204, preparation is made for the formation of the gate structure.

[0123] The process space for forming the gate structure between the fin 205 and the bottommost channel layer 2012 is relatively large. Therefore, when the semiconductor structure is working, the gate structure has a strong control over the bottommost channel layer 2012, and at the same time, the gate structure has a strong control over the fin 205, which is beneficial to improving the electrical performance of the semiconductor structure.

[0124] In this embodiment, a mask layer 210 is also formed on top of the channel stack 201. During the formation of the semiconductor structure, the mask layer 210 is used to protect the top of the stacked structure from damage.

[0125] Specifically, the material of the mask layer 210 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, boron silicon nitride, and boron silicon carbide. In this embodiment, the material of the mask layer 210 includes silicon nitride.

[0126] In other embodiments, an isolation structure is formed on the substrate between the stacked structures, the top surface of the isolation structure being lower than the bottom surface of the second sacrificial layer.

[0127] The material of the first dielectric structure 213 is a material with low stress. Even if the first dielectric structure 213 is only formed on one sidewall of the first stacked structure 202 and the second stacked structure 203, the first stacked structure 202 and the second stacked structure 203 are subjected to less stress from the first dielectric structure 213, and are not easily bent or misaligned. The morphology of the first stacked structure 202 and the second stacked structure 203 is better, the semiconductor process control is better, and the electrical performance of the final semiconductor structure is better.

[0128] In this embodiment, the material of the first dielectric structure 213 includes silicon oxide. Silicon oxide has low stress, is a commonly used and low-cost dielectric material, and has high process compatibility, which helps to reduce the process difficulty and cost of forming the first dielectric structure 213.

[0129] It should be noted that the first dielectric structure 213 should not be too thick or too thin. If the first dielectric structure 213 is too thick, that is, if an excessively thick first dielectric structure 213 is formed on one sidewall of the first stacked structure 202 and the second stacked structure 203, even if the stress of the material of the first dielectric structure 213 is small, the first stacked structure 202 and the second stacked structure 203 are still prone to bending or tilting under the action of the excessively thick first dielectric structure 213. The morphology of the first stacked structure 202 and the second stacked structure 203 is poor, the semiconductor process control is poor, and the electrical performance of the final semiconductor structure is poor. If the first dielectric structure 213 is too thin, during the formation of the first dielectric structure 213, the first dielectric layer will have difficulty surrounding the gap region 207 between the first stacked structure 202 and the second stacked structure 203. This makes it difficult to form an air wall between the first stacked structure 202 and the second stacked structure 203. In the subsequent step of forming the second dielectric structure 214, the second dielectric structure 214 is likely to be formed in the gap region 207, occupying the space for the formation of the subsequent dielectric wall. The electrical isolation effect between the channel layer 2012 in the first stacked structure 202 and the channel layer 2012 in the second stacked structure 203 will be poor, resulting in poor electrical performance of the semiconductor structure. In this embodiment, the thickness of the first dielectric structure 213 is 2 nanometers to 200 nanometers.

[0130] The second dielectric structure 214 and the first dielectric structure 213 together prepare for the subsequent formation of the isolation layer. The material of the second dielectric structure 214 is a material with low stress. Even if the second dielectric structure 214 is only formed on one side of the first stacked structure 202 and the second stacked structure 203, the first stacked structure 202 and the second stacked structure 203 are not easily bent or misaligned. The morphology of the first stacked structure 202 and the second stacked structure 203 is better, and the semiconductor process control is better, resulting in better electrical performance of the final semiconductor structure.

[0131] In this embodiment, the material of the second dielectric structure 214 includes silicon oxide. Silicon oxide has low stress, is a commonly used and low-cost dielectric material, and has high process compatibility, which helps to reduce the process difficulty and cost of forming the second dielectric structure 214.

[0132] It should be noted that the second dielectric structure 214 is also formed on top of the first dielectric structure 213.

[0133] The semiconductor structure can be formed using the formation method of the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here. Although the embodiments of this application have been disclosed above, the embodiments of this application are not limited thereto.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises: providing a substrate, the substrate comprising a first region and a second region spaced apart, the substrate comprising a substrate and a plurality of stack structures on the substrate, the stack structures in the first region as first stack structures, the stack structures in the second region as second stack structures; forming a first dielectric layer conformally covering the first stack structures, second stack structures, and surrounding a spacing region between the first stack structures and the second stack structures, forming an air wall between the first stack structures and the second stack structures; after forming the air wall, forming a second dielectric layer on a side of the first stack structures and the second stack structures away from the air wall; removing the first dielectric layer on top of the air wall; after removing the first dielectric layer on top of the air wall, forming a dielectric wall in the spacing region between the first stack structures and the second stack structures.

2. The method of forming a semiconductor structure of claim 1, wherein, The first dielectric layer is formed by a plasma chemical vapor deposition process.

3. The method of forming a semiconductor structure of claim 1, wherein, In the step of forming the first dielectric layer, the thickness of the first dielectric layer is 2 nm to 100 nm.

4. The method of forming a semiconductor structure of claim 1, wherein, The material of the first dielectric layer comprises silicon oxide.

5. The method of forming a semiconductor structure of claim 1, wherein, In the step of providing the substrate, the spacing region between the first stack structures and the second stack structures has a lateral dimension of 3 nm to 30 nm in a lateral direction parallel to the surface of the substrate and perpendicular to the extension direction of the stack structures.

6. The method of forming a semiconductor structure of claim 1, wherein, The second dielectric layer is formed by a flowable chemical vapor deposition process.

7. The method of forming a semiconductor structure of claim 1, wherein, The material of the second dielectric layer comprises silicon oxide.

8. The method of forming a semiconductor structure of claim 1, wherein, The step of removing the first dielectric layer on top of the air wall comprises planarizing the first dielectric layer on top of the air wall.

9. The method of forming a semiconductor structure of claim 8, wherein, The planarization process comprises a chemical mechanical polishing process.

10. The method of forming a semiconductor structure of claim 8, wherein, The step of removing the first dielectric layer on top of the air wall comprises etching the first dielectric layer on top of the air wall by a dry etching process.

11. The method of forming a semiconductor structure of claim 1, wherein, The material of the dielectric wall comprises one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, boron nitride, boron silicon nitride, and boron carbon silicon nitride.

12. The method of forming a semiconductor structure of claim 1, wherein, The step of forming a dielectric wall in the spacing region between the first stack structures and the second stack structures comprises: forming a film of dielectric material in the spacing region between the first stack structures and the second stack structures and on the first stack structures and the second stack structures; removing the film of dielectric material above the first stack structures and the second stack structures, the remaining film of dielectric material in the spacing region between the first stack structures and the second stack structures as the dielectric wall.

13. The method of forming a semiconductor structure of claim 1, wherein, In the step of providing the substrate, the stack structures comprise a fin, a plurality of channel stacks on the fin, the channel stacks comprising a first sacrificial layer and a channel layer on the first sacrificial layer; The stack structures further comprise a second sacrificial layer between the fin and the channel stacks.

14. The method of claim 13, wherein: In the step of forming the first dielectric layer, the first stack structures, the second stack structures, the first dielectric layer, and the substrate enclose an air wall; The method further comprises: etching the first dielectric layer and the second dielectric layer to form an isolation layer, a top surface of the isolation layer being lower than a bottom surface of the second sacrificial layer.

15. The method of forming a semiconductor structure of claim 13, wherein, In the step of providing the substrate, an isolation structure is formed on the substrate between the stack structures, a top surface of the isolation structure being lower than a bottom surface of the second sacrificial layer; In the step of forming the first dielectric layer, the first dielectric layer is formed on the isolation structure, the air wall being enclosed by the isolation structure, the first stack structure, the second stack structure and the first dielectric layer.

16. A semiconductor structure, characterized by formed based on the forming method as in claim 1, comprising: a substrate, the substrate comprising a first region and a second region; stack structures, being separated on the substrate, the stack structures in the first region being first stack structures, the stack structures in the second region being second stack structures, a spacing region being formed between the first stack structures and the second stack structures; a first dielectric structure, being located on a side wall of the first stack structures and the second stack structures away from the spacing region; a second dielectric structure, being located on a side wall of the first dielectric structure.

17. The semiconductor structure of claim 16, wherein, In a lateral direction parallel to a surface of the substrate and perpendicular to an extending direction of the stack structures, a lateral dimension of the spacing region between the first stack structures and the second stack structures is 3 nanometers to 30 nanometers.

18. The semiconductor structure of claim 16, wherein, A thickness of the first dielectric structure is 2 nanometers to 100 nanometers.

19. The semiconductor structure of claim 16, wherein, A material of the first dielectric structure comprises silicon oxide.

20. The semiconductor structure of claim 16, wherein, A material of the second dielectric structure comprises silicon oxide.

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