Method and apparatus for smoothing dynamic random access memory bit line metal

Abstract

A process for smoothing the top surface of bit line metal of a memory structure to reduce the resistance of the bit line stack. The process includes depositing a titanium layer of about 10 A to about 50 A on a polysilicon layer on a substrate, depositing a first titanium nitride layer of about 10 A to about 50 A on the titanium layer, annealing the substrate at a temperature of about 700 °C to about 850 °C, depositing a second titanium nitride layer of about 10 A to about 50 A on the first titanium nitride layer after annealing, depositing a ruthenium bit line metal layer on the second titanium nitride layer, annealing the bit line metal layer at a temperature of about 550 °C to about 650 °C, and soaking the bit line metal layer in a hydrogen-based environment for about 3 minutes to about 6 minutes during annealing.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the fields of electronic devices and electronic device manufacturing. More specifically, embodiments of this disclosure provide electronic devices including bit lines having a smooth top surface and methods for forming the same. Background Technology

[0002] Modern integrated circuits typically feature very fine spacing and high density in their conductive interconnect layers. Even a small defect in the precursor metal film that ultimately forms the metal interconnect layers of the integrated circuit can be localized to severely compromise the operational integrity of the integrated circuit. Bit line stacking deposition presents several potential problems. Surface reactions between the metal and the silicon nitride hard mask can occur due to the high deposition temperatures experienced during hard mask formation. Bit line resistance increases due to the interdiffusion of silicon into the bit lines and metal atoms into the silicon nitride hard mask. Furthermore, the high temperatures during formation cause metal surface roughness, making it difficult to grow the metal using grain growth techniques.

[0003] Therefore, the inventors provide a method and apparatus for smoothing the top surface of bit line metal. Summary of the Invention

[0004] This article provides methods and apparatus for smoothing the top surface of bit line metal.

[0005] In some embodiments, a method for smoothing the top surface of the bit line metal of a memory structure may include: depositing approximately [missing information - likely a specific material] on a polysilicon layer on a substrate. to approximately A titanium layer; approximately [amount missing] is deposited on the titanium layer. to approximately A first titanium nitride layer; the substrate is annealed at a temperature of about 700°C to about 850°C; after annealing, about [amount missing] titanium nitride is deposited on the first titanium nitride layer. to approximately A second titanium nitride layer; a ruthenium site metal layer is deposited on the second titanium nitride layer; the site metal layer is annealed at a temperature of about 550°C to about 650°C; and the site metal layer is immersed in a hydrogen-based environment for about 3 minutes to about 6 minutes during the annealing process.

[0006] In some embodiments, the method may further include: depositing a capping layer on the bit line metal layer at a deposition temperature of about 350°C to about 400°C, and depositing a hard mask layer on the capping layer at a deposition temperature above about 500°C, wherein the capping layer comprises one or more of silicon nitride or silicon carbonitride, wherein the capping layer is about to approximately The capping layer is deposited using chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes, wherein the hard mask layer comprises silicon nitride, wherein the hard mask layer is deposited using low-pressure chemical vapor deposition (LPCVD) at a deposition temperature below about 400°C on the bit line metal layer, wherein the hard mask layer is deposited using low-pressure chemical vapor deposition (LPCVD) processes, and / or wherein the bit line metal layer has a top surface with a root mean square roughness (RMS) of 1.15 nm or less.

[0007] In some embodiments, a method of forming a memory structure may include: forming a barrier metal layer on a polysilicon layer on a substrate; annealing the barrier metal layer at a temperature of about 700°C to about 850°C; forming a barrier layer on the barrier metal layer; depositing a bit line metal layer on the barrier layer; annealing the bit line metal layer at a temperature of about 550°C to about 650°C; and immersing the bit line metal layer in a hydrogen-based environment for about 3 minutes to about 6 minutes during the annealing process.

[0008] In some embodiments, the method may further include: wherein the barrier metal layer is formed on the polysilicon layer. to approximately The titanium layer and approximately formed on the titanium layer to approximately A titanium nitride layer, wherein the barrier metal layer is annealed to form a titanium silicide layer on the polycrystalline silicon layer, wherein the barrier layer is approximately... to approximately The titanium nitride layer, wherein the bit line metal layer is a grain-grown metal layer with a top surface roughness root mean square (RMS) of 1.15 nm or less, is used to form a capping layer on the bit line metal layer using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process at a deposition temperature of about 350 °C to about 400 °C, and a hard mask layer is formed on the capping layer using a low-pressure chemical vapor deposition (LPCVD) process at a deposition temperature above about 500 °C, wherein the capping layer is about to approximately And / or a hard mask layer is deposited on the bit line metal layer using a low-pressure chemical vapor deposition (LPCVD) process at a deposition temperature below about 400°C.

[0009] In some embodiments, a method for smoothing the top surface of the bit line metal of a memory structure may include: depositing approximately [missing information - likely a specific material] on a polysilicon layer on a substrate using a plasma vapor deposition (PVD) chamber. to approximately A titanium layer is deposited; the substrate is annealed at a temperature of about 700°C to about 850°C, without breaking the vacuum between the deposition of the titanium layer and the annealing of the substrate; after annealing, approximately [amount missing] is deposited on the titanium layer. to approximately A titanium nitride layer; a ruthenium dot metal layer is deposited on the titanium nitride layer; the dot metal layer is annealed at a temperature of about 550°C to about 650°C; and the dot metal layer is immersed in a hydrogen-based environment for about 3 minutes to about 6 minutes during the annealing process, such that the top surface of the dot metal has a root mean square roughness (RMS) of 1.15 nm or less.

[0010] In some embodiments, the method may further include: depositing a capping layer on the bit line metal layer at a deposition temperature of about 350°C to about 400°C and depositing a hard mask layer on the capping layer at a deposition temperature above about 500°C, or depositing a hard mask layer on the bit line metal layer at a deposition temperature below about 400°C.

[0011] Other and further implementation methods are disclosed below. Attached Figure Description

[0012] The embodiments of this principle, which are briefly summarized above and discussed in more detail below, can be understood by referring to the illustrative embodiments depicted in the accompanying drawings. However, the drawings only show typical embodiments of this principle and should therefore not be considered as a limitation of the scope, as these principles can allow for other equally effective embodiments.

[0013] Figure 1 Circuit diagrams of dynamic memory cells in DRAM memory with improved characteristics according to some embodiments of this principle are depicted.

[0014] Figure 2 Cross-sectional views of membrane stacks according to some embodiments of this principle are depicted.

[0015] Figure 3 This refers to a method for forming film stacks based on some implementations of this principle.

[0016] Figure 4 This is a method for forming a film stack with a smooth bit line metal layer according to some embodiments of this principle.

[0017] Figure 5 This is a cross-sectional view of a barrier metal layer according to some embodiments of this principle.

[0018] Figure 6 This is a top view of a clustering tool based on some implementations of this principle.

[0019] Figure 7These are substrate manufacturing methods based on some embodiments of this principle.

[0020] Figure 8 This is a cross-sectional view of a substrate according to some embodiments of this principle.

[0021] Figure 9 This is a method for smoothing the top surface of a bit line metal layer according to some embodiments of this principle.

[0022] For ease of understanding, the same reference numerals have been used where possible to denote common elements in the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be advantageously incorporated into other embodiments without further description. Detailed Implementation

[0023] Bit line stacking and methods for forming bit line stacks with reduced resistance and bit line surface roughness are provided. One or more embodiments of this disclosure advantageously address the problem of reducing resistivity despite the need for node shrinkage. In some embodiments, the resistivity of the bit lines is reduced by providing a cleaner interface with existing bit line metals and by reducing the surface roughness of the bit line metals. Some embodiments of this disclosure advantageously provide one or more of the following: flexibility in the selection of bit line metals; flexibility in the temperature of silicon nitride hard mask deposition; ensuring a clean metal-dielectric interface resulting in lower resistivity; or minimizing or eliminating the risk of contamination of the high-temperature silicon nitride hard mask deposition chamber by new bit line metals.

[0024] Some embodiments of this disclosure provide a low-temperature deposition method using a capping layer to prevent roughening of the bit line metal surface when the selected metal exhibits grain growth characteristics. In some embodiments, a high-density, non-porous film is used to act as a good diffusion barrier at elevated temperatures. Some embodiments provide a dielectric material, such as silicon nitride (SiN) or silicon carbonitride (SiCN), to act as a capping layer to minimize or eliminate the adverse effects on the RC time constant by acting as a good diffusion barrier for the bit line metal and the SiN hard mask. Some embodiments include annealing the metal layer prior to deposition of the grain growth metal to reduce the surface roughness of the grain growth metal, thereby reducing resistance. Some embodiments include annealing the grain growth material used for the bit line metal layer to reduce surface roughness while maintaining low resistivity. The RC time constant is the time associated with charging a capacitor to one percent of its full charge through a resistor or discharging a capacitor to a portion of its initial voltage. The RC time constant is equal to the product of the circuit resistance and the circuit capacitance. Some embodiments of this disclosure advantageously provide a low-temperature (e.g., <500°C) deposition process. Some implementations provide a deposition process compatible with the underlying bitline metal to minimize or eliminate surface reactions during film deposition.

[0025] One or more embodiments of this disclosure generally provide structures including one or more low resistivity features formed of a thin-film refractory metal (e.g., tungsten), as can be implemented in bit line structures and / or gate stacks. Some embodiments include methods for forming bit line stacks. For example, the bit line stack structure formed according to embodiments of this disclosure can be a memory-type semiconductor device, such as a DRAM-type integrated circuit.

[0026] Figure 1 A schematic circuit diagram 100 is shown, which illustrates a transistor and a capacitor cell that can be used in a DRAM memory. Figure 1 The memory cell depicted includes a storage capacitor 110 and a select transistor 120. The select transistor 120 is formed as a field-effect transistor and has a first source / drain electrode 121 and a second source / drain electrode 123, with an active region 122 disposed between them. Above the active region 122 are a gate insulating layer or dielectric layer 124 (typically thermally grown oxide) and a gate electrode / metal 125 (referred to as a word line in a memory device), which together act as a parallel-plate capacitor and can affect the charge density in the active region 122 to form or block a current conduction channel between the first source / drain electrode 121 and the second source / drain electrode 123.

[0027] The second source / drain electrode 123 of the select transistor 120 is connected to the first electrode 111 of the storage capacitor 110 via a metal line 114. The second electrode 112 of the storage capacitor 110 is sequentially connected to capacitor plates, which may be common to the storage capacitors arranged in a DRAM memory cell. The second electrode 112 of the storage capacitor 110 may be connected to electrical ground via a metal line 115. The first source / drain electrode 121 of the select transistor 120 is further connected to a bit line 116 so that information stored in the storage capacitor 110 in the form of charge can be written and read. The write or read operation is controlled via a word line 117 or the gate electrode 125 of the select transistor 120 and the bit line 116 connected to the first source / drain electrode 121. The write or read operation occurs by applying a voltage to create a current conduction channel in the active region 122 between the first source / drain electrode 121 and the second source / drain electrode 123.

[0028] Figure 2 The illustration shows a portion of a memory device 200 according to one or more embodiments of the present disclosure. Figure 3 The diagram is used to form Figure 2 An exemplary processing method 300 of the memory device 200 illustrated in the figures is shown. Those skilled in the art will recognize that the film stack illustrated in the figures is an exemplary portion (bit line portion) of the memory device. Reference Figure 2 and Figure 3 The formation of memory device 200 includes providing a substrate 210 in operation 310, on which a film stack 205 may be formed. As used in the specification and appended claims, the term “provide” means to make the substrate available for processing (e.g., placed in a processing chamber).

[0029] As used in the specification and appended claims, the term "substrate" means a surface or part thereof on which a process is performed. Reference to a substrate may refer only to a portion of the substrate unless the context clearly indicates otherwise. Furthermore, reference to deposition on a substrate may refer to a bare substrate and a substrate on which one or more films or features are deposited or formed. As used herein, "substrate" means any substrate on which a film treatment is performed during a manufacturing process or a material surface formed on a substrate. For example, substrate surfaces on which treatments can be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes such as polishing, etching, reduction, oxidation, hydroxylation, annealing, and / or baking of the substrate surface. In addition to performing film treatments directly on the surface of the substrate, any film treatment steps disclosed in this disclosure may also be performed on an underlying layer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include the underlying layer as indicated by the context. Thus, for example, when a film / layer or a portion of a film / layer has been deposited onto the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0030] In some embodiments, the provided substrate 210 includes a film stack 205 comprising a polysilicon layer 215 and a bit line metal layer 240. In some embodiments, the provided substrate 210 includes a polysilicon layer 215, and the bit line metal layer 240 is formed as part of method 300. In some embodiments, the substrate 210 includes an oxide layer (not shown) on a silicon wafer. In some embodiments, the oxide layer is a native oxide formed on the silicon wafer. In some embodiments, the oxide layer is intentionally formed on the silicon wafer and has a thickness greater than that of the native oxide film. The oxide layer can be formed by any suitable technique known to those skilled in the art, including but not limited to thermal oxidation, plasma oxidation, and exposure to atmospheric conditions.

[0031] In some embodiments, the substrate 210 provided in operation 310 further includes a barrier metal layer 220 (also referred to as a conductive layer) located on the polysilicon layer 215. The barrier metal layer 220 can be any suitable conductive material. In some embodiments, the barrier metal layer 220 includes one or more of titanium (Ti), tantalum (Ta), titanium silicide (TiSi), or tantalum silicide (TaSi). In some embodiments, the barrier metal layer 220 includes titanium. In some embodiments, the barrier metal layer 220 is substantially composed of titanium. In some embodiments, the barrier metal layer 220 includes tantalum or is substantially composed of tantalum. In some embodiments, the barrier metal layer 220 includes titanium silicide or is substantially composed of titanium silicide. In some embodiments, the barrier metal layer 220 includes tantalum silicide or is substantially composed of tantalum silicide. As used in this way, the term "substantially composed of" means that the subject film comprises, on an atomic basis, greater than or equal to about 95%, 98%, 99%, or 99.9% of said element or composition. For example, the barrier metal layer 220, which is essentially composed of titanium, has a film deposited with titanium of about 95%, 98%, 99%, or 99.5%.

[0032] In some embodiments, the substrate 210 provided in operation 310 further includes a barrier layer 230 on the conductive layer (barrier metal layer 220). The barrier layer 230 may be formed between the barrier metal layer 220 and the bit line metal layer 240. In some embodiments, method 300 includes an operation prior to operation 310 in which the bit line metal layer 240 is formed on the barrier layer 230. The barrier layer 230 may be any suitable barrier layer material. In some embodiments, the barrier layer 230 comprises one or more of a nitride or oxide of the barrier metal layer 220. In some embodiments, the barrier layer 230 is substantially composed of a nitride of the barrier metal layer 220. For example, a barrier layer 230 substantially composed of titanium nitride means that the total amount of titanium and nitrogen atoms in the film constitutes, on an atomic basis, greater than or equal to about 95%, 98%, 99%, or 99.5% of the deposited barrier layer 230.

[0033] In some embodiments, the barrier metal layer 220 comprises titanium (Ti) and the barrier layer 230 comprises titanium nitride (TiN). In some embodiments, the barrier metal layer 220 is substantially composed of titanium and the barrier layer 230 is substantially composed of titanium nitride. In one or more embodiments, the barrier metal layer 220 comprises one or more metals selected from cobalt (Co), copper (Cu), nickel (Ni), ruthenium (Ru), manganese (Mn), silver (Ag), gold (Au), platinum (Pt), iron (Fe), molybdenum (Mo), rhodium (Rh), titanium (Ti), tantalum (Ta), silicon (Si), or tungsten (W). In one or more specific embodiments, the barrier metal layer 220 (conductive material) comprises one or more of titanium (Ti), copper (Cu), cobalt (Co), tungsten (W), or ruthenium (Ru). In some embodiments, the barrier layer 230 comprises a nitride, oxynitride, carbonitride, or oxycarbonitride of the metal in the barrier metal layer 220. In some embodiments, the barrier metal layer 220 comprises tantalum or tantalum silicide (or is substantially composed of tantalum or tantalum silicide), and the barrier layer 230 comprises tantalum nitride (or is substantially composed of tantalum nitride). In some embodiments, the barrier metal layer 220 comprises titanium or titanium silicide (or is substantially composed of titanium or titanium silicide), and the barrier layer 230 comprises titanium nitride (or is substantially composed of titanium nitride).

[0034] In some embodiments, the bit line metal layer 240 is included in the substrate provided in operation 310 of method 300. The bit line metal layer 240 can be deposited by any suitable technique known to those skilled in the art. In some embodiments, the bit line metal layer 240 comprises one or more of tungsten (W), ruthenium (Ru), iridium (Ir), platinum (Pt), rhodium (Rh), or molybdenum (Mo). In some specific embodiments, the bit line metal layer 240 comprises one or more of ruthenium or tungsten or is substantially composed of one or more of ruthenium or tungsten. Ruthenium requires different processing to replace tungsten in the bit line metal layer. Tungsten generally has a lower surface roughness and resistivity than ruthenium. The inventors have discovered methods, as discussed below, to improve the surface roughness of ruthenium while maintaining a low resistivity to allow ruthenium to replace tungsten. The thickness of the bit line metal layer 240 can be varied. In some embodiments, the thickness of the bit line metal layer 240 is approximately to approximately Within the range, or about to approximately Within the range, or about to approximately Within the range, or about to approximately Within the scope of this method, the bit line metal layer 240 can be deposited using any suitable technique known to those skilled in the art. In some embodiments, the bit line metal layer 240 is deposited by one or more of chemical vapor deposition, atomic layer deposition, or physical vapor deposition.

[0035] In operation 320, a capping layer 250 is formed on the bit line metal layer 240. In some embodiments, the capping layer 250 is deposited at a lower temperature than the temperature typically used to form the subsequent hard mask layer 260. Unbound from any particular operational theory, the inventors believe that the lower deposition temperature minimizes the diffusion of elements from the capping layer 250 into the bit line metal layer 240. In some embodiments, the inventors believe that the low-temperature deposition of the capping layer 250 minimizes grain growth at the interface of the bit line metal layer 240 and minimizes the influence of grain size and roughness on the resistivity of the resulting bit line metal layer 240.

[0036] The capping layer 250 can be deposited using any suitable technique known to those skilled in the art. In some embodiments, the capping layer 250 is deposited by one or more of chemical vapor deposition or atomic layer deposition. In some embodiments, the capping layer 250 comprises the same compound as the subsequent hard mask 260. In some embodiments, the capping layer 250 comprises one or more of silicon nitride, silicon carbonitride, or silicon carbide. In some embodiments, the capping layer 250 is substantially composed of silicon nitride. In some embodiments, the capping layer 250 is substantially composed of silicon carbonitride. In some embodiments, the capping layer 250 is substantially composed of silicon carbide. The thickness of the capping layer 250 can be varied to minimize the effects of high-temperature formation of the hard mask 260. In some embodiments, the thickness of the capping layer 250 is approximately... To date Within a certain range. The deposition temperature of the capping layer 250 can be controlled to, for example, maintain the thermal budget of the device being formed. In some embodiments, the capping layer 250 is formed at a temperature below or equal to about 500°C, or about 450°C, or about 400°C, or about 350°C, or about 300°C. In some embodiments, the capping layer 250 is formed at a temperature in the range of about 350°C to about 550°C or in the range of about 400°C to about 500°C.

[0037] In operation 330, a hard mask 260 is formed on the capping layer 250. In some embodiments, the hard mask 260 is formed in a furnace at temperatures above about 500°C, about 600°C, about 650°C, about 700°C, or about 750°C. In some embodiments, the hard mask 260 comprises the same composition as the capping layer 250. In some embodiments, the capping layer 250 and the hard mask 260 comprise silicon nitride, silicon oxide, or silicon carbide, or are substantially composed of silicon nitride, silicon oxide, or silicon carbide. In some embodiments, the hard mask 260 has a different density than the capping layer 250. In some embodiments, the hard mask 260 has a different porosity than the capping layer 250. In some embodiments, the hard mask 260 has a different deposition temperature than the capping layer 250.

[0038] In some embodiments, the bit line metal layer 240 comprises or is substantially composed of tungsten, and one or more of the capping layer 250 or hard mask 260 comprises or is substantially composed of silicon nitride. In some embodiments, the bit line metal layer 240 comprises or is substantially composed of ruthenium, and one or more of the capping layer 250 or hard mask 260 comprises or is substantially composed of silicon oxide or silicon nitride. In some embodiments, migration of elements from the hard mask 260 into the bit line metal layer 240 is substantially prevented. For example, if the hard mask 260 comprises silicon and nitrogen atoms, migration of silicon or nitrogen atoms into the bit line metal layer 240 is substantially prevented. When used in this manner, the term "substantially prevented" means that less than or equal to about 10% or 5% of the elements of the hard mask 260 migrate through the capping layer 250 into the bit line metal layer 240.

[0039] The inventors have discovered that when the grain growth metal is annealed to reduce resistance before the formation of the capping layer 250, the annealing causes silicide formation in the underlying barrier metal layer 220. Furthermore, silicon diffuses into the barrier layer 230. The additional stress caused by the annealing of the grain growth metal causes the surface 232 of the barrier layer 230 to crack. When the grain growth metal of the bitline metal layer 240 grows on the cracked surface of the barrier layer 230, the cracked surface of the barrier layer 230 results in a roughened top surface 242 for the bitline metal layer 240. The roughness of the top surface 242 of the bitline metal layer 240 directly affects the resistivity of the bitline metal layer 240. The inventors have discovered that by annealing the barrier metal layer 220 before the formation of the barrier layer 230, the silicide formation effect caused by the annealing of the grain growth metal of the bitline metal layer 240 is significantly reduced or eliminated, thereby allowing the bitline metal layer 240 to have a smoother top surface 242 and reduced resistivity.

[0040] Figure 4This is a method 400 for forming a film stack with a smooth bit line metal layer 240. In operation 402, a barrier metal layer 220 is formed on a polysilicon layer 215 on a substrate 210. In some embodiments, the barrier metal layer 220 is formed by first depositing approximately to approximately A conductive material 502 (e.g., titanium, tantalum, etc.) is then deposited, and approximately... to approximately The oxygen barrier layer 504 is formed (see Figure 5 (See Figure 500). In processes using different chambers for deposition and annealing, substrate 210 is exposed to the atmosphere when transported between chambers. An oxygen barrier layer 504 (e.g., titanium nitride, tantalum nitride, etc.) prevents the conductive material 502 from oxidizing during the transport of substrate 210. In some embodiments, such as Figure 6 The integrated tool 600 shown can be used to provide a process without air interruption between deposition and annealing processes. In embodiments using the integrated cluster tool 600, the oxygen barrier layer 504 deposition process can be removed because the substrate is never exposed to the atmosphere and the deposited conductive material 502 is not oxidized.

[0041] In operation 404, the barrier metal layer 220 is annealed at a temperature of approximately 700°C to approximately 850°C. The temperature can vary depending on the composition of the barrier metal layer 220. During the annealing of the barrier metal layer 220, the conductive material 502 is silicided and the oxygen barrier layer 504 allows silicon to migrate through the oxygen barrier layer 504, damaging the surface 506. Compared to the approximately 2.2 nm surface roughness RMS without the barrier metal layer annealing process, the annealing of the barrier metal layer 220 results in an improved surface roughness RMS (root mean square) of approximately 1.7 nm for the ruthenium dot line metal layer (measured using atomic force microscopy (AFM)). In operation 406, a barrier layer 230 is formed on the barrier metal layer 220. The thickness of the barrier layer 230 can be approximately To date Defects on surface 506 can be masked by the deposition of barrier layer 230, which helps to reduce roughness and resistivity. Barrier layer 230 may include, for example, a nitride variant of conductive material 502 used in barrier metal layer 220.

[0042] In operation 408, a bit line metal layer 240 is formed on the barrier layer 230. The bit line metal layer 240 includes a grain growth metal, such as, but not limited to, ruthenium, which is used... Figure 9The hydrogen annealing process described in method 900 grows on the surface of barrier layer 230. For simplicity, ruthenium is used as an example grain growth metal material in method 900, but this is not intended to be limiting. In block 902, a ruthenium siding metal layer is deposited on a substrate in a deposition chamber. The deposition chamber may include a physical vapor deposition chamber, a chemical vapor deposition chamber, or an atomic layer deposition chamber, etc. In some embodiments, the thickness of the ruthenium siding metal layer can be from approximately To date In some implementations, the thickness of the ruthenium site metal layer can be approximately

[0043] In box 904, after the deposition process, the substrate is transferred to an annealing chamber, such as, for example, a rapid thermal processing (RTP) chamber. In box 906, the substrate is then annealed at a temperature of approximately 550°C to approximately 650°C. In box 908, during the annealing process, the substrate is immersed in a hydrogen-based environment for approximately 3 minutes to approximately 6 minutes. The hydrogen-based environment is provided by hydrogen gas and / or hydrogen radicals. The hydrogen annealing process of method 900 promotes primarily horizontal grain growth of the ruthenium siding metal layer with slower kinetics, resulting in lower resistivity and a smoother top surface of the ruthenium siding metal layer. Because of the slower kinetics of the hydrogen annealing process, a longer annealing time is used. The hydrogen annealing process of method 900 further improves the surface roughness of the ruthenium siding metal layer from an RMS of 1.7 nm (see above, RMS improvement using a barrier metal layer annealing process) to an RMS of 1.15 nm or less. In some implementations, the ruthenium site metal layer is annealed at 550°C for about 4 minutes to produce a surface roughness RMS of about 1.1 nm and about 5.55 ohms / cm. 2 Thin film resistivity (R) s In some embodiments, the ruthenium site metal layer is annealed at 600°C for about 5 minutes to produce a surface roughness RMS of about 1.15 nm and a surface roughness of about 5.5 ohms / cm. 2 R s A longer soaking time helps reduce Rs while maintaining surface smoothness. The inventors have found that reducing the soaking time may reduce surface roughness, but at the cost of increasing Rs. Similarly, increasing the soaking time may increase Rs, but at the cost of increasing surface roughness. A balance is chosen to produce an acceptable Rs value at an acceptable surface roughness RMS value.

[0044] Compared to typical nitrogen or argon annealing processes, hydrogen annealing offers a 20% to 30% improvement in top surface smoothness while maintaining the resistivity (Rresistivity) of nitrogen or argon annealing. sThe high-energy annealing process achieves better grain growth while maintaining low resistivity, and the hydrogen environment provides a smoother top surface. Longer immersion durations (compared to nitrogen or argon annealing) allow for slower grain growth, thus maintaining low resistivity and a smoother top surface. Longer durations (e.g., 7 minutes or longer) at temperatures above 700°C will reduce R0. s The value is increased, but at the cost of increased surface roughness (e.g., RMS of 1.4 nm). Different levels of RMS can be obtained by changing the three main parameters of the annealing process—duration, temperature, and ambient gas. s and surface smoothness.

[0045] In operation 410, a capping layer 250 may optionally be formed on the bit line metal layer 240 at a temperature of about 350°C to about 400°C. The low process temperature helps maintain the thermal budget of the film stack 205 and reduces the surface roughness of the bit line metal layer. The inventors have found that if the temperature is too low, the density of the capping layer 250 is insufficient, and if the temperature is too high, the surface roughness of the bit line metal layer increases. The temperature also depends on the bit line metal layer material and is adjusted accordingly. In operation 412, as described above, a hard mask 260 is formed on the capping layer 250 (when present) at a temperature of about 650°C. If the capping layer is not present, the hard mask 260 may be formed at a temperature below 400°C to maintain the thermal budget of the film stack 205. The lower temperature used to form the hard mask 260 when the capping layer 250 is not present is due to the increased deposition time (e.g., the hard mask may be approximately 400°C). The trade-off between thicker hard masks and lower hard mask density (260).

[0046] The methods described in this article, which are executed in individual processing chambers, can also be executed in cluster tools, for example, as described below. Figure 6 The described cluster tool 600, or integrated tool, offers the advantage of eliminating vacuum interruptions and eliminating substantial process lag between deposition and processing. Examples of the cluster tool 600 include those available from Applied Materials, Inc., Santa Clara, California. Integrated tooling. However, the methods described herein can be implemented using other clustering tools with suitable processing chambers or in other suitable processing chambers. For example, in some embodiments, the methods of the invention discussed above can advantageously be performed in clustering tools, thereby eliminating vacuum disruption between processes. For example, eliminating vacuum disruption can limit or prevent substrate contamination (oxidation) between processes.

[0047] Figure 6 This is a schematic diagram of a cluster tool 600 configured for substrate fabrication (e.g., post-poly plug fabrication). The cluster tool 600 includes one or more vacuum transfer modules (VTMs). Figure 6The diagram shows VTMs 601 and 602, a front-end module 604, multiple processing chambers / modules 606, 608, 610, 612, 614, 616, and 618, and a process controller (controller 620). In embodiments with more than one VTM, for example... Figure 6 As shown, one or more pass-through chambers can be provided to facilitate vacuum transfer from one VTM to another. In conjunction with... Figure 6 In the consistent implementation shown, two passage chambers may be provided (e.g., passage chamber 640 and passage chamber 642). The front-end module 604 includes a loading port 622 configured to receive one or more substrates, for example, from a FOUP (Front-Opening Standard Container) or other suitable substrate cassette or carrier, which will be processed using the clustering tool 600. The loading port 622 may include three loading areas 624a-624c, which can be used to load one or more substrates. However, more or fewer loading areas may be used.

[0048] The front-end module 604 includes an atmospheric transfer module (ATM) 626 for transferring substrates loaded into loading ports 622. More specifically, the ATM 626 includes one or more robotic arms 628 (shown in dashed lines) configured to transfer substrates from loading areas 624a-624c to the ATM 626 via doors 635 (shown in dashed lines) connecting the ATM 626 to the loading ports 622. Each loading port typically has one door (624a-624c) to allow substrates to be transferred from the respective loading port to the ATM 626. The robotic arms 628 are also configured to transfer substrates from the ATM 626 to the airlocks 630a, 630b via doors 632 (shown in dashed lines, each for each airlock) connecting the ATM 626 to the airlocks 630a, 630b. The number of airlocks may be more or less than two, but for illustrative purposes only, two airlocks (630a and 630b) are shown, each with a door to connect the airlock to the ATM 626.

[0049] Under the control of controller 620, airlocks 630a and 630b can be maintained in an atmospheric pressure environment or a vacuum pressure environment and serve as intermediate or temporary holding spaces for substrates being transferred to or from VTMs 601 and 602. VTM 601 includes a robotic arm 638 (shown in dashed lines) configured to transfer substrates from airlocks 630a and 630b to one or more of the plurality of processing chambers 606 and 608, or to one or more of the passage chambers 640 and 642, without disrupting the vacuum, i.e., while maintaining the vacuum pressure environment within VTM 602 and the plurality of processing chambers 606 and 608 and passage chambers 640 and 642. VTM 602 includes a robotic arm 638 (shown in dashed lines) configured to transfer a substrate from airlocks 630a, 630b to one or more of the plurality of processing chambers 606, 608, 610, 612, 614, 616, and 618 without disrupting the vacuum, i.e., while maintaining the vacuum pressure environment within VTM 602 and the plurality of processing chambers 606, 608, 610, 612, 614, 616, and 618. In some embodiments, airlocks 630a, 630b may be omitted, and controller 620 may be configured to move the substrate directly from ATM 626 to VTM 602.

[0050] Door 634, such as a slit valve, connects each corresponding gas lock 630a, 630b to VTM 601. Similarly, door 636, such as a slit valve, connects each processing module to the VTM to which the corresponding processing module is coupled (e.g., VTM 601 or VTM 602). Multiple processing chambers 606, 608, 610, 612, 614, 616, and 618 are configured to perform one or more processes typically associated with the fabrication of polysilicon post-insertion substrates as described herein.

[0051] Controller 620 controls the overall operation of cluster tool 600 and includes memory 621 to store data or commands / instructions related to the operation of cluster tool 600. For example, controller 620 controls robotic arms 628, 638, and 639 of ATM 626, VTM 601, and VTM 602 respectively for transferring substrates in and out of VTM 601 and between VTM 601 and VTM 602. Controller 620 controls the opening and closing of doors 632, 634, and 636, and controls the pressure of airlocks 630a and 630b, for example, maintaining the atmospheric / vacuum pressure environment within airlocks 630a and 630b as required by the substrate transfer process. Controller 620 also controls the operation of individual processing chambers 606, 608, 610, 612, 614, 616, and 618 to perform associated operations, as described in more detail below.

[0052] Figure 7 This is a method of manufacturing DRAM bit-line stacking processes and polysilicon plugs using cluster tool 600. For illustrative purposes, Figure 8 A cross-sectional view is shown of a portion of a substrate 800, including a polysilicon plug 802, after the polysilicon plug 802 has been formed on the substrate 800 outside the clustering tool 600. During execution Figure 7 Prior to this method, substrate 800 can be loaded into loading port 622 via one or more of loading areas 624a-624c. Under the control of controller 620, robotic arm 628 of ATM 626 can transfer substrate 800 with polysilicon plug 802 from loading area 624a to ATM 626.

[0053] Controller 620 can determine whether at least one of airlocks 630a and 630b is in an atmospheric pressure environment, depending on whether one or both of airlocks 630a and 630b are being used. For illustrative purposes, it is assumed that only airlock 630a is being used. If controller 620 determines that airlock 630a is in an atmospheric pressure environment, controller 620 can open the door (part of 632) connecting ATM 626 to airlock 630a. Conversely, if controller 620 determines that airlock 630a is not in an atmospheric pressure environment, controller 620 can adjust the pressure within airlock 630a to an atmospheric pressure environment (e.g., via a pressure control valve operably connected to airlocks 630a and 630b and controlled by controller 620), and can recheck the pressure within airlock 630a. The controller can instruct the robotic arm 628 to transfer the substrate 800 from the ATM 626 to the airlock 630a, close the door 632, and adjust the pressure inside the airlock 630a to a vacuum pressure environment, such as matching or substantially matching the vacuum pressure environment inside the VTM 601.

[0054] Controller 620 can determine whether airlock 630a is in a vacuum pressure environment. If controller 620 determines that airlock 630a is in a vacuum pressure environment, controller 620 can open door 634 connecting VTM 601 to airlock 630a. Conversely, if controller 620 determines that airlock 630a is not in a vacuum pressure environment, controller 620 can adjust the pressure inside airlock 630a to a vacuum pressure environment (e.g., via a pressure control valve operably connected to airlocks 630a and 630b and controlled by controller 620) and recheck the pressure inside airlock 630a.

[0055] Controller 620 controls the operation of cluster tool 600 using direct control of the processing chambers or alternatively by controlling a computer (or controller) associated with the processing chambers and cluster tool 600. In operation, controller 620 enables the collection of data and feedback from the various chambers and systems to optimize the performance of cluster tool 600. Controller 620 typically includes a central processing unit (CPU) 619, memory 621, and support circuitry 625. CPU 619 can be any form of general-purpose computer processor suitable for industrial environments. Support circuitry 625 is conventionally coupled to CPU 619 and may include cache, clock circuitry, input / output subsystems, power supply, etc. Software routines, such as those described above, can be stored in memory 621 and, when executed by CPU 619, transform CPU 619 into a dedicated computer (controller 620). Software routines can also be stored and / or executed by a second controller (not shown) located remotely from cluster tool 600.

[0056] Memory 621 is in the form of a computer-readable storage medium containing instructions that, when executed by CPU 619, facilitate the operation of semiconductor processes and devices. The instructions in memory 621 are in the form of a program product, such as a program implementing the methods of this principle. The program code may conform to any of a variety of different programming languages. In one example, this disclosure may be implemented as a program product stored on a computer-readable storage medium for use by a computer system. The program product defines the functionality of aspects (including the methods described herein). Exemplary computer-readable storage media include, but are not limited to: non-writable storage media on which information is permanently stored (e.g., read-only memory devices within a computer, such as CD-ROM discs readable by a CD-ROM drive, flash memory, ROM chips, or any type of solid-state non-volatile semiconductor memory); and writable storage media on which information can be changed (e.g., floppy disks in a floppy disk drive or hard disk drive, or any type of solid-state random access semiconductor memory). Such computer-readable storage media are aspects of this principle when carrying computer-readable instructions that direct the functionality of the methods described herein.

[0057] At 700, controller 620 instructs robotic arm 638 to transfer substrate 800 from pneumatic lock 630a through door 634 to VTM 601 and close door 634. Alternatively, door 634 may remain open, for example, to receive the outgoing substrate after processing is completed within cluster tool 600. At 702, controller 620 instructs robotic arm 638 to transfer substrate 800 to one or more processing chambers, thereby enabling substrate fabrication—that is, completing bit line stacking on top of polysilicon plugs 802 on substrate 800. For example, at 702, controller 620 may instruct robotic arm 638 to open door 636 corresponding to processing chamber 606. Once opened, controller 620 can instruct robotic arm 638 to transfer substrate 800 (without disrupting the vacuum, i.e., maintaining a vacuum pressure environment within VTM 601 and VTM 602 while transferring substrate 800 between processing chambers 606, 608, 610, 612, and 614) to a pre-cleaning chamber (e.g., processing chamber 606). Processing chamber 606 can be used to perform one or more pre-cleaning processes to remove contaminants that may be present on substrate 800, such as native oxides that may be present on substrate 800. One such pre-cleaning chamber is SiCoNi, commercially available from Applied Materials, Inc., Santa Clara, California. TM Processing tools.

[0058] Next, at 704, controller 620 opens door 636 and instructs robotic arm 638 to transfer substrate 800 to the next processing chamber. For example, at 704, controller 620 may instruct robotic arm 638 to transfer substrate 800 from a pre-cleaning chamber to a barrier metal deposition chamber without breaking the vacuum. For example, controller 620 may instruct robotic arm 638 to transfer substrate from processing chamber 606 to, for example, processing chamber 608 under vacuum. Processing chamber 608 is configured to perform a barrier metal deposition process on substrate 800 (e.g., depositing barrier metal 804 on top of the cleaned substrate 800 and polysilicon plug 802). The barrier metal may be one of titanium (Ti) or tantalum (Ta).

[0059] Next, at 706, controller 620 can instruct robotic arm 638 to transfer substrate 800 from the barrier metal deposition chamber to the barrier layer deposition chamber or annealing chamber without breaking the vacuum. If substrate 800 is transferred to the annealing chamber, it will be brought back to the barrier metal deposition chamber for anti-oxidation deposition (e.g., a nitride variant of the barrier metal). After the barrier metal deposition chamber, substrate 800 is transferred to the barrier layer deposition chamber. For example, controller 620 can instruct robotic arm 638 to transfer the substrate from processing chamber 608 to any of chambers 640, 642 under vacuum, at which point robotic arm 639 inside VTM 602 can pick up substrate 800 and move it to, for example, processing chamber 610. Processing chamber 610 is configured to perform a barrier layer deposition process on substrate 800 (e.g., to deposit barrier layer 806 on top of barrier metal 804). The barrier layer can be one of titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN).

[0060] Next, at 708, controller 620 may instruct robotic arm 639 to transfer substrate 800 from processing chamber 610 to, for example, processing chamber 612 without breaking the vacuum. Processing chamber 612 is configured to perform a bit line metal deposition process on substrate 800 (e.g., depositing a bit line metal layer 808 on top of the barrier layer 806 deposited at 706). The bit line metal may be one of tungsten (W), molybdenum (Mo), ruthenium (Ru), iridium (Ir), or rhodium (Rh). Next, at 710, controller 620 may instruct robotic arm 639 to transfer substrate 800 from processing chamber 612 to, for example, processing chamber 614 without breaking the vacuum. Processing chamber 614 is configured to perform a hard mask deposition process on substrate 800 (e.g., depositing a hard mask layer 810 on top of the bit line metal layer 808 deposited at 708). The hard mask can be one of silicon nitride (SiN), silicon oxide (SiO) or silicon carbide (SiC).

[0061] In some embodiments, an annealing process may be performed on the substrate 800 before or after the deposition of the barrier layer 806, as shown at 705. The annealing process can be any suitable annealing process, such as rapid thermal processing (RTP) annealing. For example, the substrate 800 may be transferred to a processing chamber 616 before being transferred from processing chamber 608 to processing chamber 610. Processing chamber 616 is configured to perform the annealing process on the substrate 800. After the annealing process, the annealed substrate 800, including the barrier layer 806, may be transferred under vacuum from the annealing chamber (e.g., processing chamber 616) to the barrier layer deposition chamber (e.g., processing chamber 610), for example using a robotic arm 639.

[0062] Alternatively or in combination, an annealing process can be performed on the substrate 800 after the deposition of the bit line metal layer 808 and before the deposition of the hard mask layer 810 on top of the bit line metal layer 808, as shown in 709a. For example, the substrate 800 can first be transferred to the processing chamber 616 (i.e., the annealing chamber) before being transferred from the processing chamber 612 to the processing chamber 614. The annealing process can be performed on the substrate 800 on which the bit line metal layer 808 is deposited, or another annealing process can be performed if annealing at 705 has already been performed, as described above. In some embodiments where the annealing process is performed in 709a, the annealed substrate 800 can be transferred to another processing chamber to deposit an optional capping layer 809 on the bit line metal layer 808, as shown in 709b. For example, a robotic arm 639 may be used to transfer an annealed substrate 800, including a bit line metal layer 808, from an annealing chamber (e.g., a processing chamber 616) to a capping deposition chamber (e.g., a processing chamber 618) under vacuum to deposit a capping layer on top of the annealed bit line metal layer 808.

[0063] In some embodiments, after depositing the bitline metal, some metal, such as ruthenium (Ru), is used as the grain growth material. The inventors have observed that subsequently depositing a hard mask layer on top of this bitline metal at high temperatures undesirably results in poor surface roughness. The inventors have discovered that hydrogen annealing of the bitline metal layer before depositing the hard mask layer (after depositing the low-temperature capping layer) can advantageously improve the surface roughness of the bitline metal layer. Furthermore, by performing each of the above sequences in an integrated tool (e.g., cluster tool 600), oxidation of the bitline metal during annealing for grain growth is further advantageously avoided.

[0064] Additional processes not described here may also be performed on substrate 800, or some of the processes described here may be omitted.

[0065] After the aforementioned processes associated with processing chambers 608, 610, 612, and 614 (and processing chambers 616 and 618, if used) have been performed on substrate 800, substrate 800 is transferred from VTM 602 back to loading port 622, for example, by using robotic arm 639 in VTM 602 to transfer substrate 800 to passage chambers 640 and 642, and by using robotic arm 638 in VTM 601 to transfer substrate 800 from passage chambers 640 and 642 to one of airlocks 630a and 630b. Robotic arm 628 can then be used to return substrate 800 to an empty slot in the FOUP in loading port 622.

[0066] The clustering tool 600 and its usage described herein advantageously allow users to perform multiple DRAM bit line processes on a polysilicon plug using a single machine configured to maintain a vacuum pressure environment throughout the DRAM bit line process. Therefore, even if oxidation does not occur on the substrate 800 during substrate fabrication, the likelihood of oxidation is reduced. Furthermore, because a vacuum pressure environment is maintained throughout the DRAM bit line process, the selection of bit line metal materials is not limited by the grain growth characteristics of the metal.

[0067] In the context of describing the materials and methods discussed herein (particularly in the context of the appended claims), the terms “a” and “described”, and similar references, are to be interpreted as covering both the singular and plural, unless otherwise stated herein or clearly contradicted by the context. Unless otherwise stated herein, references to numerical ranges are intended only as a shorthand method for individually referring to each individual value falling within that range, and each individual value is incorporated into the specification as if it were individually referenced herein. Unless otherwise stated herein or clearly contradicted by the context, all methods described herein may be performed in any suitable order. Unless otherwise stated, the use of any and all example or exemplary language (e.g., “such as”) provided herein is intended only to better illustrate the materials and methods and does not constitute a limitation on the scope. No language in the specification should be construed as indicating that any unclaimed element is essential for the practice of the disclosed materials and methods.

[0068] Throughout this specification, references to "one embodiment," "some embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Therefore, phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in an embodiment" appearing in various places throughout the specification do not necessarily refer to the same embodiment of this disclosure. Furthermore, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0069] Although the disclosure herein has been described with reference to specific embodiments, these embodiments are merely illustrative of the principles and applications of the disclosure. Those skilled in the art will understand that various modifications and variations can be made to the methods and apparatus of this disclosure without departing from the spirit and scope of the disclosure. Therefore, this disclosure includes modifications and variations within the scope of the appended claims and their equivalents.

[0070] Implementations based on this principle can be carried out in hardware, firmware, software, or any combination thereof. Implementations can also be implemented as instructions stored using one or more computer-readable media, which can be read and executed by one or more processors. Computer-readable media can include any means for storing or transmitting information in a machine-readable form (e.g., a computing platform or a “virtual machine” running on one or more computing platforms). For example, computer-readable media can include any suitable form of volatile or non-volatile memory. In some implementations, computer-readable media can include non-transitory computer-readable media.

[0071] While the foregoing describes an implementation of this principle, other and further implementations of this principle can be designed without departing from its basic scope.

Claims

1. A method for smoothing the top surface of bit line metal in a memory structure, comprising: A titanium layer of 30 Å to 50 Å is deposited on a polycrystalline silicon layer on a substrate; A first titanium nitride layer of 15 Å to 40 Å is deposited on the titanium layer; The substrate is annealed at a temperature of 700°C to 850°C; After annealing, a second titanium nitride layer of 15 Å to 40 Å is deposited on the first titanium nitride layer; A ruthenium site metal layer is deposited on the second titanium nitride layer; The bit line metal layer is annealed at a temperature of 550°C to 650°C; and During annealing, the bit line metal layer is immersed in a hydrogen-based environment for 3 to 6 minutes.

2. The method according to claim 1, further comprising: A capping layer is deposited on the bitline metal layer at a deposition temperature of 350°C to 400°C; and A hard mask layer is deposited on the cap layer at a deposition temperature above 500°C.

3. The method of claim 2, wherein the capping layer comprises one or more of silicon nitride or silicon carbonitride.

4. The method of claim 2, wherein the capping layer is 30 Å to 50 Å.

5. The method of claim 2, wherein the capping layer is deposited by a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process.

6. The method of claim 2, wherein the hard mask layer comprises silicon nitride.

7. The method of claim 2, wherein the hard mask layer is deposited using a low-pressure chemical vapor deposition (LPCVD) process.

8. The method of claim 1, further comprising: A hard mask layer is deposited on the bit line metal layer at a deposition temperature below 400°C.

9. The method of claim 8, wherein the hard mask layer is deposited using a low-pressure chemical vapor deposition (LPCVD) process.

10. The method of claim 1, wherein the bit line metal layer has a top surface with a root mean square roughness (RMS) of 1.15 nm or less.

11. A method for forming a memory structure, comprising: A barrier metal layer is formed on the polysilicon layer on the substrate; The barrier metal layer is annealed at a temperature of 700°C to 850°C; A barrier layer is formed on the barrier metal layer; A ruthenium site metal layer is deposited on the barrier layer; The bit line metal layer is annealed at a temperature of 550°C to 650°C; and During annealing, the bit line metal layer is immersed in a hydrogen-based environment for 3 to 6 minutes.

12. The method of claim 11, wherein the barrier metal layer is a 30 Å to 50 Å titanium layer formed on the polycrystalline silicon layer and a 15 Å to 40 Å titanium nitride layer formed on the titanium layer.

13. The method of claim 12, wherein the barrier metal layer is annealed to form a titanium silicide layer on the polycrystalline silicon layer.

14. The method of claim 11, wherein the barrier layer is a titanium nitride layer of 15 Å to 40 Å.

15. The method of claim 11, wherein the bit line metal layer is a grain-grown metal layer having a top surface with a roughness root mean square (RMS) of 1.15 nm or less.

16. The method of claim 11, further comprising: A capping layer is formed on the bit line metal layer using chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes at a deposition temperature of 350°C to 400°C. and A hard mask layer is formed on the capping layer using a low-pressure chemical vapor deposition (LPCVD) process at a deposition temperature above 500°C.

17. The method of claim 16, wherein the capping layer is 30 Å to 50 Å.

18. The method of claim 11, further comprising: A hard mask layer is deposited on the bit line metal layer using a low-pressure chemical vapor deposition (LPCVD) process at a deposition temperature below 400°C.

19. A method for smoothing the top surface of bit line metal in a memory structure, comprising: A titanium layer of 30 Å to 50 Å was deposited on a polycrystalline silicon layer on a substrate using a plasma vapor deposition (PVD) chamber. The substrate is annealed at a temperature of 700°C to 850°C, without breaking the vacuum between the deposition of the titanium layer and the annealing of the substrate. After annealing, a titanium nitride layer of 15 Å to 40 Å is deposited on the titanium layer; A ruthenium site metal layer is deposited on the titanium nitride layer; The bit line metal layer is annealed at a temperature of 550°C to 650°C; and During annealing, the bit line metal layer is immersed in a hydrogen-based environment for 3 to 6 minutes, so that the top surface of the bit line metal has a roughness root mean square (RMS) of 1.15 nm or less.

20. The method of claim 19, further comprising: A capping layer is deposited on the bitline metal layer at a deposition temperature of 350°C to 400°C, and a hard mask layer is deposited on the capping layer at a deposition temperature above 500°C; or A hard mask layer is deposited on the bit line metal layer at a deposition temperature below 400°C.

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