Semiconductor integrated circuit component
By designing buried semiconductor and gate regions in integrated circuits and using bias voltage to control the function of the active region, the problem of easy reverse engineering analysis of integrated circuits is solved, achieving both security and versatility.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- STMICROELECTRONICS (CROLLES 2) SAS
- Filing Date
- 2021-10-22
- Publication Date
- 2026-07-14
AI Technical Summary
Existing integrated circuits are easily reverse engineered, resulting in insufficient security and necessitating the provision of semiconductor components that are difficult to analyze and operate in complex ways.
Design an integrated circuit that includes a buried semiconductor region and a gate region, controls the function of the active region by different bias voltages, the buried structure makes the component difficult to detect from the front, and the use of wells makes doping adjustment easier, and the control of the depletion region enables multifunctional operation.
It improves the security of integrated circuits, makes them difficult to reverse engineer, and makes the manufacturing process easier. It can also implement a variety of functions such as NAND gates, NOR gates, and variable resistors.
Smart Images
Figure CN114496957B_ABST
Abstract
Description
[0001] Priority Statement
[0002] This application claims the preferred right of French patent application No. 2010911, filed on October 23, 2020, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field
[0003] The embodiments and implementations relate to integrated circuits, and more specifically to semiconductor components for such integrated circuits. Background Technology
[0004] Integrated circuits typically consist of many semiconductor components. These semiconductor components are configured to perform functions specific to them.
[0005] There are methods that allow for the reverse engineering analysis of integrated circuits, for example, by specifically analyzing their semiconductor components.
[0006] Specifically, some semiconductor components are visible on the surface of an integrated circuit, making them easy to analyze.
[0007] To facilitate unauthorized copying of integrated circuits, third-party analysis of the integrated circuit can be performed. This analysis can also be performed to understand the operation of the integrated circuit. Once the operation of the integrated circuit is understood, it may be possible to identify potential security vulnerabilities.
[0008] Therefore, integrated circuits that can be easily analyzed are not secure enough.
[0009] To improve the security of integrated circuits, it is preferable to provide semiconductor components whose structure makes it more complex to analyze integrated circuits through reverse engineering.
[0010] Therefore, there is a need to provide semiconductor components that have structures that are difficult to analyze and / or detect or that have complex operations.
[0011] There is also a need to provide a semiconductor component that is easy to manufacture. Summary of the Invention
[0012] According to one aspect, an integrated circuit includes: a semiconductor substrate and a semiconductor component, comprising: a buried semiconductor region disposed in the semiconductor substrate and having a first conductivity type; a first gate region and a second gate region configured to be spaced apart from each other and each extending from the front side of the semiconductor substrate into the buried semiconductor region; a third gate region extending from the front side of the semiconductor substrate into the semiconductor substrate in depth and configured to be electrically connected to the buried semiconductor region; and an active region of the semiconductor substrate defined by the first gate region, the second gate region and the buried semiconductor region, the active region having a second conductivity type opposite to the first conductivity type.
[0013] This semiconductor device is configured to have different functions depending on different bias voltages applied to its third gate region, but also to its first and second gate regions. These different functions will be described in detail below.
[0014] Specifically, the voltage applied to the first gate region, the second gate region, and the third gate region can affect the conductivity type state of the active region.
[0015] Therefore, this semiconductor device has a buried gate region and an active region that is also buried. Because the gate region and the active region are buried, the semiconductor device is difficult to detect from the front side of the semiconductor substrate.
[0016] Furthermore, because semiconductor components are configured to perform multiple functions depending on the voltage applied to their gate region, the behavior of semiconductor components is difficult to analyze through reverse engineering.
[0017] Preferably, the semiconductor substrate comprises a well of a second conductivity type. A buried semiconductor region is then positioned within the well, and an active region is included within the well.
[0018] The use of this trap makes it easier to adjust the doping in the active region during the manufacturing of semiconductor components.
[0019] Alternatively, a semiconductor substrate already having the desired doping for the active region may be provided. However, the use of a well makes it more difficult for a third party to measure the doping concentration of the active region, and thus makes it more difficult for a third party to reproduce the integrated circuit. Furthermore, the use of a well allows the proposed electronic component to be isolated from other components of the integrated circuit.
[0020] Advantageously, the semiconductor component also includes an input and an output positioned between and spaced apart from a first gate region and a second gate region, and the active region includes: a channel configured to be formed between the input and the output; and a depletion region surrounding the channel.
[0021] The depletion region is also designated by those skilled in the art as a “depletion region,” “space charge region,” or “waste region,” and corresponds to a region without free carriers that appears in a MOS (metal-oxide-semiconductor) structure or PN junction between an N-doped region and a P-doped region.
[0022] The voltages applied to the first gate region, the second gate region, and the third gate region allow the depletion region to be acted upon so that the channel can be turned off or on.
[0023] Therefore, the voltage (depending on whether it is applied) or current (depending on whether it is applied) at the output of the semiconductor component depends on the voltage applied to the three bias gates.
[0024] Preferably, the integrated circuit is configured to apply a rated voltage or zero voltage to the first gate region and the second gate region.
[0025] Furthermore, preferably, the integrated circuit is configured to apply a predefined voltage to the input of the semiconductor component. When using the semiconductor component, it is advantageous to continuously apply this voltage to the input of the semiconductor component. It can typically be about 1.2 volts.
[0026] When the channel is closed, the voltage at the output is lower than the voltage at the input.
[0027] In an advantageous embodiment, the first gate region and the second gate region each have a distal end, the distal end including a gate oxide layer that contacts the semiconductor substrate and the buried semiconductor region.
[0028] Furthermore, advantageously, the third gate region has a distal end comprising a gate oxide layer that contacts the buried semiconductor region, and the third gate region has the same conductivity type as the buried semiconductor region. Therefore, the third gate region is configured to be electrically connected to the buried semiconductor region.
[0029] In an advantageous embodiment, the integrated circuit includes at least one shallow isolation trench formed in a semiconductor substrate above a buried semiconductor region, and a first gate region and a second gate region extending in depth into the substrate through the shallow isolation trench to reach the buried semiconductor region.
[0030] The gate oxide layers of the first and second gate regions are then positioned under shallow isolation trenches.
[0031] In an advantageous embodiment, the buried semiconductor region includes: an isolation semiconductor layer extending through the semiconductor substrate parallel to the front side of the semiconductor substrate, a third gate region connected to the isolation semiconductor layer; and two regions having a first conductivity type and protruding from the isolation semiconductor layer, the isolation semiconductor layer connecting the two regions, the first gate region extending in depth to one of the two regions, and the second gate region extending in depth to the other of the two regions.
[0032] The active region is then defined by these two regions, the isolation semiconductor layer between the two regions, and the first gate region and the second gate region.
[0033] The oxide layers of the first gate region and the second gate region can then contact the region connected to the gate region.
[0034] Specifically, preferably, the third gate region then has a distal end that contacts the isolation semiconductor layer.
[0035] Therefore, this integrated circuit allows the use of an isolation semiconductor layer, enabling the third gate region to be electrically connected to both regions. Thus, this integrated circuit facilitates the electrical connection between the third gate region and the two regions.
[0036] Alternatively, the buried semiconductor region includes two bonded regions having a first conductivity type, a first gate region extending in depth to one of the two regions, a second gate region extending in depth to the other of the two regions, and a third gate region connected to both regions.
[0037] The active region is then defined by these two regions, and by the first gate region and the second gate region.
[0038] The oxide layers of the first gate region and the second gate region can then contact the region connected to the gate region.
[0039] Specifically, preferably, the third gate region then has a distal end that contacts both regions.
[0040] This integrated circuit has the advantage of eliminating the need for an isolation semiconductor layer, allowing the third gate region to be connected to both regions. This embodiment also allows for significant gains in surface area between libraries of basic logic gate cells (“standard cells”) and ease of integration of the proposed electronic components. In fact, the production of deep isolation semiconductor layers requires silicon implantation with high-energy dopants, thus necessitating the use of thick photoresist to protect the non-implanted areas. To achieve depth of field in industrial photography, this requires wide openings in the resin, thus necessitating the presence of an isolation semiconductor layer on a large surface area of the silicon wafer.
[0041] Semiconductor components can be configured to perform several functions.
[0042] Specifically, advantageously, the semiconductor components are configured such that the depletion region around the channel is only combined when the first gate region and the second gate region are powered at a rated voltage and the third gate region is powered at a first bias voltage.
[0043] Therefore, by applying a first bias voltage to the third gate region, the channel will only close when a rated voltage is applied to the first and second gate regions; otherwise, the channel will open. Thus, the output voltage of the semiconductor device is low only when a rated voltage is applied to the first and second gate regions.
[0044] Therefore, when the first bias voltage is applied to the third gate region, the semiconductor device functions as a NAND gate, taking the voltage applied to the first gate region and the second gate region as input.
[0045] The first bias voltage is, for example, equal to 1.2V.
[0046] In an advantageous embodiment, the semiconductor components are configured such that the depletion region around the channel is isolated only when the first gate region and the second gate region are not powered and the third gate region is powered with a second bias voltage.
[0047] Therefore, by applying a second bias voltage to the third gate region, the channel will only open when zero voltage is applied to the first and second gate regions; otherwise, the channel will close. Thus, the output voltage of the semiconductor device is high only when zero voltage is applied to the first and second gate regions.
[0048] Therefore, when the second bias voltage is applied to the third gate region, the semiconductor device functions as a NOR gate, taking the voltage applied to the first gate region and the second gate region as input.
[0049] Advantageously, the second bias voltage is larger than the first bias voltage. For example, the second bias voltage is equal to 1.8V.
[0050] In an advantageous embodiment, the semiconductor components are configured such that the depletion region is always isolated when the third gate region is powered by a third bias voltage.
[0051] Therefore, the channel will be opened by applying a third bias voltage to the third gate region, regardless of the voltage applied to the first gate region and the second gate region.
[0052] Therefore, when the third bias voltage is applied to the third gate region, the channel of the semiconductor component acts as a resistor between the input and the output.
[0053] Furthermore, depending on the voltage applied to the first and second gate regions that can act as depletion regions, the channel may not be fully open. Therefore, the semiconductor component can be used as a variable resistor.
[0054] For example, specifically, the resistance of the channel can be set between 500 ohms and 1 megohm.
[0055] Advantageously, the third bias voltage is lower than the first bias voltage.
[0056] The behavior of the active region can be adapted by adjusting, for example, its doping and the size of its cross-section, specifically defined by the distance between the first gate region and the second gate region and the distance between the shallow isolation trench and the buried semiconductor region.
[0057] Specifically, in an advantageous embodiment, the active region, specifically the channel, has been included in 10 15 at / cm 3 Up to 10 19 at / cm 3 Doping between, for example, about 10 17 at / cm 3 Specifically, this doping allows for the promotion of depletion in the active region.
[0058] Preferably, the first gate region and the second gate region are spaced apart by a certain distance, which is between 50 nm and 1 μm, for example, about 150 nm.
[0059] In an advantageous embodiment, the buried semiconductor region is spaced apart from the far end of the shallow isolation trench by a distance ranging from 50 nm to 800 nm, for example, about 200 nm.
[0060] In an advantageous embodiment, the integrated circuit includes a second semiconductor component, comprising: a buried semiconductor region disposed in a semiconductor substrate and having a first conductivity type; a first gate region and a second gate region configured to be spaced apart from each other and each extending in depth from the front side of the semiconductor substrate into the substrate to reach the buried semiconductor region; a third gate region extending in depth from the front side of the semiconductor substrate into the semiconductor substrate and configured to be electrically connected to the buried semiconductor region; an active region of the semiconductor substrate defined by the first gate region, the second gate region and the buried semiconductor region, the active region having a second conductivity type opposite to the first conductivity type; and an isolation region having a first conductivity type extending into the active region between the first gate region and the second gate region.
[0061] Therefore, the second semiconductor component differs from the first semiconductor component in that it includes an isolation region across the active region between the first gate region and the second gate region.
[0062] This isolation region helps prevent current from flowing between the input and output of the semiconductor component. Therefore, this isolation region electrically disconnects the input and output of the semiconductor component.
[0063] Therefore, this second semiconductor component is not suitable for performing functions that can be performed by the first semiconductor component.
[0064] This type of semiconductor component can complicate the analysis of integrated circuits through reverse engineering. In fact, this second semiconductor component is difficult to distinguish from the first semiconductor component, but it cannot perform the same functions as the first semiconductor component.
[0065] According to another aspect, a method for manufacturing a semiconductor component in a semiconductor substrate is provided, the method comprising: forming a buried semiconductor region in the semiconductor substrate, the buried semiconductor region having a first conductivity type; forming a first gate region and a second gate region spaced apart such that they each extend in depth from the front side of the semiconductor substrate into the buried semiconductor region; forming an active region of the semiconductor substrate defined by the first gate region, the second gate region and the buried semiconductor region, and having a second conductivity type opposite to the first conductivity type; and forming a third gate region electrically connected to the buried semiconductor region. Attached Figure Description
[0066] Other advantages and features of the invention become apparent upon examination of the detailed description of the embodiments and examples (without any limitation) and the accompanying drawings, wherein:
[0067] Figures 1 to 3 The diagram illustrates an integrated circuit according to a first embodiment, including semiconductor components;
[0068] Figure 4 The diagram illustrates what can be used to obtain Figures 1 to 3 An embodiment of the method for manufacturing the semiconductor component shown;
[0069] Figure 5 and Figure 6 The illustration shows a semiconductor component according to another embodiment;
[0070] Figure 7 The diagram illustrates what can be used to obtain Figures 5 to 6 An embodiment of the method for manufacturing the semiconductor component shown;
[0071] Figure 8 The illustration shows a top view of a semiconductor component formed in a semiconductor substrate;
[0072] Figure 9 The diagram illustrates what can be used to obtain Figure 8 An embodiment of the method for manufacturing the semiconductor component shown; and
[0073] Figure 10 The diagram illustrates an integrated circuit, including at least one semiconductor component (such as...). Figures 1 to 3 or Figures 5 to 6 The semiconductor components shown) and at least one semiconductor component (such as Figure 8 (The semiconductor component shown). Detailed Implementation
[0074] Figures 1 to 3 An integrated circuit according to a first embodiment is illustrated, including a semiconductor component CS1. Figure 1 This is a top view of semiconductor component CS1. Figure 2 It is along Figure 1 The view of the semiconductor component CS1 in section AA shown. Figure 3 It is along Figure 1 The view of the semiconductor component CS1 in section BB shown.
[0075] Integrated circuits (CI) include semiconductor substrates (SUB).
[0076] The semiconductor substrate SUB has a front-side FA.
[0077] Semiconductor component CS1 includes a semiconductor region RSE buried in a semiconductor substrate SUB. The buried semiconductor region RSE has a first conductivity type, preferably N-type.
[0078] The semiconductor substrate SUB also includes a well CSN having a second conductivity type, such as P-type, in contrast to the first conductivity type. The well CSN extends in depth from the front surface FA of the substrate SUB into the substrate SUB.
[0079] Integrated circuits (ICs) also include shallow isolation trenches (TIPPs) (also known as the acronym for "shallow trench isolation"). The shallow isolation trench (TIPP) extends from the front side (FA) of the semiconductor substrate (SUB) into the semiconductor substrate to the far end. The depth of the shallow isolation trench (TIPP) into the semiconductor substrate (SUB) is less than that of the well (CSN). The well (CSN) thus surrounds the shallow isolation trench (TIPP).
[0080] Near the isolation layer TIPP, the well CSN preferably has doping, with the dopant being included in 10 15 at / cm 3 Up to 10 19 at / cm 3 Between, for example, about 10 17 at / cm 3 .
[0081] Shallow isolation trenches (TIPPs) can extend in depth into the semiconductor substrate (SUB) by a distance ranging from 200 nm to 500 nm, for example, approximately 350 nm.
[0082] Shallow isolation trenches (TIPPs) are formed from dielectric materials such as silicon dioxide.
[0083] Semiconductor component CS1 can be used to perform various functions as described below.
[0084] In this first embodiment, the buried semiconductor region RSE includes an isolation semiconductor layer CISO. Therefore, the isolation semiconductor layer CISO has a first conductivity type. The isolation semiconductor layer CISO extends parallel to the front surface FA of the semiconductor substrate SUB.
[0085] Specifically, the isolation semiconductor layer CISO extends directly below the well CSN. Therefore, the isolation semiconductor layer CISO is at least partially located below the shallow isolation trench TIPP.
[0086] For example, the isolation semiconductor layer CISO is positioned at a distance relative to the front FA of the semiconductor substrate SUB, the distance being between 500 nm and 2000 nm. Specifically, the semiconductor layer is spaced apart from the far end of the shallow isolation trench TIPP by a distance being between 50 nm and 800 nm, for example, approximately 200 nm.
[0087] Preferably, the isolation semiconductor layer CISO is doped, and the doping is included in 10 16 at / cm 3 Up to 10 19 at / cm 3 Between, for example, about 10 17 at / cm 3 .
[0088] Furthermore, the buried semiconductor region RSE includes two regions RE1 and RE2 that protrude from the isolation semiconductor layer CISO. These two regions RE1 and RE2 also have a first conductivity type.
[0089] These two areas, RE1 and RE2, were located beneath the shallow isolation trench TIPP.
[0090] Preferably, these two regions RE1 and RE2 are doped, and the meal is included in 10 17 at / cm 3 Up to 10 20 at / cm 3 Between, for example, approximately 3 × 10 18 at / cm 3 .
[0091] The semiconductor component CS1 also includes a first gate region PRG and a second gate region DRG.
[0092] The first gate region PRG extends in depth into the semiconductor substrate SUB through a shallow isolation trench TIPP to a distal PED located below the shallow isolation trench TIPP, which contacts the well CSN and region RE1.
[0093] The second gate region DRG extends in depth into the semiconductor substrate SUB through a shallow isolation trench TIPP to reach the distal DED located below the shallow isolation trench TIPP, which contacts the well CSN and region RE2.
[0094] Specifically, the first gate region PRG and the second gate region DRG extend a certain distance in depth, which is included between 300nm and 700nm, for example, about 500nm.
[0095] The first gate region PRG and the second gate region DRG have widths that are between 40 nm and 400 nm, for example, about 70 nm.
[0096] The first gate region PRG and the second gate region DRG extend parallel to each other in length within the semiconductor substrate SUB.
[0097] The first gate region PRG and the second gate region DRG are spaced apart by a distance between 50 nm and 1 μm, for example, about 150 nm.
[0098] The first gate region PRG and the second gate region DRG are formed of polysilicon.
[0099] The distal end PED of the first gate region PRG and the distal end DED of the second gate region DRG include gate oxide layers POG and DOG, which are respectively opposite to the well CSN and regions RE1 and RE2. These oxide layers POG and DOG may also extend on the sides of the first gate region PRG and the second gate region DRG.
[0100] The semiconductor component CS1 also includes a third gate region TRG having a first conductivity type, specifically N+. This third gate region TRG extends deep into the substrate, reaching its distal end TED in contact with an isolation semiconductor layer CISO of the same conductivity type.
[0101] Specifically, the third gate region TRG is formed in a region REC having a first conductivity type, which surrounds the first gate region PRG and the second gate region DRG.
[0102] Region REC is doped and is included in 1015 at / cm 3 Up to 10 19 at / cm 3 Between, for example, about 10 17 at / cm 3 .
[0103] The third gate region TRG is doped and included in 10 16 at / cm 3 Up to 10 20 at / cm 3 Between, for example, in the isolation semiconductor region far from the front-side FA, approximately 10 17 at / cm 3 However, the value near the surface of the frontal FA is approximately 5×10. 19 at / cm 3 .
[0104] In addition, the semiconductor component CS1 also includes a contact region ZPC located on the first gate region PRG, the second gate region DRG and the third gate region TRG and located on the input IN and the output OUT.
[0105] The semiconductor component then includes a region of the well CSN, referred to as the active region ZA, which is defined by the isolation semiconductor layer CISO, regions RE1, RE2, the first gate region PRG and the second gate region DRG, and the shallow isolation trench TIPP.
[0106] The active region ZA includes a channel CAN with a second conductivity type and a depletion region (not shown). The depletion region is located between the two regions RE1, RE2 and the channel CAN, and between the isolation semiconductor layer CISO and the channel CAN.
[0107] Specifically, the higher the voltage applied to the gate region, the more depletion regions there are in the active region, thereby reducing the cross-section of the channel.
[0108] More specifically, the integrated circuit is configured such that the first gate region and the second gate region can be powered at a rated voltage. Preferably, the rated voltage is approximately 1.1V.
[0109] Semiconductor component CS1 is configured to perform several functions by modifying the state of the active region ZA.
[0110] Semiconductor component CS1 is configured to make it possible to change the behavior of the channel CAN according to the voltage applied to the third gate region TRG.
[0111] Therefore, the semiconductor component CS1 is configured to perform several functions by modifying the behavior of the CAN channel.
[0112] Specifically, the voltages applied to the first gate region PRG, the second gate region DRG, and the third gate region TRG can be applied to the depletion region of the active region ZA.
[0113] More specifically, when the voltage applied to the first gate region PRG, the second gate region DRG, and the third gate region TRG is zero, the depletion region is small enough to open the channel CAN, thereby allowing current to flow between the input IN and the output OUT.
[0114] Furthermore, the semiconductor component CS1 can be configured to operate as a NAND gate when the voltage applied to the third gate region TRG is equal to the first bias voltage. The input of this logic gate is then the voltage applied to the first gate region PRG and the second gate region DRG, and the output of the logic gate is the output OUT.
[0115] The first bias voltage can be, for example, equal to 1.2V.
[0116] Specifically, when the first bias voltage is applied to the third gate region TRG, the depletion region around the channel CAN will only be combined when the first gate region PRG and the second gate region DRG are powered at their rated voltages.
[0117] In this configuration, the CAN channel is only turned off when a rated voltage is applied to the first gate region PRG and the second gate region DRG; otherwise, the CAN channel is on. Therefore, the voltage at the output OUT of semiconductor component CS1 is low only when a rated voltage is applied to the first gate region PRG and the second gate region DRG. When zero voltage is applied to the first gate region PRG and / or the second gate region DRG, the voltage at the output OUT is high.
[0118] Furthermore, the semiconductor component CS1 can be configured to operate as a NOR gate when the voltage applied to the third gate region TRG is equal to the second bias voltage. The input of this logic gate is then the voltage applied to the first gate region PRG and the second gate region DRG, and the output of the logic gate is the output OUT.
[0119] The second bias voltage can be, for example, equal to 1.8V.
[0120] Specifically, when the second bias voltage is applied to the third gate region TRG, the depletion region around the channel CAN will only be separated when the first gate region PRG and the second gate region DRG are not powered.
[0121] In this configuration, the CAN channel is only turned on when the first gate region PRG and the second gate region DRG are not powered; otherwise, the CAN channel is turned off. Therefore, the voltage at the output OUT of the semiconductor device is high only when zero voltage is applied to the first gate region PRG and the second gate region DRG. When a rated voltage is applied to the first gate region PRG and / or the second gate region DRG, the voltage at the output OUT is low.
[0122] Furthermore, the semiconductor component CS1 can be configured to operate as a variable resistor when the voltage applied to the third gate region TRG is equal to the third bias voltage. This variable resistor is then formed by the channel CAN between the input IN and the output OUT.
[0123] This third bias voltage can be, for example, equal to 0.6V.
[0124] Specifically, when a third bias voltage is applied to the third gate region TRG, the depletion region is always isolated.
[0125] Therefore, by applying a third bias voltage to the third gate region TRG, the CAN channel will be turned on, regardless of the voltage applied to the first gate region PRG and the second gate region DRG.
[0126] However, it is still possible to influence the resistance of the CAN channel by acting on the depletion region. Therefore, it is possible to change the channel resistance based on the voltage applied to the first gate region PRG and the second gate region DRG.
[0127] For example, specifically, the resistance of the CAN channel can be set between 500 ohms and 1 megohm.
[0128] Figure 4 The diagram illustrates what can be used to obtain Figures 1 to 3 An embodiment of the manufacturing method of the semiconductor component CS1 shown.
[0129] The manufacturing method includes step 20: forming shallow isolation trenches (TIPPs) in a semiconductor substrate (SUB).
[0130] The manufacturing method then includes step 21: forming an isolation semiconductor layer CISO in a semiconductor substrate SUB by implanting a dopant of a first conductivity type.
[0131] The manufacturing method then includes step 22: forming a well CSN in a semiconductor substrate SUB by implanting a dopant of a second conductivity type.
[0132] The manufacturing method then includes step 23: forming two regions RE1, RE2 in a semiconductor substrate by implanting a first conductivity type.
[0133] The manufacturing method then includes step 24: forming a first gate region PRG and a second gate region DRG.
[0134] Step 24, forming the first gate region PRG and the second gate region DRG, includes etching two trenches that extend parallel to each other from the front side of the semiconductor substrate to regions RE1 and RE2, passing through a shallow isolation trench TIPP. The trenches then define the outlines of the first gate region PRG and the second gate region DRG. Step 24 also includes forming gate oxide layers POG and DOG on the sides of the trenches, particularly for regions RE1 and RE2. This step further includes depositing polysilicon to fill the trenches.
[0135] The manufacturing method also includes step 25: forming region REC by implanting a dopant having a first conductivity type.
[0136] The manufacturing method also includes step 26: forming a third gate region TRG by implanting a dopant having a first conductivity type into region REC.
[0137] The manufacturing method also includes step 27: forming input IN and output OUT by implanting a dopant having a second conductivity type.
[0138] The manufacturing method then includes step 28: forming contact regions ZPC for the first gate region PRG, the second gate region DRG, and the third gate region TRG, as well as contact regions ZPC for the input IN and the output OUT.
[0139] Figure 5 and Figure 6 The illustration shows a semiconductor component CS2 according to another embodiment. Figure 5 This is a top view of semiconductor component CS2. Figure 6 It is along Figure 5 The view of the semiconductor component CS2 in section AA shown.
[0140] In this embodiment, the semiconductor component CS2 is formed in the semiconductor substrate SUB.
[0141] This embodiment and Figure 1 The difference shown is that the isolation semiconductor layer CISO is not used to electrically connect the third gate region TRG to regions RE1 and RE2.
[0142] In fact, in this embodiment, the buried semiconductor region RSE only includes the bonded regions RE1 and RE2.
[0143] Therefore, the semiconductor component CS2 includes a first gate region PRG and a second gate region DRG, which extend in depth from the front surface FA of the semiconductor substrate SUB into the semiconductor substrate SUB via shallow isolation trenches. The first gate region PRG and the second gate region DRG each include gate oxide layers POG and DOG at their distal ends.
[0144] Specifically, the shallow isolation trench TIPP extends from the front FA of the semiconductor substrate SUB into the semiconductor substrate SUB in depth.
[0145] The third gate region TRG then extends into the semiconductor substrate SUB, reaching the distal end that contacts at least one of regions RE1 and RE2.
[0146] Specifically, the third gate region TRG is formed in the semiconductor region RET, extends in depth into the semiconductor substrate SUB, and has a first conductivity type. Specifically, the semiconductor region RET extends orthogonally to the first gate region and the second gate region in the length direction.
[0147] For semiconductor component CS1, semiconductor component CS2 includes a well CSN in which a buried semiconductor region is formed. Semiconductor component CS2 also includes an input IN and an output OUT formed between a first gate region and a second gate region.
[0148] Therefore, the semiconductor component CS2 includes the active region ZA of the well CSN, which is defined by regions RE1, RE2, the first gate region PRG and the second gate region DRG, and the shallow isolation trench TIPP.
[0149] The active region ZA includes a channel CAN with a second conductivity type located between the input IN and the output OUT, and a depletion region (not shown). The depletion region is located between the two regions RE1, RE2 and the channel CAN.
[0150] Semiconductor component CS2 is configured to perform the same functions as semiconductor component CS1, in particular in the same manner as semiconductor component CS1 described above.
[0151] Figure 7 The diagram illustrates what can be used to obtain Figures 5 to 6 An embodiment of the manufacturing method of the semiconductor component CS2 shown.
[0152] The manufacturing method includes step 30: forming shallow isolation trenches (TIPP).
[0153] The manufacturing method then includes step 31: forming a well CSN in a semiconductor substrate SUB by implanting a second conductivity type.
[0154] The manufacturing method then includes step 32: forming two regions RE1, RE2 in a semiconductor substrate SUB by implanting a first conductivity type.
[0155] The manufacturing method also includes step 33: forming a semiconductor region RET by implanting a dopant of a first conductivity type.
[0156] The manufacturing method then includes step 34: forming a first gate region PRG and a second gate region DRG.
[0157] Step 34, forming the first gate region PRG and the second gate region DRG, includes etching two trenches that extend parallel to each other from the front side of the semiconductor substrate SUB to regions RE1, RE2, and through a shallow isolation trench TIPP. The trenches then define the outlines of the first gate region PRG and the second gate region DRG. Step 34 also includes forming gate oxide layers POG and DOG in the trenches for regions RE1, RE2. This step further includes depositing polysilicon to fill the trenches.
[0158] The manufacturing method also includes step 35: forming a third gate region TRG by implanting a dopant having a second conductivity type into the semiconductor region RET.
[0159] The manufacturing method also includes step 36: forming input IN and output OUT by implanting a dopant having a second conductivity type.
[0160] The manufacturing method then includes step 37: forming contact regions ZPC for the first gate region PRG, the second gate region DRG and the third gate region TRG, as well as contact regions ZPC for the input and output.
[0161] also, Figure 8 The illustration shows a top view of a semiconductor component FCS formed in a semiconductor substrate SUB.
[0162] The semiconductor component FCS includes a first gate region PRG and a second gate region DRG, which extend in depth into the semiconductor substrate SUB through shallow isolation trenches (not shown).
[0163] Specifically, the shallow isolation trench TIPP extends from the front FA of the semiconductor substrate SUB into the semiconductor substrate SUB in depth.
[0164] The semiconductor component FCS also includes a semiconductor region buried beneath a shallow isolation trench. This buried semiconductor region can be integrated with... Figures 1 to 3 The buried semiconductor region of the semiconductor component CS1 shown is the same as or similar to... Figure 5 and Figure 6 The buried semiconductor region of the semiconductor component CS2 shown is the same.
[0165] The semiconductor component FCS may also include a third gate region (not shown) that then extends into the semiconductor substrate to a distal end that contacts the buried semiconductor region.
[0166] For semiconductor components CS1 and CS2, semiconductor component FCS includes a well (not shown) in which a buried semiconductor region is formed. Semiconductor component FCS also includes an input IN and an output OUT, formed between a first gate region PRG and a second gate region DRG.
[0167] Therefore, the semiconductor component FCS includes an active region ZA of the well, defined by a buried semiconductor region, defined by a first gate region PRG and a second gate region DRG, and defined by a shallow isolation trench.
[0168] The active region ZA includes a channel CAN with a second conductivity type located between the input IN and the output OUT, and a depletion region. The depletion region is located between the buried semiconductor region and the channel.
[0169] The semiconductor component FCS also includes an isolation region RIS having a first conductivity type, extending into the active region ZA between the first gate region PRG and the second gate region DRG.
[0170] The isolation region RIS prevents current from flowing between the input IN and output OUT of the semiconductor component FCS. Therefore, the isolation region RIS allows the input IN of the semiconductor component FCS to be electrically disconnected from the output OUT.
[0171] Therefore, this type of semiconductor component FCS is not suitable for performing functions that can be performed by... Figures 1 to 3 or Figure 5 and Figure 6 The semiconductor components CS1 and CS2 shown are executed.
[0172] Figure 9 The diagram illustrates what can be used to obtain Figure 8 An embodiment of the manufacturing method of the semiconductor component FCS shown.
[0173] The manufacturing method includes step 40: forming shallow isolation trenches (TIPP).
[0174] The manufacturing method includes step 41: forming a well CSN in a semiconductor substrate by implanting a second conductivity type.
[0175] The manufacturing method then includes step 42: forming a buried semiconductor region RE in a semiconductor substrate by implanting a first conductivity type.
[0176] The manufacturing method then includes step 43: forming a first gate region PRG and a second gate region DRG.
[0177] Step 43, forming the first gate region PRG and the second gate region DRG, includes etching two trenches that extend parallel to each other from the front side FA of the semiconductor substrate SUB to the buried semiconductor region RE, passing through a shallow isolation trench. The trenches then define the outlines of the first gate region PRG and the second gate region DRG. Step 43 also includes forming a gate oxide layer in the trenches for the buried semiconductor region RE. This step further includes depositing polysilicon to fill the trenches.
[0178] The manufacturing method may optionally include step 44: forming a third gate region TRG by implanting a dopant having a first conductivity type.
[0179] The manufacturing method also includes step 45: forming input IN and output OUT by implanting a dopant having a second conductivity type.
[0180] The manufacturing method then includes step 46: forming contact regions ZPC for a first gate region PRG, a second gate region DRG, contact regions ZPC for input IN and output OUT, and optionally a contact region for a third gate region.
[0181] Advantageously, such as Figure 10 As shown, the integrated circuit CI may include at least one semiconductor component CS1, CS2 (such as...) Figures 1 to 3 or Figures 5 to 6 The semiconductor components shown) and at least one semiconductor component FCS (such as Figure 8 (The semiconductor component shown).
[0182] In this circuit, it is difficult to distinguish the semiconductor component FCS from semiconductor components CS1 and CS2 through reverse engineering. In fact, the only difference between semiconductor component FCS and semiconductor components CS1 and CS2 is that they include an isolation region RIS spanning the active region ZA, located between the first gate region PRG and the second gate region DRG.
[0183] The quarantined area is difficult to test.
[0184] As seen earlier, the isolation region RIS prevents current from flowing between the input IN and output OUT of the semiconductor component FCS. Therefore, the isolation region RIS allows the input IN and output OUT of the semiconductor component FCS to be electrically disconnected.
[0185] Therefore, this semiconductor component FCS is not suitable for performing functions that can be performed by semiconductor components CS1 and CS2.
[0186] This type of semiconductor component FCS can be used to complicate the analysis of integrated circuits through reverse engineering. In fact, this semiconductor component FCS is difficult to distinguish from semiconductor components CS1 and CS2, but it cannot perform the same functions as these semiconductor components CS1 and CS2.
[0187] Of course, the embodiments described herein are susceptible to various changes and modifications, which will be apparent to those skilled in the art. For example, in the above embodiments, the function of the electronic component is defined by the bias voltage applied to the third gate region. However, it is entirely possible to provide such an electronic component whose function is defined based on the voltage applied to the first gate region or the second gate region, or different voltages applied to the first gate region, the second gate region, and the third gate region.
Claims
1. An integrated circuit, comprising: Semiconductor substrate; as well as The first semiconductor component includes: A buried semiconductor region is disposed in the semiconductor substrate and has a first conductivity type; The first gate region and the second gate region are configured to be a certain distance apart from each other, and each extends from the front side of the semiconductor substrate into the buried semiconductor region in depth. A third gate region extends in depth from the front side of the semiconductor substrate into the semiconductor substrate and is configured to be electrically connected to the buried semiconductor region; and The active region of the semiconductor substrate is defined by the first gate region, the second gate region and the buried semiconductor region, and the active region has a second conductivity type opposite to the first conductivity type.
2. The integrated circuit of claim 1, wherein the semiconductor substrate comprises a well of the second conductivity type, wherein the buried semiconductor region is located in the well, and wherein the active region is located within the well.
3. The integrated circuit of claim 1, wherein the first semiconductor component further comprises an input and an output, the input and the output being positioned between the first gate region and the second gate region and spaced apart from each other, the active region comprising: A channel is configured to be formed between the input and the output; as well as The depleted area surrounds the channel.
4. The integrated circuit of claim 3, wherein the first semiconductor component is configured such that the depletion region around the channel is combined only when the first gate region and the second gate region are powered at a rated voltage and the third gate region is powered at a first bias voltage.
5. The integrated circuit of claim 3, wherein the first semiconductor component is configured such that the depletion region around the channel is isolated only when the first gate region and the second gate region are not powered and the third gate region is powered with a second bias voltage.
6. The integrated circuit of claim 3, wherein the first semiconductor component is configured such that the depletion region is always isolated when the third gate region is powered by a third bias voltage.
7. The integrated circuit of claim 1, wherein the first gate region and the second gate region each have a distal end, the distal end comprising a gate oxide layer in contact with the semiconductor substrate and the buried semiconductor region.
8. The integrated circuit according to claim 1, comprising: At least one shallow isolation trench is positioned in the semiconductor substrate above the buried semiconductor region.
9. The integrated circuit of claim 1, wherein the first gate region and the second gate region extend in depth into the substrate to reach the buried semiconductor region via shallow isolation trenches.
10. The integrated circuit of claim 9, wherein the buried semiconductor region is spaced apart from the distal end of the shallow isolation trench at a distance between 50 nm and 800 nm.
11. The integrated circuit of claim 1, wherein the buried semiconductor region comprises: An isolation semiconductor layer extends through the semiconductor substrate parallel to the front side of the semiconductor substrate, and the third gate region is connected to the isolation semiconductor layer; Two regions having the first conductivity type and protruding from the isolation semiconductor layer, the isolation semiconductor layer connecting the two regions, the first gate region extending in depth to one of the two regions, and the second gate region extending in depth to the other of the two regions; as well as The active region is defined by the two regions, the isolation semiconductor layer between the two regions, and the first gate region and the second gate region.
12. The integrated circuit of claim 1, wherein the buried semiconductor region includes two bonding regions having the first conductivity type, wherein the first gate region extends in depth to one of the two bonding regions, and the second gate region extends in depth to the other of the two bonding regions, and wherein the third gate region is connected to the two bonding regions.
13. The integrated circuit of claim 12, wherein the active region is defined by the two bonding regions and the first gate region and the second gate region.
14. The integrated circuit of claim 1, wherein the active region has a range of 10 15 at / cm 3 Up to 10 19 at / cm 3 Doping between them.
15. The integrated circuit of claim 1, wherein the first gate region and the second gate region are spaced apart by a distance between 500 nm and 1 μm.
16. The integrated circuit of claim 1, further comprising a second semiconductor component, the second semiconductor component comprising: An additional buried semiconductor region is disposed in the semiconductor substrate and has the first conductivity type; The additional first gate region and the additional second gate region are configured to be spaced apart from each other, and each extends in depth from the front side of the semiconductor substrate into the additional buried semiconductor region. An additional third gate region extends into the semiconductor substrate in depth and is configured to be electrically connected to the additional buried semiconductor region; The additional active region of the semiconductor substrate is defined by the additional first gate region, the additional second gate region and the additional buried semiconductor region, the additional active region having a second conductivity type opposite to the first conductivity type; as well as An isolation region, having the first conductivity type, extends into the additional active region between the additional first gate region and the additional second gate region.
17. A method for manufacturing a semiconductor component in a semiconductor substrate, comprising: A buried semiconductor region is formed in the semiconductor substrate, the buried semiconductor region having a first conductivity type; A first gate region and a second gate region are formed, the first gate region and the second gate region being a certain distance apart from each other, such that the first gate region and the second gate region respectively extend from the front side of the semiconductor substrate into the substrate to reach the buried semiconductor region; An active region is formed in the semiconductor substrate, defined by the first gate region, the second gate region and the buried semiconductor region, and has a second conductivity type opposite to the first conductivity type; as well as A third gate region is formed, extending in depth from the front side of the semiconductor substrate into the semiconductor substrate, and is configured to be electrically connected to the buried semiconductor region.
18. An integrated circuit, comprising: A semiconductor substrate, including a well, the well including an active region; A buried semiconductor region is disposed within the semiconductor substrate; The buried semiconductor region has a first conductivity type, and the well has a second conductivity type; An insulating region is located in a trench in the semiconductor substrate and extends over the well; The first gate region and the second gate region are configured to be a certain distance apart from each other, and each extends through the insulating region, through the trap and into the buried semiconductor region respectively; The conductive portions of the first gate region and the second gate region are isolated from the well and the buried semiconductor region by a gate insulating layer; The third gate region extends through the insulating region to make electrical contact with the buried semiconductor region.
19. The integrated circuit of claim 18, wherein the buried semiconductor region is formed by a buried doped layer in the semiconductor substrate below the well.
20. The integrated circuit of claim 18, wherein the buried semiconductor region further comprises a first doped region and a second doped region located below the first gate region and the second gate region.
21. The integrated circuit of claim 18, wherein the buried semiconductor region is formed by a first doped region and a second doped region located below the first gate region and the second gate region, wherein the first doped region and the second doped region are in contact with each other.
22. The integrated circuit of claim 18, further comprising an input and an output positioned between the first gate region and the second gate region, and separated from each other by the active region of the well forming a channel.
23. The integrated circuit of claim 22, further comprising a depletion region surrounding the channel.
24. The integrated circuit of claim 22, further comprising an isolation region of the first conductivity type, positioned between the first gate region and the second gate region, and positioned between the input and the output.