A transistor, a method for manufacturing the same, and a DRAM device
By forming a multi-fin channel region structure on a semiconductor substrate, the contact area between the channel region and the gate stack is increased, which solves the problems of increased memory structure thickness and short-channel effect limitations caused by increased fin height in the prior art, and achieves improved drive current and reduced process cost.
CN114497036BActive Publication Date: 2026-05-26INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD +1
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2020-11-11
- Publication Date
- 2026-05-26
AI Technical Summary
Technical Problem
In the prior art, increasing the fin height leads to an increase in the thickness of the memory structure, which limits the improvement of the short-channel effect, and the existing single fin structure has insufficient channel drive current.
Method used
By employing a multi-fin channel structure, multiple sub-fins are formed on the semiconductor substrate, and gate stacks are formed between them, increasing the contact area between the channel region and the gate stack and improving the short-channel effect.
Benefits of technology
It effectively increases the channel length, improves the drive current and gate control capability, reduces leakage current, reduces process cost, and improves switching speed and power consumption.
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Smart Images
Figure CN114497036B_ABST
Abstract
This invention relates to a transistor, its manufacturing method, and a DRAM device, belonging to the field of semiconductor technology. It addresses the problem that increasing the fin height in existing transistors leads to increased memory structure thickness, thus limiting the improvement of short-channel effects. The transistor includes: a semiconductor substrate; fins located on the semiconductor substrate, wherein the fins include source / drain regions at both ends and at least two channel regions sandwiched between the source / drain regions; a STI located on the semiconductor substrate and at least on both sides of the fins, with the top of the fins higher than the top of the STIs; and a gate stack intersecting the fins across the channel regions. The multi-fin channel region increases the contact area between the channel regions and the gate stack, thereby effectively improving the short-channel effect.
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