Semiconductor device

Abstract

A semiconductor device includes a first active pattern and a second active pattern on a first active region and a second active region of a substrate, respectively; a gate electrode on a first channel pattern and a second channel pattern; an active contact electrically connected with at least one of a first source / drain pattern and a second source / drain pattern; a gate contact electrically connected with the gate electrode; a first metal layer on the active contact and the gate contact and including a first power line and a second power line; and a first gate cut pattern and a second gate cut pattern under the first power line and the second power line. The first active pattern can include the first channel pattern between a pair of the first source / drain patterns. The second active pattern can include the second channel pattern between a pair of the second source / drain patterns. The first gate cut pattern and the second gate cut pattern can cover outermost surfaces of the first channel pattern and the second channel pattern, respectively.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0151739, filed on November 13, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor device, and more specifically, to a semiconductor device including a field-effect transistor and a method of manufacturing the semiconductor device. Background Technology

[0004] Semiconductor devices are considered essential components in the electronics industry due to their small size, versatility, and / or low cost. Semiconductor devices are classified into semiconductor memory devices for storing data, semiconductor logic devices for processing data, and hybrid semiconductor devices that include both memory and logic elements. With advancements in the electronics industry, the demand for semiconductor devices with improved characteristics is constantly increasing. For example, there is a growing need for semiconductor devices with high reliability, high performance, and / or versatility. To meet this demand, the complexity and / or integration density of semiconductor devices are increasing. Summary of the Invention

[0005] Embodiments of the present invention provide a semiconductor device and / or a method of manufacturing thereof with increased integration density and improved electrical characteristics.

[0006] According to embodiments of the present invention, a semiconductor device may include: a substrate including a first active region and a second active region; a first active pattern on the first active region, the first active pattern including a pair of first source / drain patterns and a first channel pattern therebetween; a second active pattern on the second active region, the second active pattern including a pair of second source / drain patterns and a second channel pattern therebetween; a gate electrode on the first channel pattern and the second channel pattern; an active contact electrically connected to at least one of the first source / drain patterns and the second source / drain pattern; a gate contact electrically connected to the gate electrode; a first metal layer on the active contact and the gate contact, the first metal layer including a first electric field line and a second electric field line; and a first gate diced pattern and a second gate diced pattern respectively below the first electric field line and the second electric field line. The first gate diced pattern may cover a first outermost surface of the first channel pattern, and the second gate diced pattern may cover a second outermost surface of the second channel pattern.

[0007] According to embodiments of the present invention, a semiconductor device may include: a substrate including a first logic cell and a second logic cell, the first logic cell and the second logic cell being adjacent to each other in a first direction; a first active pattern on the first logic cell, the first active pattern including a pair of first source / drain patterns and a first channel pattern therebetween; a second active pattern on the second logic cell, the second active pattern including a pair of second source / drain patterns and a second channel pattern therebetween; a first gate electrode on the first channel pattern; a second gate electrode on the second channel pattern; a gate dicing pattern on the boundary between the first logic cell and the second logic cell, the gate dicing pattern being between the first gate electrode and the second gate electrode; an active contact electrically connected to at least one of the first source / drain patterns and the second source / drain pattern; a gate contact electrically connected to the first gate electrode; and a metal layer stacked on the active contact and the gate contact. The gate dicing pattern may cover a first outermost surface of the first channel pattern and a second outermost surface of the second channel pattern.

[0008] According to an embodiment of the present invention, a semiconductor device may include: a substrate including logic cells, the logic cells including PMOSFET regions and NMOSFET regions spaced apart from each other in a first direction, the logic cells having first to fourth boundaries, the first and second boundaries being opposite to each other in a second direction intersecting the first direction, and third and fourth boundaries being opposite to each other in the first direction; a device isolation layer on the substrate, the device isolation layer defining a first active pattern on the PMOSFET regions and a second active pattern on the NMOSFET regions, the first and second active patterns extending along the second direction, the upper portion of each of the first and second active patterns protruding above the device isolation layer; a gate electrode spanning the first and second active patterns, the gate electrode extending along the first direction; a first source / drain pattern and a second source / drain pattern in the upper portion of the first and second active patterns, respectively, each of the first and second source / drain patterns being adjacent to one side of the gate electrode; The system comprises: a partition structure on at least one of a first boundary and a second boundary; a first gate dicing pattern and a second gate dicing pattern on a third boundary and a fourth boundary, respectively, wherein a first end of a gate electrode contacts the first gate dicing pattern and a second end of a gate electrode contacts the second gate dicing pattern; a gate spacer on at least one side surface of the gate electrode; a gate capping pattern on the top surface of the gate electrode; an interlayer insulating layer on the gate capping pattern; an active contact penetrating the interlayer insulating layer and electrically connected to at least one of the first source / drain pattern and the second source / drain pattern; a gate contact penetrating the interlayer insulating layer and the gate capping pattern and electrically connected to the gate electrode; a first metal layer on the interlayer insulating layer, the first metal layer including a first electric field line and a second electric field line on the first gate dicing pattern and the second gate dicing pattern, respectively, and the first metal layer including a first interconnect line between the first electric field line and the second electric field line, the first interconnect line being electrically connected to the active contact and the gate contact and respectively; and a second metal layer on the first metal layer. The second metal layer may include a second interconnect line electrically connected to the first metal layer. The upper portion of each of the first and second active patterns may include a first side surface and a second side surface opposite to each other. A first gate dicing pattern may cover the second side surface of the first active pattern, and a second gate dicing pattern may cover the second side surface of the second active pattern. A gate electrode may be located on the first side surface of the first active pattern and the first side surface of the second active pattern. Attached Figure Description

[0009] The exemplary embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The drawings illustrate non-limiting exemplary embodiments described herein.

[0010] Figures 1 to 3This is a conceptual diagram illustrating the logic unit of a semiconductor device according to an embodiment of the present invention.

[0011] Figure 4 This is a plan view illustrating a semiconductor device according to an embodiment of the concept of the present invention.

[0012] Figures 5A to 5D They are along Figure 4 The cross-sectional views taken from lines A-A', B-B', C-C' and D-D'.

[0013] Figure 6 It is along Figure 4 A cross-sectional view taken along line D-D' to illustrate a semiconductor device of a comparative example according to the present invention.

[0014] Figure 7 , Figure 9 , Figure 11 and Figure 13 This is a plan view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0015] Figure 8A , Figure 10A , Figure 12A and Figure 14A They are along Figure 7 , Figure 9 , Figure 11 and Figure 13 A cross-sectional view taken from line A-A'.

[0016] Figure 8B , Figure 10B , Figure 12B and Figure 14B They are along Figure 7 , Figure 9 , Figure 11 and Figure 13 The cross-sectional view taken by line B-B'.

[0017] Figure 10C , Figure 12C and Figure 14C They are along Figure 7 , Figure 9 , Figure 11 and Figure 13 The cross-sectional view taken from line C-C'.

[0018] Figure 8C , Figure 10D , Figure 12D and Figure 14D They are along Figure 7 , Figure 9 , Figure 11 and Figure 13 The cross-sectional view taken by line D-D'.

[0019] Figure 15 It is along Figure 4 A cross-sectional view taken along line D-D' to illustrate a semiconductor device according to an embodiment of the present invention.

[0020] Figure 16 It is shown Figure 15 Enlarged cross-sectional view of part M.

[0021] Figure 17 , Figure 18 , Figure 19 and Figure 20 Each of them is along Figure 4 A cross-sectional view taken along line D-D' to illustrate a semiconductor device according to an embodiment of the present invention.

[0022] Figures 21A to 21D They are respectively along Figure 4 Cross-sectional views taken along lines A-A', B-B', C-C', and D-D' are shown to illustrate a semiconductor device according to an embodiment of the concept of the present invention.

[0023] Figure 22 and Figure 23 Each of them is along Figure 4 A cross-sectional view taken along line D-D' to illustrate a semiconductor device according to an embodiment of the present invention.

[0024] Figure 24 This is a plan view illustrating a semiconductor device according to an embodiment of the concept of the present invention.

[0025] Figure 25A It is along Figure 24 The cross-sectional view taken by lines A-A' and B-B'.

[0026] Figure 25B It is along Figure 24 The cross-sectional view taken from line C-C'.

[0027] It should be noted that these figures are intended to illustrate the general characteristics of the methods, structures, and / or materials used in some exemplary embodiments and to supplement the written description provided below. However, these figures are not drawn to scale and do not accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the range of values ​​or characteristics contained in the exemplary embodiments. For example, the relative thickness and positioning of molecules, layers, regions, and / or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numerals in the various figures is intended to indicate the presence of similar or identical elements or features. Detailed Implementation

[0028] When the terms “about” or “substantially” are used in conjunction with numerical values ​​in this specification, the associated numerical values ​​are intended to include manufacturing or operational tolerances (e.g., ±10%) near said numerical values. Furthermore, when the words “generally” and “substantially” are used in conjunction with geometry, it is intended that precision of the geometry is not required, but rather a tolerance of the shape is within the scope of this disclosure. Moreover, regardless of whether a numerical value or shape is modified to “about” or “substantially,” it should be understood that these numerical values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) near said numerical values ​​or shapes.

[0029] Expressions such as “at least one of…” modify the entire list of elements (e.g., A, B, and C) when they follow the list of elements, rather than individual elements in the list. For example, “at least one of A, B, and C,” “at least one of A, B, or C,” “one or a combination of A, B, and C,” and “one or a combination of A, B, and C” can be interpreted as covering any one of the following combinations: A; B; A and B; A and C; B and C; and A, B, and C.

[0030] Exemplary embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, which illustrate exemplary embodiments.

[0031] Figures 1 to 3 This is a conceptual diagram illustrating the logic unit of a semiconductor device according to an embodiment of the present invention.

[0032] refer to Figure 1 A single-height cell (SHC) can be provided. Specifically, a first electric field line M1_R1 and a second electric field line M1_R2 can be disposed on the substrate 100. The first electric field line M1_R1 can be a conduction path that provides a drain voltage VDD (e.g., a power supply voltage). The second electric field line M1_R2 can be a conduction path that provides a source voltage VSS (e.g., a ground voltage).

[0033] A single-height cell SHC can be defined between a first power line M1_R1 and a second power line M1_R2. A single-height cell SHC may include a PMOSFET region PR and an NMOSFET region NR. In other words, a single-height cell SHC may have a CMOS structure disposed between the first power line M1_R1 and the second power line M1_R2.

[0034] Each of the PMOSFET region PR and the NMOSFET region NR can have a first width W1 in the first direction D1. The length of the single-height cell SHC in the first direction D1 can be defined as the first height HE1. The first height HE1 can be substantially the same as the distance (e.g., pitch) between the first electric field line M1_R1 and the second electric field line M1_R2.

[0035] A single-height cell (SHC) can constitute a single logic unit. In this specification, a logic unit can refer to a logic device configured to perform a specific function (e.g., AND, OR, XOR, XNOR, inverter, etc.). In other words, a logic unit can include transistors constituting the logic device and interconnects connecting the transistors to each other.

[0036] refer to Figure 2 A dual-height cell (DHC) can be provided. Specifically, a first electric field line M1_R1, a second electric field line M1_R2, and a third electric field line M1_R3 can be disposed on the substrate 100. The first electric field line M1_R1 can be disposed between the second electric field line M1_R2 and the third electric field line M1_R3. The third electric field line M1_R3 can be a conduction path that provides the source voltage VSS.

[0037] The dual-height cell (DHC) can be defined between the second power line M1_R2 and the third power line M1_R3. The dual-height cell (DHC) may include a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2.

[0038] The first NMOSFET region NR1 can be adjacent to the second electric field line M1_R2. The second NMOSFET region NR2 can be adjacent to the third electric field line M1_R3. The first PMOSFET region PR1 and the second PMOSFET region PR2 can be adjacent to the first electric field line M1_R1. When viewed in a plan view, the first electric field line M1_R1 can be positioned between the first MOSFET region PR1 and the second MOSFET region PR2.

[0039] The length of the dual-height unit DHC in the first direction D1 can be defined as the second height HE2. The second height HE2 can be... Figure 1 The first height HE1 is approximately twice that of the second height. The first PMOSFET region PR1 and the second PMOSFET region PR2 of the dual-height cell DHC can be combined to serve as a single PMOSFET region.

[0040] Therefore, the channel size of the PMOS transistor in the dual-height cell DHC can be larger than that of the previous reference. Figure 1 The channel size of the PMOS transistor in the single-height cell SHC is described. For example, the channel size of the PMOS transistor in the dual-height cell DHC can be approximately twice that of the PMOS transistor in the single-height cell SHC. In this case, the dual-height cell DHC can operate at a higher speed than the single-height cell SHC. In one embodiment, Figure 2The dual-height cell (DHC) shown can be defined as a multi-height cell. Although not shown, a multi-height cell can include a triple-height cell, whose cell height is approximately three times that of a single-height cell (SHC).

[0041] Reference Figure 3 The first single-height unit SHC1, the second single-height unit SHC2, and the double-height unit DHC can be disposed two-dimensionally on the substrate 100. The first single-height unit SHC1 can be disposed between the first electric field line M1_R1 and the second electric field line M1_R2. The second single-height unit SHC2 can be disposed between the first electric field line M1_R1 and the third electric field line M1_R3. The second single-height unit SHC2 can be adjacent to the first single-height unit SHC1 in the first direction D1.

[0042] The dual-height unit DHC can be located between the second power line M1_R2 and the third power line M1_R3. The dual-height unit DHC can be adjacent to the first single-height unit SHC1 and the second single-height unit SHC2 in the second direction D2.

[0043] The partition structure DB can be set between the first single-height unit SHC1 and the dual-height unit DHC, and between the second single-height unit SHC2 and the dual-height unit DHC. The active region of the dual-height unit DHC can be electrically separated from the active regions of each of the first single-height unit SHC1 and the second single-height unit SHC2 by the partition structure DB.

[0044] Figure 4 This is a plan view illustrating a semiconductor device according to an embodiment of the concept of the present invention. Figures 5A to 5D They are along Figure 4 The cross-sectional views taken from lines A-A', B-B', C-C', and D-D'. Figure 4 and Figures 5A to 5D It shows Figure 3 Examples of the detailed structures of the first single-height unit SHC1 and the second single-height unit SHC2.

[0045] Reference Figure 4 and Figures 5A to 5D The first single-height cell SHC1 and the second single-height cell SHC2 can be disposed on the substrate 100. Logic transistors constituting the logic circuit can be disposed on each of the first single-height cell SHC1 and the second single-height cell SHC2. The substrate 100 can be a semiconductor substrate formed of silicon, germanium, silicon-germanium, compound semiconductor materials, etc., or a semiconductor substrate including silicon, germanium, silicon-germanium, compound semiconductor materials, etc. For example, the substrate 100 can be a silicon wafer.

[0046] The substrate 100 may include a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2. Each of the first PMOSFET region PR1, the second PMOSFET region PR2, the first NMOSFET region NR1, and the second NMOSFET region NR2 may extend in a second direction D2.

[0047] The first PMOSFET region PR1, the second PMOSFET region PR2, the first NMOSFET region NR1, and the second NMOSFET region NR2 can be defined by a second trench TR2 formed in the upper portion of the substrate 100. For example, the second trench TR2 can be located between the first NMOSFET region NR1 and the first PMOSFET region PR1. The second trench TR2 can be located between the first PMOSFET region PR1 and the second PMOSFET region PR2. The second trench TR2 can be located between the second PMOSFET region PR2 and the second NMOSFET region NR2.

[0048] A first active pattern AP1 can be provided on each of the first PMOSFET region PR1 and the second PMOSFET region PR2. A second active pattern AP2 can be provided on each of the first NMOSFET region NR1 and the second NMOSFET region NR2.

[0049] The first active pattern AP1 and the second active pattern AP2 may extend along the second direction D2 and be parallel to each other. The first active pattern AP1 and the second active pattern AP2 may be vertical protrusions of the substrate 100. The first trench TR1 may be defined between adjacent first active patterns AP1 in the first active pattern AP1 and between adjacent second active patterns AP2 in the second active pattern AP2. The first trench TR1 may be shallower than the first trench TR2.

[0050] The device isolation layer ST may fill the first trench TR1 and the second trench TR2. The device isolation layer ST may be formed of silicon oxide or include silicon oxide. The upper portion of each of the first active pattern AP1 and the second active pattern AP2 may be a protruding pattern that extends vertically above the device isolation layer ST (e.g., see...). Figure 5D The upper portion of each of the first active pattern AP1 and the second active pattern AP2 may have a fin shape. The device isolation layer ST may not cover the upper portion of each of the first active pattern AP1 and the second active pattern AP2. The device isolation layer ST may cover the lower surface of each of the first active pattern AP1 and the second active pattern AP2.

[0051] A first source / drain pattern SD1 can be formed on each of the first PMOSFET region PR1 and the second PMOSFET region PR2. The first source / drain pattern SD1 can be formed in the upper part of each of the first active patterns AP1. The first source / drain pattern SD1 can be an impurity region of a first conductivity type (e.g., p-type). A first channel pattern CH1 can be inserted between each pair of first source / drain patterns SD1 that are adjacent to each other along the second direction D2.

[0052] A second source / drain pattern SD2 can be formed on each of the first NMOSFET region NR1 and the second NMOSFET region NR2. The second source / drain pattern SD2 can be formed in the upper part of each of the second active patterns AP2. The second source / drain pattern SD2 can be an impurity region of a second conductivity type (e.g., n-type). A second channel pattern CH2 can be inserted between each pair of second source / drain patterns SD2 that are adjacent to each other along the second direction D2.

[0053] The first source / drain region SD1 and the second source / drain region SD2 can be epitaxial patterns formed by a selective epitaxial growth process. As an example, the first source / drain pattern SD1 and the second source / drain pattern SD2 can have top surfaces that are coplanar with the top surfaces of the first channel pattern CH1 and the second channel pattern CH2. As another example, the top surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be higher than the top surfaces of the first channel pattern CH1 and the second channel pattern CH2.

[0054] The first source / drain pattern SD1 may comprise a semiconductor material (e.g., SiGe) with a lattice constant greater than that of the substrate 100. In this case, the first source / drain pattern SD1 may apply compressive stress to the first channel pattern CH1 therebetween. In one embodiment, the second source / drain pattern SD2 may be formed of or comprise the same semiconductor material (e.g., Si) as the substrate 100.

[0055] A gate electrode GE can be configured to span the first active pattern AP1 and the second active pattern AP2 and extend in a first direction D1. The gate electrode GE can be arranged in a second direction D2 at a first spacing. The gate electrode GE can vertically overlap with the first channel pattern CH1 and the second channel pattern CH2. Each of the gate electrodes GE can be configured to face the top surface of the first channel pattern CH1 and the opposite side surface of the second channel pattern CH2.

[0056] Return to reference Figure 5DThe gate electrode GE can be disposed on at least one of the first side surfaces SW1 of the channel pattern CH1 or CH2 and on the first top surface TS1. In other words, the transistor according to this embodiment can be a three-dimensional field-effect transistor (e.g., FinFET), wherein the gate electrode GE is configured to surround the channel patterns CH1 and CH2 in three dimensions.

[0057] For example, the first single-height unit SHC1 may have a first boundary BD1 and a second boundary BD2 that are opposite to each other in the second direction D2. The first boundary BD1 and the second boundary BD2 may extend in the first direction D1. The first single-height unit SHC1 may have a third boundary BD3 and a fourth boundary BD4 that are opposite to each other in the first direction D1. The third boundary BD3 and the fourth boundary BD4 may extend in the second direction D2.

[0058] The gate dicing pattern CT can be disposed on the boundary parallel to the second direction D2 of each of the first single-height cells SHC1 and the second single-height cell SHC2. For example, the gate dicing pattern CT can be disposed on the third boundary BD3 and the fourth boundary BD4 of the first single-height cell SHC1. The gate dicing pattern CT can be arranged along the third boundary BD3 at a first spacing. The gate dicing pattern CT can be arranged along the fourth boundary BD4 at a first spacing. When viewed in a plan view, the gate dicing patterns CT on the third boundary BD3 and the fourth boundary BD4 can be configured to overlap with the gate electrode GE, respectively. The gate dicing pattern CT can be formed of or include at least one of an insulating material (e.g., silicon oxide or silicon nitride).

[0059] The gate electrode GE on the first single-height unit SHC1 can be separated from the gate electrode GE on the second single-height unit SHC2 by a gate cutting pattern CT. The gate cutting pattern CT can be inserted between the gate electrodes GE on the first single-height unit SHC1 and the second single-height unit SHC2, which are aligned with each other along the first direction D1. In other words, the gate electrode GE extending in the first direction D1 can be divided into multiple gate electrodes GE by the gate cutting pattern CT.

[0060] Return to reference Figure 4 and Figures 5A to 5DA pair of gate spacers GS can be disposed on opposite side surfaces of each of the gate electrodes GE. The gate spacers GS can extend along the gate electrode GE in a first direction D1. The top surface of the gate spacers GS can be higher than the top surface of the gate electrode GE. The top surface of the gate spacers GS can be coplanar with the top surface of the first interlayer insulating layer 110, as will be described below. The gate spacers GS can be formed of or include at least one of SiCN, SiCON, or SiN. In one embodiment, the gate spacers GS can be a multilayer structure comprising at least two different materials selected from SiCN, SiCON, and SiN.

[0061] A gate capping pattern GP can be formed on each gate electrode GE. The gate capping pattern GP can extend along the gate electrode GE or in the first direction D1. The gate capping pattern GP can be formed of or include a material having etch selectivity relative to the first interlayer insulating layer 110 and the second interlayer insulating layer 120, as will be discussed below. Specifically, the gate capping pattern GP can be formed of or include at least one of SiON, SiCN, SiCON, or SiN.

[0062] A gate insulating layer GI can be inserted between the gate electrode GE and the first active pattern AP1, and between the gate electrode GE and the second active pattern AP2. The gate insulating layer GI can extend along the bottom surface of the gate electrode GE thereon. As an example, the gate insulating layer GI can cover the first top surface TS1 and the first side surface SW1 of the channel pattern CH1 or CH2. The gate insulating layer GI can cover the top surface of the device isolation layer ST below the gate electrode GE (see, for example, [reference needed]). Figure 5D ).

[0063] In one embodiment, the gate insulating layer GI may be formed of or comprise a high-k dielectric material with a dielectric constant higher than that of the silicon oxide layer. For example, the high-k dielectric material may include at least one of the following: hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0064] In another embodiment, the semiconductor device may include a negative capacitance (NC) FET that uses a negative capacitor. For example, the gate insulating layer GI may include a ferroelectric layer exhibiting ferroelectric properties and a paraelectric layer exhibiting paraelectric properties.

[0065] The ferroelectric layer can have negative capacitance, and the paraelectric layer can have positive capacitance. When two or more capacitors are connected in series and each capacitor has positive capacitance, the total capacitance can be reduced to less than the value of each individual capacitor. Conversely, when at least one of the capacitors connected in series has negative capacitance, the total capacitance of the capacitors connected in series can have a positive value and can be greater than the absolute value of each individual capacitor.

[0066] When a ferroelectric layer with negative capacitance and a paraelectric layer with positive capacitance are connected in series, the total capacitance of the series-connected ferroelectric and paraelectric layers may increase. Due to this increase in total capacitance, a transistor including a ferroelectric layer may have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0067] The ferroelectric layer can possess ferroelectric properties. The ferroelectric layer can be formed from or include at least one of the following: for example, hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and / or lead zirconium titanium oxide. In this document, hafnium zirconium oxide can be a hafnium oxide doped with zirconium (Zr). Alternatively, hafnium zirconium oxide can be a compound composed of hafnium (Hf), zirconium (Zr), and / or oxygen (O).

[0068] The ferroelectric layer may also include dopants. For example, dopants may include at least one of the following: aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and / or tin (Sn). The type of dopant in the ferroelectric layer may vary depending on the ferroelectric material included in the ferroelectric layer.

[0069] When the ferroelectric layer includes hafnium oxide, the dopant in the ferroelectric layer may include at least one of the following: for example, gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al) and / or yttrium (Y).

[0070] When the dopant is aluminum (Al), the aluminum content in the ferroelectric layer can range from 3 at% to 8 at% (atomic percentage). In this paper, the aluminum content as a dopant can be the ratio of the number of aluminum atoms to the number of hafnium atoms and aluminum atoms.

[0071] When the dopant is silicon (Si), the silicon content in the ferroelectric layer can range from 2 at% to 10 at%. When the dopant is yttrium (Y), the yttrium content in the ferroelectric layer can range from 2 at% to 10 at%. When the dopant is gadolinium (Gd), the gadolinium content in the ferroelectric layer can range from 1 at% to 7 at%. When the dopant is zirconium (Zr), the zirconium content in the ferroelectric layer can range from 50 at% to 80 at%.

[0072] The paraelectric layer may have paraelectric properties. The paraelectric layer may be formed of or include at least one of, for example, silicon oxide and / or a high-k metal oxide. The metal oxide that can be used as the paraelectric layer may include at least one of, for example, hafnium oxide, zirconium oxide, and / or aluminum oxide, but the inventive concept is not limited to these examples.

[0073] The ferroelectric layer and the paraelectric layer can be formed from or comprise the same material. The ferroelectric layer may have ferroelectric properties, but the paraelectric layer may not. For example, in the case where both the ferroelectric and paraelectric layers contain hafnium oxide, the crystal structure of the hafnium oxide in the ferroelectric layer may differ from the crystal structure of the hafnium oxide in the paraelectric layer.

[0074] A ferroelectric layer can only exhibit ferroelectric properties when its thickness is within a specific range. In one embodiment, the ferroelectric layer may have a thickness ranging from 0.5 nm to 10 nm, but the inventive concept is not limited to this example. Since the critical thickness associated with the occurrence of ferroelectric properties varies depending on the type of ferroelectric material, the thickness of the ferroelectric layer can be varied depending on the type of ferroelectric material.

[0075] As an example, the gate insulating layer GI may include a single ferroelectric layer. As another example, the gate insulating layer GI may include multiple ferroelectric layers spaced apart from each other. The gate insulating layer GI may have a multilayer structure in which multiple ferroelectric layers and multiple paraelectric layers are stacked alternately.

[0076] The gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be disposed on the gate insulating layer GI adjacent to the first channel pattern CH1 and the second channel pattern CH2. The first metal pattern may include a work function metal, which can be used to adjust the threshold voltage of the transistor. By adjusting the thickness and composition of the first metal pattern, a transistor with a desired threshold voltage can be realized.

[0077] The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include at least one metallic material selected from the group consisting of titanium (TI), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo), as well as nitrogen (N). The first metal pattern may also include carbon (C). The first metal pattern may include multiple stacked work function metal layers.

[0078] The second metal pattern may include a metal material with a lower electrical resistance than the first metal pattern. For example, the second metal pattern may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta).

[0079] A first interlayer insulating layer 110 may be disposed on a substrate 100. The first interlayer insulating layer 110 may cover a gate spacer GS and a first source / drain pattern SD1 and a second source / drain pattern SD2. The top surface of the first interlayer insulating layer 110 may be substantially coplanar with the top surface of the gate cap pattern GP and the top surface of the gate spacer GS. A second interlayer insulating layer 120 may be disposed on the first interlayer insulating layer 110 to cover the gate cap pattern GP. A third interlayer insulating layer 130 may be disposed on the second interlayer insulating layer 120. A fourth interlayer insulating layer 140 may be disposed on the third interlayer insulating layer 130. In one embodiment, at least one of the first to fourth interlayer insulating layers 140 may include a silicon oxide layer.

[0080] A pair of separator structures DB can be disposed on both sides of each of the first single-height unit SHC1 and the second single-height unit SHC2, facing each other in the second direction D2. For example, the pair of separator structures DB can be disposed on the first boundary BD1 and the second boundary BD2 of the first single-height unit SHC1, respectively. The isolation structure DB can extend in the first direction D1 and parallel to the gate electrode GE. The spacing between the separator structure DB and the adjacent gate electrode GE can be equal to the first spacing.

[0081] The separator structure DB can penetrate the first interlayer insulation layer 110 and the second interlayer insulation layer 120 and can extend into the first active pattern AP1 and the second active pattern AP2. The separator structure DB can penetrate the upper part of each of the first active pattern AP1 and the second active pattern AP2. The separator structure DB can electrically separate the active area of ​​each of the first single-height unit SHC1 and the second single-height unit SHC2 from the active area of ​​the adjacent unit.

[0082] Active contacts AC can be configured to penetrate the first interlayer insulation layer 110 and the second interlayer insulation layer 120, and can be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. Each of the active contacts AC can be disposed between a pair of gate electrodes GE. When viewed in a plan view, each of the active contacts AC can be a strip or line pattern extending along a first direction D1.

[0083] The active contact AC can be a self-aligned contact. For example, the active contact AC can be formed using a gate cap pattern GP and a gate spacer GS via a self-aligned process. For example, the active contact AC can cover at least a portion of the side surface of the gate spacer GS. Although not shown, the active contact AC can cover a portion of the top surface of the gate cap pattern GP.

[0084] The silicide pattern SC can be inserted between the active contact AC and the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. The active contact AC can be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2 through the silicide pattern SC, respectively. The silicide pattern SC can be formed of or include at least one of a metal silicide material (e.g., titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, or cobalt silicide).

[0085] Return to reference Figure 5C At least one of the active contacts AC on the first single-height unit SHC1 can be used to electrically connect the first source / drain pattern SD1 of the first PMOSFET region PR1 to the second source / drain pattern SD2 of the first NMOSFET region NR1. The active contact AC can extend along a first direction D1 from the second source / drain pattern SD2 of the first NMOSFET region NR1 to the first source / drain pattern SD1 of the first PMOSFET region PR1. The active contact AC can include a first body portion BP1 on the first source / drain pattern SD1 and a second body portion BP2 on the second source / drain pattern SD2. The first body portion BP1 can be connected to the top surface of the first source / drain pattern SD1 via a silicide pattern SC, and the second body portion BP2 can be connected to the top surface of the second source / drain pattern SD2 via a silicide pattern SC. The first active contact AC1 can also include a protrusion PP inserted between the first body portion BP1 and the second body portion BP2. The protrusion PP can be disposed on the device isolation layer ST between the first PMOSFET region PR1 and the first NMOSFET region NR1.

[0086] The protruding portion PP may extend from the first body portion BP1 toward the device isolation layer ST along the inclined side surface of the first source / drain pattern SD1. The protruding portion PP may extend from the second body portion BP2 toward the device isolation layer ST along the inclined side surface of the second source / drain pattern SD2. The bottom surface of the protruding portion PP may be lower than the bottom surface of each of the first body portion BP1 and the second body portion BP2. The bottom surface of the protruding portion PP may be located at a level higher than the device isolation layer ST. In other words, the protruding portion PP may be spaced apart from the device isolation layer ST, wherein the first interlayer insulating layer 110 is inserted between them.

[0087] In one embodiment, the active contact AC can be connected to the top surface of the first source / drain pattern SD1 via the first body portion BP1, and also to the inclined side surface of the first source / drain pattern SD1 via the protruding portion PP. In other words, the protruding portion PP can increase the contact area between the active contact AC and the first source / drain pattern SD1. Therefore, the resistance between the active contact AC and the first source / drain pattern SD1 can be reduced. Similarly, the protruding portion PP can reduce the resistance between the active contact AC and the second source / drain pattern SD2. Therefore, the operating characteristics (e.g., operating speed) of the semiconductor device according to embodiments of the present invention can be improved.

[0088] A gate contact GC, electrically connected to and separately connected to the gate electrode GE, can be configured to penetrate the second interlayer insulating layer 120 and the gate cap pattern GP. When viewed in a plan view, the gate contact GC on the first single-height cell SHC1 can be configured to overlap with the first PMOSFET region PR1. In other words, the gate contact GC on the first single-height cell SHC1 can be located on the first active pattern AP1 (e.g., see...). Figure 5A ).

[0089] The gate contact GC can be freely disposed on the gate electrode GE, and its position is not restricted. For example, the gate contact GC on the second single-height cell SHC2 can be disposed on the second PMOSFET region PR2, the second NMOSFET region NR2, and the device isolation layer ST that fills the second trench TR2, respectively.

[0090] In one embodiment, reference Figure 5A and Figure 5CThe upper portion of the active contact AC adjacent to the gate contact GC can be filled with an upper insulating pattern UIP. The bottom surface of the upper insulating pattern UIP can be lower than the bottom surface of the gate contact GC. In other words, the top surface of the active contact AC adjacent to the gate contact GC can be formed at a level lower than the bottom surface of the gate contact GC by the upper insulating pattern UIP. Therefore, it is possible to prevent adjacent gate contacts GC and active contacts AC from contacting each other, thereby preventing short circuit problems.

[0091] Each of the active contact AC and the gate contact GC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may be formed of or include at least one of a metallic material (e.g., aluminum, copper, tungsten, molybdenum, or cobalt). The barrier pattern BM may cover the side and bottom surfaces of the conductive pattern FM. In one embodiment, the barrier pattern BM may include a metal layer and a metal nitride layer. The metal layer may be formed of or include at least one of titanium, tantalum, tungsten, nickel, cobalt, or platinum. The metal nitride layer may be formed of or include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), or platinum nitride (PtN).

[0092] The first metal layer M1 may be disposed in the third interlayer insulating layer 130. For example, the first metal layer M1 may include a first electric field line M1_R1, a second electric field line M1_R2, a third electric field line M1_R3, and a first interconnect line M1_I. The interconnect lines M1_R1, M1_R2, M1_R3, and M1_I of the first metal layer M1 may extend in the second direction D2 to be parallel to each other.

[0093] Specifically, the first power line M1_R1 and the second power line M1_R2 can be respectively disposed on the third boundary BD3 and the fourth boundary BD4 of the first single-height unit SHC1. The first power line M1_R1 can extend along the third boundary BD3 and in the second direction D2. The second power line M1_R2 can extend along the fourth boundary BD4 and in the second direction D2.

[0094] The first interconnects M1_I of the first metal layer M1 can be arranged with a second spacing in the first direction D1. The second spacing can be smaller than the first spacing. The linewidth of each of the first interconnects M1_I can be smaller than the linewidth of each of the first electric field line M1_R1, the second electric field line M1_R2, and the third electric field line M1_R3.

[0095] The first metal layer M1 may further include a first via VI1. The first via VI1 may be disposed below the interconnects M1_R1, M1_R2, M1_R3, and M1_I of the first metal layer M1, respectively. The interconnects and active contacts AC of the first metal layer M1 may be electrically connected to each other through the first via VI1. The interconnects and gate contacts GC of the first metal layer M1 may be electrically connected to each other through the first via VI1.

[0096] The interconnects of the first metal layer M1 and the first via VI1 beneath it can be formed by separate processes. For example, the first via VI1 and the interconnects of the first metal layer M1 can be formed by their respective single damascene processes. The semiconductor device according to this embodiment can be manufactured using a sub-20nm process.

[0097] The second metal layer M2 may be disposed in the fourth interlayer insulating layer 140. The second metal layer M2 may include a plurality of second interconnects M2_1. Each of the second interconnects M2_1 in the second metal layer M2 may be a linear or strip pattern extending along the first direction D1. In other words, the second interconnects M2_1 may extend in the first direction D1 and be parallel to each other.

[0098] The second metal layer M2 may further include a second via VI2 disposed below the second interconnect M2_I. The interconnects of the first metal layer M1 and the second metal layer M2 can be electrically connected to each other through the second via VI2. The interconnects of the second metal layer M2 and the second via VI2 below it can be formed together using a dual damascene process.

[0099] The interconnects of the first metal layer M1 may be formed of or include the same or different conductive material as the conductive material of the second metal layer M2. For example, the interconnects of the first metal layer M1 and the second metal layer M2 may be formed of or include at least one of a metallic material (e.g., aluminum, copper, tungsten, molybdenum, or cobalt). Although not shown, multiple metal layers (e.g., M3, M4, M5, etc.) may be additionally stacked on the fourth interlayer insulating layer 140. Each stacked metal layer may include interconnects that serve as wiring paths between cells.

[0100] Return to reference Figure 5D The gate electrode GE on the first single-height unit SHC1 may include a first terminal EN1 and a second terminal EN2. Each of the first terminal EN1 and the second terminal EN2 may be in contact with the gate dicing pattern CT. The first active pattern AP1 on the first PMOSFET region PR1 may include a first outermost active pattern AP1_p in contact with the gate dicing pattern CT. The second active pattern AP2 on the first NMOSFET region NR1 may include a second outermost active pattern AP2_p in contact with the gate dicing pattern CT.

[0101] Specifically, the first outermost active pattern AP1_p may include a second top surface TS2, a second side surface SW2, and a third side surface SW3 opposite to the second side surface SW2. The second top surface TS2 and the second side surface SW2 may be covered by a gate insulating layer GI. The second top surface TS2 and the second side surface SW2 may face the gate electrode GE, with the gate insulating layer GI inserted therebetween. In other words, the second top surface TS2 and the second side surface SW2 may vertically overlap with the gate electrode GE. The third side surface SW3 may not be covered by the gate insulating layer GI. The third side surface SW3 may contact the gate diced pattern CT. The third side surface SW3 may not vertically overlap with the gate electrode GE.

[0102] The first end EN1 of the gate electrode GE may not extend beyond the third side surface SW3 of the first outermost active pattern AP1_p, and the second end EN2 of the gate electrode GE may not extend beyond the third side surface SW3 of the second outermost active pattern AP2_p. The gate electrode GE may have a first length L1 in the first direction D1 (e.g., the length from the first end EN1 to the second end EN2). The gate dicing pattern CT may have a second length L2 in the first direction D1.

[0103] Figure 6 It is along Figure 4 A cross-sectional view taken along line D-D' is provided to illustrate a semiconductor device of a comparative example according to the invention. (Refer to...) Figure 6 , compared with previous reference Figure 5D The described gate electrode GE is different. Figure 6 The gate electrode GE can cover both the first outermost active pattern AP1_p and the second outermost active pattern AP2_p. In other words, Figure 6 The gate electrode GE can have a larger than Figure 5D The first length L1 and the third length L3. Because Figure 6 The gate electrode GE on the first single-height unit SHCl has a relatively large third length L3, so the previously referenced Figure 1 The cell height HE1 described can be increased relatively. With an increase in the cell height HE1 of a single-height cell SHC, their two-dimensional arrangement may require an increase in chip area.

[0104] At the same time, return to reference Figure 5D The semiconductor device according to this embodiment may include a gate electrode GE having a relatively small length (e.g., a first length L1). Therefore, the size can be reduced. Figure 1 The cell height HE1 of the single-height cell SHC. By reducing the cell height of each logic cell, the area of ​​the two-dimensionally arranged chip can be reduced. Therefore, the semiconductor device in this embodiment can have increased integration density.

[0105] Each of the first active pattern AP1 and the second active pattern AP2 according to this embodiment can have a thin-body structure. In this case, the semiconductor device according to this embodiment can have essentially the same characteristics as a fully depleted device. Therefore, even as Figure 5D As shown, when the gate electrode GE in this embodiment does not cover the third side surface SW3 of the first outermost active pattern AP1_p, no breakdown problem will occur between the source electrode and the drain electrode. In other words, the first outermost active pattern AP1_p can be used as the body of a normal transistor.

[0106] Figure 7 , Figure 9 , Figure 11 and Figure 13 This is a plan view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 8A , Figure 10A , Figure 12A and Figure 14A They are along Figure 7 , Figure 9 , Figure 11 and Figure 13 A cross-sectional view taken from line A-A'. Figure 8B , Figure 10B , Figure 12B and Figure 14B They are along Figure 7 , Figure 9 , Figure 11 and Figure 13 The cross-sectional view taken by line B-B'. Figure 10C , Figure 12C and Figure 14C They are along Figure 7 , Figure 9 , Figure 11 and Figure 13 The cross-sectional view taken from line C-C'. Figure 8C Figure 100 Figure 12D and Figure 14D They are along Figure 7 , Figure 9 , Figure 11 and Figure 13 The cross-sectional view taken by line D-D'.

[0107] Reference Figure 7 and Figures 8A to 8CA substrate 100 may be provided having a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2. The first NMOSFET region NR1 and the first PMOSFET region PR1 may define a first single-height unit SHCl, and the second NMOSFET region NR2 and the second PMOSFET region PR2 may define a second single-height unit SHC2.

[0108] The substrate 100 can be patterned to form a first active pattern AP1 and a second active pattern AP2. The first active pattern AP1 can be formed on each of the first PMOSFET region PR1 and the second PMOSFET region PR2. The second active pattern AP2 can be formed on each of the first NMOSFET region NR1 and the second NMOSFET region NR2.

[0109] A device isolation layer ST may be formed on the substrate 100. The device isolation layer ST may be formed of or include at least one of an insulating material (e.g., silicon oxide). The device isolation layer ST may be recessed to expose the upper portion of each of the first active pattern AP1 and the second active pattern AP2. Therefore, the upper portion of each of the first active pattern AP1 and the second active pattern AP2 may protrude vertically over the device isolation layer ST.

[0110] The sacrificial pattern SAP can be formed across the first active pattern AP1 and the second active pattern AP2. The sacrificial pattern SAP can be formed as a line or strip extending along the first direction D1.

[0111] Specifically, the formation of the sacrificial pattern SAP may include forming a sacrificial layer on a substrate 100; forming a mask pattern MA on the sacrificial layer; and using the mask pattern MA as an etch mask to pattern the sacrificial layer. The sacrificial layer may be formed of or comprise polysilicon.

[0112] In one embodiment, the patterning process for forming the sacrificial pattern SAP may include a photolithography process using extreme ultraviolet (EUV) light. In this specification, the wavelength of the EUV light can be in the range of 4 nm to 124 nm, specifically 4 nm to 20 nm, for example, ultraviolet light with a wavelength of 13.5 nm. The energy of the EUV light can be in the range of 6.21 eV to 124 eV, specifically, in the range of 90 eV to 95 eV.

[0113] Photolithography processes using EUV light can include an exposure process that irradiates a photoresist layer with EUV light and a development process. For example, the photoresist layer can be an organic photoresist layer comprising an organic polymer (e.g., polyhydroxystyrene). The organic photoresist layer can also include a photosensitive compound that can react with EUV light. The organic photoresist layer can also contain materials with high EUV absorption (e.g., organometallic materials, iodine-containing materials, or fluorine-containing materials). As another example, the photoresist layer can be an inorganic photoresist layer comprising an inorganic material (e.g., tin oxide).

[0114] The photoresist layer can be formed to have a relatively small thickness. A photoresist pattern can be formed by developing a photoresist layer exposed to EUV light. When viewed in a planar view, the photoresist pattern can be formed to have a line shape, island shape, sawtooth shape, honeycomb shape, or circular shape extending in a specific direction, but the inventive concept is not limited to these examples.

[0115] A mask pattern MA can be formed by patterning at least one layer disposed beneath it using a photoresist pattern as an etch mask. Subsequently, a desired pattern (e.g., a sacrificial pattern SAP) can be formed on the wafer by patterning a target layer (e.g., a sacrificial layer) using the mask pattern MA as an etch mask.

[0116] In a comparative example of the inventive concept, multiple patterning (MPT) techniques using two or more photomasks are required to form fine-pitch patterns on a wafer. In contrast, when performing an EUV lithography process according to an embodiment of the inventive concept, a sacrificial pattern SAP can be formed with fine pitch using only a single photomask.

[0117] For example, the minimum spacing between sacrificial patterned SAPs achieved by the EUV lithography process according to this embodiment can be less than or equal to 45 nm. In other words, the EUV lithography process can be performed to precisely and finely form sacrificial patterned SAPs without the need for multiple patterning techniques.

[0118] In one embodiment, EUV lithography can be used not only in the patterning process for forming the sacrificial pattern SAP, but also in the patterning process for forming the first active pattern AP1 and the second active pattern AP2 as described above, but the inventive concept is not limited to this example.

[0119] A pair of gate spacers GS can be formed on opposite side surfaces of each sacrificial pattern SAP. Formation of the gate spacers GS may include conformally forming a gate spacer layer on substrate 100 and anisotropically etching the gate spacer layer. The gate spacer layer may be formed of or include at least one of SiCN, SiCON, or SiN. Alternatively, the gate spacer layer may be a multilayer structure including at least two of SiCN, SiCON, or SiN.

[0120] Reference Figure 9 and Figures 10A to 10D The first source / drain pattern SD1 can be formed on the upper part of each first active pattern AP1 or in the upper part of each first active pattern AP1. A pair of first source / drain patterns SD1 can be formed on both sides of each sacrificial pattern SAP.

[0121] Specifically, the first recess can be formed by etching the upper portion of the first active pattern AP1 using a mask pattern MA and a gate spacer GS as an etching mask. During the etching of the upper portion of the first active pattern AP1, the device isolation layer ST between the first active patterns AP1 can be recessed, such as... Figure 8C As shown.

[0122] The first source / drain pattern SD1 can be formed by performing a selective epitaxial growth process using the inner surface of the first recess of the first active pattern AP1 as a seed layer. As a result of forming the first source / drain pattern SD1, a first channel pattern CH1 can be defined between each pair of first source / drain patterns SD1. For example, the selective epitaxial growth process can include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process. The first source / drain pattern SD1 can include a semiconductor material (e.g., SiGe) with a lattice constant greater than that of the substrate 100. Each first source / drain pattern SD1 can be a multilayer structure comprising multiple semiconductor layers.

[0123] In one embodiment, the first source / drain pattern SD1 can be doped in situ during a selective epitaxial growth process. In another embodiment, after the formation of the first source / drain pattern SD1, impurities can be implanted into the first source / drain pattern SD1. The first source / drain pattern SD1 can be doped to have a first conductivity type (e.g., p-type).

[0124] A second source / drain pattern SD2 can be formed on top of the second active pattern AP2. A pair of second source / drain patterns SD2 can be formed on both sides of each sacrificial pattern SAP.

[0125] Specifically, the second recess can be formed by etching the upper portion of the second active pattern AP2 using a mask pattern MA and a gate spacer GS as an etching mask. The second source / drain pattern SD2 can be formed by performing a selective epitaxial growth process using the inner surface of the second recess of the second active pattern AP2 as a seed layer. As a result of forming the second source / drain pattern SD2, a second channel pattern CH2 can be defined between each pair of second source / drain patterns SD2. For example, the second source / drain pattern SD2 can be formed of the same semiconductor material as the substrate 100 (e.g., Si) or include the aforementioned semiconductor material. The second source / drain pattern SD2 can be doped to have a second conductivity type (e.g., n-type).

[0126] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be formed in different process sequences. In other words, the first source / drain pattern SD1 and the second source / drain pattern SD2 can be formed at different times.

[0127] Reference Figure 11 and Figures 12A to 12D The first interlayer insulating layer 110 may be formed to cover the first source / drain pattern SD1 and the second source / drain pattern SD2, the mask pattern MA and the gate spacer GS. In one embodiment, the first interlayer insulating layer 110 may be formed of silicon oxide or include silicon oxide.

[0128] The first interlayer insulating layer 110 can be planarized to expose the top surface of the sacrificial pattern SAP. Planarization of the first interlayer insulating layer 110 can be performed using an etch-back process or a chemical mechanical polishing (CMP) process. In one embodiment, the mask pattern MA can be completely removed during the planarization process. Therefore, the first interlayer insulating layer 110 can have a top surface that is coplanar with the top surface of the sacrificial pattern SAP and the top surface of the gate spacer GS.

[0129] The sacrificial pattern SAP can be replaced by the gate electrode GE. Specifically, the exposed sacrificial pattern SAP can be selectively removed. Since the sacrificial pattern SAP has been removed, empty spaces can be formed. The gate insulating layer GI and the gate electrode GE can be formed in each empty space. The gate electrode GE can include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern can be formed of a work function metal used to adjust the threshold voltage of the transistor, and the second metal pattern can be formed of a metal material with low resistance.

[0130] After replacing the sacrificial pattern SAP with a gate electrode GE, the gate electrode GE can be patterned to form a gate cleavage pattern CT. The gate cleavage pattern CT can be formed by dividing each gate electrode GE into multiple gate electrodes GE.

[0131] Specifically, a photolithography process can be performed to form a mask layer with openings, where the openings can be used to define the location and shape of the gate cleaving pattern CT. An etching process can be used to selectively remove the portions of the gate electrode GE exposed by the openings. When partially removing the gate electrode GE, the gate insulating layer GI can also be removed. The gate cleaving pattern CT can be formed by filling the empty areas created by removing the gate electrode GE with an insulating material. (See previous references...) Figure 5D The gate dicing pattern CT can be formed to contact the side surface SW3 of the first outermost active pattern AP1_p and the side surface SW3 of the second outermost active pattern AP2_p.

[0132] The gate cap pattern GP can be formed on the gate electrode GE and the gate cut pattern CT.

[0133] Reference Figure 13 and Figures 14A to 14D A second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 may include a silicon oxide layer. A pair of separator structures DB may be formed on both sides of the first single-height cell SHC1, respectively. The separator structures DB may overlap with the gate electrode GE, which is formed on both sides of the first single-height cell SHC1, respectively. For example, forming the separator structures DB may include: forming a hole to penetrate the first interlayer insulating layer 110 and the second interlayer insulating layer 120 and the gate electrode GE, and extending into the first active pattern AP1 and the second active pattern AP2; and then filling the hole with an insulating layer.

[0134] The active contact AC can be formed to penetrate the second interlayer insulating layer 120 and the first interlayer insulating layer 110 and be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. An upper insulating pattern UIP can be formed by replacing the upper portion of each active contact AC with insulating material. The gate contact GC can be formed to penetrate the second interlayer insulating layer 120 and the gate cap pattern GP and be electrically connected to the gate electrode GE.

[0135] The third interlayer insulation layer 130 may be formed on the second interlayer insulation layer 120. The first metal layer M1 may be formed in the third interlayer insulation layer 130. The formation of the first metal layer M1 may include forming a first electric field line M1_R1, a second electric field line M1_R2, a third electric field line M1_R3, and a first interconnect line M1_I.

[0136] A fourth interlayer insulating layer 140 may be formed on the first metal layer M1. A second metal layer M2 may be formed in the fourth interlayer insulating layer 140. The formation of the second metal layer M2 may include forming a second interconnect M2_I. For example, the second interconnect M2_I may be formed by a dual damascene process.

[0137] In one embodiment, forming interconnects in the first metal layer M1 and / or the second metal layer M2 may include a photolithography process using EUV light. The EUV photolithography used for forming the interconnects (e.g., the BEOL process) may be performed in substantially the same manner as forming the sacrificial pattern SAP. For example, the minimum spacing between the first interconnects M1_I implemented by the EUV photolithography process according to this embodiment may be less than or equal to 45 nm.

[0138] Figure 15 It is along Figure 4 A cross-sectional view taken along line D-D' to illustrate a semiconductor device according to an embodiment of the present invention. Figure 16 It is shown Figure 15 An enlarged cross-sectional view of part M. In the following description, previously referred to... Figure 4 and Figures 5A to 5D The components described herein can be identified by the same reference numerals, and will not be described further.

[0139] Reference Figure 4 , Figure 15 and Figure 16 The first end EN1 of the gate electrode GE can be located on the second top surface TS2 of the first outermost active pattern AP1_p. The second end EN2 of the gate electrode GE can be located on the second top surface TS2 of the second outermost active pattern AP2_p. The gate electrode GE can partially cover the second top surface TS2 of the first outermost active pattern AP1_p.

[0140] Specifically, the second top surface TS2 of the first outermost active pattern AP1_p may include a first region P1 that vertically overlaps with the gate electrode GE. The remaining regions of the second top surface TS2 other than the first region P1 (hereinafter referred to as the second region P2) may not vertically overlap with the gate electrode GE. The second region P2 of the second top surface TS2 may be in contact with the gate dicing pattern CT.

[0141] The upper portion of the first outermost active pattern AP1_p may have a second width W2. As mentioned above, the second width W2 may be small enough that the device exhibits essentially the same physical characteristics as a fully depleted device. For example, the second width W2 may be in the range of 1 nm to 30 nm. The first region P1 of the second top surface TS2 may have a third width W3. The third width W3 may be smaller than the second width W2. The ratio of the third width W3 to the second width W2 may be in the range of 0.1 to 0.9.

[0142] In one embodiment, although not shown, the gate electrode GE may cover the second side surface SW2 of the first outermost active pattern AP1_p without covering the second top surface TS2 of the first outermost active pattern AP1_p. That is, the entire second top surface TS2 may be covered by the gate cut pattern CT, and in this case, the third width W3 may be substantially zero.

[0143] Even when the second top surface TS2 is completely covered by the gate cut pattern CT, the semiconductor device according to this embodiment can be operated as a normal device via the gate electrode GE on the second side surface SW2, because it behaves similarly to a fully depleted device.

[0144] Furthermore, as in this embodiment, when the gate electrode GE is configured to partially or not cover the second top surface TS2 of the first outermost active pattern AP1_p, the length of the gate electrode GE in the first direction D1 can be further reduced. Therefore, the cell height can be further reduced and the integration density of the semiconductor device increased.

[0145] Figure 17 , Figure 18 , Figure 19 and Figure 20 Each of them is along Figure 4 A cross-sectional view taken along line D-D' is provided to illustrate a semiconductor device according to an embodiment of the present invention. In the following description, prior reference is made to... Figure 4 and Figures 5A to 5D The components described herein can be identified by the same reference numerals, and will not be described further.

[0146] First refer to Figure 17 The gate electrode GE on the first single height unit SHC1 may include the first gate electrode GE1 on the first active pattern AP1 and the second gate electrode GE2 on the second active pattern AP2.

[0147] The gate dicing pattern CT may include a first gate dicing pattern CT1 and a second gate dicing pattern CT2. The first gate dicing pattern CT1 may be disposed between adjacent cells in a plurality of cells. The second gate dicing pattern CT2 may be disposed to penetrate the gate electrode GE between the first PMOSFET region PR1 and the first NMOSFET region NR1, thereby dividing the gate electrode GE into a first gate electrode GE1 and a second gate electrode GE2.

[0148] A second gate dicing pattern CT2 may extend toward the substrate 100 to fill a recessed region RSR formed in the upper portion of the substrate 100. The second gate dicing pattern CT2 may include an isolation pattern ISP, which is configured to fill the recessed region RSR between the first PMOSFET region PR1 and the first NMOSFET region NR1. The substrate 100 may include an impurity region DPR formed along the recessed region RSR. The impurity region DPR may be formed by an ion implantation process. The impurity region DPR and the isolation pattern ISP filling the recessed region RSR can electrically disconnect the first PMOSFET region PR1 and the first NMOSFET region NR1 from each other.

[0149] Due to the isolation pattern ISP of the impurity region DPR and the filled recess region RSR, carrier conduction between the first PMOSFET region PR1 and the first NMOSFET region NR1 can be effectively prevented even when the distance between the first PMOSFET region PR1 and the first NMOSFET region NR1 is reduced. Therefore, in this embodiment, the distance between the first PMOSFET region PR1 and the first NMOSFET region NR1 can be further reduced, thereby further reducing the cell height.

[0150] Furthermore, according to this embodiment, since the gate electrode GE is divided into a first gate electrode GE1 and a second gate electrode GE2, the parasitic capacitance generated near the gate electrode GE can be reduced. Therefore, the electrical characteristics of the semiconductor device according to this embodiment can be improved.

[0151] Reference Figure 18 , can Figure 17 A bridge electrode BRE is disposed on the first gate electrode GE1 and the second gate electrode GE2. The bridge electrode BRE can electrically connect the first gate electrode GE1 and the second gate electrode GE2 to each other. The gate contact GC can be connected to the bridge electrode BRE.

[0152] In this embodiment, the first gate electrode GE1 may have a fourth length L4, and the second gate electrode GE2 may have a fifth length L5. The fourth length L4 may be different from the fifth length L5. For example, the fourth length L4 may be greater than the fifth length L5.

[0153] Reference Figure 19The first active pattern AP1 may include a pair of first outermost active patterns AP1_p. The first gate electrode GE1 may not cover the side surface SW3 of each of the first outermost active patterns AP1_p. The side surface SW3 of each of the pair of first outermost active patterns AP1_p may be covered with a gate cleaved pattern CT. The second active pattern AP2 may include a pair of second outermost active patterns AP2_p. The second gate electrode GE2 may not cover the side surface of each of the second outermost active patterns AP2_p.

[0154] In this embodiment, the first gate electrode GE1 and the second gate electrode GE2 can be respectively compared to Figure 18 The first gate electrode GE1 and the second gate electrode GE2 are short. Due to... Figure 18 Compared to the first gate electrode GE1 and the second gate electrode GE2 in this embodiment, each of the first gate electrode GE1 and the second gate electrode GE2 has a reduced size, thus more effectively reducing the parasitic capacitance generated near the gate electrode GE. Accordingly, the electrical characteristics of the semiconductor device can be improved.

[0155] Reference Figure 20 Each of the first active patterns AP1 may have a first top surface TS1. The first gate electrode GE1 may have a third top surface TS3. The third top surface TS3 may be located at the same level as or below the first top surface TS1. The top surface of the second gate electrode GE2 may also be coplanar with or below the top surface of each of the second active patterns AP2.

[0156] In this embodiment, the first gate electrode GE1 and the second gate electrode GE2 can be smaller than 1 / 2 mm. Figure 19 The first gate electrode GE1 and the second gate electrode GE2. Due to the... Figure 19 Compared to the first gate electrode GE1 and the second gate electrode GE2, each of the first gate electrode GE1 and the second gate electrode GE2 in this embodiment has a reduced size, thus more effectively reducing the parasitic capacitance generated near the gate electrode GE.

[0157] Figures 21A to 21D They are respectively along Figure 4 Cross-sectional views taken along lines A-A', B-B', C-C', and D-D' are provided to illustrate a semiconductor device according to an embodiment of the present invention. In the following description, prior reference is made to... Figure 4 and Figures 5A to 5D The components described herein can be identified by the same reference numerals, and will not be described further.

[0158] Reference Figure 4 and Figures 21A to 21DA substrate 100 may be provided, comprising a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2. A device isolation layer ST may be disposed on the substrate 100. The device isolation layer ST may define a first active pattern AP1 and a second active pattern AP2 in the upper part of the substrate 100. The first active pattern AP1 may be defined on each of the first PMOSFET region PR1 and the second PMOSFET region NR2, and the second active pattern AP2 may be defined on each of the first NMOSFET region NR1 and the second NMOSFET region NR2.

[0159] The first active pattern AP1 may include a first channel pattern CH1 disposed on its upper portion. The second active pattern AP2 may include a second channel pattern CH2 disposed on its upper portion. Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 stacked in sequence. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be spaced apart from each other in a vertical direction (e.g., third direction D3).

[0160] Each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be formed of or include at least one of silicon (Si), germanium (Ge), or silicon-germanium (SiGe). In one embodiment, each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be formed of or include crystalline silicon.

[0161] The first active pattern AP1 may further include a first source / drain pattern SD1. The stacked first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3 of the first channel pattern CH1 may be inserted between each pair of adjacent first source / drain patterns SD1. The stacked first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3 may connect each pair of adjacent first source / drain patterns SD1 to each other.

[0162] The second active pattern AP2 may further include a second source / drain pattern SD2. The stacked first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3 of the second channel pattern CH2 may be inserted between each pair of adjacent second source / drain patterns SD2. The stacked first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3 may connect each pair of adjacent second source / drain patterns SD2 to each other.

[0163] A gate electrode GE can be configured to span the first channel pattern CH1 and the second channel pattern CH2 and extend in the first direction D1. The gate electrode GE can vertically overlap the first channel pattern CH1 and the second channel pattern CH2. A pair of gate spacers GS can be provided on opposite side surfaces of the gate electrode GE. A gate capping pattern GP can be provided on the gate electrode GE.

[0164] Return to reference Figure 21D The gate electrode GE can be configured to surround a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 around each of the first channel pattern CH1 and the second channel pattern CH2. The transistor according to this embodiment can be a three-dimensional field-effect transistor (e.g., an MBCFET or a GAAFET), wherein the gate electrode GE is configured to surround the channel pattern CH1 or CH2 in three dimensions. Specifically, each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may include a fourth top surface TS4, a fourth side surface SW4, a fifth side surface SW5 opposite to the fourth side surface SW4, and a bottom surface BS. The fifth side surface SW5 may be the outermost surface of the semiconductor pattern. The gate electrode GE may cover the fourth top surface TS4, the fourth side surface SW4, and the bottom surface BS. The gate electrode GE may not cover the fifth side surface SW5 and may cover the fifth side surface SW5. The fifth side surface SW5 may be covered with a gate diced pattern CT.

[0165] In this embodiment, since the gate electrode GE does not cover the fifth side surface SW5 of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3, the gate electrode GE can have a relatively small length. In one embodiment, since each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 has a thin-body structure, the semiconductor device according to this embodiment can operate like a fully depleted device. Figure 21D As shown, the device can operate normally even when the gate electrode GE does not cover the outermost surface SW5 of the semiconductor pattern.

[0166] The gate insulating layer GI can be disposed between each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 and the gate electrode GE. The gate insulating layer GI can be disposed around each of the first channel pattern CH1 and the second channel pattern CH2.

[0167] An inner spacer IP inserted between the gate insulating layer GI and the second source / drain pattern SD2 can be disposed on each of the first NMOSFET region NR1 and the second NMOSFET region NR2. The gate electrode GE can be spaced apart from the second source / drain pattern SD2 by the gate insulating layer GI and the inner spacer IP. In contrast, the inner spacer IP can be omitted on the first PMOSFET region PR1 and the second PMOSFET region PR2.

[0168] The first interlayer insulating layer 110 and the second interlayer insulating layer 120 can be disposed on the substrate 100. The active contact AC can be configured to penetrate the first interlayer insulating layer 110 and the second interlayer insulating layer 120, and can be connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. The gate contact GC can be configured to penetrate the second interlayer insulating layer 120 and the gate cap pattern GP, ​​and can be connected to the gate electrode GE, respectively. The active contact AC and the gate contact GC can be configured to have the same characteristics as previously referenced. Figure 4 and Figures 5A to 5D The features described in the embodiments are substantially the same.

[0169] A third interlayer insulating layer 130 may be disposed on the second interlayer insulating layer 120. A fourth interlayer insulating layer 140 may be disposed on the third interlayer insulating layer 130. A first metal layer M1 may be disposed in the third interlayer insulating layer 130. A second metal layer M2 may be disposed in the fourth interlayer insulating layer 140. The first metal layer M1 and the second metal layer M2 may be configured to have the same characteristics as previously referenced. Figure 4 and Figures 5A to 5D The features described in the embodiments are substantially the same.

[0170] Figure 22 and Figure 23 Each of them is along Figure 4 A cross-sectional view taken along line D-D' is provided to illustrate a semiconductor device according to an embodiment of the present invention. In the following description, prior reference is made to... Figure 4 and Figures 21A to 21D The components described herein can be identified by the same reference numerals, and will not be described further.

[0171] Reference Figure 22 The gate electrode GE on the first single-height unit SHC1 may include a first gate electrode GE1 on the first active pattern AP1 and a second gate electrode GE2 on the second active pattern AP2. The gate electrode GE may also include a bridge electrode BRE on the first gate electrode GE1 and the second gate electrode GE2.

[0172] A first gate dicing pattern CT1 may cover the outermost surface of each of the first channel pattern CH1 and the second channel pattern CH2. A second gate dicing pattern CT2 may be disposed between the first gate electrode GE1 and the second gate electrode GE2. A recessed region RSR may be defined between the first PMOSFET region PR1 and the first NMOSFET region NR1, and the second gate dicing pattern CT2 may include an isolation pattern ISP filling the recessed region RSR. The substrate 100 may include an impurity region DPR surrounding the recessed region RSR.

[0173] Reference Figure 23 Each of the first gate electrode GE1 and the second gate electrode GE2 may include a third top surface TS3. The third semiconductor pattern SP3 of each of the first channel pattern CH1 and the second channel pattern CH2 may include a fourth top surface TS4. The third top surface TS3 may be located at the same level as or below the fourth top surface TS4.

[0174] Figure 24 This is a plan view illustrating a semiconductor device according to an embodiment of the concept of the present invention. Figure 25A It is along Figure 24 The cross-sectional view taken by lines A-A' and B-B'. Figure 25B It is along Figure 24 The cross-sectional view taken from line C-C'.

[0175] refer to Figure 24 , Figure 25A and Figure 25B A single-height cell (SHC) can be disposed on the substrate 100. The single-height cell (SHC) can be a logic cell comprising logic devices (e.g., inverters, flip-flops, etc.) configured to perform specific functions. The single-height cell (SHC) can include vertical transistors constituting the logic devices and interconnects connecting the vertical transistors to each other.

[0176] The single-height cell SHC on substrate 100 may include a first active region PR and a second active region NR. For example, the first active region PR may be a PMOSFET region, and the second active region NR may be an NMOSFET region. The first active region PR and the second active region NR may be defined by a trench TR formed in the upper portion of substrate 100. The first active region PR and the second active region NR may be spaced apart from each other in a first direction D1.

[0177] The first lower epitaxial pattern SOP1 can be disposed on the first active region PR, and the second lower epitaxial pattern SOP2 can be disposed on the second active region NR. When viewed in a planar view, the first lower epitaxial pattern SOP1 can overlap with the first active region PR, and the second lower epitaxial pattern SOP2 can overlap with the second active region NR. The first lower epitaxial pattern SOP1 and the second lower epitaxial pattern SOP2 can be epitaxial patterns formed by a selective epitaxial growth process. The first lower epitaxial pattern SOP1 can be disposed in the first recessed region RS1 of the substrate 100, and the second lower epitaxial pattern SOP2 can be disposed in the second recessed region RS2 of the substrate 100.

[0178] A first active pattern AP1 can be disposed on a first active region PR, and a second active pattern AP2 can be disposed on a second active region NR. Each of the first active pattern AP1 and the second active pattern AP2 can be a vertically protruding fin-shaped pattern. When viewed in a plan view, each of the first active pattern AP1 and the second active pattern AP2 can have a stripe pattern extending in a first direction D1. The first active pattern AP1 can be arranged along a second direction D2, and the second active pattern AP2 can be arranged along a second direction D2.

[0179] Each of the first active patterns AP1 may include a first channel pattern CHP1 that protrudes vertically from the first lower epitaxial pattern SOP1 and a first upper epitaxial pattern DOP1 disposed on the first channel pattern CHP1. Each of the second active patterns AP2 may include a second channel pattern CHP2 that protrudes vertically from the second lower epitaxial pattern SOP2 and a second upper epitaxial pattern DOP2 disposed on the second channel pattern CHP2.

[0180] A device isolation layer ST can be disposed on the substrate 100 to fill the trench TR. The device isolation layer ST can cover the top surface of the first lower epitaxial pattern SOP1 and the second lower epitaxial pattern SOP2. The first active pattern AP1 and the second active pattern AP2 can protrude vertically above the device isolation layer ST.

[0181] The gate electrode GE can be disposed on the device isolation layer ST and can extend parallel to each other along a first direction D1. The gate electrode GE can be arranged along a second direction D2. The gate electrode GE can surround a first channel pattern CHP1 of a first active pattern AP1 and can surround a second channel pattern CHP2 of a second active pattern AP2.

[0182] For example, the first channel pattern CHP1 of the first active pattern AP1 may have sixth to ninth side surfaces SW6, SW7, SW8, and SW9. The sixth side surface SW6 and the seventh side surface SW7 may be opposite to each other in the second direction D2, and the eighth side surface SW8 and the ninth side surface SW9 may be opposite to each other in the first direction D1. The gate electrode GE may be disposed on the sixth side surface SW6, the seventh side surface SW7, and the eighth side surface SW8. However, the gate electrode GE may not be disposed on the ninth side surface SW9, which is the outermost surface, and the ninth side surface SW9 may be exposed.

[0183] A gate insulating layer GI can be inserted between the gate electrode GE and each of the first channel pattern CHP1 and the second channel pattern CHP2. The gate insulating layer GI can cover the bottom surface and inner surface of the gate electrode GE. For example, the gate insulating layer GI can directly cover the sixth side surface SW6, the seventh side surface SW7, and the eighth side surface SW8 of the first active pattern AP1. The gate insulating layer GI may not cover the ninth side surface SW9.

[0184] The first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2 can protrude vertically above the gate electrode GE. The top surface of the gate electrode GE can be lower than the bottom surface of each of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. In other words, each of the first active pattern AP1 and the second active pattern AP2 can have a structure that protrudes vertically from the substrate 100 and penetrates the gate electrode GE.

[0185] The semiconductor device according to this embodiment may include a vertical transistor in which charge carriers move along a third direction D3. For example, when the transistor is turned on by applying a voltage to the gate electrode GE, charge carriers can move from the lower epitaxial pattern SOP1 or SOP2 to the upper epitaxial pattern DOP1 or DOP2 through the channel pattern CHP1 or CHP2. The semiconductor device according to this embodiment may include a three-dimensional field-effect transistor (e.g., VFET) in which the gate electrode GE is disposed around the side surface of the channel pattern CHP1 or CHP2.

[0186] In this embodiment, because the channel patterns CHP1 or CHP2 have a thin-body structure, the semiconductor device according to this embodiment can behave like a fully depleted device. Figure 24 and Figure 25B As shown, the device can operate normally even when the gate electrode GE does not cover the outermost surface SW9 of the channel pattern CHP1 or CHP2.

[0187] The spacer SPC can be disposed on the device isolation layer ST to cover the gate electrode GE and the first active pattern AP1 and the second active pattern AP2. The spacer SPC can comprise a silicon nitride layer or a silicon oxynitride layer. The spacer SPC can include a lower spacer LS, an upper spacer US, and a gate spacer GS between the lower spacer LS and the upper spacer US. The spacer SPC can cover the exposed surfaces of the channel patterns CHP1 or CHP2 (e.g., the outermost surface SW9).

[0188] The lower spacer LS can directly cover the top surface of the device isolation layer ST. The gate electrode GE can be spaced from the device isolation layer ST in the third direction D3 by the lower spacer LS. The gate spacer GS can cover the top surface and outer surface of each gate electrode GE. The upper spacer US can cover the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. However, the upper spacer US can not cover the top surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2, and can expose the top surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2.

[0189] A first interlayer insulating layer 110 may be disposed on the spacer SPC. The first interlayer insulating layer 110 may have a top surface substantially coplanar with the top surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. Second to fourth interlayer insulating layers 120, 130, and 140 may be sequentially stacked on the first interlayer insulating layer 110. A second interlayer insulating layer 120 may cover the top surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2.

[0190] At least one first active contact AC1 can be provided to penetrate the second interlayer insulating layer 120 and couple to the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. At least one second active contact AC2 can be provided to sequentially penetrate the second interlayer insulating layer 120, the first interlayer insulating layer 110, the lower spacer LS, and the device isolation layer ST and couple to the first lower epitaxial pattern SOP1 and the second lower epitaxial pattern SOP2. A gate contact GC can be provided to sequentially penetrate the second interlayer insulating layer 120, the first interlayer insulating layer 110, and the gate spacer GS and couple to the gate electrode GE.

[0191] A first metal layer M1 may be disposed in a third interlayer insulating layer 130. A second metal layer M2 may be disposed in a fourth interlayer insulating layer 140. The first metal layer M1 and the second metal layer M2 may be configured to have the same characteristics as previously referenced. Figure 4 and Figures 5A to 5D The features described in the embodiments are substantially the same.

[0192] In a semiconductor device according to an embodiment of the present invention, the gate electrode on the logic cell can be configured to have a reduced length, which reduces the cell height of the logic cell. Therefore, the area of ​​the chip in which the logic cells are arranged in two dimensions can be reduced, thereby increasing the integration density of the semiconductor device. Furthermore, by dividing the gate electrode and reducing its size, parasitic capacitance generated near the gate electrode can be reduced. This also improves the electrical characteristics of the semiconductor device.

[0193] While exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: The substrate includes a first active region and a second active region; The first active pattern, on the first active region, includes a pair of first source / drain patterns and a first channel pattern located therebetween. The second active pattern, on the second active region, includes a pair of second source / drain patterns and a second channel pattern located therebetween; Gate electrode, on the first channel pattern and the second channel pattern; An active contact is electrically connected to at least one of the first source / drain pattern and the second source / drain pattern; The gate contact is electrically connected to the gate electrode. A first metal layer is provided on the active contact and the gate contact, and the first metal layer includes a first electric field line and a second electric field line. as well as The first gate dicing pattern and the second gate dicing pattern are respectively located below the first electric field line and the second electric field line. Wherein, the first gate dicing pattern contacts and covers the first outermost surface of the first channel pattern, and The second gate dicing pattern contacts and covers the second outermost surface of the second channel pattern. Wherein, the first end of the gate electrode contacts the first gate dicing pattern, and the second end of the gate electrode contacts the second gate dicing pattern.

2. The semiconductor device according to claim 1, wherein, The gate electrode has a gate length from a first end to a second end of the gate electrode, and The gate length corresponds to the cell height of the logic cell.

3. The semiconductor device according to claim 1, wherein, The first active pattern includes a plurality of first channel patterns, and the first channel patterns are included in the plurality of first channel patterns. One of the plurality of first channel patterns includes a first side surface and a second side surface opposite to the first side surface. The outermost first channel pattern among the plurality of first channel patterns includes a first outermost surface and a third side surface opposite to the first outermost surface, and The gate electrode is located on the first side surface, the second side surface, and the third side surface.

4. The semiconductor device according to claim 1, wherein, The top surface of the first channel pattern includes: The first region overlaps with the gate electrode in the vertical direction; and The second region is covered with the first gate dicing pattern. The ratio of the width of the first region to the width of the first channel pattern is in the range of 0.1 to 0.

9.

5. The semiconductor device according to claim 1, wherein, The gate electrode includes a first gate electrode on the first channel pattern and a second gate electrode on the second channel pattern, and The length of the first gate electrode is different from the length of the second gate electrode.

6. The semiconductor device according to claim 5, further comprising: A third gate dicing pattern is located between the first gate electrode and the second gate electrode, wherein... The third gate dicing pattern includes an isolation pattern that fills the recessed region between the first active region and the second active region of the substrate.

7. The semiconductor device according to claim 5, wherein, The gate electrode also includes a bridge electrode. The bridge electrode is located on the first gate electrode and the second gate electrode to connect the first gate electrode and the second gate electrode to each other. The gate contact is connected to the bridge electrode.

8. The semiconductor device according to claim 1, wherein, Each of the first and second channel patterns includes a semiconductor pattern, which is stacked and spaced apart from each other in a vertical direction to provide a stacked semiconductor pattern. Each of the stacked semiconductor patterns includes a top surface, a bottom surface, a first side surface, and a second side surface opposite to the first side surface. The second side surface of the stacked semiconductor pattern of the first channel pattern constitutes the first outermost surface, and The second side surface of the stacked semiconductor pattern of the second channel pattern constitutes the second outermost surface.

9. The semiconductor device according to claim 8, wherein, The first gate diced pattern contacts and covers the second side surface of the stacked semiconductor pattern of the first channel pattern, and The second gate dicing pattern contacts and covers the second side surface of the stacked semiconductor pattern of the second channel pattern.

10. The semiconductor device according to claim 8, wherein, The gate electrode is located on the top surface, the bottom surface, and the first side surface of each of the stacked semiconductor patterns.

11. A semiconductor device, comprising: The substrate includes a first logic unit and a second logic unit, the first logic unit and the second logic unit being adjacent to each other in a first direction; The first active pattern, on the first logic unit, includes a pair of first source / drain patterns and a first channel pattern located therebetween. The second active pattern, on the second logic unit, includes a pair of second source / drain patterns and a second channel pattern located therebetween. The first gate electrode is on the first channel pattern; The second gate electrode is on the second channel pattern; A gate dicing pattern is located on the boundary between the first logic cell and the second logic cell, and the gate dicing pattern is between and contacts the first gate electrode and the second gate electrode. An active contact is electrically connected to at least one of the first source / drain pattern and the second source / drain pattern; The gate contact is electrically connected to the first gate electrode. as well as A metal layer is stacked on the active contact and the gate contact. The gate dicing pattern contacts and covers the first outermost surface of the first channel pattern and the second outermost surface of the second channel pattern.

12. The semiconductor device according to claim 11, wherein, The first active pattern includes a plurality of first channel patterns, and the first channel patterns are included in the plurality of first channel patterns. One of the plurality of first channel patterns includes a first side surface and a second side surface opposite to the first side surface. The outermost first channel pattern among the plurality of first channel patterns includes a first outermost surface and a third side surface opposite to the first outermost surface, and The first gate electrode is located on the first side surface, the second side surface, and the third side surface.

13. The semiconductor device according to claim 11, wherein, The top surface of the first channel pattern includes: A first region, overlapping the first gate electrode in the vertical direction; and The second region is covered with the gate dicing pattern. The ratio of the width of the first region to the width of the first channel pattern is in the range of 0.1 to 0.

9.

14. The semiconductor device according to claim 11, wherein, The first channel pattern includes semiconductor patterns that are stacked and spaced apart from each other in the vertical direction to provide a stacked semiconductor pattern. Each of the stacked semiconductor patterns includes a top surface, a bottom surface, a first side surface, and a second side surface opposite to the first side surface. The second side surface of the stacked semiconductor pattern constitutes the first outermost surface.

15. The semiconductor device according to claim 14, wherein, The first gate electrode is on the top surface, the bottom surface, and the first side surface of each of the stacked semiconductor patterns.

16. A semiconductor device, comprising: A substrate includes logic cells, the logic cells comprising PMOSFET regions and NMOSFET regions spaced apart from each other in a first direction. The logic unit has a first boundary, a second boundary, a third boundary, and a fourth boundary. The first boundary and the second boundary are opposite to each other in a second direction that intersects with the first direction, and the third boundary and the fourth boundary are opposite to each other in the first direction. A device isolation layer is provided on the substrate, the device isolation layer defining a first active pattern on the PMOSFET region and a second active pattern on the NMOSFET region, the first active pattern and the second active pattern extending along the second direction, the upper portion of each of the first active pattern and the second active pattern protruding over the device isolation layer; A gate electrode spans the first active pattern and the second active pattern, and the gate electrode extends along the first direction; The first source / drain pattern and the second source / drain pattern are respectively located above the first active pattern and the second active pattern, and each of the first source / drain pattern and the second source / drain pattern is adjacent to one side of the gate electrode. A separating structure, on at least one of the first boundary and the second boundary; The first gate dicing pattern and the second gate dicing pattern are respectively located on the third boundary and the fourth boundary. The first end of the gate electrode is in contact with the first gate dicing pattern, and the second end of the gate electrode is in contact with the second gate dicing pattern. Gate spacers on at least one side surface of the gate electrode; A gate capping pattern is formed on the top surface of the gate electrode; An interlayer insulating layer is present on the gate cap pattern; An active contact penetrates the interlayer insulation layer and is electrically connected to at least one of the first source / drain pattern and the second source / drain pattern; The gate contact penetrates the interlayer insulating layer and the gate capping pattern, and is electrically connected to the gate electrode. A first metal layer is provided on the interlayer insulating layer. The first metal layer includes a first power line and a second power line on the first gate dicing pattern and the second gate dicing pattern, respectively. The first metal layer also includes a first interconnect between the first power line and the second power line. The first interconnect is electrically connected to the active contact and the gate contact and is connected to the active contact and the gate contact, respectively. as well as A second metal layer on top of the first metal layer The second metal layer includes a second interconnect line electrically connected to the first metal layer. The upper portion of each of the first active pattern and the second active pattern includes a first side surface and a second side surface that are opposite each other. The first gate dicing pattern contacts and covers the second side surface of the first active pattern. The second gate dicing pattern contacts and covers the second side surface of the second active pattern, and The gate electrode is located on the first side surface of the first active pattern and the first side surface of the second active pattern.

17. The semiconductor device according to claim 16, wherein, The gate electrode has a gate length from the first end to the second end, and The gate length corresponds to the cell height of the logic cell.

18. The semiconductor device according to claim 16, wherein, The upper part of the first active pattern includes multiple channel patterns. One of the plurality of channel patterns includes a third side surface and a fourth side surface that are opposite to each other. The outermost channel pattern among the plurality of channel patterns includes the first side surface and the second side surface, and The gate electrode is located on the third side surface and the fourth side surface.

19. The semiconductor device according to claim 16, wherein, The top surface of the first active pattern includes: The first region overlaps with the gate electrode in the vertical direction; and The second region is covered by the first gate dicing pattern. The ratio of the width of the first region to the width of the first active pattern is in the range of 0.1 to 0.

9.

20. The semiconductor device according to claim 16, wherein, The gate electrode includes a first gate electrode on the first active pattern and a second gate electrode on the second active pattern, and The length of the first gate electrode is different from the length of the second gate electrode.

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