Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the semiconductor structure comprising: a groove penetrating a floating gate and a partial thickness substrate, comprising a main groove located in a cell array region, a first offset groove located in an adjacent side selection gate region, a first transition groove located in a first transition region, and a first groove arranged in a row direction with intervals from the first offset groove, the first transition groove having a first transition sidewall and a second transition sidewall corresponding to the first side and the second side along the row direction, respectively, and the first groove having a secondary sidewall opposite to the second transition sidewall; a first reference edge and a second reference edge located in the first transition region and arranged parallel to the second transition sidewall; the first transition sidewall is located on the first side of the first reference edge along the row direction; or, the secondary sidewall is located on the side of the second reference edge away from the second transition sidewall; or, the first transition sidewall is located on the first side of the first reference edge along the row direction and the secondary sidewall is located on the side of the second reference edge away from the second transition sidewall. The present invention improves the performance of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the development of semiconductor process technology, flash memory with faster access speed has been developed in storage devices. Flash memory is also called flash memory. The main feature of flash memory is that it can retain stored information for a long time without power supply. It has the advantages of high integration, fast access speed, easy erasing and reading and writing, so it has become the mainstream memory of non-volatile memory (NVM).

[0003] According to the different structures, flash memory is divided into NOR Flash Memory and NAND Flash Memory. NOR flash uses memory random read technology. Each unit is connected in parallel, and the storage unit is uniformly addressed (with independent address lines), so any word can be accessed randomly. In the NOR flash array, when a word line is selected, the M NVM units originally connected to the word are all activated. On the other hand, the other NVM units connected to the unselected word lines are electrically separated from the M bit lines. Through the connected M bit lines, the current changes of the drains of the M selected NVM units can be detected. Because the bias and signal in the NOR flash array are directly applied to the electrodes of the selected NVM cells, generally speaking, the NOR flash array has a faster read access speed and a lower operating voltage than the NAND flash array. Also, because the NOR flash array has dedicated address pins for addressing, it is easier to connect to other chips and supports local execution.

[0004] A NOR flash array is currently proposed, which includes a plurality of NOR cells, wherein the paired drains of the plurality of NOR cells form a plurality of diffused sub-bit lines, and the diffused sub-bit lines are separated by trench field isolation regions. The diffused sub-bit lines are twisted along the extension direction of the trench field isolation regions in a manner less than or equal to a column pitch, so that the diffused sub-bit lines can connect the diffusion lines of their sub-feature size (whose feature size is less than the minimum feature size F) to a plurality of full feature size diffusion regions, and a plurality of full feature size contacts can be set on the full feature size diffusion regions. In this NOR flash array, the area of ​​the NVM cell can be only 4F. 2 (where F is the minimum feature size feature), which is beneficial to improving the storage unit area density.

[0005] However, the performance of current NOR flash array devices still needs to be improved. Summary of the invention

[0006] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are beneficial to improving the performance of a NOR flash array device.

[0007] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate, comprising a plurality of discrete cell array regions, for forming storage cells; the substrate further comprising a selection gate region located between the cell array regions along the column direction, and a first transition region located between the cell array region and an adjacent side selection gate region along the column direction; a floating gate located on the substrate; a plurality of grooves extending along the column direction and arranged along the row direction, penetrating the floating gate and a portion of the thickness of the substrate, the grooves comprising a main groove located in the cell array region, a first offset groove located in the adjacent side selection gate region, and a first transition groove located between the main groove and the first offset groove, the first transition groove having a first transition sidewall along the first side of the row direction and a second transition sidewall along the second side of the row direction, the first offset groove being offset toward the first side along the row direction relative to the main groove; the groove further comprising a groove spaced from the first offset groove along the row direction A first groove is arranged, the first groove has a secondary side wall located in the first transition region opposite to the second transition side wall; a first reference edge and a second reference edge are set in the first transition region and parallel to the second transition side wall, respectively corresponding to the first side and the second side of the second transition side wall along the row direction, the first reference edge connects the side walls of the main groove and the first offset groove along the first side of the row direction, and the second reference edge connects the side wall of the first groove located in the selection gate region along the first side of the row direction; wherein the first transition side wall is located on the first side of the first reference edge along the row direction; or, the secondary side wall is located on the side of the second reference edge away from the second transition side wall; or, the first transition side wall is located on the first side of the first reference edge along the row direction, and the secondary side wall is located on the side of the second reference edge away from the second transition side wall; an isolation structure is located in the groove.

[0008] Accordingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a plurality of discrete cell array regions for forming storage cells; the substrate further comprising a selection gate region located between the cell array regions along the column direction, and a first transition region located between the cell array region and an adjacent side selection gate region along the column direction; forming a floating gate on the substrate; patterning the floating gate and a portion of the thickness of the substrate to form a plurality of grooves extending along the column direction and arranged along the row direction, the grooves comprising a main groove located in the cell array region, a first offset groove located in the adjacent side selection gate region, and a first transition groove located between the main groove and the first offset groove, the first transition groove having a first transition sidewall along the first side of the row direction and a second transition sidewall along the second side of the row direction, the first offset groove being offset toward the first side relative to the main groove along the row direction; the groove further comprising a groove extending in the row direction and extending in the direction from the first offset groove. A first groove is arranged at intervals, wherein the first groove has a secondary side wall located in the first transition region opposite to the second transition side wall; a first reference edge and a second reference edge are set in the first transition region and parallel to the second transition side wall, respectively corresponding to the first side and the second side of the second transition side wall along the row direction, the first reference edge connects the side walls of the main groove and the first offset groove along the first side of the row direction, and the second reference edge connects the side wall of the first groove located in the selection gate region along the first side of the row direction; wherein the first transition side wall is located on the first side of the first reference edge along the row direction; or, the secondary side wall is located on the side of the second reference edge away from the second transition side wall; or, the first transition side wall is located on the first side of the first reference edge along the row direction, and the secondary side wall is located on the side of the second reference edge away from the second transition side wall; an isolation structure is formed in the groove.

[0009] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0010] In the semiconductor structure provided by an embodiment of the present invention, the first transition sidewall is located on the first side of the first reference edge along the row direction; or, the secondary sidewall is located on the side of the second reference edge away from the second transition sidewall; or, the first transition sidewall is located on the first side of the first reference edge along the row direction, and the secondary sidewall is located on the side of the second reference edge away from the second transition sidewall; compared with the position where the first transition sidewall is located at the first reference edge, when the first transition sidewall is located on the first side of the first reference edge along the row direction, the first transition groove has a larger space along the row direction; compared with the position where the secondary sidewall of the first groove is located at the second reference edge, when the secondary sidewall of the first groove is located on the side of the second reference edge away from the second transition sidewall, the second sidewall of the second transition sidewall is located on the second side of the second reference edge along the row direction. The size of the floating gate and the substrate is larger; the process of forming the groove includes forming a mask layer that patterns the floating gate and the partial thickness substrate, and a mask opening for defining the groove pattern is formed in the mask layer. The mask layer is usually formed by a photolithography process. The embodiment of the present invention increases the space of the first transition groove along the row direction, or increases the size of the floating gate and the substrate located on the second side of the second transition sidewall along the row direction, and correspondingly increases the size of the mask opening at the corresponding position, which is beneficial to increase the process window of the photolithography process for forming the mask layer, for example: alleviating the limitation of the resolution of the photolithography process, improving the optical proximity effect, etc., thereby helping to reduce the process difficulty of forming the groove, improve the accuracy of pattern transfer, and also help to improve the pattern accuracy and morphology quality of the groove, and correspondingly improve the performance of the semiconductor structure.

[0011] In addition, the embodiment of the present invention makes the first transition side wall located on the first side of the first reference edge in the row direction, or makes the secondary side wall located on the side of the second reference edge away from the second transition side wall. Compared with the first transition side wall being located at the first reference edge, the secondary side wall being located at the second reference edge, and increasing the area of ​​the first transition zone along the column direction to increase the spacing between the side walls of the first transition groove, the embodiment of the present invention avoids increasing the area of ​​the first transition zone, thereby avoiding an increase in the invalid area, which is beneficial to improving the utilization rate of the wafer area. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic diagram of the structure of a semiconductor structure;

[0013] Figure 2 Shown with Figure 1 A design pattern corresponding to the semiconductor structure shown, and a mask pattern after optical proximity correction simulation is performed on the design pattern;

[0014] Figure 3 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0015] Figures 4 to 10 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0016] The devices currently formed still have the problem of poor performance. The reasons for the poor performance of the devices are now analyzed in combination with a semiconductor structure. Figure 1 It is a structural diagram of a semiconductor structure.

[0017] The semiconductor structure comprises: a substrate 1, comprising a plurality of discrete cell array regions C for forming memory cells; the substrate further comprises a plurality of cell array regions C along a column direction (e.g. Figure 1 The select gate region S is located between the cell array regions C along the column direction (shown in the y direction); the transition region I is located between the cell array region C and the select gate region S on the adjacent side along the column direction; the floating gate 2 is located on the substrate 1; a plurality of lines extending along the column direction and along the row direction (as shown in the y direction) Figure 1 The present invention relates to a groove arranged along the x direction (as shown in the x direction), which penetrates the floating gate 2 and a partial thickness of the substrate 1, wherein the groove comprises a main groove 3 located in the cell array area C, an offset groove 4 located in the adjacent side selection gate area S, and a transition groove 5 located between the main groove 3 and the offset groove 4, wherein the offset groove 4 is offset toward the first side along the row direction relative to the main groove 3, and the transition groove 5 has a first transition sidewall 51 on the first side along the row direction and a second transition sidewall 52 on the second side along the row direction, wherein the first transition sidewall 51 is parallel to and opposite to the second transition sidewall 52; the groove further comprises a secondary groove 6 arranged at intervals with the offset groove 4 along the row direction, wherein the secondary groove 6 comprises a secondary sidewall 63 opposite to the second transition sidewall 52 of the transition groove 5, and wherein the secondary sidewall 63 is parallel to the second transition sidewall 52.

[0018] The trench is used to provide a spatial position for forming an isolation structure. The trench is formed by patterning the floating gate 2 and a partial thickness substrate 1 using a mask layer as a mask, and the mask layer is usually formed by a photolithography process.

[0019] like Figure 1 As shown, the first transition side wall 51 of the transition groove 5 is parallel to the second transition side wall 52. When the cell array area C transitions to the selection gate area S, the structure of the active area (AA) and the groove will turn in the row direction at a certain angle, that is, the first transition side wall 51 or the second transition side wall 52 of the transition groove 5 has an angle with the column direction. Therefore, compared with the width dimension of the main groove 3 along the row direction, the space (Space) S between the first transition side wall 51 and the second transition side wall 52 of the transition groove 5 is smaller (the space S refers to the minimum distance between the first side wall 51 and the second side wall 52).

[0020] However, in the actual photolithography process, due to the influence of the optical proximity effect (Optical Proximity Correction) or the limitation of the resolution of the photolithography process, it is easy to cause the size of the mask layer at the position corresponding to the interval to be smaller than the designed interval. After the pattern of the mask layer is transferred to the substrate 1 and the floating gate 2, the interval S of the transition groove 5 will be significantly smaller than the designed size, which can easily cause the substrate 1 on both sides of the transition groove 5 to contact (Bridge), or cause the floating gate 2 on both sides of the transition groove 5 to contact, thereby causing the shape and size of the groove to fail to meet the design requirements.

[0021] For example, Figure 2 As shown, Figure 2 Shown with Figure 1 The design pattern 7 corresponding to the semiconductor structure shown in FIG. 2 and the mask pattern 8 after the optical proximity correction (OPC) simulation of the design pattern 7 are shown in FIG. 2 . As can be seen from FIG. 2 , the interval of the mask layer at the corresponding position of the transition groove 5 is smaller than the design interval (such as Figure 2 The graphics on both sides of the corresponding positions of the transition groove 5 are easily in contact with each other (as shown by the dotted circle in the middle).

[0022] The width L of the offset groove 4 along the row direction corresponds to the minimum dimension of the process. The width L of the offset groove 4 along the row direction is usually difficult to increase. Figure 1 The length H of the triangle shown in the transition area I of the secondary groove 6 is related, and the interval S is equal to the height T of the triangle, and the interval S becomes longer with the side length of H.

[0023] Therefore, in the current process, the interval S is usually increased by increasing the length H of the triangle to reduce the probability of contact between the substrate 1 or the floating gate 2 located on both sides of the transition groove 5 in the actual process. However, increasing the length H of the triangle correspondingly increases the area of ​​the transition region I along the column direction, and the transition region I does not form a device, which easily leads to an increase in the invalid area, thereby reducing the area utilization rate of the wafer surface.

[0024] In order to solve the technical problem, in the semiconductor structure provided by the embodiment of the present invention, the first transition sidewall is located on the first side of the first reference edge in the row direction; or, the secondary sidewall is located on the side of the second reference edge away from the second transition sidewall; or, the first transition sidewall is located on the first side of the first reference edge in the row direction, and the secondary sidewall is located on the side of the second reference edge away from the second transition sidewall; compared with the position where the first transition sidewall is located at the first reference edge, when the first transition sidewall is located on the first side of the first reference edge in the row direction, the first transition groove has a larger space along the row direction; compared with the position where the secondary sidewall of the first groove is located at the second reference edge, when the secondary sidewall of the first groove is located on the side of the second reference edge away from the second transition sidewall, the second transition sidewall The size of the floating gate and the substrate along the second side of the row direction is larger; the process of forming the groove includes forming a mask layer that patterns the floating gate and a partially thick substrate, and a mask opening for defining the groove pattern is formed in the mask layer. The mask layer is usually formed by a photolithography process. The embodiment of the present invention increases the space of the first transition groove along the row direction, or increases the size of the floating gate and the substrate located on the second side of the second transition sidewall along the row direction, and correspondingly increases the size of the mask opening at the corresponding position, which is beneficial to increase the window of the photolithography process for forming the mask layer, for example: alleviating the limitation of the resolution of the photolithography process, improving the optical proximity effect, etc., which is beneficial to reducing the process difficulty of forming the groove, improving the accuracy of pattern transfer, and also beneficial to improving the pattern accuracy and morphology quality of the groove, and correspondingly improving the performance of the semiconductor structure.

[0025] In addition, the embodiment of the present invention makes the first transition side wall located on the first side of the first reference edge in the row direction, or makes the secondary side wall located on the side of the second reference edge away from the second transition side wall. Compared with the first transition side wall being located at the first reference edge, and the secondary side wall being located at the second reference edge, and increasing the area of ​​the first transition zone along the column direction to increase the spacing between the side walls of the first transition groove, the embodiment of the present invention avoids increasing the area of ​​the first transition zone, thereby avoiding an increase in the invalid area, which is beneficial to improving the utilization rate of the wafer area.

[0026] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. Figure 5 and Figure 6 ,refer to Figure 3 , shows a schematic diagram of a semiconductor structure according to an embodiment of the present invention. Figure 3 a is the top view, Figure 3 b is Figure 3 a Cross-sectional view at position dd.

[0027] The semiconductor structure comprises: a substrate 100, comprising a plurality of discrete cell array regions C for forming storage cells; the substrate 100 further comprising a selection gate region S located between the cell array regions C along the column direction, and a first transition region I located between the cell array region C and the adjacent selection gate region S along the column direction; a floating gate 110 located on the substrate 100; a plurality of grooves (not shown) extending along the column direction and arranged along the row direction, penetrating the floating gate 110 and a portion of the thickness of the substrate 100, the grooves comprising a main groove 200 located in the cell array region C, ... The main groove 200 includes a first offset groove 210, and a first transition groove 230 located between the main groove 200 and the first offset groove 210, wherein the first transition groove 230 has a first transition sidewall 31 on the first side along the row direction and a second transition sidewall 32 on the second side along the row direction, and the first offset groove 210 is offset toward the first side along the row direction relative to the main groove 200; the groove further includes a first secondary groove 250 arranged in the row direction with the first offset groove 230 at intervals, and the first secondary groove 250 has a secondary sidewall 30 located in the first transition area I and opposite to the second transition sidewall 32. In this embodiment, the secondary sidewall 30 serves as the first secondary sidewall 30.

[0028] A first reference edge 10 and a second reference edge 20 are set in parallel to the first transition region I and the second transition sidewall 32, which correspond to the first side and the second side of the second transition sidewall 32 along the row direction respectively, the first reference edge 10 connects the sidewalls of the main groove 200 and the first offset groove 210 along the first side of the row direction, and the second reference edge 20 connects the sidewall of the first first groove 250 located at the first side of the selection gate region S along the row direction; the first transition sidewall 31 is located at the first side of the first reference edge 10 along the row direction; or, the first first sidewall 30 is located on the side of the second reference edge 20 away from the second transition sidewall 32; or, the first transition sidewall 31 is located on the first side of the first reference edge 10 along the row direction, and the first first sidewall 30 is located on the side of the second reference edge 20 away from the second transition sidewall 32; an isolation structure 300 is located in the groove.

[0029] Compared with the position where the first transition sidewall is located at the first reference edge, when the first transition sidewall 31 is located at the first side of the first reference edge 10 along the row direction, the first transition groove 230 has a larger space along the row direction; compared with the position where the first sidewall of the first groove is located at the second reference edge, when the first sidewall 30 is located on the side of the second reference edge 20 away from the second transition sidewall 32, the size of the floating gate 110 and the substrate 100 located on the second side of the second transition sidewall 32 along the row direction is larger; the process of forming the groove includes forming a mask layer for patterning the floating gate 110 and a partial thickness substrate 100, wherein the mask layer is formed with The mask opening used to define the groove pattern, the mask layer is usually formed by a photolithography process. In this embodiment, the space of the first transition groove 230 along the row direction is increased, or the size of the floating gate 110 and the substrate 100 located on the second side of the second transition sidewall 32 along the row direction is increased, and the width size of the mask opening at the corresponding position is correspondingly increased, which is beneficial to increase the process window of the photolithography process for forming the mask layer, for example: alleviating the limitation of the resolution of the photolithography process, improving the optical proximity effect, etc., and then it is beneficial to reduce the process difficulty of forming the groove, which is correspondingly beneficial to improve the accuracy of the pattern transfer, and improve the pattern accuracy and morphology quality of the groove.

[0030] In addition, this embodiment makes the first transition side wall 31 located on the first side of the first reference edge 10 along the row direction, or makes the first side wall 30 located on the side of the second reference edge 20 away from the second transition side wall 32. Compared with the side wall of the first transition groove along the second side of the row direction being located at the position of the first reference edge, and the first side wall being located at the position of the second reference edge, and increasing the area of ​​the first transition zone along the column direction to increase the spacing between the side walls of the first transition groove, this embodiment avoids increasing the area of ​​the first transition zone I, thereby avoiding an increase in the invalid area, which is beneficial to improving the utilization rate of the wafer area.

[0031] The substrate 100 provides a process platform for forming a NOR Flash Memory. Specifically, in this embodiment, the substrate 100 is used to form a 4F 2 In this NOR flash array, the area of ​​the NVM cell can be only 4F. 2 (where F is the minimum feature size feature), which is beneficial to improving the storage unit area density.

[0032] The cell array region C is used to form memory cells. The select gate region S is located between the cell array regions C along the column direction and is used to form a select gate (SG).

[0033] The first transition region I is used to connect the cell array region C and the adjacent selection gate region S.

[0034] In this embodiment, the substrate 100 further includes a second transition region II located along the column direction between the cell array region C and the adjacent other side selection gate region S. The first transition region I and the adjacent selection gate region S constitute a first selection gate unit (not labeled); the second transition region II and the adjacent selection gate region S constitute a second selection gate unit (not labeled), and the second selection gate unit and the first selection gate unit are symmetrical about the center of the cell array region C.

[0035] In this embodiment, the base 100 includes a substrate. As an example, the substrate is a silicon substrate.

[0036] The floating gate 110 is used to form a floating gate structure later. When the NOR flash memory is working, the floating gate structure can capture and store electrons, and after power failure, the electrons stored in the floating gate structure will not be lost, and the amount of charge stored in the floating gate structure can change the conduction voltage of the field effect tube, and different conduction voltages can represent different states, thereby realizing information storage.

[0037] In this embodiment, the floating gate 110 is made of polysilicon.

[0038] In this embodiment, the semiconductor structure further includes: a tunneling oxide layer 101 located on the substrate 100, which is used to isolate the floating gate 110 from the substrate 100, and the tunneling oxide layer 101 is also used to provide a tunneling channel for electrons from the substrate 100 to the floating gate structure. In this embodiment, the material of the tunneling oxide layer 101 is silicon oxide.

[0039] In this embodiment, the semiconductor structure further includes: a stress buffer layer 102 located on the floating gate 110, and a hard mask layer 120 located on the stress buffer layer 102. The stress buffer layer 102 is used to provide a buffering effect when the hard mask layer 120 is formed, which is beneficial to reduce the probability of dislocation problems when the hard mask layer 120 is directly formed on the floating gate 110. In this embodiment, the material of the stress buffer layer 102 is silicon oxide.

[0040] The hard mask layer 120 is used as a mask for etching the floating gate 110 and a portion of the thickness of the substrate 100 to form a trench. In this embodiment, the material of the hard mask layer 120 is silicon nitride.

[0041] The trench is used to provide a spatial position for forming the isolation structure 300, and the trench is also used to define the active area and the isolation area of ​​the substrate 100. The substrate 100 isolated by the trench serves as the active area, and the remaining area serves as the isolation area.

[0042] The groove includes a bottom groove 10 (eg, Figure 4 ) and a top trench 20 located on the bottom trench 10, the top trench 20 is connected to the bottom trench 10. The bottom trench 10 provides a spatial position for forming an isolation structure 300.

[0043] The main trench 200 is used to isolate the active area of ​​the cell array region C, and the main trench 200 provides a space for forming the main extension of the isolation structure 300. The first offset trench 210 is used to isolate the active area of ​​the select gate region S, and the first offset trench 210 is used to provide a space for forming the first offset extension of the isolation structure 300. The first transition trench 230 is used to connect the first offset trench 210 and the main trench 200. Subsequently, the first transition extension of the isolation structure 300 is formed in the first transition trench 230.

[0044] In this embodiment, the first offset groove 210 is offset toward the first side along the row direction relative to the main groove 200, so the first transition groove 230 is bent toward the first side along the row direction relative to the main groove 200. Specifically, in this embodiment, an angle is formed between the second transition sidewall 32 and the sidewall of the main groove 200. The sidewall of the main groove 200 extends along the column direction, and an angle is formed between the second transition sidewall 32 and the column direction.

[0045] In this embodiment, the angle between the second transition sidewall 32 and the column direction is a reference angle θ.

[0046] The first reference side 10 and the second reference side 20 are both parallel to the second transition side wall 32 , so the angle between the first reference side 10 or the second reference side 20 and the column direction is also the reference angle θ.

[0047] In this embodiment, the angle between the first transition sidewall 31 of the first transition groove 230 and the first reference edge 10 is greater than 0° and less than or equal to the reference angle θ.

[0048] The angle between the first transition side wall 31 and the first reference edge 10 is greater than 0°, so that the first transition side wall 31 is further away from the second transition side wall 32 relative to the first reference edge 10, and the first transition side wall 31 is deflected toward the first side along the row direction relative to the first reference edge 10, and the space of the first transition groove 230 along the row direction is correspondingly increased; the angle between the first transition side wall 31 and the first reference edge 10 is less than or equal to the reference angle θ, so as to ensure that the first transition side wall 31 will not be relative to the side wall of the first offset groove 210 along the first side of the row direction. The first side of the row direction is deflected to prevent the graphic structure of the first transition groove 230 along the first side of the row direction from being affected. The semiconductor structure also includes a source region 500 in the active area substrate 100 located between adjacent main grooves 200 along the row direction. The source region 500 also extends along the column direction to the first side of the first transition groove 230 along the row direction. The angle between the first transition side wall 31 and the first reference edge 10 is less than or equal to the reference angle θ, so it is beneficial to prevent the source region 500 from being affected, which is correspondingly beneficial to improving process compatibility and reducing process risks.

[0049] As an example, the first transition sidewall 31 is located on the first side of the first reference edge 10 along the row direction, and the first transition sidewall 31 is flush with the sidewall of the first offset groove 210, that is, the angle between the first transition sidewall 31 and the first reference edge 10 is θ, and the first transition sidewall 31 is parallel to the column direction.

[0050] Accordingly, in the present embodiment, the first transition groove 230 is composed of a parallel groove (not shown) formed by the second transition sidewall 32 and the first reference edge 10, and a triangular groove formed by the first reference edge 10 and the first transition sidewall 31. The parallel groove is a parallelogram structure, and the triangular groove is a right-angled triangle structure. The triangular groove also includes a side wall opposite to the angle between the first reference edge 10 and the first transition sidewall 31, and the side wall opposite to the angle between the first reference edge 10 and the first transition sidewall 31 is parallel to the row direction, thereby preventing the first transition groove 230 from being located on the unit array area C, and correspondingly preventing adverse effects on the graphics of the unit array area C, and also helping to reduce the pattern complexity of the first transition groove 230.

[0051] The first sub-groove 250 is located in the selection gate region S and is used to isolate the active regions located on both sides of the first sub-groove 250 along the row direction. The first sub-groove 250 is also used to provide a formation space for the first extension portion of the isolation structure 300. In this embodiment, the angle between the first sub-sidewall 30 and the second reference edge 20 is greater than 0° and less than or equal to the complementary angle of the reference angle θ.

[0052] The angle between the first sidewall 30 and the second reference edge 20 is greater than 0°, so that the first sidewall 30 is farther away from the second transition sidewall 32 relative to the second reference edge 20, and the first transition sidewall 31 is deflected toward the first side along the row direction relative to the first reference edge 10, correspondingly increasing the size of the substrate 100 and the floating gate 110 located on the second side of the second transition sidewall 32 along the row direction; the angle between the first sidewall 30 and the second reference edge 20 is less than or equal to the complementary angle of the reference angle θ, thereby ensuring that while increasing the size of the substrate 100 and the floating gate 110 on the second side of the second transition sidewall 32 along the row direction, the first sidewall 30 is at most perpendicular to the column direction, and will not be closer to the selection gate area S on this basis, correspondingly ensuring the first extension portion located in the selection gate area S to isolate adjacent active areas along the row direction.

[0053] It should be noted that in the actual process, taking into account process deviations and increasing the process window for forming the grooves, the first side wall 30 may have a certain error angle with the row direction, and when a selection gate is formed on the selection gate region S, there is a certain distance between the edge of the selection gate and the first transition region I. Therefore, even if there is an error angle between the first side wall 30 and the row direction, the impact on the performance of the semiconductor structure is relatively small.

[0054] In this embodiment, the first sidewall 30 is located on the side of the second reference edge 20 away from the second transition sidewall 32, the first sidewall 30 is perpendicular to the column direction, and the angle between the first sidewall 30 and the second reference edge 20 is equal to the complementary angle of the reference angle, that is, the first trench 250 is a rectangular structure trench located in the selection gate region S, which is conducive to reducing the pattern complexity of the first trench 250 and correspondingly reducing the process difficulty of forming the first trench 250. Accordingly, in this embodiment, the first sidewall 30 is located at the junction between the first transition region I and the selection gate region S along the column direction.

[0055] It should be noted that, in this embodiment, the shapes of the first groove 250 and the first transition groove 230 and the positions of the sidewalls are only used as an example. In other embodiments, the shapes and positions of the first groove and the first transition groove are not limited to these, as long as the following conditions are met: the first transition sidewall is located on the first side of the first reference edge in the row direction; or, the first sidewall is located on the side of the second reference edge away from the second transition sidewall; or, the first transition sidewall is located on the first side of the first reference edge in the row direction, and the first sidewall is located on the side of the second reference edge away from the second transition sidewall.

[0056] In this embodiment, the substrate 100 also includes a second transition region II located along the column direction between the cell array region C and the adjacent selection gate region S on the other side. The first transition region I and the adjacent selection gate region S constitute a first selection gate unit (not marked); the second transition region II and the adjacent selection gate region S constitute a second selection gate unit (not marked), and the second selection gate unit and the first selection gate unit are symmetrical about the center of the cell array region C.

[0057] Accordingly, in this embodiment, the trench further includes a second offset trench 220 located in the selection gate region S on the other side adjacent to the cell array region C, and a second transition trench 240 located between the main trench 200 and the second offset trench 220, and the second offset trench 220 is offset toward the second side along the row direction relative to the main trench 200.

[0058] The second transition groove 240 has a third transition sidewall 41 on the first side along the row direction and a fourth transition sidewall 42 on the second side along the row direction; the second secondary groove 260 has a second secondary sidewall 60 located in the second transition region II opposite to the third transition sidewall 41 .

[0059] A third reference edge 61 and a fourth reference edge 62 are set in parallel with the third transition side wall 41 in the second transition region II, corresponding to the second side and the first side of the third transition side wall 41 along the row direction, respectively. The third reference edge 61 connects the side walls of the main groove 200 and the second offset groove 220 along the second side of the row direction, and the fourth reference edge 62 connects the side wall of the second secondary groove 260 located in the selection gate region S along the second side of the row direction.

[0060] Similarly, in this embodiment, the fourth transition side wall 42 is located on the second side of the third reference edge 61 along the row direction; or, the second side wall 60 is located on the side of the fourth reference edge 62 away from the third transition side wall 41; or, the fourth transition side wall 42 is located on the second side of the third reference edge 61 along the row direction, and the second side wall 60 is located on the side of the fourth reference edge 62 away from the third transition side wall 41.

[0061] Accordingly, compared with the position where the fourth transition sidewall is located at the third reference edge, when the fourth transition sidewall 42 is located at the second side of the third reference edge 61 along the row direction, the space of the second transition groove 240 along the row direction can be increased; compared with the position where the second sidewall is located at the fourth reference edge, when the second sidewall 60 is located on the side of the fourth reference edge 62 away from the third transition sidewall 41, the size of the floating gate 110 and the substrate 100 located on the first side of the second transition groove 240 along the row direction can be increased; therefore, the size of the mask layer used to form the groove is also correspondingly larger at the corresponding position, thereby increasing the window of the photolithography process when forming the groove.

[0062] The detailed description of the second transition groove 240 and the second secondary groove 260 can be analogously referred to the aforementioned specific description of the first transition groove 230 and the first secondary groove 250 , and will not be repeated here.

[0063] The isolation structure 300 is used to isolate adjacent devices in a row direction. Specifically, the isolation structure 300 is used to isolate adjacent active regions.

[0064] The isolation structure 300 includes a main extension portion (not labeled) located in the main groove 200, a first offset extension portion (not labeled) located in the first offset groove 210, a second offset extension portion (not labeled) located in the second offset groove 220, a first transition extension portion (not labeled) located in the first transition groove 230, and a second transition extension portion (not labeled) located in the second transition groove 240.

[0065] In this embodiment, the isolation structure 300 further includes a first extension portion (not labeled) located in the first trench 250 and a second extension portion (not labeled) located in the second trench 260 .

[0066] In this embodiment, the isolation structure 300 is formed in the bottom trench 10. In this embodiment, the isolation structure 300 is a shallow trench isolation structure, and the material of the isolation structure 300 is silicon oxide.

[0067] In this embodiment, the semiconductor structure also includes: an opening 400 extending in the column direction, located in the floating gate 110 between adjacent main extensions, the opening 400 penetrating the cell array region C, the adjacent first transition region I and second transition region II, and a portion of the selection gate region S in the column direction; a first drain region 510, located in the substrate 100 along the second side wall of the main extension, the first transition extension, and a portion of the first offset extension in the row direction; a second drain region 520, located in the substrate 100 along the first side wall of the main extension, the second transition extension, and a portion of the second offset extension in the row direction; a source region 500, located in the substrate 100 below the opening 400 of the cell array region C, the first transition region I and the second transition region II, and a portion of the selection gate region S.

[0068] The bottom of the opening 400 is used to define a formation region of the source region 500 .

[0069] In this embodiment, the opening 400 also extends along the column direction to a portion of the selection gate region S adjacent to the first transition region I and a portion of the selection gate region S adjacent to the second transition region II. Therefore, the source region 500 can also extend to the selection gate region S to be connected to the selection gate.

[0070] In this embodiment, the opening 400 that also extends along the column direction to the portion of the selection gate region S adjacent to the first transition region I is located between the first offset extension portion and the first extension portion adjacent to the first side along the row direction; the opening 400 that also extends along the column direction to the portion of the selection gate region S adjacent to the second transition region II is located between the second offset extension portion and the second extension portion adjacent to the second side along the row direction.

[0071] In this embodiment, the tunnel oxide layer 101 is exposed at the bottom of the opening 400 . The tunnel oxide layer 101 can protect the substrate 100 during ion implantation to form the source region 500 or the drain region, thereby reducing implantation damage to the substrate 100 caused by ion implantation.

[0072] As can be seen from the foregoing, this embodiment increases the space of the first transition groove 230 along the row direction or increases the size of the floating gate 110 and the substrate 100 located on the second side of the first transition groove 230 along the row direction, and correspondingly increases the width size of the mask opening at the corresponding position, which is beneficial to increase the process window of the lithography process for forming the mask layer and reduce the process difficulty of forming the groove, which is correspondingly beneficial to improve the accuracy of graphic transfer, the graphic accuracy and morphology quality of the groove, and is beneficial to prevent the active areas located on both sides of the first transition groove 230 from contacting each other, thereby preventing the first drain area 510 located on the second side of the first transition extension along the row direction from contacting the active area located on the first side of the first transition extension along the row direction, thereby ensuring the isolation effect of the first transition extension, and correspondingly improving the performance of the semiconductor structure.

[0073] Similarly, this embodiment increases the space of the second transition groove 240 along the row direction, or increases the size of the floating gate 110 and the substrate 100 located on the first side of the third transition side wall 41 along the row direction, which is also beneficial to increase the window of the photolithography process when forming the groove, and is beneficial to prevent the active areas located on both sides of the second transition groove 240 from contacting each other, thereby preventing the second drain area 520 located on the first side of the second transition extension along the row direction and the active area located on the second side of the second transition extension along the row direction from contacting each other, thereby ensuring the isolation effect of the second transition extension and correspondingly improving the performance of the semiconductor structure.

[0074] In the present embodiment, the first drain region 510 is used to form a first drain sub-bit line. The first drain region 510 extends along the side wall of the main extension portion and the first transition extension portion along the second side of the row direction. The first drain region 510 also extends to a portion of the substrate 100 along the side wall of the first offset extension portion adjacent to the first transition extension portion along the second side of the row direction, so that the first drain region 510 extends to a portion of the selection gate region S adjacent to the first transition region I, thereby connecting the storage unit corresponding to the first drain sub-bit line to the selection gate.

[0075] In the present embodiment, the second drain region 520 is used to form a second drain sub-bit line. The second drain region 520 extends along the side wall of the main extension portion and the second transition extension portion along the first side of the row direction. The second drain region 520 also extends to a portion of the substrate 100 along the side wall of the second offset extension portion adjacent to the second transition extension portion along the first side of the row direction, so that the second drain region 520 extends to a portion of the selection gate region S adjacent to the second transition region II, thereby connecting the storage unit corresponding to the second drain sub-bit line to the selection gate.

[0076] The source region 500 is used as a common source region (Common Source). The source region 500 is located in the substrate 100 below the opening 400, and the source region 500 extends along the column direction.

[0077] In this embodiment, the doping depths of the first drain region 510, the second drain region 520 and the source region 500 in the substrate 100 are less than the depth of the isolation structure 300, so that the first drain region 510 and the source region 500, the first drain region 510 and the second drain region 520, and the second drain region 520 and the source region 500 can be isolated by the isolation structure 300.

[0078] When forming an NMOS device, the doping ions of the first drain region 510, the second drain region 520 and the source region 500 are N-type ions; when forming a PMOS device, the doping ions of the first drain region 510, the second drain region 520 and the source region 500 are P-type ions.

[0079] In this embodiment, for the convenience of illustration and description, only the tunnel oxide layer 101 is illustrated in the cross-sectional view.

[0080] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 4 to 10 The following is a structural schematic diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. The specific embodiment of the method for forming a semiconductor structure of the present invention is described in detail in conjunction with the accompanying drawings.

[0081] refer to Figure 4 , Figure 4 a is the top view, Figure 4 b is Figure 4 a along the row direction (such as Figure 4 a), providing a substrate 100, including a plurality of discrete cell array regions C for forming memory cells; the substrate 100 also includes a cell array region C along the column direction (such as Figure 4 a) a selection gate region S located between the cell array regions C, and a first transition region I located between the cell array region C and the selection gate region S on one side of the cell array region C along the column direction.

[0082] The substrate 100 provides a process platform for forming a NOR Flash Memory. Specifically, in this embodiment, the substrate 100 is used to form a 4F 2 In this NOR flash array, the area of ​​the NVM cell can be only 4F. 2 (where F is the minimum feature size feature), which is beneficial to improving the storage unit area density.

[0083] The cell array region C is used to form a storage cell. The select gate region S is located between the cell array regions C along the column direction and is used to form a select gate (SG). Subsequently, a main trench located in the cell array region C, a first offset trench located in the select gate S region on the adjacent side, and a first transition trench located between the main trench and the first offset trench are formed, and the first offset trench is offset toward the first side along the row direction relative to the main trench. The first transition region I is used to connect the cell array region C and the adjacent select gate region S.

[0084] In this embodiment, the substrate 100 further includes a second transition region II located along the column direction between the cell array region C and the adjacent other side selection gate region S. The first transition region I and the adjacent selection gate region S constitute a first selection gate unit (not labeled); the second transition region II and the adjacent selection gate region S constitute a second selection gate unit (not labeled), and the second selection gate unit and the first selection gate unit are symmetrical about the center of the cell array region C.

[0085] In this embodiment, the base 100 includes a substrate. As an example, the substrate is a silicon substrate.

[0086] Continue to refer Figure 4 , a floating gate 110 is formed on a substrate 100 .

[0087] The floating gate 110 is used to form a floating gate structure later. When the NOR flash memory is working, the floating gate structure can capture and store electrons, and after power failure, the electrons stored in the floating gate structure will not be lost, and the amount of charge stored in the floating gate structure can change the conduction voltage of the field effect tube, and different conduction voltages can represent different states, thereby realizing information storage.

[0088] In this embodiment, the floating gate 110 is made of polysilicon.

[0089] In this embodiment, before forming the floating gate 110, the forming method further includes: forming a tunnel oxide (TOX) layer 101 (such as Figure 4 b). The tunneling oxide layer 101 is used to isolate the floating gate 110 from the substrate 100, and the tunneling oxide layer 101 is also used to provide a tunneling channel for electrons from the substrate 100 to the floating gate structure. In this embodiment, the material of the tunneling oxide layer 101 is silicon oxide.

[0090] In this embodiment, after forming the floating gate 110 , the forming method further includes: forming a stress buffer layer 102 on the floating gate 110 ; and forming a hard mask material layer 103 on the stress buffer layer 102 .

[0091] The stress buffer layer 102 is used to provide a buffering effect when forming the hard mask material layer 103 , which is beneficial to reducing the probability of dislocation problems when the hard mask material layer 103 is directly formed on the floating gate 110 .

[0092] In this embodiment, the material of the stress buffer layer 102 is silicon oxide.

[0093] Subsequently, a mask layer is formed, and then the pattern of the mask layer is transferred to the hard mask material layer 103 to form a hard mask layer, which is used as a mask for etching the floating gate 110 and a portion of the substrate 100 to form a trench. In this embodiment, the material of the hard mask material layer 103 is silicon nitride.

[0094] refer to Figures 5 to 7 , Figure 5 a is the top view, Figure 5 b is Figure 5 a is the cross-sectional view at position dd, Figure 6 for Figure 5 a A partial enlarged view of the cell array region, the first transition region and the adjacent selection gate region, Figure 7 for Figure 5a A partial enlarged view of the cell array region, the second transition region and the adjacent selection gate region, the patterned floating gate 110 and the partially thick substrate 100 are formed to form a plurality of grooves (not shown) extending in the column direction and arranged in the row direction, the grooves include a main groove 200 located in the cell array region C, a first offset groove 210 located in the adjacent side selection gate region S, and a first transition groove 230 located between the main groove 200 and the first offset groove 210, the first transition groove 230 having a first transition sidewall 31 on the first side along the row direction and a second transition sidewall 32 on the second side along the row direction, the first offset groove 210 being offset toward the first side along the row direction relative to the main groove 200; the grooves also include a first secondary groove 250 arranged in the row direction with the first offset groove 210 at intervals, the first secondary groove 250 having a secondary sidewall 30 located in the first transition region I and opposite to the second transition sidewall 32. In this embodiment, the secondary sidewall 30 serves as the first secondary sidewall 30.

[0095] A first reference edge 10 and a second reference edge 20 are set in the first transition region I and are arranged parallel to the second transition sidewall 32, which correspond to the first side and the second side of the second transition sidewall 32 along the row direction, respectively. The first reference edge 10 connects the sidewalls of the main groove 200 and the first offset groove 210 along the first side of the row direction, and the second reference edge 20 connects the sidewall of the first first groove 250 located at the first side of the selection gate region S along the row direction; wherein the first transition sidewall 31 is located at the first side of the first reference edge 10 along the row direction; or, the first first sidewall 30 is located at the side of the second reference edge 20 away from the second transition sidewall 32; or, the first transition sidewall 31 is located at the first side of the first reference edge 10 along the row direction, and the first first sidewall 30 is located at the side of the second reference edge 20 away from the second transition sidewall 32.

[0096] Compared with the position where the first transition sidewall is located at the first reference edge, when the first transition sidewall 31 is located at the first side of the first reference edge 10 along the row direction, the first transition groove 230 has a larger space along the row direction; compared with the position where the first transition sidewall is located at the second reference edge, when the first transition sidewall 30 is located at the side of the second reference edge 20 away from the second transition sidewall 32, the size of the floating gate 110 and the substrate 100 located at the second side of the second transition sidewall 32 along the row direction is larger; the process of forming the groove includes forming a mask layer of patterned floating gate 110 and partial thickness substrate 100, and the mask layer is formed with a plurality of layers for defining the floating gate 110 and the substrate 100. The mask opening of the groove pattern, the mask layer is usually formed by a photolithography process. In this embodiment, the space of the first transition groove 230 along the row direction is increased, or the size of the floating gate 110 and the substrate 100 located on the second side of the second transition sidewall 32 along the row direction is increased, and the size of the mask opening at the corresponding position is correspondingly increased, which is beneficial to increase the process window of the photolithography process for forming the mask layer, for example: alleviating the limitation of the resolution of the photolithography process, improving the optical proximity effect, etc., and then helping to reduce the process difficulty of forming the groove, which is correspondingly beneficial to improve the accuracy of the pattern transfer, and improve the pattern accuracy and morphology quality of the groove.

[0097] In addition, the present embodiment locates the first transition sidewall 31 on the first side of the first reference edge 10 along the row direction, or locates the first sidewall 30 on the side of the second reference edge 20 away from the second transition sidewall 32. Compared with the first transition sidewall being located at the first reference edge, the first sidewall being located at the second reference edge, and increasing the area of ​​the first transition zone along the column direction to increase the spacing between the side walls of the first transition groove, the present embodiment avoids increasing the area of ​​the first transition zone, thereby avoiding an increase in the invalid area, which is beneficial to improving the utilization rate of the wafer area.

[0098] The trench is used to provide a spatial location for the subsequent formation of an isolation structure, and is also used to define an active area (AA) and an isolation area of ​​the substrate 100. The substrate 100 isolated by the trench is used as the active area, and the remaining area is used as the isolation area.

[0099] The trenches include a bottom trench 10 located in the substrate 100 and a top trench 20 located on the bottom trench 10, and the top trench 20 is connected to the bottom trench 10. The bottom trench 10 provides a spatial position for forming an isolation structure.

[0100] The main trench 200 is used to isolate the active area of ​​the cell array region C, and the main trench 200 provides a space for forming a main extension portion of the isolation structure. The first offset trench 210 is used to isolate the active area of ​​the select gate region S, and the first offset trench 210 is used to provide a space for forming a first offset extension portion of the isolation structure. The first transition trench 230 is used to connect the first offset trench 210 and the main trench 200. The first transition extension portion of the isolation structure is subsequently formed in the first transition trench 230.

[0101] In this embodiment, the first offset groove 210 is offset toward the first side along the row direction relative to the main groove 200, so the first transition groove 230 is bent toward the first side along the row direction relative to the main groove 200. Specifically, an angle is formed between the second transition sidewall 32 and the sidewall of the main groove 200. The sidewall of the main groove 200 extends along the column direction, that is, an angle is formed between the second transition sidewall 32 and the column direction.

[0102] In this embodiment, the angle between the second transition sidewall 32 and the column direction is a reference angle θ.

[0103] The first reference side 10 and the second reference side 20 are both parallel to the second transition side wall 32 , so the angle between the first reference side 10 or the second reference side 20 and the column direction is also the reference angle θ.

[0104] In this embodiment, the angle between the first transition side wall 31 and the first reference edge 10 is greater than 0° and less than or equal to the reference angle θ.

[0105] The angle between the first transition sidewall 31 and the first reference edge 10 is greater than 0°, so that the first transition sidewall 31 is farther away from the second transition sidewall 32 relative to the first reference edge 10, and the first transition sidewall 31 deflects toward the first side along the row direction relative to the first reference edge 10, correspondingly increasing the space of the first transition groove 230 along the row direction; the angle between the first transition sidewall 31 and the first reference edge 10 is less than or equal to the reference angle θ, thereby ensuring that the first transition sidewall 31 will not deflect toward the first side along the row direction relative to the sidewall of the first offset groove 210 on the first side along the row direction, so as to prevent the graphic structure of the first transition groove 230 along the first side of the row direction from being affected. Subsequently, a source region is formed in the active area substrate 100 between adjacent main grooves 200 along the row direction, and the source region also extends along the column direction to the first side of the first transition groove 230 along the row direction. The angle between the first transition sidewall 31 and the first reference edge 10 is less than or equal to the reference angle θ, which is beneficial to preventing the source region from being affected, and correspondingly improving the process compatibility and reducing the process risk.

[0106] As an example, the first transition sidewall 31 is located on the first side of the first reference edge 10 along the row direction, and the first transition sidewall 31 is flush with the sidewall of the first offset groove 210, that is, the angle between the first transition sidewall 31 and the first reference edge 10 is θ, and the first transition sidewall 31 is parallel to the column direction.

[0107] Accordingly, in the present embodiment, the first transition groove 230 is composed of a parallel groove (not shown) formed by the second transition sidewall 32 and the first reference edge 10, and a triangular groove formed by the first reference edge 10 and the first transition sidewall 31. Among them, the parallel groove is a parallelogram structure, and the triangular groove is a right-angled triangle structure. The triangular groove also includes a side wall opposite to the angle between the first reference edge 10 and the first transition sidewall 31, and the side wall opposite to the angle between the first reference edge 10 and the first transition sidewall 31 is parallel to the row direction, thereby preventing the first transition groove 230 from being located on the unit array area C, and correspondingly preventing adverse effects on the graphics of the unit array area C, and also helping to reduce the pattern complexity of the first transition groove 230, and correspondingly reducing the difficulty of forming the first transition groove 230.

[0108] The first sub-trench 250 is located on the selection gate region S and is used to isolate the active regions located on both sides of the first sub-trench 250 along the row direction. The first sub-trench 250 is also used to provide space for the subsequent formation of the first extension portion.

[0109] In this embodiment, the angle between the first side wall 30 and the second reference edge 20 is greater than 0° and less than or equal to the complementary angle of the reference angle θ.

[0110] The angle between the first sidewall 30 and the second reference edge 20 is greater than 0°, so that the first sidewall 30 is farther away from the second transition sidewall 32 relative to the second reference edge 20, and the size of the substrate 100 and the floating gate 110 located on the second side of the second transition sidewall 32 along the row direction is correspondingly increased; the angle between the first sidewall 30 and the second reference edge 20 is less than or equal to the complementary angle of the reference angle θ, so as to ensure that while the size of the substrate 100 and the floating gate 110 located on the second side of the second transition sidewall 32 along the row direction is increased, the first sidewall 30 is at most perpendicular to the column direction, and will not be closer to the selection gate area S on this basis, and accordingly ensure the isolation effect of the subsequent first extension portion located in the selection gate area S on the adjacent active areas along the row direction.

[0111] It should be noted that in the actual process, taking into account process deviations and increasing the process window for forming the groove, the first side wall 30 may have a certain error angle with the row direction, and when a selection gate is subsequently formed on the selection gate region S, there is a certain distance between the edge of the selection gate and the first transition region I. Therefore, even if there is an error angle between the first side wall 30 and the row direction, the impact on the performance of the semiconductor structure is relatively small.

[0112] In this embodiment, the first sidewall 30 is located on the side of the second reference edge 20 away from the second transition sidewall 32, the first sidewall 30 is perpendicular to the column direction, and the angle between the first sidewall 30 and the second reference edge 20 is equal to the complementary angle of the reference angle, that is, the first trench 250 is a rectangular structure trench located in the selection gate region S, which is conducive to reducing the pattern complexity of the first trench 250 and correspondingly reducing the process difficulty of forming the first trench 250. Accordingly, in this embodiment, the first sidewall 30 is located at the junction between the first transition region I and the selection gate region S along the column direction.

[0113] It should be noted that, in this embodiment, the shapes of the first groove 250 and the first transition groove 230 and the positions of the sidewalls are only used as an example. In other embodiments, the shapes and positions of the first groove and the first transition groove are not limited to these, as long as the following conditions are met: the first transition sidewall is located on the first side of the first reference edge in the row direction; or, the first transition sidewall is located on the side of the second reference edge away from the second transition sidewall; or, the first transition sidewall is located on the first side of the first reference edge in the row direction, and the first transition sidewall is located on the side of the second reference edge away from the second transition sidewall.

[0114] In this embodiment, the substrate 100 also includes a second transition region II located along the column direction between the cell array region C and the adjacent selection gate region S on the other side; the first transition region I and the adjacent selection gate region S constitute a first selection gate unit (not marked), and the second transition region II and the adjacent selection gate region S constitute a second selection gate unit (not marked), and the second selection gate unit and the first selection gate unit are symmetrical about the center of the cell array region C.

[0115] Accordingly, in this embodiment, the trench further includes a second offset trench 220 located in the selection gate region S on the other side adjacent to the cell array region C, and a second transition trench 240 located between the main trench 200 and the second offset trench 220, and the second offset trench 220 is offset toward the second side along the row direction relative to the main trench 200.

[0116] The second transition groove 240 has a third transition sidewall 41 on the first side along the row direction and a fourth transition sidewall 42 on the second side along the row direction; the second secondary groove 260 has a second secondary sidewall 60 located in the second transition region II opposite to the third transition sidewall 41 .

[0117] A third reference edge 61 and a fourth reference edge 62 are set in parallel with the third transition side wall 41 in the second transition region II, corresponding to the second side and the first side of the third transition side wall 41 along the row direction, respectively. The third reference edge 61 connects the side walls of the main groove 200 and the second offset groove 220 along the second side of the row direction, and the fourth reference edge 62 connects the side wall of the second secondary groove 260 located in the selection gate region S along the second side of the row direction.

[0118] Similarly, in this embodiment, the fourth transition side wall 42 is located on the second side of the third reference edge 61 along the row direction; or, the second side wall 60 is located on the side of the fourth reference edge 62 away from the third transition side wall 41; or, the fourth transition side wall 42 is located on the second side of the third reference edge 61 along the row direction, and the second side wall 60 is located on the side of the fourth reference edge 62 away from the third transition side wall 41.

[0119] Accordingly, compared with the position where the fourth transition sidewall is located at the third reference edge, when the fourth transition sidewall 42 is located at the second side of the third reference edge 61 along the row direction, the space of the second transition groove 240 along the row direction can be increased; compared with the position where the second sidewall is located at the fourth reference edge, when the second sidewall 60 is located on the side of the fourth reference edge 62 away from the third transition sidewall 41, the size of the floating gate 110 and the substrate 100 located on the first side of the second transition groove 240 along the row direction can be increased; therefore, the size of the mask layer for forming the groove is also correspondingly larger at the corresponding position, which is beneficial to increase the window of the photolithography process for forming the groove.

[0120] The detailed description of the second transition groove 240 and the second secondary groove 260 can be analogously referred to the aforementioned specific description of the first transition groove 230 and the first secondary groove 250 , and will not be repeated here.

[0121] In this embodiment, the step of forming the groove includes: forming a mask layer (not shown) on the floating gate 110, wherein a plurality of mask openings extending along the column direction and arranged along the row direction are formed in the mask layer (not shown); using the mask layer as a mask, etching the floating gate 110 and a partial thickness of the substrate 100 in sequence along the mask openings to form a groove.

[0122] In the present embodiment, a hard mask material layer 103 is also formed on the floating gate 110. Therefore, a mask layer is formed on the hard mask material layer 103, and the hard mask material layer 103 is etched along the mask opening using the mask layer as a mask to form a hard mask layer 120. The pattern of the mask layer is first transferred to the hard mask material layer 103, and then the floating gate 110 and a partial thickness substrate 100 are patterned using the hard mask layer 120 as a mask, which is beneficial to improving the stability and process effect of the patterning process.

[0123] In this embodiment, the process of etching the floating gate 110 and the partial thickness substrate 100 includes an anisotropic dry etching process. The anisotropic dry etching process has the characteristics of anisotropic etching, which is conducive to improving the controllability of the etching profile and the accuracy of pattern transfer.

[0124] refer to Figure 8 , Figure 8 a is the top view, Figure 8 b is Figure 8a is a cross-sectional view at position dd, in which an isolation structure 300 is formed in the trench. The isolation structure 300 is used to isolate adjacent devices in the row direction. Specifically, the isolation structure 300 is used to isolate adjacent active regions.

[0125] The isolation structure 300 includes a main extension portion (not labeled) located in the main groove 200, a first offset extension portion (not labeled) located in the first offset groove 210, a second offset extension portion (not labeled) located in the second offset groove 220, a first transition extension portion (not labeled) located in the first transition groove 230, and a second transition extension portion (not labeled) located in the second transition groove 240.

[0126] In this embodiment, the isolation structure 300 further includes a first extension portion (not labeled) located in the first trench 250 and a second extension portion (not labeled) located in the second trench 260 .

[0127] In this embodiment, the isolation structure 300 is formed in the bottom trench 10. In this embodiment, the isolation structure 300 is a shallow trench isolation (STI) structure, and the material of the isolation structure 300 is silicon oxide.

[0128] In this embodiment, the steps of forming the isolation structure 300 include: forming an isolation material layer (not shown) filling the trench; etching back a portion of the thickness of the isolation material layer, and the remaining isolation material layer located in the bottom trench serves as the isolation structure 300. The material for forming the isolation material layer includes a flow chemical vapor deposition process.

[0129] The material of the isolation material layer is different from that of the substrate 100 and the floating gate 110. The process of etching back the isolation material layer has a larger etching selectivity between the isolation material layer and the substrate 100, and between the isolation material layer and the floating gate 110. Therefore, in this embodiment, a maskless etching process can be used to etch a portion of the thickness of the isolation material layer to form the isolation structure 300, which is beneficial to reducing the process difficulty of forming the isolation structure 300 and saving process costs. Moreover, compared with the solution of etching the isolation material layer and the floating gate in the same step, in this embodiment, a portion of the thickness of the isolation material layer is first etched back, which is also beneficial to reducing the problem of footing defects at the bottom of the floating gate 110. In addition, the etching process has a higher etching selectivity between the isolation material layer and the floating gate 110, and between the isolation material layer and the substrate 100, which is beneficial to reducing the probability of damage to the floating gate 110 and the substrate 100.

[0130] Combined with reference Fig. 9 , Fig. 9 a is the top view, Fig. 9 b is Fig. 9a is a cross-sectional view at the position dd. In this embodiment, the formation method further includes: after forming the isolation structure 300, etching a portion of the floating gate 110 between adjacent isolation structures 300 in the cell array region C, forming an opening 400 extending along the column direction in the floating gate 110, and the opening 400 passes through the cell array region C, the adjacent first transition region I and the second transition region II, and a portion of the selection gate region S along the column direction. The bottom of the opening 400 is used to define the formation area of ​​the source region.

[0131] In this embodiment, in the step of forming the opening 400, only the material of the floating gate 110 is etched. Compared with etching the material of the isolation structure in the same step, this embodiment is beneficial to reducing the difficulty of forming the opening 400 and reducing the probability of generating a foot defect at the bottom of the floating gate 110.

[0132] In this embodiment, the opening 400 also extends along the column direction to a portion of the selection gate region S adjacent to the first transition region I, and a portion of the selection gate region S adjacent to the second transition region II, so that after a source region is subsequently formed in the substrate 100 below the opening 400, and a selection gate is subsequently formed in the selection gate region S, the source region can extend to the selection gate region S to be connected to the selection gate.

[0133] In this embodiment, the opening 400 that also extends along the column direction to the portion of the selection gate region S adjacent to the first transition region I is located between the first offset extension portion and the first extension portion adjacent to the first side along the row direction; the opening 400 that also extends along the column direction to the portion of the selection gate region S adjacent to the second transition region II is located between the second offset extension portion and the second extension portion adjacent to the second side along the row direction.

[0134] In this embodiment, the tunnel oxide layer 101 is exposed at the bottom of the opening 400 . The tunnel oxide layer 101 can protect the substrate 100 during the subsequent ion implantation to form a source region or a drain region, thereby reducing implantation damage to the substrate 100 caused by the ion implantation.

[0135] In this embodiment, the step of forming the opening 400 includes: forming a blocking layer (not shown) to cover the isolation structure 300, part of the floating gate 110 on both sides of the main extension portion, and part of the floating gate 110 in the selection gate area S; etching the floating gate 110 using the blocking layer as a mask to form the opening 400.

[0136] The shielding layer is used as a mask for etching the floating gate 110 to form the opening 400. In this embodiment, the material of the shielding layer includes photoresist, and the shielding layer can be formed by photolithography processes such as exposure and development.

[0137] In the present embodiment, in the step of forming a blocking layer, a graphic opening (not shown) is formed in the blocking layer to expose a portion of the floating gate 110 located between the main extension portions and extending along the column direction. The graphic opening passes through the cell array region C, the adjacent first transition region I and second transition region II, and a portion of the selection gate region S along the column direction.

[0138] In this embodiment, the side walls of the graphic opening do not need to be aligned with the side walls of the main extension portion 120, which is beneficial to the requirement for the accuracy of the overlay offset in forming the graphic opening, and correspondingly helps to reduce the difficulty of the photolithography process for forming the shielding layer, and further helps to increase the process window of the photolithography process for forming the opening 400.

[0139] In this embodiment, an anisotropic dry etching process is used to etch the portion of the floating gate 110 between the adjacent main extensions, and an opening 400 is formed in the floating gate 110. Specifically, in this embodiment, in the step of etching the portion of the floating gate 110 between the adjacent main extensions using the shielding layer as a mask, the portion of the hard mask layer 120, the stress buffer layer 102, and the floating gate 110 between the main extensions are sequentially etched.

[0140] After forming the opening 400 , the forming method further includes: removing the shielding layer to prepare for subsequent ion implantation. Specifically, the process of removing the shielding layer includes an ashing process.

[0141] Combined with reference Fig.10 , Fig.10 a is the top view, Fig.10 b is Fig.10 a is a cross-sectional view at the position dd. In this embodiment, the formation method also includes: forming a first drain region 510 in the substrate 100 along the second side wall of the main extension portion, the first transition extension portion and a portion of the first offset extension portion, and forming a second drain region 520 in the substrate 100 along the first side wall of the main extension portion, the second transition extension portion and a portion of the second offset extension portion, and forming a source region 500 in the substrate 100 below the opening 400 of the cell array region C, the first transition region I and the second transition region II and a portion of the selection gate region S.

[0142] As can be seen from the foregoing, this embodiment increases the space of the first transition groove 230 along the row direction or increases the size of the floating gate 110 and the substrate 100 located on the second side of the first transition groove 230 along the row direction, and correspondingly increases the size of the mask opening in the mask layer at the corresponding position, which is beneficial to increase the process window of the photolithography process for forming the mask layer, and further helps to reduce the process difficulty of forming the groove, and correspondingly helps to improve the accuracy of graphic transfer, improve the graphic accuracy and morphology quality of the groove, and help prevent the active areas located on both sides of the first transition groove 230 from contacting each other, thereby preventing the first drain area 510 located on the second side of the first transition extension along the row direction and the active area along the first side of the first transition extension from contacting each other, thereby ensuring the isolation effect of the first transition extension, and correspondingly improving the performance of the semiconductor structure.

[0143] Similarly, this embodiment increases the space of the second transition groove 240 along the row direction, or increases the size of the floating gate 110 and the substrate 100 located on the first side of the third transition side wall 41 along the row direction, which is also beneficial to increase the process window of the lithography process when forming the groove, and is beneficial to prevent the active areas located on both sides of the second transition groove 240 from contacting each other, thereby preventing the second drain area 520 located on the first side of the second transition extension along the row direction and the active area located on the second side of the second transition extension along the row direction from contacting each other, thereby ensuring the isolation effect of the second transition extension and correspondingly improving the performance of the semiconductor structure.

[0144] In the present embodiment, the first drain region 510 is used to form a first drain sub-bit line. The first drain region 510 extends along the sidewalls of the main extension portion and the first transition extension portion along the second side of the row direction. The first drain region 510 also extends to a portion of the substrate 100 along the sidewalls of the adjacent first offset extension portion along the second side of the row direction, so that the first drain region 510 extends to a portion of the selection gate region S adjacent to the first transition region I, thereby connecting the storage unit corresponding to the first drain sub-bit line to the selection gate.

[0145] In the present embodiment, the second drain region 520 is used to form a second drain sub-bit line. The second drain region 520 extends along the side wall of the main extension portion and the second transition extension portion along the first side of the row direction. The second drain region 520 also extends to a portion of the substrate 100 along the side wall of the adjacent second offset extension portion along the first side of the row direction, so that the second drain region 520 extends to a portion of the selection gate region S adjacent to the second transition region II, thereby connecting the storage unit corresponding to the second drain sub-bit line to the selection gate.

[0146] The source region 500 is used as a common source region (Common Source). The source region 500 is located in the substrate 100 below the opening 400, and the source region 500 extends along the column direction.

[0147] In this embodiment, the doping depths of the first drain region 510, the second drain region 520 and the source region 500 in the substrate 100 are less than the depth of the isolation structure 300, so that the first drain region 510 and the source region 500, the first drain region 510 and the second drain region 520, and the second drain region 520 and the source region 500 can be isolated by the isolation structure 300.

[0148] When forming an NMOS device, the doping ions of the first drain region 510, the second drain region 520 and the source region 500 are N-type ions; when forming a PMOS device, the doping ions of the first drain region 510, the second drain region 520 and the source region 500 are P-type ions.

[0149] In this embodiment, for the convenience of illustration and description, only the tunnel oxide layer 101 is illustrated in the cross-sectional view.

[0150] Subsequent process steps also include: removing the hard mask layer 120; forming a gate oxide layer that conformally covers the substrate 100, the floating gate 110, and the isolation structure 300; and forming a control gate located in the cell array region C and the selection gate region S and extending along the row direction on the gate oxide layer. The subsequent process steps will not be described in detail in this embodiment.

[0151] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, comprising a plurality of discrete cell array regions for forming memory cells; the substrate further comprising a selection gate region located between the cell array regions along the column direction, and a first transition region located between the cell array region and an adjacent side selection gate region along the column direction; A floating gate, located on the substrate; A plurality of grooves extending in the column direction and arranged in the row direction, penetrating the floating gate and a part of the thickness of the substrate, the grooves comprising a main groove located in the cell array region, a first offset groove located in the adjacent side selection gate region, and a first transition groove located between the main groove and the first offset groove, the first transition groove having a first transition sidewall along the first side of the row direction and a second transition sidewall along the second side of the row direction, the first offset groove being offset toward the first side along the row direction relative to the main groove; the grooves further comprising a first secondary groove arranged in the row direction with an interval from the first offset groove, the first secondary groove having a secondary sidewall located in the first transition region opposite to the second transition sidewall; A first reference edge and a second reference edge are set in the first transition region and are arranged parallel to the second transition sidewall, respectively corresponding to the first side and the second side of the second transition sidewall along the row direction, the first reference edge connects the sidewalls of the main trench and the first offset trench along the first side of the row direction, and the second reference edge connects the sidewall of the first sub-trench located at the first side of the selection gate region along the row direction; Wherein, the first transition sidewall is located on the first side of the first reference edge in the row direction; or, the secondary sidewall is located on the side of the second reference edge away from the second transition sidewall; or, the first transition sidewall is located on the first side of the first reference edge in the row direction, and the secondary sidewall is located on the side of the second reference edge away from the second transition sidewall; The isolation structure is located in the trench.

2. The semiconductor structure according to claim 1, wherein: The substrate further includes a second transition region located between the cell array region and the adjacent selection gate region on the other side along the column direction; the groove further includes a second offset groove located at the adjacent selection gate region on the other side of the cell array region, and a second transition groove located between the main groove and the second offset groove, wherein the second offset groove is offset toward the second side relative to the main groove along the row direction; The first transition region and the first selection gate region constitute a first selection gate unit; the second transition region and the second selection gate region constitute a second selection gate unit, and the second selection gate unit and the first selection gate unit are symmetrical about the center of the cell array region.

3. The semiconductor structure according to claim 1 or 2, characterized in that: The angle between the second transition sidewall and the column direction is a reference angle, and the angle between the sidewall of the first transition groove along the first side of the row direction and the first reference edge is greater than 0° and less than or equal to the reference angle.

4. The semiconductor structure according to claim 1 or 2, characterized in that: The angle between the second transition side wall and the column direction is a reference angle, and the angle between the secondary side wall and the second reference edge is greater than 0° and less than or equal to the complementary angle of the reference angle.

5. The semiconductor structure according to claim 1 or 2, characterized in that: The first transition sidewall is located at a first side of the first reference edge in a row direction, and the first transition sidewall is flush with a sidewall of the first offset groove.

6. The semiconductor structure according to claim 1 or 2, characterized in that: The secondary sidewall is located at a side of the second reference edge away from the second transition sidewall, and the secondary sidewall is perpendicular to the column direction.

7. The semiconductor structure according to claim 2, wherein: The grooves include a bottom groove located in the substrate and a top groove located on the bottom groove, wherein the top groove is connected to the bottom groove; The isolation structure is located in the bottom trench; The isolation structure includes a main extension located in the main trench, a first offset extension located in the first offset trench, a second offset extension located in the second offset trench, a first transition extension located in the first transition trench, and a second transition extension located in the second transition trench; The semiconductor structure further comprises: an opening extending in the column direction, located in the floating gate between adjacent main extensions, the opening penetrating the cell array region, the adjacent first transition region and the second transition region, and a portion of the selection gate region in the column direction; A first drain region is located in the substrate along the main extension portion, the first transition extension portion and a portion of the first offset extension portion toward the second side wall; A second drain region is located in the substrate along the main extension portion, the second transition extension portion and a portion of the second offset extension portion toward the first side wall; The source region is located in the substrate below the opening of the cell array region, the first transition region, the second transition region and a portion of the selection gate region.

8. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, including a plurality of discrete cell array regions for forming memory cells; the substrate also includes a selection gate region located between the cell array regions along the column direction, and a first transition region located between the cell array region and an adjacent side selection gate region along the column direction; forming a floating gate on the substrate; Patterning the floating gate and the substrate with a partial thickness to form a plurality of grooves extending in the column direction and arranged in the row direction, wherein the grooves include a main groove located in the cell array region, a first offset groove located in the adjacent side selection gate region, and a first transition groove located between the main groove and the first offset groove, wherein the first transition groove has a first transition sidewall along the first side of the row direction and a second transition sidewall along the second side of the row direction, and the first offset groove is offset toward the first side along the row direction relative to the main groove; the grooves also include a first secondary groove arranged in the row direction with an interval from the first offset groove, wherein the first secondary groove has a secondary sidewall located in the first transition region opposite to the second transition sidewall; A first reference edge and a second reference edge are set in the first transition region and are arranged parallel to the second transition sidewall, respectively corresponding to the first side and the second side of the second transition sidewall along the row direction, the first reference edge connects the sidewalls of the main trench and the first offset trench along the first side of the row direction, and the second reference edge connects the sidewall of the first sub-trench located at the first side of the selection gate region along the row direction; Wherein, the first transition sidewall is located on the first side of the first reference edge in the row direction; or, the secondary sidewall is located on the side of the second reference edge away from the second transition sidewall; or, the first transition sidewall is located on the first side of the first reference edge in the row direction, and the secondary sidewall is located on the side of the second reference edge away from the second transition sidewall; An isolation structure is formed in the trench.

9. The method for forming a semiconductor structure according to claim 8, wherein: The substrate further includes a second transition region located between the cell array region and the adjacent selection gate region on the other side along the column direction; the groove further includes a second offset groove located at the adjacent selection gate region on the other side of the cell array region, and a second transition groove located between the main groove and the second offset groove, wherein the second offset groove is offset toward the second side relative to the main groove along the row direction; The first transition region and the adjacent selection gate region constitute a first selection gate unit; the second transition region and the adjacent selection gate region constitute a second selection gate unit, and the second selection gate unit and the first selection gate unit are symmetrical about the center of the cell array region.

10. The method for forming a semiconductor structure according to claim 8 or 9, characterized in that: The angle between the second transition sidewall and the column direction is a reference angle, and the angle between the sidewall of the first transition groove along the first side of the row direction and the first reference edge is greater than 0° and less than or equal to the reference angle.

11. The method for forming a semiconductor structure according to claim 8 or 9, characterized in that: The angle between the second transition side wall and the column direction is a reference angle, and the angle between the secondary side wall and the second reference edge is greater than 0° and less than or equal to the complementary angle of the reference angle.

12. The method for forming a semiconductor structure according to claim 8 or 9, characterized in that: The first transition sidewall is located at a first side of the first reference edge in the row direction, and the first transition groove sidewall is flush with the sidewall of the first offset groove.

13. The method for forming a semiconductor structure according to claim 8 or 9, characterized in that: The secondary sidewall is located at a side of the second reference edge away from the second transition sidewall, and the secondary sidewall is perpendicular to the column direction.

14. The method for forming a semiconductor structure according to claim 8, wherein: The step of forming the trench comprises: forming a mask layer on the floating gate, wherein a plurality of mask openings extending in a column direction and arranged in a row direction are formed in the mask layer; The mask layer is used as a mask, and the floating gate and a portion of the thickness of the substrate are sequentially etched along the mask opening to form the groove.

15. The method for forming a semiconductor structure according to claim 14, wherein: The process of etching the floating gate and the partial thickness substrate includes an anisotropic dry etching process.

16. The method for forming a semiconductor structure according to claim 9, wherein: The grooves include a bottom groove located in the substrate and a top groove located on the bottom groove, wherein the top groove is connected to the bottom groove; The isolation structure is formed in the bottom trench; The isolation structure includes a main extension located in the main trench, a first offset extension located in the first offset trench, a second offset extension located in the second offset trench, a first transition extension located in the first transition trench, and a second transition extension located in the second transition trench; The method for forming the semiconductor structure further comprises: after forming the isolation structure, etching a portion of the floating gate located between adjacent isolation structures in the cell array region, forming an opening extending in a column direction in the floating gate, wherein the opening passes through the cell array region, the adjacent first transition region and the second transition region, and a portion of the selection gate region in the column direction; A first drain region is formed in the substrate along the second side wall of the main extension portion, the first transition extension portion and a portion of the first offset extension portion, and a second drain region is formed in the substrate along the first side wall of the main extension portion, the second transition extension portion and a portion of the second offset extension portion, and a source region is formed in the substrate below the opening of the cell array region, the first transition region, the second transition region and a portion of the selection gate region.

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