Three-dimensional memory, methods of making three-dimensional memory, and three-dimensional memory systems

Abstract

The application provides a three-dimensional memory, a method for manufacturing the three-dimensional memory, and a three-dimensional memory system. The method for manufacturing the three-dimensional memory includes: forming a stack structure including a plurality of stepped terraces, wherein each of the stepped terraces includes a dielectric layer and a sacrificial layer on the dielectric layer; forming a preset layer on the stepped terraces; removing at least a portion of the preset layer to form a first recess, wherein the first recess exposes a portion of the sacrificial layer; covering a conductive layer on the exposed portion of the sacrificial layer via the first recess; and removing the sacrificial layer and filling a gate layer in a gap formed after the sacrificial layer is removed.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and manufacturing, and more specifically, to a three-dimensional memory (3D NAND) structure, fabrication method, and three-dimensional memory system. Background Technology

[0002] 3D NAND flash memory is a type of flash memory device constructed by stacking memory cells in three dimensions. A typical 3D NAND memory structure includes a stacked structure with storage functionality and an external circuit structure that provides interconnectivity. The stacked structure can be formed by alternating gate layers and dielectric layers. Generally, word lines are led out through word line contacts located in the stepped regions of the stacked structure to achieve electrical connection between the memory cells and the external circuitry.

[0003] It should be understood that the content described in the background section is only for the purpose of helping to understand the technical solutions disclosed in this application, and is not necessarily prior art before the filing date of this application. Summary of the Invention

[0004] According to a first aspect of this application, a method for fabricating a three-dimensional memory is provided. The method includes: forming a stacked structure comprising a plurality of stepped steps, wherein each stepped step includes a dielectric layer and a sacrificial layer located on the dielectric layer; forming a preset layer on the stepped step; removing at least a portion of the preset layer to form a first groove, wherein the first groove exposes a portion of the sacrificial layer; covering the exposed portion of the sacrificial layer with a conductive layer via the first groove; and removing the sacrificial layer and filling a gate layer within the void formed after removing the sacrificial layer.

[0005] In one embodiment, before exposing a portion of the sacrificial layer, the method further includes: forming an insulating layer covering the top surface and sidewalls of each of the stepped steps, and forming the preset layer on the insulating layer; forming a step region dielectric layer covering the preset layer on the side of the insulating layer adjacent to the preset layer; forming a dummy channel hole penetrating the step region dielectric layer, the preset layer, the insulating layer, and the stacked structure; and removing a portion of the preset layer and the insulating layer via the dummy channel hole to expose a portion of the sacrificial layer.

[0006] In one embodiment, the method further includes: removing a portion of the preset layer via the dummy channel hole to form the first groove; and removing a portion of the sacrificial layer near the dummy channel hole via the dummy channel hole to form the second groove.

[0007] In one embodiment, the etching rate of the preset layer is faster than the etching rate of the sacrificial layer, so that when the second groove is etched, the size of the first groove in a first direction is larger than the size of the second groove in the same direction, wherein the first direction includes a direction perpendicular to the stacking direction of the stacked structure.

[0008] In one embodiment, before exposing part of the sacrificial layer, the method further includes forming an initial isolation layer in the first groove, the second groove, and the dummy channel hole, wherein the initial isolation layer includes a first isolation layer formed in the second groove, a second isolation layer formed in the first isolation layer and the dielectric layer on the side near the dummy channel hole, and a third isolation layer formed in the first groove.

[0009] In one embodiment, the step of exposing a portion of the sacrificial layer includes: removing the third isolation layer to expose a portion of the insulating layer; and removing the exposed portion of the insulating layer to form a third groove, wherein the third groove exposes a portion of the sacrificial layer.

[0010] In one embodiment, the step of forming the preset layer includes: forming an initial preset layer covering the top surface and sidewalls of the insulating layer; and removing the portion of the initial preset layer that contacts the sidewalls of the insulating layer to form the preset layer.

[0011] In one embodiment, during the process of exposing a portion of the sacrificial layer, the method further includes: removing the second isolation layer; and after exposing a portion of the sacrificial layer, the method further includes: covering the conductive layer on the side of the first isolation layer near the dummy channel hole, the exposed portion of the sacrificial layer, and the side of the third groove near the step region dielectric layer.

[0012] In one embodiment, the method further includes: filling the remaining space of the dummy channel hole after the conductive layer is formed with an insulating material; or filling the remaining space of the dummy channel hole after the conductive layer is formed with a conductive material.

[0013] In one embodiment, after filling the dummy channel via, the method further includes: forming a gate line gap through the stacked structure, removing the sacrificial layer through the gate line gap, and filling the gate layer into the void formed after removing the sacrificial layer.

[0014] In one embodiment, the material of the preset layer includes a first silicon nitride, and the material of the sacrificial layer includes a second silicon nitride, wherein the second silicon nitride is denser than the first silicon nitride.

[0015] According to a second aspect of this application, a three-dimensional memory is also provided, comprising: a stacked structure including a plurality of stepped steps, wherein each stepped step includes a dielectric layer and a gate layer located on the dielectric layer; a dummy channel structure penetrating the portion of the stacked structure having the stepped steps; and a conductive layer filling the sidewalls of the dummy channel structure and connected to the gate layer.

[0016] In one embodiment, the dummy channel structure includes a first groove structure located on the stepped platform, a portion of the conductive layer located within the first groove structure being connected to the gate layer, and the first groove structure having a dimension in a first direction greater than the dimension of the remaining portion of the dummy channel structure in the same direction, wherein the first direction includes a direction perpendicular to the stacking direction of the stacked structure.

[0017] In one embodiment, it further includes: a second groove structure located on the side of the gate layer near the dummy channel structure, which isolates the gate layer from the conductive layer in the first direction.

[0018] In one embodiment, the system further includes: a stepped region dielectric layer located on the side of the stacked structure near the first groove structure, and the dummy channel structure penetrating the stepped region dielectric layer.

[0019] In one embodiment, the dummy channel structure includes the conductive layer and a filling layer, wherein the filling layer is located on the side of the conductive layer away from the sidewall of the dummy channel structure, and the filling layer is made of the same material as the conductive layer, or the filling layer is made of an insulating material.

[0020] According to a third aspect of this application, a three-dimensional memory system is also provided, comprising: a three-dimensional memory as described in the second aspect above, wherein the three-dimensional memory includes a storage string for storing data; and a controller electrically connected to the three-dimensional memory and configured to control the operation of the storage string.

[0021] In one embodiment, the three-dimensional memory system includes at least one of an SSD and a memory card.

[0022] In one embodiment, the three-dimensional memory includes a 3D NAND memory.

[0023] The solution of this application effectively improves the problem of poor contact between word line contact (CT) and gate layer in existing processes by forming a virtual channel structure that runs through the three-dimensional memory stack structure and forming a conductive layer that is tightly connected to the gate layer in the virtual channel structure. In addition, the virtual channel structure formed according to the embodiment of this application can also serve as device support and stress buffer. Attached Figure Description

[0024] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings:

[0025] Figures 1 to 2 These are schematic diagrams illustrating the fabrication process of three-dimensional memory in some implementation methods;

[0026] Figure 3 A flowchart illustrating a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application is shown schematically;

[0027] Figures 4 to 11 This is a schematic diagram of the fabrication method of a three-dimensional memory according to an exemplary embodiment of this application;

[0028] Figure 12 This is a schematic diagram of the structure of a three-dimensional memory according to an exemplary embodiment of this application; and

[0029] Figure 13 This is a schematic diagram of a three-dimensional memory system according to an exemplary embodiment of this application. Detailed Implementation

[0030] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first groove discussed herein may also be referred to as the second groove, and the first isolation layer may also be referred to as the second isolation layer, and vice versa.

[0032] In the accompanying drawings, the thickness, dimensions, and shapes of the components have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. For example, the thickness of the first groove filling structure depicted in the drawings of this application is not proportional to actual production. Terms such as “approximately,” “about,” and similar expressions used herein are used as terms of approximation, not as terms of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by those skilled in the art.

[0033] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0034] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0035] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0036] The features, principles and other aspects of this application are described in detail below.

[0037] Figures 1 to 2 This is a schematic diagram illustrating the fabrication process of a three-dimensional memory according to some implementation methods. For example... Figure 1 As shown, the stacked structure 100 includes multiple stepped steps 110, each of which consists of a stacked dielectric layer 120 and a gate layer 130. Generally, the step 110 is formed by first etching away a sacrificial layer (not shown) in the stacked structure 100, and then depositing the gate layer 130 in the void formed after etching away the sacrificial layer. The gate layer 130 is located above the dielectric layer 120 (along the y-direction) and is partially exposed. Further, the gate layer 130 may consist of a first sub-gate layer 131 and a second sub-gate layer 132, with the first sub-gate layer 131 protruding from its exposed area. A word line contact 140 penetrates the first gate layer 131 and extends into the interior of the second gate layer 132, forming an electrical connection.

[0038] The inventors of this application have discovered that as the number of layers in 3D NAND increases, the gate material (e.g., tungsten metal) required for the contact position 150 between the word line contact 140 and the gate layer 130 also becomes thicker. This necessitates a sufficiently thick sacrificial layer at the contact position 150 before the formation of the gate layer 130. However, when the sacrificial layer at the contact position 150 is too thick, it becomes difficult to fill the gaps after etching with conductive material (e.g., tungsten metal). In subsequent word line contact etching steps, the conductive material is completely removed, resulting in the deposited word line contact 140 and the gate layer 130 contact position 150 lacking conductive material, leading to... Figure 2 The situation is shown.

[0039] Figure 3 This is a flowchart of a method 1000 for fabricating a three-dimensional memory according to an embodiment of this application. For example... Figure 3 As shown, this application provides a method 1000 for fabricating a three-dimensional memory, including step S1100, forming a stacked structure comprising multiple stepped steps, wherein each stepped step comprises a dielectric layer and a sacrificial layer located on the dielectric layer. Next, in step S1200, a preset layer is formed on the stepped step. In step S1300, at least a portion of the preset layer is removed to form a first groove, wherein the first groove exposes a portion of the sacrificial layer. In step S1400, a conductive layer is covered on the exposed portion of the sacrificial layer via the first groove. Finally, in step S1500, the sacrificial layer is removed, and a gate layer is filled into the void formed after removing the sacrificial layer.

[0040] It should be understood that the steps shown in method 1000 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. Furthermore, some of the steps shown may be performed simultaneously or in a sequence different from the steps described. Figure 3 The execution is performed in the order shown.

[0041] Figures 4 to 11 This is a schematic diagram of the fabrication method 1000 of the three-dimensional memory according to an embodiment of this application. The following is in conjunction with... Figures 4 to 11 The above steps S1100 to S1500 are further described.

[0042] Step S1100: Forming a stacked structure comprising multiple stepped steps, wherein each stepped step comprises a dielectric. The dielectric layer and the sacrificial layer located on the dielectric layer.

[0043] like Figure 4As shown, in step S1100, a stacked structure 200 may be formed on the substrate 210. The stacked structure 200 includes a plurality of stepped steps 220, wherein each stepped step 220 consists of a stacked dielectric layer 230 and a sacrificial layer 240, the sacrificial layer 240 being located above the dielectric layer 230 (along the y-direction), and the upper surface of the sacrificial layer 240 being at least partially exposed. An insulating layer 250 is formed on the top surface and sidewalls of each stepped step 220, the insulating layer 250 covering the exposed portion of the sacrificial layer 240, and an initial preset layer 260 is formed on the top surface and sidewalls of the insulating layer 250.

[0044] In some embodiments, the material of substrate 210 may include, for example, silicon (e.g., single-crystal silicon, polycrystalline silicon), silicon-germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or any combination thereof. In some examples, substrate 210 may include a substrate and a composite layer (not shown) located on the substrate, wherein the substrate has a certain thickness and can serve as a structural support for a device structure (e.g., stacked structure 200) formed thereon, and alternatively, the substrate may be removed in some subsequent process steps.

[0045] In some embodiments, the stacked structure 200 may include a plurality of dielectric layers 230 and a plurality of sacrificial layers 240 alternately stacked in a direction perpendicular or substantially perpendicular to the substrate 210 (y-direction). Under the same etching conditions, the sacrificial layer 240 and the dielectric layer 230 may have a high etch selectivity ratio, so that the dielectric layer 230 is hardly removed when the sacrificial layer 240 is removed in a subsequent process. In some examples, the material for the dielectric layer 230 includes, for example, silicon oxide; the material for the insulating layer 250 includes, for example, oxide; the material for the initial preset layer 260 includes, for example, first silicon nitride (TS SIN); and the material for the sacrificial layer 240 includes, for example, second silicon nitride (SIN). It should be noted that the materials of TS SIN and SIN may both be silicon nitride, but the material of TS SIN is more porous than that of SIN, so that TS SIN and SIN have a higher etch selectivity ratio, and thus, under the same etching conditions, the etching size of TS SIN in the first direction (e.g., the x-direction) is larger than the etching size of SIN in the same direction.

[0046] For example, a stacked structure 200 can be formed on a substrate 210 by alternatingly forming a plurality of sacrificial layers 240 and dielectric layers 230 through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, and an insulating layer 250 and an initial preset layer 260 can be formed on the stacked structure 200.

[0047] In some embodiments, the stacked structure 200 may include a plurality of stepped steps 220. Optionally, the method of forming the stepped steps 220 includes a repeated etch-trimming process of the sacrificial layer 240 and the dielectric layer 230 from the side of the stacked structure 200 away from the substrate 210 using a patterned photoresist as a mask, thereby forming a... Figure 4 The stepped step 220 is shown. In some examples, each stepped step 220 includes the thickness of at least one pair of sacrificial layer 240 / dielectric layer 230 with exposed sidewalls, and each stepped step 220 includes a sacrificial layer 240 having an upper surface remote from the substrate 210, at least a portion of which is exposed.

[0048] It should be understood that the number of layers in the stacked structure 200 is not limited to the number shown in the figure. Rather, the number of stacked layers and the stacking height of the stacked structure 200 can be designed according to actual needs. This application does not make any specific limitations in this regard.

[0049] Step S1200: A preset layer is formed on the steps.

[0050] like Figure 5 As shown, the portion of the initial preset layer 260 in contact with the sidewall of the insulating layer 250 is removed to form a preset layer 261, wherein the sidewall of the preset layer 261 is isolated from the sidewall of the insulating layer 250. A stepped dielectric layer 270 can then be formed on the upper side (along the y-direction) of the insulating layer 250, completely covering the preset layer 261. The preset layers 261 located at adjacent upper and lower steps 220 are spaced apart from each other, effectively preventing short circuits caused by word lines bridging between adjacent gate layers.

[0051] In some embodiments, the method for removing a portion of the initial preset layer 260 on the sidewall of the insulating layer 250 may include, but is not limited to, etching. For example, dry etching such as deep ion reactive etching (RIDE) may be used, as well as wet etching (e.g., using phosphoric acid, hot sulfuric acid, etc. as etchants).

[0052] In some embodiments, after removing a portion of the initial preset layer 260 located on the sidewall of the insulating layer 250, a step region dielectric layer 270 may be deposited on the upper side of the preset layer 261 and in the gap between the preset layer 261 and the insulating layer 250. As an example, the step region dielectric layer 270 may be further planarized using processes such as chemical mechanical polishing (CMP) to provide a substantially flat upper surface.

[0053] In some embodiments, a stepped dielectric layer 270 may be formed on the upper side of the insulating layer 250 by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The material for forming the stepped dielectric layer 270 includes, for example, silicon oxide.

[0054] Step S1300: Remove at least a portion of the preset layer to form a first groove, wherein the first groove exposes... This is part of the sacrificial layer.

[0055] Figure 6 This is a schematic diagram illustrating the removal of a portion of the preset layer and a portion of the sacrificial layer in a three-dimensional memory according to an embodiment of this application. Figure 6 As shown, a dummy channel via 280 is formed, penetrating the dielectric layer 270, the preset layer 261, the insulating layer 250, and the stacked structure 200 in the step region. In some examples, the dummy channel via 280 may also extend into the substrate 210. Removing a portion of the preset layer 261 through the dummy channel via 280 forms a first groove 262 (shown in the area within the dashed box), and removing a portion of the sacrificial layer 240 through the dummy channel via 280 forms a second groove 241 (shown in the area within the dashed box). The first groove 262 and the second groove 241 can be formed in the same etching process. For example, a wet etching process can be used to remove a portion of the preset layer 261 and a portion of the sacrificial layer 240 through the dummy channel via 280 in one pass, forming the first groove 262 and the second groove 241, respectively.

[0056] In some embodiments, the preset layer 261 is completely removed to form the first groove 262. In other embodiments, most of the preset layer 261 may be etched away to form the first groove 262, and a small portion of the preset layer 261 remaining will be removed in the subsequent etching process of the sacrificial layer 240.

[0057] For example, the material forming the preset layer 261 can be TS SIN, and the material forming the sacrificial layer 240 can be SIN. When wet etching is performed using an etchant such as phosphoric acid or hot sulfuric acid, the etching rate of TS SIN material is about two to three times faster than that of normal SIN. Under the same etching conditions, more of the preset layer 261 is etched away than the portion of the sacrificial layer 240 is etched away. It can be understood that the dimension of the second groove 241 in the x-direction is smaller than the dimension of the first groove 262 in the same direction.

[0058] In some embodiments, a combination of processes such as photolithography and dry etching can be used to remove portions of the step region dielectric layer 270, preset layer 261, insulating layer 250, and stacked structure 200 to form a dummy channel hole 280.

[0059] like Figure 7As shown, in some embodiments, an initial insulating layer 268 is further formed within the first groove 262, the second groove 241, and the dummy channel hole 280. The initial insulating layer 268 may include a first insulating layer 242 formed within the second groove 241, a second insulating layer 243 formed on the side of the first insulating layer 242 and the dielectric layer 230 near the dummy channel hole 280, and a third insulating layer 263 formed on the side of the first groove 262 away from the dummy channel hole 280, near the insulating layer 250, and near the step region dielectric layer 270. The first insulating layer 242 completely fills the second groove 242, and because the first groove 262 has a larger dimension in the x-direction, the third insulating layer 263 only fills a portion of the first groove 262. In some embodiments, the initial insulating layer further includes a fourth insulating layer 264 formed on the side of the step region dielectric layer 270 near the dummy channel hole 280.

[0060] For example, the initial isolation layer 268 can be formed by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The materials of the first isolation layer 242, the second isolation layer 243, the third isolation layer 263, and the fourth isolation layer 264 can be the same or different, for example, all of which are silicon oxide.

[0061] Figure 8 This is a schematic diagram of the exposed sacrificial layer of a three-dimensional memory according to an embodiment of this application. For example... Figure 8 As shown, the second isolation layer 243, the third isolation layer 263, and the fourth isolation layer 264 are removed using an etching process. In some embodiments, the first isolation layer 242 and a portion of the dielectric layer 230 are also removed to align them on the side closest to the dummy channel via 280, forming a flat or near-flat surface. The first isolation layer 242 is at least partially retained to isolate the sidewalls (x-direction) of the gate layer 310 and the sidewalls of the conductive layer 290 in subsequent processes (e.g., ...). Figure 9 (as shown in the figure) has the following function.

[0062] In some embodiments, after the third insulating layer 263 is removed, a portion of the insulating layer 250 is exposed. An etching process is used to remove the exposed portion of the insulating layer 250 to form a third groove 265 (shown in the area within the dashed box). The third groove 265 exposes a portion of the upper surface of the sacrificial layer 240 in the stepped step 220.

[0063] In step S1400, a conductive layer is covered on the exposed portion of the sacrificial layer via the first groove.

[0064] like Figure 9As shown, a conductive layer 290 is deposited on the upper surface of the exposed portion of the sacrificial layer 240, connecting the sacrificial layer 240 to the conductive layer 290. In some embodiments, conductive material is further deposited on the side of the third groove 265 away from the dummy channel via 280, the side of the third groove 265 away from the substrate 210, the side of the stepped dielectric layer 270 near the dummy channel via 280, and the side of the first isolation layer 242 and the dielectric layer 230 near the dummy channel via 280 to form the conductive layer 290. The conductive layer 290 has a continuous structure and is connected to the gate layer 310 formed in subsequent processes. Figure 11 (As shown) Connection. Electrical signals from the peripheral circuit can be transmitted to the gate layer 310 through the conductive layer 290 to realize the addressing operation of the memory cell corresponding to each gate layer 310.

[0065] In some embodiments, the conductive layer 290 extends into the substrate 210. The conductive layer 290 can be formed by thin-film deposition processes such as CVD, PVD, ALD, or any combination thereof, and the material of the conductive layer 290 may include metals such as tungsten.

[0066] Step S1500: Remove the sacrificial layer and fill the gap formed after removing the sacrificial layer with the gate layer.

[0067] like Figure 10 As shown, a dummy channel structure 300 is formed by depositing filler material in the remaining space of the dummy channel via 280 after the formation of the conductive layer 290 and in the unfilled space of the third groove 265. In some embodiments, a conductive material, such as tungsten metal, may be filled to form the dummy channel structure 300. In other embodiments, an insulating material, such as silicon oxide, may be filled to form the dummy channel structure 300. In some embodiments, the dummy channel structure 300 can be formed by thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. The dummy channel structure 300 may serve as device support and stress buffer.

[0068] In some embodiments, after the dummy channel structure 300 is formed, gate line slots (not shown) can be formed in the stacked structure 200, and the sacrificial layer 240 can be removed through these gate line slots. Exemplarily, the sacrificial layer 240 is removed using a process such as wet etching.

[0069] In other embodiments, after a portion of the preset layer 261 is removed to form the first groove 262, a portion of the preset layer 261 remains on the stepped step 220. The process of removing the sacrificial layer 240 also includes etching away a small portion of the conductive layer 290 and etching away the remaining portion of the preset layer 261.

[0070] like Figure 11As shown, the gaps formed by removing the sacrificial layer 240, the gaps formed by removing a small portion of the conductive layer 290, and the gaps formed by removing the remaining portion of the preset layer 261 are filled with conductive materials such as tungsten and titanium nitride to form a gate layer 310. A portion of the upper surface of the gate layer 310 is electrically connected to the conductive layer 290. It can be understood that the first groove 262 is formed by etching away most of the preset layer 261, leaving a small portion of the preset layer 261. Therefore, during the etching process of the sacrificial layer 240, the remaining portion of the preset layer 261 is easily removed. During the gate layer 310 filling process, the gaps formed by removing the remaining portion of the preset layer 261 and the gaps formed by removing only a small portion of the conductive layer 290 are also easily filled with conductive materials to form a pore-free structure. For example, the gaps formed after removing the remaining portion of the preset layer 261 are filled with a conductive material of the same material as the gate layer 310 to form the first conductive layer 291.

[0071] Another aspect of this application provides a three-dimensional memory. This three-dimensional memory can be fabricated using any of the fabrication methods described in the above embodiments.

[0072] refer to Figure 12 As shown, the three-dimensional memory includes a stacked structure 200', a dummy channel structure 300, and a conductive layer 290. Exemplarily, the stacked structure 200' includes a plurality of stepped steps 220' consisting of a dielectric layer 230 and a gate layer 310. The dummy channel structure 300 extends through the portion of the stacked structure 200' having stepped steps 220'. The conductive layer 290 fills the sidewalls of the dummy channel structure 300 and is connected to the gate layer 310. In some embodiments, the dummy channel structure 300 has a first recessed structure 267 (shown in dashed boxes) located on the stepped steps 220' (along the y-direction). The portion of the conductive layer 290 located within the first recessed structure 267 is connected to the gate layer 310 in the stepped steps 220'. The dimension of the first recessed structure 267 in the x-direction is larger than the dimension of the remaining portion of the dummy channel structure 300 in the same direction.

[0073] In some embodiments, the three-dimensional memory further includes a second recess structure 241'. The second recess structure 241' is located on the side of the gate layer 310 near the dummy channel structure 300 and isolates the gate layer 310 and the conductive layer 290 in the x-direction. The second recess structure 241' is formed of an insulating material, which can effectively avoid electrical problems caused by the electrical connection between the conductive layer 290 and each gate layer 310.

[0074] In some embodiments, the three-dimensional memory further includes a step region dielectric layer 270 covering the side of the stepped step 220' away from the substrate 210 and enclosing the first groove structure 267, as well as the substrate 210. A stacked structure 200' is located on the substrate 210 (along the y-direction). A dummy channel structure 300 penetrates the stepped region dielectric layer 270 and the stacked structure 200' and extends to the substrate 210. The material of the stepped region dielectric layer 270 includes an insulating material, such as silicon oxide.

[0075] In some embodiments, the dummy channel structure 300 may include a conductive layer 290 and a fill layer 292. The conductive layer 290 is located across the entire sidewall of the dummy channel structure 300 and forms a continuous structure. The portion of the conductive layer 290 located within the first recess structure 267 is connected to the gate layer 310 in the stepped step 220. Electrical signals from peripheral circuits are transmitted to the gate layer 310 through the conductive layer 290 to enable addressing operations for memory cells corresponding to each gate layer 310. The fill layer 292 is located on the side of the conductive layer 290 away from the sidewall of the dummy channel structure 300. In some embodiments, the fill layer 292 is made of the same material as the conductive layer 290. In other embodiments, the fill layer 292 is made of an insulating material, such as an oxide.

[0076] Since the content and structure described in the preparation method 1000 above can be fully or partially applied to the three-dimensional memory described here, related or similar content will not be repeated.

[0077] Another aspect of this application provides a three-dimensional memory system, such as Figure 13 As shown, the three-dimensional storage system includes a three-dimensional memory 401 and a controller 402 as described in any embodiment of this application. The three-dimensional memory 401 includes multiple memory strings with storage functions, each memory string being composed of multiple memory cells. The controller 402 is electrically connected to the three-dimensional memory 401 and is configured to control the operation of the memory strings.

[0078] In some embodiments, memory 401 is electrically connected to and controlled by controller 402. Controller 402 may, for example, control the application of different voltage signals to memory cells (not shown) in memory 401 to control memory 401 to perform at least one of, for example, read operations, programming operations, and erase operations.

[0079] In some implementations, controller 402 may be configured to control the operation of memory 401, such as read, program, and erase operations. Controller 402 may also be configured to manage various functions related to data stored or to be stored in memory 401, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.

[0080] In some embodiments, the three-dimensional memory 401 includes a 3D NAND memory, which comprises a plurality of memory cells arranged in a three-dimensional stacked manner. In some embodiments, the three-dimensional memory system also includes a connector 403, which can be connected to a device such as a host computer for transmitting data.

[0081] In some embodiments, the three-dimensional memory system includes a solid-state drive (SSD), a memory card, or any combination thereof. In some embodiments, the controller 402 and the memory 401 may be integrated onto the SSD to form the three-dimensional memory system. The storage capacity and / or operating speed of the SSD may be higher than that of the memory card. The three-dimensional memory 401 of any embodiment of this application can be applied to storage devices or memory cards such as memory sticks, PC cards, compact flash (CF) cards, smart media (SM) cards, multimedia cards, SD cards, and universal flash memory (UFS).

[0082] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for fabricating a three-dimensional memory, wherein, The method includes: A stacked structure comprising multiple stepped steps is formed, wherein each stepped step comprises a dielectric layer and a sacrificial layer located on the dielectric layer; A predetermined layer is formed on the stepped platform; A stepped area medium layer is formed on the preset layer, and a portion of the stepped area medium layer is located between the preset layers on adjacent steps; At least a portion of the preset layer is removed to form a first groove, wherein the first groove exposes a portion of the sacrificial layer; A conductive layer is covered on the exposed portion of the sacrificial layer via the first groove; and Remove the sacrificial layer and fill the void formed after removing the sacrificial layer with the gate layer.

2. The method of claim 1, further comprising, before exposing a portion of the sacrificial layer: An insulating layer is formed covering the top surface and sidewalls of each of the steps, and the preset layer is formed on the insulating layer; A virtual channel hole is formed that penetrates the dielectric layer, the preset layer, the insulating layer, and the stacked structure of the stepped area; as well as A portion of the preset layer and the insulating layer are removed via the dummy channel hole to expose a portion of the sacrificial layer.

3. The method according to claim 2, further comprising: The first groove is formed by removing a portion of the preset layer through the dummy channel hole; A second groove is formed by removing the portion of the sacrificial layer near the dummy channel hole through the dummy channel hole.

4. The method according to claim 3, wherein, The etching rate of the preset layer is faster than that of the sacrificial layer, so that when the second groove is etched, the size of the first groove in the first direction is larger than the size of the second groove in the same direction. The first direction includes a direction perpendicular to the stacking direction of the stacked structure.

5. The method of claim 4, further comprising, before exposing a portion of the sacrificial layer: An initial isolation layer is formed within the first groove, the second groove, and the dummy channel hole. The initial isolation layer includes a first isolation layer formed in the second groove, a second isolation layer formed in the first isolation layer and the dielectric layer near the dummy channel hole, and a third isolation layer formed in the first groove.

6. The method according to claim 5, wherein, The steps of exposing the sacrificial layer include: Remove the third insulating layer to expose a portion of the insulating layer; and Removing the exposed portion of the insulating layer forms a third groove, wherein the third groove exposes a portion of the sacrificial layer.

7. The method according to claim 2, wherein, The steps for forming the preset layer include: Forming an initial pre-defined layer covering the top surface and sidewalls of the insulating layer; and The initial preset layer is formed by removing the portion of the initial preset layer that is in contact with the sidewall of the insulating layer.

8. The method of claim 6, wherein during the process of exposing a portion of the sacrificial layer, the method further comprises: Remove the second isolation layer; as well as After exposing a portion of the sacrificial layer, the method further includes: The conductive layer is covered on the side of the first isolation layer near the dummy channel hole, the exposed portion of the sacrificial layer, and the side of the third groove near the step region dielectric layer.

9. The method according to claim 2, further comprising: The remaining space of the dummy channel hole after the conductive layer is formed is filled with insulating material; or The remaining space of the dummy channel hole after the conductive layer is formed is filled with conductive material.

10. The method according to claim 9, further comprising, after filling the dummy channel hole: A gate line gap is formed through the stacked structure, and the sacrificial layer is removed through the gate line gap, and the gate layer is filled in the gap formed after the sacrificial layer is removed.

11. The method according to claim 4, wherein, The material of the preset layer includes a first silicon nitride, and the material of the sacrificial layer includes a second silicon nitride, wherein the second silicon nitride is denser than the first silicon nitride.

12. A three-dimensional memory, comprising: A stacked structure includes multiple stepped steps, wherein each stepped step includes a dielectric layer and a gate layer located on the dielectric layer; A stepped area medium layer is located on one side of the plurality of stepped steps; A virtual channel structure is constructed, penetrating the stepped medium layer and the portion of the stacked structure containing the stepped sections; and A conductive layer is filled in the sidewalls of the dummy channel structure and connected to the gate layer in the stacking direction of the stacked structure. Wherein, the end of the dummy channel structure away from the stacked structure along the stacking direction is located in the dielectric layer of the step region; A portion of the stepped dielectric layer is located in a first direction between the end of the conductive layer that contacts the gate layer and the gate layer of the previous step, the first direction including a direction perpendicular to the stacking direction.

13. The three-dimensional memory according to claim 12, wherein, The virtual channel structure includes a first groove structure located on the stepped platform. The portion of the conductive layer located within the first groove structure is connected to the gate layer, and The dimension of the first groove structure in the first direction is greater than the dimension of the rest of the dummy channel structure in the same direction.

14. The three-dimensional memory according to claim 13, wherein, Also includes: The second groove structure is located on the side of the gate layer near the dummy channel structure and isolates the gate layer from the conductive layer in the first direction.

15. The three-dimensional memory according to claim 13, wherein, Part of the stepped area dielectric layer is located on the side of the stacked structure closest to the first groove structure.

16. The three-dimensional memory according to claim 12, wherein, The dummy channel structure includes a filling layer located on the side of the conductive layer away from the sidewall of the dummy channel structure. The filling layer is made of the same material as the conductive layer, or the filling layer is made of an insulating material.

17. A three-dimensional memory system, comprising: The three-dimensional memory according to any one of claims 12-16, wherein the three-dimensional memory includes a storage string for storing data; and A controller, electrically connected to the three-dimensional memory, is configured to control the operation of the memory string.

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