Three-dimensional memory and methods of making the same, memory systems

Abstract

The present application provides a three-dimensional memory and a manufacturing method thereof, a memory system, the manufacturing method comprising: forming a stack layer comprising alternatingly stacked dielectric layers and sacrificial layers on a substrate, the stack layer comprising a step structure having a plurality of stepped terraces; forming at least one buffer layer on the plurality of stepped terraces at a first temperature; and performing a heat treatment on the buffer layer at a second temperature greater than the first temperature to form an etch stop layer. The etch stop layer formed by the manufacturing method of the present application can increase the landing window of the word line contact portion. In addition, since the portion of the etch stop layer located on the sidewall of the stepped terrace does not need to be removed by an etching process, the morphology of the stepped terrace and the film layer quality of the sacrificial layer are guaranteed.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology. Specifically, this application relates to a three-dimensional memory and its manufacturing method, as well as a memory system. Background Technology

[0002] Planar NAND devices have reached their practical expansion limits. To further increase storage capacity and reduce the cost per bit, 3D NAND memory devices have been proposed. In the structure of 3D NAND memory devices, dielectric and conductive layers can be stacked alternately vertically or approximately vertically to form a stacked structure. The stacked structure includes a core region and a step region. The core region can be used to form an array of channel structures, and the step region can be used to form a step structure.

[0003] It should be understood that the background section is intended to provide some useful background for understanding the technology; however, this content is not necessarily what was known or understood by a person skilled in the art prior to the filing date of this application. Summary of the Invention

[0004] One aspect of this application provides a method for manufacturing a three-dimensional memory, comprising: forming a stacked layer on a substrate comprising alternating stacked dielectric layers and sacrificial layers, the stacked layer comprising a stepped structure having a plurality of stepped steps; forming at least one buffer layer on the plurality of stepped steps at a first temperature; and heat-treating the buffer layer at a second temperature greater than the first temperature to form an etch stop layer.

[0005] In one embodiment of this application, the surface of the stepped steps facing away from the substrate exposes at least a portion of the sacrificial layer, and forming the at least one buffer layer includes: forming the at least one buffer layer on the sidewalls of the plurality of stepped steps and the exposed at least portion of the sacrificial layer at the first temperature.

[0006] In one embodiment of this application, the buffer layer is formed using atomic layer deposition or plasma-enhanced chemical vapor deposition.

[0007] In one embodiment of this application, the first temperature range is 200°C to 800°C.

[0008] In one embodiment of this application, the second temperature range is 550°C to 1100°C.

[0009] In one embodiment of this application, at least one of the sacrificial layer or the etch stop layer is made of a different material than the buffer layer.

[0010] In one embodiment of this application, the sacrificial layer comprises silicon nitride, and at least one of the buffer layer or the etch stop layer comprises silicon oxynitride.

[0011] In one embodiment of this application, the method further includes: removing the sacrificial layer using an etching process, and forming a conductive layer in the sacrificial gap formed by removing the sacrificial layer, wherein the etching rate of the etching stop layer is greater than the etching rate of the buffer layer by the same etching process.

[0012] In one embodiment of this application, under the same etching process, the etching selectivity ratio of the sacrificial layer to the etching stop layer ranges from 10 to 30:1.

[0013] In one embodiment of this application, the method further includes: forming a fill layer on the etch stop layer; and forming word line contacts that sequentially penetrate the fill layer and the etch stop layer and extend to the corresponding conductive layer.

[0014] In one embodiment of this application, forming the word line contact portion includes: forming a contact hole above the stepped structure that penetrates the filler layer and extends into the etch stop layer; and removing the etch stop layer located at the bottom of the contact hole so that the contact hole extends into the conductive layer.

[0015] In one embodiment of this application, forming the word line contact portion further includes filling the contact hole with a conductive material to form the word line contact portion.

[0016] Another aspect of this application provides a three-dimensional memory, comprising: a stacked structure including alternately stacked dielectric and conductive layers, the stacked structure including a stepped structure having a plurality of steps, each step having a thickness of at least one conductive and dielectric layer pair, wherein the top of the step includes at least a portion of the conductive layer; at least one etch stop layer disposed on the sidewall of each step and on the at least a portion of the conductive layer; and a fill layer located on the etch stop layer.

[0017] In one embodiment of this application, the etch stop layer comprises silicon oxynitride.

[0018] In one embodiment of this application, the three-dimensional memory further includes: a word line contact portion that sequentially penetrates the filling layer and the etch stop layer and extends to the corresponding conductive layer.

[0019] Another aspect of this application provides a memory system comprising: a three-dimensional memory as described in any of the preceding claims; and a memory controller coupled to the three-dimensional memory and configured to control the three-dimensional memory.

[0020] In one embodiment of this application, the memory system includes a solid-state drive or a memory card. Attached Figure Description

[0021] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. In the drawings,

[0022] Figures 1 to 4 This is a schematic diagram of a manufacturing process for a three-dimensional memory according to some embodiments of this application.

[0023] Figure 5 This is a schematic flowchart of a method for manufacturing a three-dimensional memory according to other embodiments of this application;

[0024] Figures 6-15 This is a partial schematic diagram of a method for manufacturing a three-dimensional memory according to other embodiments of this application after performing certain steps;

[0025] Figure 16 This is a cross-sectional schematic diagram of a three-dimensional memory according to some other embodiments of this application;

[0026] Figure 17 This is a schematic diagram of a three-dimensional memory including peripheral circuitry according to other embodiments of this application;

[0027] Figure 18 A block diagram of an exemplary system including a three-dimensional memory according to other embodiments of this application;

[0028] Figure 19 This is a schematic diagram of an exemplary memory card including a three-dimensional memory according to other embodiments of this application;

[0029] Figure 20 This is a schematic diagram of an exemplary solid-state drive (SSD) including a three-dimensional memory according to some other embodiments of this application. Detailed Implementation

[0030] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements.

[0031] Note that references to "one implementation," "implementation," "example implementation," "some implementations," etc., in the specification indicate that the described implementation may include a specific feature, structure, or characteristic, but other implementations may not necessarily include that specific feature, structure, or characteristic. Furthermore, when a specific feature, structure, or characteristic is described in connection with an implementation, whether explicitly stated or not, implementing that feature, structure, or characteristic in conjunction with other implementations will be within the knowledge of those skilled in the art.

[0032] Generally, terms can be understood, at least in part, from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Furthermore, the term "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0033] It should be readily understood that the meanings of “above,” “on top,” and “above” in this disclosure should be interpreted in the broadest sense, such that “above” means not only “directly on something” but also includes “on something” with an intermediate feature or layer therebetween, and that “on top” or “above” means not only “above” or “above” something but also includes “above” or “above” something without an intermediate feature or layer therebetween (i.e., directly on something).

[0034] Furthermore, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for ease of description to describe the relationship between one element or feature and another element(s) or feature(s) as shown in the figures. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures.

[0035] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. Furthermore, a layer can be a region of a continuous structure, whether homogeneous or non-homogeneous, whose thickness is less than the thickness of the continuous structure. Additionally, a layer may comprise a single sublayer or multiple sublayers.

[0036] In the accompanying drawings, for ease of illustration, the drawings are for illustrative purposes only and are not drawn to scale; therefore, the thickness, dimensions, and shapes of the parts shown may not correspond to actual parts. For example, the terms “approximately,” “about,” and similar terms used herein are used as expressions of approximation rather than expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0037] It should also be understood that the terms "comprising," "including," "having," "containing," and / or "comprising," when used in this specification, indicate the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplarily" is intended to refer to an example or illustration.

[0038] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0039] It should be noted that, where there is no conflict, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0040] Figures 1-4 This is a schematic diagram illustrating the fabrication process of a three-dimensional memory according to some implementation methods. For example... Figure 1 As shown, in some examples, a structure such as the one formed on the sacrificial layer 950 exposed by the stepped step 910 can be created. Figure 2 The silicon nitride buffer layer 920 shown is then applied as follows: Figure 3 As shown, the portion of the silicon nitride buffer layer 920 located on the sidewall of the stepped step 910 can be removed by dry etching or wet etching processes, thereby spacing the silicon nitride buffer layers 920 on adjacent stepped steps 910 apart from each other. Therefore, the sacrificial layer 950 is replaced by the conductive layer 940. Figure 4 In this case, this spacing effectively prevents adjacent word lines from bridging each other and causing short circuits. For example... Figure 4As shown, in some examples where the sacrificial layer 950 includes silicon nitride material, the sacrificial layer 950 and buffer layer 920 can be replaced in appropriate steps with conductive layer 940 and contact structure 930 of the same conductive material, thereby increasing the process window for word line contact 960 to land on conductive layer 940, in order to compensate for the defect that the etching depth of word line contact 960 in conductive layer 930 is difficult to control precisely.

[0041] The inventors discovered that as the number of stacked layers in a 3D memory increases, on the one hand, the depth at which the word line contact 960 lands on the conductive layer 940 becomes increasingly difficult to control. This results in significant differences in the etching depth of the conductive layer 940 at different steps in the stepped structure 910. For some layers of conductive layer 940, the word line contact 960 is prone to penetrating the conductive layer 940 and contacting adjacent conductive layers, leading to word line leakage. On the other hand, with the increasing demand for thickness of the contact structure 930, gaps can easily appear during the process of filling the conductive material to form the conductive layer 940 and the contact structure 930. If the word line contact 960 lands precisely at a gap, it cannot electrically lead out the conductive layer 940.

[0042] The inventors' research also revealed that during the removal of the portion of the silicon nitride buffer layer 920 located on the sidewall of the stepped step 910 using dry or wet etching processes, the sacrificial layer 950 located below the silicon nitride buffer layer 920 and on the sidewall of the stepped step 910 are easily subjected to etching damage. Furthermore, the degree of etching damage to the sacrificial layer 950 varies at different heights of the stepped step 910, making it difficult to control the morphology of the stepped step 910, the film quality of the sacrificial layer 950, and the uniformity of the film.

[0043] To at least partially address the aforementioned problems, embodiments of this application propose a method for manufacturing a three-dimensional memory. Figure 5 A flowchart of the three-dimensional memory manufacturing method 300 is shown. Figures 6-14 This is a partial schematic diagram showing the manufacturing method 300 described above after certain steps have been performed.

[0044] The manufacturing method 300 described above will now be described in conjunction with the accompanying drawings. It should be understood that the operations shown in the method are not exhaustive, and other operations may be performed before, after, or between any of the operations described. Furthermore, some operations in method 300 may be performed simultaneously or in a sequence different from the described operations. Figure 5 The execution is performed in the order shown.

[0045] Reference Figure 5 The manufacturing method 300 includes operation S310, wherein a stacked layer comprising alternating stacked dielectric layers and sacrificial layers is formed on a substrate, the stacked layer comprising a stepped structure having multiple stepped steps.

[0046] like Figure 6 As shown, the material of the substrate 10 may include, for example, silicon (e.g., single-crystal silicon, polycrystalline silicon), silicon-germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), glass, III-V compound semiconductors, or any combination thereof.

[0047] In some examples, substrate 10 may include a base 100 and a stop layer 101 and a first sacrificial layer 102 sequentially formed on the base 100. Exemplarily, the base 100 may have a relatively thicker thickness than the stop layer 101 and the first sacrificial layer 102, thereby enabling the base 100 to serve as a structural support for a device structure (e.g., a stacked layer 200) formed thereon.

[0048] In some embodiments, the methods for forming the stop layer 101 and the first sacrificial layer 102 may include one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, and thermal oxidation. Exemplarily, the material of the substrate 100 may include, for example, silicon, the material of the stop layer 101 may include, for example, silicon dioxide, and the material of the first sacrificial layer 102 may include, for example, polycrystalline silicon.

[0049] In this operation, a stacked layer 200 may be formed on a substrate 10. The stacked layer 200 may include a plurality of dielectric layers 202 and a plurality of sacrificial layers 201 alternately stacked in a direction perpendicular or substantially perpendicular to the substrate 10. Optionally, the plurality of dielectric layers 202 and the plurality of sacrificial layers 201 may be alternately stacked on the substrate 10 by one or more deposition processes, such as CVD, PVD, and ALD.

[0050] It should be understood that the number and thickness of the dielectric layer 202 and the sacrificial layer 201 are not limited to... Figure 6 The quantities and thicknesses shown herein, without departing from the concept of this application, allow those skilled in the art to create any number and thickness of dielectric layers 202 and sacrificial layers 201 as needed. Furthermore, the materials of dielectric layers 202 and sacrificial layers 201 may be selected from suitable materials known in the art. For example, dielectric layer 202 may be an oxide layer (e.g., silicon oxide), and sacrificial layer 201 may be a nitride layer (e.g., silicon nitride).

[0051] For example, substrate 10 can be used for forming structures such as channel structures 111 thereon. Figure 6The grid line gap structure (not shown) provides mechanical support and is removed in subsequent processes.

[0052] Refer again Figure 6 Optionally, prior to forming the stacked layer 200, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to sequentially form an oxide layer (e.g., silicon oxide) 103 and a polysilicon layer 104 on the substrate 10, for example, on the first sacrificial layer 102.

[0053] The stacked layer 200 may include a core region 120 and a step region 140. In some examples, the step region 140 may be located outside the core region 120, and in other examples, the step region 140 may be located in the middle of the core region 120. It should be noted that in the accompanying drawings of the embodiments of this application, only the step region 140 on one side of the stacked layer 200 and the portion of the core region 120 connected to the step region 140 on that side are shown.

[0054] Optionally, the core region 120 may include an array of channel structures 111. As an example, the channel structure 111 may extend vertically or substantially vertically through the dielectric layer 202 and the sacrificial layer 201; optionally, the channel structure 111 may extend into the first sacrificial layer 102. In some embodiments, the channel structure 111 includes a barrier layer 112, a storage layer 114, a tunneling layer 116, and a channel layer 118, disposed sequentially from the outside in. Optionally, the channel layer 118 may include polysilicon. The tunneling layer 116 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 114 may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer 112 may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof.

[0055] In some examples, photolithography and etching processes (e.g., dry or wet etching), CMP processes, or any combination thereof, can be used in appropriate steps to remove (e.g., sequentially remove) the substrate 100, stop layer 101, and first sacrificial layer 102 from the side of the substrate 10 opposite to the stacked layer 200, thereby exposing the portion of the channel structure 111 extending into the substrate 10. Optionally, the stop layer 101 can stop the process of removing the substrate 10 at this layer, thereby facilitating the control of the process uniformity of removing the substrate 10. Similarly, the first sacrificial layer 102 can stop the process of removing the stop layer 101 at this layer, thereby facilitating the control of the process uniformity of removing the stop layer 101.

[0056] Exemplarily, portions of the barrier layer 112, storage layer 114, and tunneling layer 116 extending into the substrate 10 can be removed, thereby exposing portions of the channel layer 118 extending into the substrate 10. In an example including an oxide layer 103 and a polysilicon layer 104, the polysilicon layer 104 can serve as a stop layer for the process exposing portions of the channel layer 118 extending into the substrate 10. In some cases, the polysilicon layer 104 can be removed in subsequent processes. As an example, a semiconductor layer 110 electrically in contact with the channel layer 118 can also be formed on the side exposing the channel layer 118. Figure 15 Semiconductor layer 110 includes, for example, polycrystalline silicon.

[0057] Continue to refer to Figure 6 The step region 140 may include a step structure 142, wherein the step structure 142 may include a plurality of stepped steps 130. In some examples, each stepped step 130 includes the thickness of at least one dielectric layer 202 / sacrificial layer 201 pair, the sidewalls of which are exposed, and at least a portion of the sacrificial layer 201 is exposed on the surface of each stepped step 130 facing away from the substrate 10. As an example, the stacked layers 200 can be formed by repeatedly etching-trimming processes using patterned mask layers (not shown) to create a shape such as Figure 6 The stepped structure 142 is shown. Optionally, the patterned mask may include a photoresist and may be removed after the stepped structure 142 is formed.

[0058] In some examples, the step structure 142 can be a single step structure that increases sequentially in one direction along the plane of the substrate 10. In other examples, the step structure 142 can also be a staircase partition scheme (SDS). The partition step has stepped steps 130 formed in two orthogonal directions along the plane of the substrate 10. The partition step can have different partitions, such as 3 partitions, 4 partitions or more partitions. For example, different partition plates can be used. The partition step is formed by multiple trimmings of the photoresist in two orthogonal directions, with each trimming followed by an etching of the stacked layer 200.

[0059] Continue to refer to Figure 5 Manufacturing method 300 includes operation S320, wherein at least one buffer layer can be formed on a plurality of stepped steps at a first temperature.

[0060] like Figure 7 As shown, exemplarily, after the step structure 142 is formed, a buffer layer 143 may be formed on at least a portion of the sidewalls of the step 130 and the exposed sacrificial layer. Optionally, a buffer layer 143 may also be formed on the exposed surface of the core region 120.

[0061] It should be understood that, Figure 7 The single buffer layer 143 formed in the process is merely an example. In other examples, two or more buffer layers 143 may be formed as needed, and this application does not limit this.

[0062] In some examples, the buffer layer 143 may be formed using a thin film deposition process such as plasma-enhanced chemical vapor deposition (PECVD), CVD, PVD, ALD, or any combination thereof. Optionally, the material of the buffer layer 143 may differ from the material of the sacrificial layer 201. In some examples, the buffer layer 143 may be formed at a first temperature of 200°C to 800°C. In other examples, the process temperature for forming the buffer layer 143 may be 300°C to 600°C.

[0063] Taking the formation of the aforementioned buffer layer 143 comprising silicon oxynitride using an ALD process as an example, silicon-based (e.g., hexachloroethane or dichloroethane), nitrogen-based (e.g., ammonia or nitrogen), and oxygen-based (e.g., oxygen, ozone, or nitrogen dioxide) gas sources can be introduced to the stepped step 130. These gas sources can form silicon oxynitride on the sidewalls of the stepped step 130 and on at least a portion of the exposed sacrificial layer 201. In some examples, the process temperature for forming the buffer layer 143 by the ALD process can be 300°C to 500°C. In other examples, the process temperature for forming the buffer layer 143 by the ALD process can be 400°C to 500°C.

[0064] It should be understood that the film density of the buffer layer 143 can be adjusted by changing the mass fraction of each element in the formed silicon oxynitride by adjusting the gas source ratio of silicon-based, nitrogen-based, and oxygen-based components. In some cases, the film density of the buffer layer 143 can be improved by increasing the proportion of silicon-based gas source. Optionally, the mass fractions of silicon and oxygen in the buffer layer 143 can be greater than the mass fraction of nitrogen, respectively.

[0065] During the formation of buffer layer 143, some silicon-based or nitrogen-based gas sources (such as hexachloroethane or dichloroethane) may introduce chlorine impurities in the form of silicon-chlorine bonds or nitrogen-chlorine bonds. These chlorine impurities can cause defects within buffer layer 143, adversely affecting its film density. In some cases, the film density of buffer layer 143 is negatively correlated with its etching rate; in other words, the higher the film density of buffer layer 143, the lower its etching rate.

[0066] Continue to refer to Figure 5 The method continues to operation S330, wherein the buffer layer can be heat-treated at a second temperature greater than the first temperature to form an etch stop layer.

[0067] In some examples where the buffer layer 143 includes silicon oxynitride, since the etching rate of the buffer layer 143 is similar to that of the sacrificial layer 201, a portion of the buffer layer 143 in contact with the sacrificial layer 201 will be removed simultaneously during the subsequent removal of the sacrificial layer 201, for example, the portion located at step 142. Figure 6 A portion of the buffer layer 143 on the sidewall of the ) will be removed simultaneously, thereby filling the conductive layer 204 described below. Figure 12 During the process, adjacent conductive layers 204 face the risk of short circuit. In some embodiments, a heat treatment process can be performed on the buffer layer 143 after its formation to form a structure as described above. Figure 8 The etching stop layer 141 is shown. Exemplarily, the above-described heat treatment process can be performed at a second temperature, which can be higher than the first temperature, thereby removing some impurity particles (e.g., chlorine impurities) contained in the buffer layer 143. In some examples, the second temperature can be 550°C to 1100°C. In other examples, the second temperature can be 650°C to 1000°C. Optionally, the second temperature can also be 750°C to 850°C.

[0068] Optionally, the above-described heat treatment process can be performed in an oxygen-free atmosphere, for example, the buffer layer 143 can be heat-treated in a nitrogen protective gas atmosphere. In some examples where the buffer layer 143 comprises silicon oxynitride, a heat treatment temperature of 550°C to 1100°C can activate chlorine atoms in the silicon oxynitride, causing the chlorine atoms to rebond in the form of chlorine gas and escape from the buffer layer 143, forming an etch stop layer 141. The film defects in the etch stop layer 141 are fewer than those in the buffer layer 143, and the film density of the etch stop layer 141 is significantly improved. Therefore, compared with the etch selectivity ratio of the buffer layer 143 to the sacrificial layer 141, the etch selectivity ratio of the etch stop layer 141 to the sacrificial layer 201 is improved, and the etch stop layer 141 will be retained during the subsequent removal of the sacrificial layer 201.

[0069] Continue to refer to Figure 5 Manufacturing method 300 includes operation S340, wherein a fill layer can be formed on the etch stop layer.

[0070] like Figure 9 As shown, in some examples, a fill layer 145 covering the step structure 142 may be formed on the etch stop layer 141. The material of the fill layer 145 may include, for example, silicon oxide. Optionally, the fill layer 145 may fill the stepped step 130 (…). Figure 6 Up to the top of stack layer 200.

[0071] In one example, a first fill layer (not shown) with good step coverage can be formed on the etch stop layer 141 by high-density plasma chemical vapor deposition (HDP-CVD) or ALD deposition process. The first fill layer includes, for example, silicon oxide.

[0072] For example, a second fill layer (not shown) with a high fill rate may be formed on the first fill layer. The second fill layer may be, for example, TEOS (Tetea-Ethyl-Ortho-Silicate) based silicon oxide. Optionally, the fill layer 145 may be further planarized using processes such as CMP, so that the fill layer 145 provides a substantially flat surface for the step region 140 of the stacked layer 200.

[0073] Refer again Figure 5 The manufacturing method 300 includes operation S350, wherein an etching process can be used to remove the sacrificial layer and form a conductive layer in the sacrificial space formed by removing the sacrificial layer, wherein the etching rate of the sacrificial layer by the same etching process is greater than the etching rate of the etching stop layer.

[0074] like Figure 10 As shown, in some embodiments, after forming the fill layer 145, a plurality of dummy channel structures 113 extending into the substrate 10 may be formed in the stacked layer 200. In some examples, forming the dummy channel structure 113 includes forming dummy channel vias (not shown) extending into the first sacrificial layer 102 in the stacked layer 200 using an etching process such as dry etching or wet etching. Optionally, the dummy channel vias may be filled with an insulating material to form the dummy channel structure 113. Figure 10 Only one dummy channel structure 113 is shown; however, it should be understood that multiple dummy channel structures 113 may be formed in the core region 120 and / or the step region 140. The dummy channel structure 113 may sequentially penetrate the filler layer 145, the etching stop layer 141, and the stepped step 130 in the step region 140. The function of the dummy channel structure 113 may include, for example, providing structural support to alleviate stress.

[0075] In some embodiments, etching processes such as dry etching or wet etching can be used to form gate gaps (not shown) in the stacked layer 200. These gate gaps can penetrate the stacked layer 200 along its thickness direction and extend into the substrate 10. Figure 11As shown, in some embodiments, the gate gap can be used as an etching channel, and an isotropic wet etching process (e.g., using hot phosphoric acid as the etching solution) can be used to remove the sacrificial layer 201 in the stacked layer 200, thereby forming the sacrificial gap 203. Optionally, the etching rate of the sacrificial layer 201 in the same etching process is greater than the etching rate of the etch stop layer 141. Optionally, under the same etching process, the etching selectivity ratio of the sacrificial layer 201 to the etch stop layer 141 is 10 to 30:1. Optionally, the etching selectivity ratio of the sacrificial layer 201 to the etch stop layer 141 can also be, for example, 20 to 30:1, so that the etch stop layer 141 in contact with the sacrificial layer 201 is hardly etched.

[0076] As mentioned above, the higher the film density of the etch stop layer 141, the lower its etching rate. Some embodiments of this application improve the film density of the etch stop layer 141 by combining ALD and heat treatment processes, thereby increasing the etching selectivity ratio between the sacrificial layer 201 and the etch stop layer 141 under the same etching process. When the sacrificial layer 201 is removed, the etch stop layer 141 is hardly etched. As a result, the etch stop layer 141 can increase the size of the subsequently formed word line contact 115. Figure 15 The landing window of the step 130 is provided. In addition, since it is not necessary to remove the portion of the etching stop layer 141 located on the side wall of the step 130 through etching process, the damage to the sacrificial layer 201 caused by the etching process is avoided, and the morphology of the step 130 and the film quality of the sacrificial layer 201 are effectively guaranteed.

[0077] like Figure 12 As shown, the gate gap can be used as a deposition channel, and conductive material can be filled into the sacrificial gap 203 to form a conductive layer 204. Optionally, the conductive layer 204 can be deposited inside the sacrificial gap 203 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Exemplarily, the material of the conductive layer 204 includes, for example, tungsten, cobalt, copper, aluminum, doped crystalline silicon, or silicides, or any combination thereof.

[0078] In other examples, at least one dielectric layer may be formed in the sacrificial gap 203 before the conductive layer 204 is formed to prevent impurities in the conductive layer 204 from diffusing into the storage layer 114.

[0079] In some examples, the gate gap may be filled in a suitable step to form a gate gap structure (not shown). Optionally, an insulating layer (not shown) and a conductor layer (not shown) may be sequentially formed on the inner wall and bottom of the gate gap using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The conductor layer may include, for example, tungsten, cobalt, copper, aluminum, doped crystalline silicon, or silicides, or any combination thereof.

[0080] Continue to refer to Figure 5The manufacturing method 300 includes operation S360, wherein word line contacts can be formed sequentially through a fill layer, an etch stop layer and extending to a corresponding conductive layer.

[0081] like Figure 15 As shown, multiple word line contacts 115 can be formed above the stepped structure 142, penetrating the filling layer 145 and extending to the corresponding conductive layer 204. For example, as... Figure 14 As shown, contact holes 117 can be formed above the stepped structure 142 by processes such as photolithography and plasma etching, which sequentially penetrate the filling layer 145, the etching stop layer 141 and extend to the corresponding conductive layer 204.

[0082] In some examples excluding the etch stop layer 141, the contact hole 117 may be formed by plasma etching. Due to the height difference of each step 130, the depth to which the contact hole 117 extends into the conductor layer 204 of each step 130 is different. For example, the plasma may first contact the conductive layer 204 away from the substrate 10, resulting in the contact hole 117 extending deeper into those conductive layers 204 than into the conductive layer 204 closer to the substrate 10. Therefore, the contact hole 117 is more likely to break through the conductive layer 204 away from the substrate 10, allowing the contact hole 117 to penetrate the corresponding conductive layer 204 and extend into the adjacent dielectric layer 202, or continue to extend into the adjacent conductive layer 204. As a result of the breakdown, the word line contact portion 115 subsequently formed in the contact hole 117 is prone to poor contact or word line leakage problems.

[0083] In some embodiments of this application, the contact holes 117 extending into the corresponding conductive layer 204 can be formed in stages. Optionally, such as... Figure 13 As shown, contact holes 117 can be formed above the stepped structure 142, penetrating the fill layer 145 and extending into the etch stop layer 141, using processes such as photolithography and plasma etching. In some examples, the etching selectivity ratio of the fill layer 145 to the etch stop layer 141 is, for example, 50–200:1, and the gas source used for etching in the plasma etching process includes, for example, CF4. In other examples, the etching selectivity ratio of the fill layer 145, the etch stop layer 141, and the conductive layer 204 can be improved by adjusting the type and proportion of the gas source used for etching in the etching process, thereby enabling the contact holes 117 to stop well in the etch stop layer 141.

[0084] In some examples, etching or other processes can be used to remove the etch stop layer 141 at the bottom of the contact hole 117, allowing the contact hole 117 to extend to the exposed surface of the conductive layer 204. In such cases... Figure 13In the example shown, the contact hole 117 can also pass through the etch stop layer 141 and extend into the conductive layer 204. In other examples, the etch selectivity ratio between the etch stop layer 141 and the conductive layer 204 can be improved by adjusting the type and proportion of gas sources used for etching in the etching process, thereby enabling the contact hole 117 to stop better in the conductive layer 204.

[0085] In some embodiments of this application, the etch stop layer 141 has a certain blocking and buffering effect, which allows the contact holes 117 at different heights to extend into the corresponding conductive layer 204 almost simultaneously, reducing the risk of word line leakage caused by the contact holes 117 breaking through the adjacent conductive layer 204.

[0086] As an example, after forming contact holes 117 extending to the corresponding conductive layers 204, conductive material can be filled into the contact holes 117 by ALD, PVD, CVD, or any combination thereof to form word line contacts 115. The word line contacts 115 can be electrically connected to their respective conductive layers 204, thereby allowing the conductive layers 204 to be electrically led out to interact with peripheral circuitry (not shown) for electrical signals. Optionally, the conductive material filled in the contact holes 117 can be at least one of tungsten, copper, silver, platinum, iron, and cobalt, or an alloy thereof.

[0087] Other embodiments of this application provide a three-dimensional memory 404, which can be manufactured by the method 300 described above. For example... Figure 16 As shown, in some examples, the three-dimensional memory 404 may include a stacked structure 200', wherein the stacked structure 200' may include a plurality of alternately stacked dielectric layers 202 and conductive layers 204.

[0088] As an example, the three-dimensional memory 404 may also include a semiconductor layer 110, wherein the stacked structure 200' may be located on the semiconductor layer 110. Alternatively, the semiconductor layer 110 may, for example, comprise polysilicon.

[0089] As an example, the stacked structure 200' may include a core region 120 and stepped regions 140 located on either side of the core region 120; optionally, the stepped regions 140 may also be located in the middle of the core region 120. It is understood that this is done for clarity. Figure 15 The stepped area 140 located on one side of the core area 120 is shown.

[0090] In some examples, the stacked structure 200' also includes an array of channel structures 111 located in the core region 120. In some embodiments, the channel structure 111 may include a barrier layer 112, a storage layer 114, a tunneling layer 116, and a channel layer 118 arranged sequentially from the outside to the inside. Optionally, the semiconductor layer 110 may be in electrical contact with the channel layer 118. In other examples, the stacked structure 200' may also include a dummy channel structure 113.

[0091] In some examples, the stacked structure 200' includes a step structure 142 located in the step region 140. The step structure 142 may include a plurality of stepped steps, each step including the thickness of at least one conductive layer 204 / dielectric layer 202 pair. Optionally, the top of the stepped step away from the semiconductor layer 110 includes at least a portion of the conductive layer 204.

[0092] In some examples, such as Figure 16 As shown, the three-dimensional memory 404 also includes at least one etch stop layer 141 located on the stepped structure 142, the material of the etch stop layer 141 including, for example, silicon oxynitride. Exemplarily, the etch stop layer 141 may be disposed on the sidewalls of each stepped step, and the etch stop layer 141 may also be disposed on at least a portion of the conductive layer 204 included on the top of each stepped step. Optionally, the etch stop layer 141 may conformally cover the sidewalls of each stepped step and the platform on which its top is located.

[0093] In some examples, such as Figure 16 As shown, the three-dimensional memory 404 also includes a filling layer 145 located above the step structure 142, which can provide a relatively flat surface for the step area 140.

[0094] In some examples, the three-dimensional memory 404 may also include a gate gap structure (not shown) that penetrates the stacked structure 200' in the core region 120 and the step region 140, respectively. Optionally, the gate gap structure may include an insulating layer (not shown) and a conductor layer (not shown) disposed sequentially from the outside to the inside.

[0095] Continue to refer to Figure 16 In some examples, the three-dimensional memory 404 also includes word line contacts 115, which can pass through the fill layer 145, the buffer layer 143 and extend into the corresponding conductive layer 204.

[0096] Since the content and structure described above regarding manufacturing method 300 are fully or partially applicable to the three-dimensional memory 404 described herein, related or similar content will not be repeated.

[0097] like Figure 17As shown, in some examples, the three-dimensional memory 404 includes a coupled memory array 401 and peripheral circuitry 301, the memory array 401 including, for example, the stacked structure 200' described above. In some embodiments, the memory array 401 and peripheral circuitry 301 may be arranged on the same chip. In other embodiments, the memory array 401 may be arranged on an array chip, and the peripheral circuitry 301 may be arranged on a different chip (e.g., implemented using complementary metal-oxide-semiconductor (CMOS) technology, and referred to as a CMOS chip). The array chip and the CMOS chip may be electrically coupled together by processes such as bonding. In some embodiments, the three-dimensional memory 404 is an integrated circuit (IC) package that encapsulates one or more array chips and CMOS chips.

[0098] Optionally, the three-dimensional memory 404 may be configured to store data in the memory array 401 and perform operations in response to received commands (CMDs). In some embodiments, the three-dimensional memory 404 may receive write commands, read commands, erase commands, etc., and may perform operations accordingly.

[0099] Typically, storage array 401 may include one or more storage planes 160, and each storage plane 160 may include multiple storage blocks (e.g., Figure 17 (See blocks -1 to -N). In some examples, concurrent operations may occur at different storage planes 160.

[0100] In some embodiments, the storage array 401 may be, for example, a flash memory array, and may be implemented using 3D NAND flash memory technology. In some embodiments, the peripheral circuitry 301 includes a row decoder (word line driver) 302, a page buffer (sensor amplifier) ​​303, a data input / output (I / O) circuitry 130, a voltage generator 305, and a control circuitry 150 coupled together.

[0101] In some examples, the line decoder (word line driver) 302 may be configured to drive the word line (WL) based on the line address (R-ADDR) from the control circuitry 150 and the word line voltage generated by the voltage generator 305. In some implementations, the line decoder (word line driver) 302 may also select / deselect and drive the source select line (SSL) and drain select line (DSL).

[0102] In some examples, the page buffer (sensor amplifier) ​​303 is coupled to the bit line (BL) of the memory array 401 and is configured to buffer data during read and write operations according to control signals from the control circuitry 150. Optionally, the page buffer (sensor amplifier) ​​303 can sense a low-power signal representing a stored data bit from the bit line (BL) during a read operation.

[0103] In some examples, peripheral circuitry 301 also includes a column decoder (bit line driver), which can be configured to be controlled by control circuitry 150.

[0104] In some examples, data I / O circuitry 304 is coupled to page buffer 303 via data line DR. In one example (e.g., during a read operation), data I / O circuitry 304 is configured to upload data read from memory array 401 to external circuitry (e.g., memory controller 406) via page buffer 303 and BL.

[0105] In some examples, voltage generator 305 is configured to generate appropriate voltages for proper operation of the three-dimensional memory 404. For example, voltage generator 305 may generate appropriate read voltages, programming voltages, or erase voltages during operation of the three-dimensional memory 404.

[0106] In some examples, control circuitry 150 is configured to receive commands (CMD) and addresses (ADDR), and based on these commands and addresses, to provide control signals to circuits such as row decoder 302, page buffer 120, data I / O circuitry 304, and voltage generator 305. For example, control circuitry 150 may generate row address R-ADDR and column address C-ADDR based on address ADDR, and provide row address R-ADDR to row decoder 302 and column address to data I / O circuitry 304. In other examples, control circuitry 150 may control voltage generator 305 to generate appropriate voltages based on the received CMD. Control circuitry 150 may coordinate other circuits to provide signals to memory array 401 at appropriate times and with appropriate voltages.

[0107] like Figure 18 As shown, in some examples, system 400 may include a host 408 and a memory system 402 having one or more three-dimensional memories 404 and a memory controller 406. Host 408 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-a-chip (SoC), such as an application processor (AP). Host 408 may be configured to send or receive data stored in the three-dimensional memory 404. Alternatively, system 400 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0108] According to some embodiments, a memory controller 406 is coupled to a 3D memory 404 and a host 408 and is configured to control the 3D memory 404. The memory controller 406 can manage data stored in the 3D memory 404 and communicate with the host 408. In some embodiments, the memory controller 406 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, the memory controller 406 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs) used for data storage in mobile devices (such as smartphones, tablets, laptops, etc.) and enterprise storage arrays. The memory controller 406 can be configured to control operations of the 3D memory 404, such as read, erase, and program operations. The memory controller 406 can also be configured to manage various functions related to data stored or to be stored in the 3D memory 404, including bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 406 is also configured to process error correction codes (ECC) for data read from or written to the 3D memory 404. The memory controller 406 may also perform any other suitable function, such as formatting the 3D memory 404. The memory controller 406 can communicate with external devices (e.g., host 408) according to specific communication protocols. For example, the memory controller 406 can communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Mini-Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0109] The memory controller 406 and one or more three-dimensional memories 404 can be integrated into various types of storage devices, for example, included in the same package, such as a Universal Flash Memory (UFS) package or an eMMC package. That is, the memory system 402 can be implemented as and packaged into different types of end electronic products. Figure 19In one example shown, the memory controller 406 and a single 3D memory 404 can be integrated into the memory card 502. The memory card 502 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 502 may further include a connection between the memory card 502 and a host computer (e.g., Figure 18 The host 408) is electrically coupled to the memory card connector 504. In such a... Figure 20 In another example shown, the memory controller 406 and multiple 3D memories 404 can be integrated into the SSD 506. The SSD 506 may further include interfaces between the SSD 506 and a host (e.g., Figure 18 The host 408 is electrically coupled to the SSD connector 508. In some embodiments, the storage capacity and / or operating speed of the SSD 506 is greater than the storage capacity and / or operating speed of the memory card 502.

[0110] Although exemplary manufacturing methods and structures of three-dimensional memory are described herein, it is understood that one or more features may be omitted, substituted, or added from the structure of the three-dimensional memory. Furthermore, the layers and materials described are merely illustrative.

[0111] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above are merely specific embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for manufacturing a three-dimensional memory, comprising: A stacked layer comprising alternating dielectric and sacrificial layers is formed on a substrate, the stacked layer including a stepped structure having a plurality of stepped steps, the surface of the stepped steps facing away from the substrate exposing at least a portion of the sacrificial layer; At least one buffer layer is formed at a first temperature on at least a portion of the exposed sidewalls of the plurality of stepped steps and the sacrificial layer, the buffer layer being made of a material comprising chlorinated silicon oxynitride; and The buffer layer is heat-treated at a second temperature greater than the first temperature to remove impurities containing chlorine and form an etch stop layer, the density of which is greater than that of the buffer layer. The sacrificial layer is removed by an etching process, and a conductive layer is formed in the sacrificial gap formed by removing the sacrificial layer, wherein the sacrificial layer and the etching stop layer are made of different materials; A fill layer is formed on the etch stop layer; and A word line contact is formed that sequentially penetrates the fill layer and the etch stop layer and extends to the corresponding conductive layer.

2. The method according to claim 1, wherein, The first temperature range is 200℃~800℃.

3. The method according to claim 1, wherein, The second temperature range is 550℃~1100℃.

4. The method according to claim 1, wherein, At least one of the sacrificial layer or the etch stop layer is made of a different material than the buffer layer.

5. The method according to claim 1, wherein, The sacrificial layer comprises silicon nitride, and at least one of the buffer layer or the etch stop layer comprises silicon oxynitride.

6. The method according to claim 1, further comprising: During the removal of the sacrificial layer, the etching rate of the sacrificial layer by the same etching process is greater than the etching rate of the etching stop layer.

7. The method according to claim 6, wherein, Under the same etching process, the etching selectivity ratio of the sacrificial layer to the etching stop layer ranges from 10 to 30:

1.

8. The method according to claim 1, wherein, The word line contact portion includes: A contact hole is formed above the stepped structure, penetrating the filler layer and extending into the etch stop layer; and Remove the etch stop layer located at the bottom of the contact hole to extend the contact hole to the conductive layer.

9. The method according to claim 8, wherein, The word line contact portion further includes: The contact hole is filled with conductive material to form the word line contact portion.

10. A three-dimensional memory, formed using the manufacturing method according to any one of claims 1-9, comprising: A stacked structure comprising alternating stacked dielectric and conductive layers, the stacked structure comprising a stepped structure having a plurality of stepped steps, each stepped step having a thickness of at least one conductive and dielectric layer pair, wherein the top of the stepped step includes at least a portion of the conductive layer. At least one etch stop layer is disposed on the sidewall of each of the stepped steps and on at least a portion of the conductive layer, the etch stop layer comprising silicon oxynitride; and A filler layer is located on the etch stop layer; The word line contact portion passes through the filling layer and the etch stop layer in sequence and extends to the corresponding conductive layer.

11. A memory system, comprising: The three-dimensional memory as described in claim 10; as well as A memory controller is coupled to the three-dimensional memory and configured to control the three-dimensional memory.

12. The memory system of claim 11, comprising: Solid-state drive or memory card.

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