Semiconductor device, three-dimensional memory having the same, and storage system

Abstract

The application provides a semiconductor device, a three-dimensional memory and a storage system having the same. The semiconductor device comprises: a semiconductor substrate; a plurality of transistor structures arranged on one side of the semiconductor substrate; an isolation structure arranged in the semiconductor substrate, the isolation structure being used to separate the semiconductor substrate into a plurality of active regions, each transistor structure comprising a gate, a gate dielectric layer and source / drain regions, the gate dielectric layer and the gate being arranged in a stack on a surface of the active region, and the source / drain regions being located in the active regions on both sides of the gate; a plurality of first conductive channels arranged on the semiconductor substrate and connected to the source / drain regions; and a semiconductor wiring layer arranged on a surface of the isolation structure away from the semiconductor substrate, and the semiconductor wiring layer being connected to at least one pair of adjacent first conductive channels separated by the isolation structure. The application can optimize the wiring efficiency, reduce the number of interconnection layers required when subsequently bonding with the memory array, and thus reduce the process difficulty.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device, a three-dimensional memory having the same, and a storage system. Background Technology

[0002] With the increasing demand for integration and storage capacity, 3D NAND flash memory emerged. 3D NAND flash memory significantly saves silicon wafer area, reduces manufacturing costs, and increases storage capacity.

[0003] In 3D NAND memory structures, multiple layers of data storage cells are vertically stacked to achieve a stacked 3D NAND memory structure. However, other circuits, such as decoders, page buffers, and latches, are peripheral circuits formed using CMOS devices. The fabrication process for CMOS devices cannot be integrated with that of 3D NAND devices. Currently, different processes are used to form the 3D NAND memory array and peripheral circuits, and then bonding the two together using bonding technology.

[0004] In the current CMOS process of 3D NAND memory, as the number of interconnect layers increases, the requirements for CMOS process also become more stringent. At the same time, as the CMOS size becomes smaller, the number of interconnect layers in the back end of line (BEOL) process also increases accordingly, thus increasing the difficulty of the process. Summary of the Invention

[0005] The main objective of this application is to provide a semiconductor device, a three-dimensional memory having the same, and a memory system, in order to solve the problem of complex processes caused by the large number of interconnect layers when bonding semiconductor devices and memory arrays.

[0006] To achieve the above objectives, according to one aspect of this application, a semiconductor device is provided, comprising: a semiconductor substrate; a plurality of transistor structures disposed on one side of the semiconductor substrate; an isolation structure disposed in the semiconductor substrate, the isolation structure being used to separate the semiconductor substrate into a plurality of active regions, each transistor structure including a gate, a gate dielectric layer and a source / drain region, the gate dielectric layer and the gate layer being stacked on the surface of the active region, the source / drain region being located in the active regions on both sides of the gate; a plurality of first conductive channels disposed on the semiconductor substrate, and the first conductive channels being connected to the source / drain regions; and a semiconductor interconnect layer disposed on the surface of the isolation structure away from the semiconductor substrate, and the semiconductor interconnect layer connecting at least one pair of adjacent first conductive channels spaced apart by the isolation structure.

[0007] Furthermore, the transistor structure is arranged in an array on one side of the semiconductor substrate. The array includes a plurality of transistor units arranged sequentially along a first direction. Each transistor unit includes a plurality of transistor structures arranged along a second direction. Adjacent first conductive channels in the first direction are connected by a semiconductor interconnect layer, and / or adjacent first conductive channels in the second direction are connected by a semiconductor interconnect layer.

[0008] Furthermore, the semiconductor interconnect layer includes: a first semiconductor interconnect portion connected to an adjacent first conductive channel in a first direction; and a second semiconductor interconnect portion connected to an adjacent first semiconductor interconnect portion.

[0009] Furthermore, the semiconductor interconnect layer includes: a third semiconductor interconnect portion connected to an adjacent first conductive channel in the second direction; and a fourth semiconductor interconnect portion connected to an adjacent third semiconductor interconnect portion.

[0010] Furthermore, the first conductive channel extends in a direction away from the semiconductor substrate, and the sidewall of the first conductive channel is disposed in contact with the semiconductor interconnect layer.

[0011] Furthermore, the semiconductor device also includes a first contact layer that covers the side of the semiconductor interconnect layer away from the isolation structure, and a first conductive channel that is connected to the semiconductor interconnect layer through the first contact layer, or the first conductive channel that is connected to both the first contact layer and the semiconductor interconnect layer.

[0012] Furthermore, the semiconductor interconnect layer is a polycrystalline silicon layer, and the first contact layer is a metal silicide layer.

[0013] Furthermore, the semiconductor device also includes a second contact layer, which is configured to contact the source / drain region, and the first conductive channel is configured to connect to the source / drain region through the second contact layer.

[0014] According to another aspect of this application, a method for fabricating the above-mentioned semiconductor device is provided, comprising the following steps: providing a semiconductor substrate; forming an isolation structure on one side of the semiconductor substrate, the isolation structure being used to separate a plurality of active regions in the semiconductor substrate; forming a plurality of transistor structures and a semiconductor interconnect layer on one side of the semiconductor substrate, each transistor structure including a gate, a gate dielectric layer and a source / drain region, the gate dielectric layer and the gate layer being stacked on the surface of the active region, the source / drain region being located in the active regions on both sides of the gate, and the semiconductor interconnect layer being located on the surface of the isolation structure away from the semiconductor substrate; forming a plurality of first conductive channels on the semiconductor substrate, the first conductive channels being connected to the source / drain regions, and at least one pair of adjacent first conductive channels spaced apart by the isolation structure being connected through the semiconductor interconnect layer.

[0015] Furthermore, the step of forming a transistor structure and a semiconductor interconnect layer on one side of the semiconductor substrate includes: forming a gate dielectric layer on the surface of the active region; forming a gate on the surface of the gate dielectric layer, while forming a semiconductor interconnect layer on the surface of the isolation structure; and forming source / drain regions in the active regions located on both sides of the gate.

[0016] Furthermore, prior to the step of forming multiple first conductive channels on the semiconductor substrate, the fabrication method further includes: forming a first contact layer and a second contact layer on one side of the semiconductor substrate, wherein the first contact layer covers the side of the semiconductor interconnect layer away from the isolation structure, and the second contact layer contacts the source / drain regions.

[0017] Furthermore, the step of forming a first contact layer and a second contact layer on one side of the semiconductor substrate includes: simultaneously covering the surface of the semiconductor interconnect layer and the surface of the source / drain region with a metal material; annealing the metal material to metallize the surface of the semiconductor interconnect layer to form the first contact layer, and simultaneously metallizing the surface of the source / drain region to form the second contact layer.

[0018] According to another aspect of this application, a three-dimensional memory is also provided, including a memory array, peripheral circuitry, and an interconnect layer. The memory array and the peripheral circuitry are bonded together through the interconnect layer. The peripheral circuitry includes the semiconductor device described above or a semiconductor device obtained using the fabrication method described above. A first conductive channel in the semiconductor device is connected to the interconnect layer.

[0019] According to another aspect of this application, a storage system is also provided, including a controller and a three-dimensional memory, the three-dimensional memory being configured to store data, and the controller being coupled to the three-dimensional memory and configured to control the three-dimensional memory, the three-dimensional memory being the aforementioned three-dimensional memory.

[0020] This application provides a semiconductor device comprising a plurality of transistor structures disposed on one side of a semiconductor substrate, an isolation structure disposed within the semiconductor substrate to divide the semiconductor substrate into a plurality of active regions, a plurality of first conductive channels disposed on the semiconductor substrate and connected to the transistor structures, and a semiconductor interconnect layer disposed on the surface of the isolation structure away from the semiconductor substrate, the semiconductor interconnect layer connecting at least one pair of adjacent first conductive channels spaced apart by the isolation structure. This application pre-implements the interconnection of the source / drain regions of the plurality of transistors through the isolation structure, and by setting the aforementioned semiconductor interconnect layer, realizes the interconnection layout on the surface of the isolation structure. This allows multiple connected first conductive channels to be led out through only one of them via the semiconductor interconnect layer to achieve the lead-out of the source / drain regions of the plurality of transistors. Subsequently, the interconnect layer is connected to the semiconductor interconnect layer, thereby optimizing interconnection efficiency, reducing the number of interconnect layers required for subsequent bonding with the memory array, and thus reducing process complexity. Attached Figure Description

[0021] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0022] Figure 1 A partial top view of a semiconductor device provided in an embodiment of this application is shown;

[0023] Figure 2 It shows Figure 1 A partial top view of region A in the semiconductor device shown;

[0024] Figure 3 It shows Figure 2 A schematic diagram of the cross-sectional structure of region A along the aa' direction in the semiconductor device shown;

[0025] Figure 4 It shows Figure 1 A top view of the semiconductor interconnect layer in the semiconductor device shown.

[0026] Figure 5 A partial top view of another semiconductor device provided in an embodiment of this application is shown;

[0027] Figure 6 It shows Figure 5 A partial top view of region B in the semiconductor device shown;

[0028] Figure 7 It shows Figure 6 A schematic diagram of the cross-sectional structure of region B along the bb' direction in the semiconductor device shown.

[0029] Figure 8 It shows Figure 5 A top view of the semiconductor interconnect layer in the semiconductor device shown.

[0030] Figure 9 A kind of Figure 1 Region A in the semiconductor device shown Figure 5 The diagram shows a cross-sectional view of region B in the Y direction of the semiconductor device shown.

[0031] Figure 10 Another one is shown Figure 1 Region A in the semiconductor device shown Figure 5 The diagram shows a cross-sectional view of region B in the Y direction of the semiconductor device shown.

[0032] Figure 11A schematic flowchart of a method for fabricating a semiconductor device provided in an embodiment of this application is shown;

[0033] Figure 12 This illustration shows a top view of the substrate after an isolation structure is formed on one side of a semiconductor substrate in a method for fabricating a semiconductor device according to an embodiment of this application.

[0034] Figure 13 It shows in Figure 12 The diagram shows a top view of the substrate after multiple transistor structures and semiconductor interconnect layers are formed on one side of the semiconductor substrate. The isolation structure is located between adjacent transistor structures, and the semiconductor interconnect layer is located on the side surface of the isolation structure away from the semiconductor substrate.

[0035] Figure 14 It shows in Figure 13 The diagram shows a top view of the substrate after a first contact layer is formed on the surface of the semiconductor interconnect layer and a second contact layer is formed on the surface of the source / drain regions.

[0036] Figure 15 It shows in Figure 14 The diagram shows a top view of the substrate after multiple first conductive channels are formed on the semiconductor substrate. The first conductive channels are contacted and arranged in a one-to-one correspondence with the transistor structure, and adjacent first conductive channels are connected through a semiconductor interconnect layer.

[0037] Figure 16 A schematic diagram of a three-dimensional memory provided according to an embodiment of this application is shown;

[0038] Figure 17 A schematic diagram of the structure of a storage system provided according to an embodiment of this application is shown.

[0039] The above figures include the following reference numerals:

[0040] 10. Semiconductor substrate; 110. Active region; 120. Fin segment; 210. Gate; 220. Gate dielectric layer; 230. Source / drain region; 30. Isolation structure; 40. First conductive channel; 50. Semiconductor interconnect layer; 510. First semiconductor interconnect portion; 520. Second semiconductor interconnect portion; 530. Third semiconductor interconnect portion; 540. Fourth semiconductor interconnect portion; 60. First contact layer; 70. Second contact layer; 80. Third contact layer; 300. Three-dimensional memory; 301. Memory array; 302. Peripheral circuit; 303. Interconnect layer; 400. Memory system; 401. Three-dimensional memory; 402. Controller. Detailed Implementation

[0041] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0042] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0043] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0044] In the current CMOS process of 3D NAND memory, as the number of interconnect layers increases, the requirements for CMOS process also become more stringent. At the same time, as the CMOS size becomes smaller, the number of interconnect layers in the BEOL back-end process also increases accordingly, thus increasing the process difficulty.

[0045] Therefore, the inventors conducted research on the above problems and proposed a semiconductor device, such as... Figures 1 to 8 As shown, the system includes a semiconductor substrate 10, multiple transistor structures, an isolation structure 30, multiple first conductive channels 40, and a semiconductor interconnect layer 50. The multiple transistor structures are disposed on one side of the semiconductor substrate 10. The isolation structure 30 is used to divide the semiconductor substrate 10 into multiple active regions 110. Each transistor structure includes a gate 210, a gate dielectric layer 220, and a source / drain region 230. The gate dielectric layer 220 and the gate 210 are stacked on the surface of the active region 110, and the source / drain region 230 is located in the active regions 110 on both sides of the gate 210. The multiple first conductive channels 40 are disposed on the semiconductor substrate 10 and are connected to the source / drain regions. The semiconductor interconnect layer 50 is disposed on the side surface of the isolation structure 30 away from the semiconductor substrate 10, and the semiconductor interconnect layer 50 connects at least one pair of adjacent first conductive channels 40 separated by the isolation structure 30.

[0046] In the prior art, the isolation structure 30 typically occupies a large area (approximately 50%) on one side of the semiconductor substrate 10 in order to separate adjacent transistor structures. In this application, the connection between the source / drain regions of multiple transistors is pre-implemented through the isolation structure. By setting the aforementioned semiconductor interconnect layer, the interconnect layout on the surface of the isolation structure is realized. This allows multiple first conductive channels connected together to be led out through only one of them via the semiconductor interconnect layer, thereby enabling the lead-out of the source / drain regions of multiple transistors. Subsequently, the interconnect layer is connected to the semiconductor interconnect layer. By making full use of the isolation structure that occupies a large area, the interconnect efficiency is optimized, and the number of interconnect layers required for subsequent bonding with the memory array via the interconnect layer is reduced, thereby reducing the process difficulty.

[0047] The semiconductor substrate 10 can be made of single-crystal silicon (Si), single-crystal germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other III-V compounds.

[0048] The aforementioned isolation structure 30 can be a structure formed by shallow trench isolation (STI) process, and the material forming the aforementioned isolation structure 30 can be a conventional insulating material in the prior art, such as silicon oxide.

[0049] In some embodiments of this application, the transistor structure described above can be arranged in an array on one side of the semiconductor substrate 10. The array includes a plurality of transistor units arranged sequentially along a first direction (X direction), and each transistor unit includes a plurality of transistor structures arranged along a second direction (Y direction). Adjacent first conductive channels 40 are connected via a semiconductor interconnect layer 50 in the first direction, and / or adjacent first conductive channels 40 are connected via a semiconductor interconnect layer 50 in the second direction. Figure 1 and Figure 5 As shown.

[0050] In an optional embodiment of this application, the transistor structure is arranged in an array on one side of the semiconductor substrate 10, and the semiconductor interconnect layer 50 includes a first semiconductor interconnect portion 510 and a second semiconductor interconnect portion 520, such as... Figure 1 and Figure 4 As shown, the first semiconductor interconnect 510 is connected to the adjacent first conductive channel 40 in the first direction (X direction); the second semiconductor interconnect 520 is connected to the adjacent first semiconductor interconnect 510.

[0051] In another optional embodiment of this application, the transistor structure is arranged in an array on one side of the semiconductor substrate 10, and the semiconductor interconnect layer 50 includes a third semiconductor interconnect portion 530 and a fourth semiconductor interconnect portion 540, such as... Figure 5and Figure 8 As shown, the third semiconductor interconnect 530 is connected to the adjacent first conductive channel 40 in the second direction (Y direction); the fourth semiconductor interconnect 540 is connected to the adjacent third semiconductor interconnect 530.

[0052] In the above-mentioned optional embodiments, a mask can be fabricated according to the arrangement of the transistor structure on one side of the semiconductor substrate 10, so that the cutout area of ​​the mask corresponds to the pre-formed semiconductor interconnect layer 50 connecting adjacent transistor structures. This allows the semiconductor interconnect layer 50, composed of the first semiconductor interconnect portion 510 and the second semiconductor interconnect portion 520, or composed of the third semiconductor interconnect portion 530 and the fourth semiconductor interconnect portion 540, to be obtained using the mask. The process is simple and easy to implement. To further simplify the fabrication of the mask, the first semiconductor interconnect portion 510, the second semiconductor interconnect portion 520, the third semiconductor interconnect portion 530, and the fourth semiconductor interconnect portion 540 can be elongated, but are not limited to these shapes.

[0053] The isolation structure 30 in the aforementioned semiconductor device is used to separate the semiconductor substrate 10 into multiple active regions 110. Each transistor structure includes a gate 210, a gate dielectric layer 220, and a source / drain region 230. The gate dielectric layer 220 and the gate 210 are stacked on the surface of the active region 110, and the source / drain region 230 is located in the active regions 110 on both sides of the gate 210. Figure 1 , Figure 3 , Figure 5 and Figure 7 As shown. For example, the transistor structure described above is a CMOS transistor structure.

[0054] The first conductive channel 40 is connected to the source / drain region 230, and by connecting the first conductive channel 40 to the semiconductor interconnect layer, the source and drain of the device are brought out. For example, the first conductive channel 40 extends in a direction away from the semiconductor substrate 10, and the sidewalls of the first conductive channel 40 are in contact with the semiconductor interconnect layer 50. Figure 3 and Figure 7 As shown.

[0055] In an optional embodiment of this application, the gate 210 in the above transistor structure is a planar gate structure, such as... Figure 9 As shown, the planar grid structure has a simple manufacturing process and is easy to implement.

[0056] In another optional embodiment of this application, the transistor structure is an X-FET structure. Exemplarily, the semiconductor substrate 10 may include fin segments 120 corresponding one-to-one with the transistor structure. The fin segments 120 are located between the source / drain regions 230 of the same transistor structure. An isolation structure 30 is located on both sides of the fin segments 120 along a first direction, and a gate 210 is disposed across the fin segments 120. A gate dielectric layer 220 is at least disposed between the gate 210 and the fin segments 120. Figure 10 As shown. The above-described arrangement of gate 210 can narrow the active region, which is beneficial for shrinking the process layout and thus for device miniaturization.

[0057] The gate 210 can be a polysilicon layer, and the gate dielectric layer 220 can be silicon oxide. The gate 210 may also include work function layers, which can be multiple layers. The materials forming the work function layers include, but are not limited to, combinations of metals, silicides, and insulating materials. Those skilled in the art can adjust the various work function layers constituting the gate 210 according to actual needs. Furthermore, the transistor structure may also include sidewalls located on both sides of the gate 210. These sidewalls define the distance between the source and drain of the transistor structure and protect the work function layers.

[0058] The aforementioned source / drain region 230 can be formed according to conventional ion implantation and annealing processes in the prior art. Those skilled in the art can reasonably select the types of implanted ions based on the prior art, which will not be elaborated further in this application.

[0059] In the semiconductor device described above in this application, preferably, the semiconductor device further includes a first contact layer 60, such as... Figure 1 , Figure 3 , Figure 5 and Figure 7 As shown, the first contact layer 60 covers the side of the semiconductor interconnect layer 50 away from the isolation structure 30. In this case, the first conductive channel 40 can be connected to the semiconductor interconnect layer 50 through the first contact layer 60, or it can be connected to both the first contact layer 60 and the semiconductor interconnect layer 50. The first contact layer 60 is used to reduce the resistance of the semiconductor interconnect layer 50, thereby reducing the RC delay time of the device.

[0060] More preferably, the semiconductor interconnect layer 50 is a polycrystalline silicon layer, and the first contact layer 60 is a metal silicide layer. In this case, the surface of the semiconductor interconnect layer 50 can be metallized to form a metal silicide layer by depositing a metal material on the surface of the semiconductor interconnect layer 50 and then annealing it. This process is simple and easy to implement. Besides the metallization process described above, the metal silicide layer can also be formed using conventional deposition processes in the prior art, and this application does not impose specific limitations on this method.

[0061] More preferably, the metal silicide layer is NiSi, and the annealing temperature in the annealing process for forming NiSi is relatively low (less than 600°C), thereby reducing damage to the device. However, the metal silicide layer is not limited to the preferred type mentioned above, and can also be a conventional type in the prior art, such as TiSi2, CoSi2, etc.

[0062] In a preferred embodiment, the semiconductor device further includes a second contact layer 70, such as... Figure 1 , Figure 3 , Figure 5 and Figure 7 As shown, the second contact layer 70 is disposed in contact with the source / drain region 230, and the first conductive channel 40 is connected to the source / drain region 230 through the second contact layer 70. The aforementioned second contact layer 70 can be used to reduce the resistance of the source and drain in the transistor structure, thereby reducing the RC delay time of the device.

[0063] More preferably, the semiconductor substrate 10 is a silicon substrate, and the second contact layer 70 is a metal silicide layer. In this case, the metal silicide layer can be formed by depositing metal material on the surface of the source / drain regions 230 in the semiconductor substrate 10 and then annealing it. This process is simple and easy to implement. In addition to the above-mentioned metallization process, the metal silicide layer can also be formed by conventional deposition processes in the prior art, which are not specifically limited in this application.

[0064] The transistor structure described above in this application may further include a third contact layer 80 located on the surface of the gate 210, such as... Figure 1 , Figure 3 , Figure 5 and Figure 7 As shown. The third contact layer 80 can be used to reduce the resistance of the gate 210, thereby further reducing the RC delay time of the device.

[0065] For example, the gate 210 is a polysilicon layer, and the third contact layer 80 is a metal silicide layer. In this case, a metal silicide layer can be formed by depositing a metal material on the surface of the gate 210 and then annealing it. The process is simple and easy to implement. In addition to the metallization process described above, the metal silicide layer can also be formed by conventional deposition processes in the prior art, and this application does not make specific limitations.

[0066] The transistor structure described above in this application may further include a second conductive channel (not shown in the figure), which is connected to the side of the gate 210 away from the semiconductor substrate 10, or connected to the side of the gate 210 away from the semiconductor substrate 10 through the third contact layer 80, for leading out the gate 210 through the interconnect layer subsequently formed.

[0067] According to embodiments of this application, a method for fabricating a semiconductor device as described above is also provided. Figure 11 As shown, it includes the following steps:

[0068] A semiconductor substrate is provided, and an isolation structure is formed on one side of the semiconductor substrate. The isolation structure is used to separate multiple active regions in the semiconductor substrate.

[0069] Multiple transistor structures and semiconductor interconnect layers are formed on one side of a semiconductor substrate. Each transistor structure includes a gate, a gate dielectric layer, and a source / drain region. The gate dielectric layer and the gate layer are stacked on the surface of the active region. The source / drain regions are located in the active regions on both sides of the gate, and the semiconductor interconnect layer is located on the surface of the isolation structure away from the semiconductor substrate.

[0070] Multiple first conductive channels are formed on a semiconductor substrate, and the first conductive channels are connected to the source / drain regions. At least one pair of adjacent first conductive channels separated by an isolation structure are connected through a semiconductor interconnect layer.

[0071] In the above-described fabrication method of this application, a semiconductor interconnect layer is formed on the surface of the isolation structure away from the semiconductor substrate, and the semiconductor interconnect layer connects adjacent first conductive channels. This allows for the pre-implementation of the connection between the source / drain regions of multiple transistors through the isolation structure. By setting the semiconductor interconnect layer, the interconnection layout on the surface of the isolation structure is realized. This allows multiple connected first conductive channels to be led out through only one of them via the semiconductor interconnect layer, thus enabling the lead-out of the source / drain regions of multiple transistors. Subsequently, the interconnect layer is connected to the semiconductor interconnect layer, thereby optimizing the interconnection efficiency and reducing the number of interconnect layers required for subsequent bonding with the memory array via the interconnect layer, thereby reducing the process difficulty.

[0072] Exemplary embodiments of the method for fabricating a semiconductor device according to the present invention will now be described in more detail with reference to the accompanying drawings. However, these exemplary embodiments may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of this application is thorough and complete, and that the concept of these exemplary embodiments is fully conveyed to those skilled in the art.

[0073] First, a semiconductor substrate 10 is provided, and an isolation structure 30 is formed on one side of the semiconductor substrate 10. The isolation structure 30 is used to separate the semiconductor substrate 10 into multiple active regions 110, such as... Figure 12 As shown.

[0074] In a preferred embodiment, the isolation structure 30 is formed using a shallow trench isolation (STI) process. Specifically, the STI process may include the following steps: forming a trench on the surface of the semiconductor substrate 10 using a masking and patterning process; filling the trench with an insulating material, which may completely fill the trench or partially protrude from it, thereby obtaining the isolation structure 30. The material forming the isolation structure 30 can be a conventional insulating material in the prior art, such as silicon oxide.

[0075] After the steps of forming the isolation structure 30 described above, a plurality of transistor structures and a semiconductor interconnect layer 50 are formed on one side of the semiconductor substrate 10. Each transistor structure includes a gate 210, a gate dielectric layer 220, and a source / drain region 230. The gate dielectric layer 220 and the gate 210 are stacked on the surface of the active region 110. The source / drain regions 230 are located in the active regions 110 on both sides of the gate 210, and the semiconductor interconnect layer 50 is located on the side of the isolation structure 30 away from the semiconductor substrate 10. Figure 13 and Figure 14 As shown.

[0076] In a preferred embodiment, the step of forming a transistor structure and a semiconductor interconnect layer 50 on one side of the semiconductor substrate 10 includes: forming a gate dielectric layer 220 on the surface of the active region 110; forming a gate 210 on the surface of the gate dielectric layer 220, while forming a semiconductor interconnect layer 50 on the surface of the isolation structure 30; and forming source / drain regions 230 in the active regions 110 located on both sides of the gate 210.

[0077] In the preferred embodiment described above, only the mask needs to be optimized to form the gate 210 and the semiconductor interconnect layer 50 simultaneously in the same process step, thus avoiding the process complexity caused by additional process steps.

[0078] More preferably, prior to the step of forming a plurality of first conductive channels 40 on the semiconductor substrate 10, the fabrication method further includes: forming a first contact layer 60 on the surface of the semiconductor interconnect layer 50, and forming a second contact layer 70 on the surface of the source / drain region 230, such as... Figure 14 As shown. Furthermore, the above-described fabrication method of this application may also include the step of forming a third contact layer 80 on the surface of the gate 210. The first contact layer 60 is used to reduce the resistance of the semiconductor interconnect layer 50, the second contact layer 70 can be used to reduce the resistance of the source and drain in the transistor structure, and the third contact layer 80 can be used to reduce the resistance of the gate 210, thereby reducing the RC delay time of the device.

[0079] For example, the material forming the gate 210 and the semiconductor interconnect layer 50 is polysilicon, and the semiconductor substrate 10 is a silicon substrate. In this case, the steps of forming the first contact layer 60, the second contact layer 70, and the third contact layer 80 may include: simultaneously covering the surface of the semiconductor interconnect layer 50, the surface of the source / drain region 230, and the surface of the gate 210 with a metal material; annealing the metal material to metallize the surface of the semiconductor interconnect layer 50 to form the first contact layer 60, the surface of the source / drain region 230 to form the second contact layer 70, and the surface of the gate 210 to form the third contact layer 80. By simultaneously forming the first contact layer 60, the second contact layer 70, and / or the third contact layer 80 in the same process step, the process is not complicated by additional process steps.

[0080] After the steps of forming multiple transistor structures and semiconductor interconnect layer 50, multiple first conductive channels 40 are formed on semiconductor substrate 10, such that the first conductive channels 40 are connected to source / drain regions 230, and at least one pair of adjacent first conductive channels 40 spaced apart by isolation structure 30 are connected through semiconductor interconnect layer 50. Figure 15 As shown.

[0081] The steps of forming the first conductive channel 40 may include: depositing a dielectric material on the transistor structure and the semiconductor interconnect layer 50 to form an interlayer dielectric layer, and forming a via through the interlayer dielectric layer so that the via is connected to the source / drain region 230 of the transistor structure, and then filling the via with conductive material to form the first conductive channel 40.

[0082] According to an embodiment of this application, a three-dimensional memory 300 is also provided, such as... Figure 16 As shown, it includes a memory array 301, peripheral circuits 302 and interconnect layer 303. The memory array 301 and peripheral circuits 302 are bonded together through interconnect layer 303. The peripheral circuits 302 include the semiconductor devices described above or semiconductor devices obtained by the above manufacturing method. The conductive channels in the semiconductor devices are connected to interconnect layer 303.

[0083] Since the semiconductor device in the three-dimensional memory also includes a semiconductor interconnect layer, which is disposed on the side surface of the isolation structure away from the semiconductor substrate and connects to the adjacent first conductive channel, the interconnect layer can be set to realize the interconnect layout on the surface of the isolation structure, thereby optimizing the interconnect efficiency, reducing the number of interconnect layers required when bonding to the memory array through the interconnect layer, and thus reducing the process difficulty.

[0084] For example, the aforementioned three-dimensional memory is a 3D NAND memory. A stacked 3D NAND memory structure can be implemented by vertically stacking multiple layers of data storage cells. To obtain the aforementioned stacked 3D NAND memory structure, a stacked structure of alternating sacrificial layers and isolation layers can be formed on a substrate. Through-channel vias are etched into the stacked structure, and after forming the memory structure in the through-channel vias, gate trenches are formed in the stacked structure. Then, the sacrificial layers are removed to fill the gates in contact with the memory structure, and a common source electrode is formed in the gate trenches. The aforementioned memory structure is used for bonding to peripheral circuits via interconnect layers.

[0085] This disclosure also provides a storage system 400, such as... Figure 16 As shown, the device includes a three-dimensional memory 401 and a controller 402. The three-dimensional memory 401 is configured to store data, and the controller 402 is coupled to the three-dimensional memory 401 and configured to control the three-dimensional memory 401. The three-dimensional memory 401 includes the aforementioned semiconductor devices, such as... Figures 1 to 10 As shown, the three-dimensional memory 401 may include a semiconductor device obtained by the above-described fabrication method, such as... Figure 17 As shown.

[0086] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0087] This application pre-implements the interconnection of source / drain regions in multiple transistors through an isolation structure, and realizes the interconnection layout on the surface of the isolation structure by setting the aforementioned semiconductor interconnect layer. This allows multiple connected first conductive channels to be led out through only one of them through the semiconductor interconnect layer, thereby realizing the lead-out of source / drain regions in multiple transistors. Subsequently, the interconnect layer is connected to the semiconductor interconnect layer, thereby optimizing the interconnection efficiency, reducing the number of interconnect layers required for subsequent bonding with the memory array through the interconnect layer, and thus reducing the process difficulty.

[0088] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor device, characterized in that, include: Semiconductor substrate; Multiple transistor structures are disposed on one side of the semiconductor substrate; An isolation structure is disposed in the semiconductor substrate, the isolation structure is used to separate the semiconductor substrate into multiple active regions, each transistor structure includes a gate, a gate dielectric layer and a source / drain region, the gate dielectric layer and the gate layer are stacked on the surface of the active region, and the source / drain region is located in the active region on both sides of the gate; Multiple first conductive channels are disposed on the semiconductor substrate, and the first conductive channels are connected to the source / drain regions; A semiconductor interconnect layer is disposed on the side surface of the isolation structure away from the semiconductor substrate, and the semiconductor interconnect layer connects at least one pair of adjacent first conductive channels spaced apart by the isolation structure. A first contact layer covers the side of the semiconductor interconnect layer away from the isolation structure. A portion of the first conductive channel is connected to the semiconductor interconnect layer through the first contact layer, and another portion of the first conductive channel is directly connected to the semiconductor interconnect layer and the first contact layer. Alternatively, the first conductive channel is connected to both the first contact layer and the semiconductor interconnect layer.

2. The semiconductor device according to claim 1, characterized in that, The transistor structures are arranged in an array on one side of the semiconductor substrate. The array includes a plurality of transistor units arranged sequentially along a first direction, and each transistor unit includes a plurality of transistor structures arranged along a second direction. Adjacent to the first conductive channel in the first direction are connected through the semiconductor interconnect layer, and / or In the second direction, adjacent to the first conductive channel are connected through the semiconductor interconnect layer.

3. The semiconductor device according to claim 2, characterized in that, The semiconductor interconnect layer includes: The first semiconductor interconnect is connected to the first conductive channel adjacent in the first direction; The second semiconductor interconnect is connected to the adjacent first semiconductor interconnect.

4. The semiconductor device according to claim 2, characterized in that, The semiconductor interconnect layer includes: The third semiconductor interconnect is connected to the first conductive channel adjacent in the second direction; The fourth semiconductor interconnect is connected to the adjacent third semiconductor interconnect.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The first conductive channel extends in a direction away from the semiconductor substrate, and the sidewall of the first conductive channel is in contact with the semiconductor interconnect layer.

6. The semiconductor device according to claim 1, characterized in that, The semiconductor interconnect layer is a polycrystalline silicon layer, and the first contact layer is a metal silicide layer.

7. The semiconductor device according to claim 5, characterized in that, The semiconductor device further includes a second contact layer, which is disposed in contact with the source / drain region, and the first conductive channel is connected to the source / drain region through the second contact layer.

8. A method for fabricating a semiconductor device according to any one of claims 1 to 7, characterized in that, Includes the following steps: A semiconductor substrate is provided, and an isolation structure is formed on one side of the semiconductor substrate, the isolation structure being used to separate the semiconductor substrate into multiple active regions; A plurality of transistor structures and semiconductor interconnect layers are formed on one side of the semiconductor substrate. Each transistor structure includes a gate, a gate dielectric layer and a source / drain region. The gate dielectric layer and the gate layer are stacked on the surface of the active region. The source / drain regions are located in the active regions on both sides of the gate. The semiconductor interconnect layer is located on the side surface of the isolation structure away from the semiconductor substrate. A plurality of first conductive channels are formed on the semiconductor substrate, such that the first conductive channels are connected to the source / drain regions, and at least one pair of adjacent first conductive channels separated by the isolation structure are connected through the semiconductor interconnect layer.

9. The manufacturing method according to claim 8, characterized in that, The step of forming the transistor structure and the semiconductor interconnect layer on one side of the semiconductor substrate includes: The gate dielectric layer is formed on the surface of the active region; The gate is formed on the surface of the gate dielectric layer, and the semiconductor interconnect layer is formed on the surface of the isolation structure. The source / drain regions are formed in the active regions located on both sides of the gate.

10. The manufacturing method according to claim 8, characterized in that, Prior to the step of forming a plurality of the first conductive channels on the semiconductor substrate, the fabrication method further includes: A first contact layer and a second contact layer are formed on one side of the semiconductor substrate. The first contact layer covers the side of the semiconductor interconnect layer away from the isolation structure, and the second contact layer contacts the source / drain region.

11. The manufacturing method according to claim 10, characterized in that, The step of forming the first contact layer and the second contact layer on one side of the semiconductor substrate includes: Simultaneously, a metallic material is coated on the surface of the semiconductor interconnect layer and the surface of the source / drain region; The metal material is annealed to metallize the surface of the semiconductor interconnect layer to form the first contact layer, and simultaneously metallize the surface of the source / drain region to form the second contact layer.

12. A three-dimensional memory, comprising a memory array, peripheral circuitry, and an interconnect layer, wherein the memory array and the peripheral circuitry are bonded together via the interconnect layer, characterized in that, The peripheral circuit includes a semiconductor device according to any one of claims 1 to 7 or a semiconductor device obtained by the manufacturing method according to any one of claims 8 to 11, wherein a first conductive channel in the semiconductor device is connected to the interconnect layer.

13. A storage system comprising a controller and a three-dimensional memory, the three-dimensional memory being configured to store data, the controller being coupled to the three-dimensional memory and configured to control the three-dimensional memory, characterized in that... The three-dimensional memory is the three-dimensional memory as described in claim 12.

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