Semiconductor memory device and method for manufacturing semiconductor memory device

Abstract

The present disclosure provides a semiconductor storage device and a manufacturing method of a semiconductor storage device. The semiconductor storage device includes a source structure, a laminated conductive layer overlapping the source structure, a first selection conductive layer and a second selection conductive layer arranged between the source structure and the laminated conductive layer, a laminated insulating layer arranged between the first selection conductive layer and the second selection conductive layer and the laminated conductive layer, and a separation insulating structure provided between the first selection conductive layer and the second selection conductive layer.

Description

Technical Field

[0001] Various embodiments of this disclosure may relate to a semiconductor memory device and a method of manufacturing the semiconductor memory device, and more specifically to a three-dimensional semiconductor memory device and a method of manufacturing the three-dimensional semiconductor memory device. Background Technology

[0002] A semiconductor memory device includes memory cells configured to store data. A three-dimensional (3D) semiconductor memory device may include memory cells arranged in three dimensions, thereby reducing the area occupied by the memory cells per unit area of ​​the substrate.

[0003] To improve the integration density of three-dimensional semiconductor memory devices, the number of stacked memory cells is increased. However, as the number of stacked memory cells increases, the operational reliability of the three-dimensional semiconductor memory device may decrease. Summary of the Invention

[0004] According to embodiments of this disclosure, a semiconductor memory device may include: a source structure; a stacked conductive layer overlapping the source structure; a first selective conductive layer and a second selective conductive layer disposed between the source structure and the stacked conductive layer; a stacked insulating layer disposed between the first selective conductive layer and the stacked conductive layer, and between the second selective conductive layer and the stacked conductive layer; a first slit structure and a second slit structure passing through the stacked conductive layer and the stacked insulating layer; and a separating insulating structure passing through the source structure, wherein the first slit structure, the second slit structure, and the separating insulating structure may be disposed between the first selective conductive layer and the second selective conductive layer, and the separating insulating structure may be disposed between the first slit structure and the second slit structure.

[0005] According to embodiments of this disclosure, a semiconductor memory device may include: a source structure; a stacked conductive layer overlapping the source structure; a first selective conductive layer and a second selective conductive layer disposed between the source structure and the stacked conductive layer; a stacked insulating layer disposed between the first selective conductive layer and the stacked conductive layer and between the second selective conductive layer and the stacked conductive layer; and a separation insulating structure passing through the source structure, wherein the separation insulating structure may be disposed between the first selective conductive layer and the second selective conductive layer, and the stacked conductive layer may include: a first conductive extension overlapping the first selective conductive layer; a second conductive extension overlapping the second selective conductive layer; and a conductive connector overlapping the separation insulating structure.

[0006] According to embodiments of this disclosure, a semiconductor memory device may include: a source structure; a stacked conductive layer overlapping the source structure; a first selective conductive layer and a second selective conductive layer disposed between the source structure and the stacked conductive layer; a stacked insulating layer disposed between the first selective conductive layer and the stacked conductive layer, and between the second selective conductive layer and the stacked conductive layer; a first slit structure and a second slit structure passing through the stacked conductive layer and the stacked insulating layer, and spaced apart from each other along a first direction; and a separating insulating structure disposed between the first slit structure and the second slit structure, wherein the first selective conductive layer and the second selective conductive layer may be spaced apart from each other due to the first slit structure, the second slit structure, and the separating insulating structure, and the width of the separating insulating structure may be greater than the width of the first slit structure and the second slit structure.

[0007] According to embodiments of this disclosure, a method for manufacturing a semiconductor memory device may include the following steps: forming a source structure having a first surface and a second surface, the first surface and the second surface facing opposite directions; forming a stack on the first surface of the source structure, the stack including a preliminary selective conductive layer, a stacked conductive layer and a stacked insulating layer; forming a cell plug passing through the stack, the cell plug being connected to the source structure; forming a separation structure hole passing through the second surface of the source structure; and forming a separation insulating structure in the separation structure hole, wherein the step of forming the separation structure hole may include separating the preliminary selective conductive layer into a first selective conductive layer and a second selective conductive layer. Attached Figure Description

[0008] Figure 1A This is a plan view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0009] Figure 1B It is along Figure 1A A cross-sectional view of a semiconductor memory device cut along line I-I'.

[0010] Figure 1C It shows along Figure 1A A cross-sectional view of a semiconductor memory device cut along lines II-II' and III-III'.

[0011] Figure 2A It is along Figure 1B A plan view of a semiconductor memory device cut along line A-A'.

[0012] Figure 2B It is along Figure 1B A plan view of a semiconductor memory device cut along line B-B'.

[0013] Figure 2C It is along Figure 1B A plan view of a semiconductor memory device cut along line C-C'.

[0014] Figure 2D It is along Figure 1B A plan view of a semiconductor memory device cut along line D-D'.

[0015] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7A , Figure 7B , Figure 8 , Figure 9 , Figure 10A , Figure 10B and Figure 11 This is a diagram illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0016] Figure 12 This is a block diagram illustrating the configuration of a storage system according to an embodiment of the present disclosure.

[0017] Figure 13 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0018] The specific structural and functional descriptions disclosed herein are merely illustrative of embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the specific embodiments set forth herein.

[0019] It should be understood that although the terms "first," "second," etc., may be used in this document to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another.

[0020] Various embodiments of this disclosure relate to semiconductor memory devices capable of improving operational reliability and methods of manufacturing such semiconductor memory devices.

[0021] Figure 1A This is a plan view illustrating a semiconductor memory device according to an embodiment of the present disclosure. Figure 1B It is along Figure 1A A cross-sectional view of a semiconductor memory device cut along line I-I'. Figure 1C It shows along Figure 1A A cross-sectional view of a semiconductor memory device cut along lines II-II' and III-III'. Figure 1C The elements shown by the dashed lines do not overlap with each other relative to the lines, but are shown to help understand the arrangement of elements in a semiconductor memory device.

[0022] Reference Figure 1A The semiconductor memory device may include gate stacks STA. Each gate stack STA may extend in a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may be the directions along which intersecting axes extend. In an embodiment, the second direction D2 may be defined as a direction perpendicular to the first direction D1.

[0023] Each gate stack STA may include a memory cell array region CAR and a first contact region AR1. The first contact region AR1 may extend from the memory cell array region CAR. In an embodiment, the first contact region AR1 may extend from the memory cell array region CAR in a first direction D1. Within the first contact region AR1, each gate stack STA may be formed as a stepped structure.

[0024] Each gate stack STA can be penetrated by a first slit structure SLS1 and a second slit structure SLS2. The first slit structure SLS1 and the second slit structure SLS2 can extend along a third direction D3. The third direction D3 can be defined as the direction along which an axis intersects the plane created based on the first direction D1 and the second direction D2 extends. In an embodiment, the third direction D3 can be defined as a direction perpendicular to the plane created based on the first direction D1 and the second direction D2. The first slit structure SLS1 and the second slit structure SLS2 can be spaced apart from each other. In an embodiment, the first slit structure SLS1 and the second slit structure SLS2 can be spaced apart from each other in the first direction D1. The first slit structure SLS1 and the second slit structure SLS2 can extend in the first direction D1.

[0025] Each gate stack STA can overlap with a separate insulating structure DIS disposed between the first slit structure SLS1 and the second slit structure SLS2.

[0026] Each gate stack STA in the memory cell array region CAR can be penetrated by a cell plug CPL. Each gate stack STA in the first contact region AR1 can be penetrated by a first dummy plug DPL1. Each gate stack STA in the memory cell array region CAR can be penetrated by a second dummy plug DPL2. Embodiments of this disclosure are not limited thereto, and the second dummy plug DPL2 may be omitted. The cell plug CPL, the first dummy plug DPL1, and the second dummy plug DPL2 may extend along a third direction D3 and may include the same material layer.

[0027] The gate stack STAs can be separated from each other by means of third slit structures SLS3. Each third slit structure SLS3 can extend in a third direction D3. Each third slit structure SLS3 can include a portion parallel to the first slit structure SLS1 and a portion parallel to the second slit structure SLS2. In an embodiment, each third slit structure SLS3 can extend in a first direction D1 parallel to the first slit structure SLS1. Furthermore, each third slit structure SLS3 can extend further in the first direction D1 than the first slit structure SLS1 to be parallel to the second slit structure SLS2.

[0028] Each gate stack STA may include a layer penetrated by a drain-separated insulating structure (DSS) and a layer overlapping the DSS. The DSS may be arranged between adjacent first slit structures SLS1 and third slit structures SLS3. The DSS may be formed to be shorter than each of the first slit structures SLS1, second slit structures SLS2, and third slit structures SLS3 in the third direction D3.

[0029] The cell plug CPL can pass through the gate stack STA on both sides of the drain-separated insulation structure DSS. The second dummy plug DPL2 can be arranged in a row along the extension direction of the drain-separated insulation structure DSS. The drain-separated insulation structure DSS can overlap with the second dummy plug DPL2.

[0030] The semiconductor memory device may include a gate contact GCT that overlaps with the gate stack STA in the first contact region AR1.

[0031] The semiconductor memory device may further include a through-contact PCT. Hereinafter, for ease of explanation, the area where the through-contact PCT is disposed is defined as a second contact region AR2. The second contact region AR2 may be an open region not covered by the gate stack STA.

[0032] Reference Figure 1B and Figure 1C The semiconductor memory device may include a substrate 100, a transistor TR, a first insulating layer 110, a first interconnect IC1, and a first bonding pad BP1.

[0033] The substrate 100 may have the shape of a plate extending in a first direction D1 and a second direction D2. In an embodiment, the substrate 100 may be a semiconductor substrate.

[0034] The substrate 100 may be covered with a first insulating layer 110. The first insulating layer 110 may include an insulating material. In an embodiment, the first insulating layer 110 may include an oxide or a nitride. The first insulating layer 110 may be a multilayer structure.

[0035] The transistor TR can be disposed between the first insulating layer 110 and the substrate 100. The transistor TR can form the peripheral circuit of the semiconductor memory device.

[0036] Each transistor TR may include an impurity region IR, a gate insulating layer GI, and a gate electrode GM. The impurity region IR can be defined by doping the active region of substrate 100 with conductive impurities. The gate electrode GM may be spaced apart from substrate 100 by the gate insulating layer GI. The gate insulating layer GI may include an insulating material. In one embodiment, the gate insulating layer GI may include an oxide. The gate electrode GM may include a conductive material. In one embodiment, the gate electrode GM may include tungsten.

[0037] The active regions of substrate 100 may be separated by an isolation layer IS. The isolation layer IS may be formed in substrate 100. Transistors TR may be insulated from each other due to the isolation layer IS. The isolation layer IS may include an insulating material. In one embodiment, the isolation layer IS may include an oxide.

[0038] A first interconnect IC1 may be formed in a first insulating layer 110. The first interconnect IC1 may be disposed between a first bonding pad BP1 and a transistor TR. The first bonding pad BP1 and the transistor TR may be electrically connected via the first interconnect IC1. The first interconnect IC1 may include a first contact CT1 and a first line ML1. The structure and arrangement of the first contact CT1 and the first line ML1 may be varied. The first contact CT1 and the first line ML1 may include a conductive material. In an embodiment, the first contact CT1 and the first line ML1 may include tungsten.

[0039] First bonding pads BP1 may be disposed in the first insulating layer 110. The width of each first bonding pad BP1 may decrease as the first bonding pad approaches the substrate 100. In an embodiment, the width of the first bonding pad BP1 in the first direction D1 may decrease as the first bonding pad approaches the substrate 100. The first bonding pads BP1 may include a conductive material. In an embodiment, the first bonding pads BP1 may include copper.

[0040] The gate stack STA may overlap with the first insulating layer 110. A second insulating layer 120 may be disposed between the gate stack STA and the first insulating layer 110. The second insulating layer 120 may include an insulating material. In some embodiments, the second insulating layer 120 may include an oxide or a nitride. The second insulating layer 120 may be a multilayer structure.

[0041] The second bonding pad BP2 and the second interconnect IC2 can be embedded in the second insulating layer 120.

[0042] Second bonding pads BP2 can be connected to first bonding pads BP1 respectively. The width of each second bonding pad BP2 can increase as it approaches the first bonding pad BP1. In an embodiment, the width of the second bonding pad BP2 in the first direction D1 can increase as it approaches the first bonding pad BP1. The width of the first bonding pad BP1 can increase as it approaches the second bonding pad BP2. In an embodiment, the width of the first bonding pad BP1 in the first direction D1 can increase as it approaches the second bonding pad BP2. The second bonding pads BP2 may include conductive material. In an embodiment, the second bonding pad BP2 may include copper.

[0043] The second interconnect IC2 can be disposed between some second bonding pads BP2 and the gate stack STA, and between some second bonding pads BP2 and the through contact PCT. The second interconnect IC2 can be connected to the second bonding pads BP2 respectively. The second interconnect IC2 may include a second contact CT2 and a second line ML2. The structure and arrangement of the second contact CT2 and the second line ML2 can be modified. The second contact CT2 and the second line ML2 may include a conductive material. In an embodiment, the second contact CT2 and the second line ML2 may include tungsten.

[0044] The semiconductor memory device may include a bit line BL and a bit line contact BCT. The bit line BL and bit line contact BCT may be disposed in a second insulating layer 120. The bit line BL and bit line contact BCT may be disposed between the gate stack STA and the second interconnect IC2. A cell plug CPL may be spaced apart from the bit line BL on a third direction D3. The bit line contact BCT may electrically connect the cell plug CPL to the bit line BL. The structure and arrangement of the bit line BL and bit line contact BCT may be modified. The bit line BL and bit line contact BCT may include a conductive material. In an embodiment, the bit line BL and bit line contact BCT may include tungsten.

[0045] The gate stack STA can be disposed on the second insulating layer 120. The semiconductor memory device may include a third insulating layer 130 between the stepped structure of the gate stack STA and the second insulating layer 120. Furthermore, the semiconductor memory device may include a source structure SOS overlapping the gate stack STA and the third insulating layer 130.

[0046] The gate stack STA may include stacked conductive layers DSL and WL, a stacked insulating layer IL, and a selectable conductive layer SSL. The stacked conductive layers DSL and WL may be spaced apart from each other on the third-direction D3. Each selectable conductive layer SSL may overlap with the stacked conductive layers DSL and WL. The stacked insulating layer IL may be disposed between adjacent stacked conductive layers DSL and WL on the third-direction D3, between the stacked conductive layers DSL and WL and the selectable conductive layer SSL, and between the selectable conductive layer SSL and the source structure SOS. The stacked insulating layer IL may be alternated with the stacked conductive layers DSL and WL on the third-direction D3.

[0047] The stacked conductive layers DSL and WL may include a word line WL and a drain select line DSL. In an embodiment, at least one layer in the stacked conductive layers DSL and WL adjacent to the bit line BL may be the drain select line DSL, while the other layers may be word lines WL. The select conductive layer SSL may be the source select line. Each of the select conductive layer SSL and the stacked conductive layers DSL and WL may include a conductive material. In an embodiment, each of the select conductive layer SSL and the stacked conductive layers DSL and WL may include tungsten. The stacked insulating layer IL may include an insulating material. For example, the stacked insulating layer IL may include an oxide.

[0048] Because the selected conductive layer SSL and the stacked conductive layers DSL and WL extend to different lengths depending on their separation distance from the substrate 100, a stepped structure of the gate stack STA can be defined. In an embodiment, the selected conductive layer SSL and the stacked conductive layers DSL and WL can extend longer in the first direction D1 as the distance from the substrate 100 increases. More specifically, the selected conductive layer SSL can extend further in the first direction D1 than the stacked conductive layers DSL and SL. The stacked insulating layer IL can also extend to different lengths depending on its distance from the substrate 100, thereby defining the stepped structure.

[0049] The third insulating layer 130 may include a stepped surface corresponding to the stepped structure of the gate stack STA. The third insulating layer 130 may be disposed between the second insulating layer 120 and the stepped structure, which is formed by a selective conductive layer SSL, stacked conductive layers DSL and WL, and a stacked insulating layer IL. The third insulating layer 130 may include an insulating material. In some embodiments, the third insulating layer 130 may include an oxide or a nitride.

[0050] The gate contact GCT may extend through the third insulating layer 130. The gate contact GCT may extend into the second insulating layer 120 to connect to some of the second interconnects IC2. The gate contact GCT may extend through at least one stacked insulating layer IL to connect to the stacked conductive layers DSL and WL and the select conductive layer SSL, respectively. The gate contact GCT may include a conductive material. In one embodiment, the gate contact GCT may include tungsten.

[0051] Bit line BL and gate contact GCT can be electrically connected to transistor TR of peripheral circuitry via second interconnect IC2, second bonding pad BP2, first bonding pad BP1, and first interconnect IC1. In an embodiment, transistor TR may include transistors for a page buffer and transistors for an X-decoder.

[0052] The selectable conductive layer SSL and the stacked conductive layers DSL and WL can be electrically connected to the transistor TR constituting the X-decoder via the gate contact GCT. The transistor TR of the X-decoder can be configured to transmit operating voltage to the selectable conductive layer SSL and the stacked conductive layers DSL and WL.

[0053] Each cell plug CPL may include a cell fill layer CFI, a cell channel layer CCH surrounding the cell fill layer CFI, and a cell storage layer CML configured to surround the cell channel layer CCH.

[0054] The cell filling layer CFI may include an insulating material. In one embodiment, the cell filling layer CFI may include an oxide. The cell channel layer CCH may include a semiconductor material. In one embodiment, the cell channel layer CCH may include polysilicon. The cell storage layer CML may include a tunnel insulating layer surrounding the cell channel layer CCH, a data storage layer surrounding the tunnel insulating layer, and a barrier layer surrounding the data storage layer. The tunnel insulating layer may include a material that enables charge tunneling. In one embodiment, the tunnel insulating layer may include an oxide. The data storage layer may include a material capable of trapping charge. In one embodiment, the data storage layer may include a nitride. Furthermore, depending on the data storage method, the data storage layer may include various materials. In one embodiment, the data storage layer may include silicon, a phase change material, or nanodots. The barrier layer may include an insulating material capable of blocking charge movement. For example, the barrier layer may include an oxide.

[0055] The first dummy plug DPL1 may include a dummy fill layer DFI, a dummy channel layer DCH surrounding the dummy fill layer DFI, and a dummy storage layer DML surrounding the dummy channel layer DCH.

[0056] The dummy fill layer DFI may include an insulating material. The dummy fill layer DFI may include the same material as the cell fill layer CFI. In one embodiment, the dummy fill layer DFI may include an oxide. The dummy channel layer DCH may include a semiconductor material. The dummy channel layer DCH may include the same material as the cell channel layer CCH. In one embodiment, the dummy channel layer DCH may include polysilicon. The dummy memory layer DML may include a tunnel insulating layer surrounding the dummy channel layer DCH, a data storage layer surrounding the tunnel insulating layer, and a barrier layer surrounding the data storage layer. The tunnel insulating layer, data storage layer, and barrier layer of the dummy memory layer DML may be made of the same material as the tunnel insulating layer, data storage layer, and barrier layer of the cell memory layer CML.

[0057] The cell channel layer CCH of the cell plug CPL can be electrically connected to the bit line BL via the bit line contact BCT. The bit line BL can be electrically connected to the transistor TR of the page buffer via the second interconnect IC2, the second bonding pad BP2, the first bonding pad BP1, and the first interconnect IC1. The page buffer can temporarily store data received via the bit line BL, or be used to sense the voltage or current of the bit line BL.

[0058] The first dummy plug DPL1 can be used to support the gate stack STA.

[0059] The source structure SOS can have the shape of a plate extending in a first direction D1 and a second direction D2. The source structure SOS can overlap with the stacked conductive layers DSL and WL. A selective conductive layer SSL can be disposed between the stacked conductive layers DSL and WL and the source structure SOS. The source structure SOS can be farther from the substrate 100 than the stacked conductive layers DSL and WL and the selective conductive layer SSL.

[0060] The source structure SOS can be connected to the cell channel layer CCH of the cell plug CPL and the dummy channel layer DCH of the first dummy plug DPL1.

[0061] A source structure SOS can be used as the source line of a semiconductor memory device. In one embodiment, the source structure SOS may include doped polycrystalline silicon. In another embodiment, the source structure SOS may be monocrystalline silicon having regions doped with impurities.

[0062] The source structure SOS may be covered with a fourth insulating layer 140. The fourth insulating layer 140 may include an insulating material. In an embodiment, the fourth insulating layer 140 may include an oxide or a nitride.

[0063] The fourth insulating layer 140 may cover the fifth insulating layer 150. The fifth insulating layer 150 may include an insulating material. In an embodiment, the fifth insulating layer 150 may include an oxide or a nitride.

[0064] The fifth insulating layer 150 may be penetrated by the top wire TML. The top wire TML may include a conductive material. In one embodiment, the top wire TML may include aluminum.

[0065] The discrete insulating structure DIS can penetrate the fourth insulating layer 140 and the source structure SOS. The discrete insulating structure DIS can be surrounded by the source structure SOS. The discrete insulating structure DIS can contact the stacked insulating layer IL between the source structure SOS and the selective conductive layer SSL. The discrete insulating structure DIS can include an insulating material. In one embodiment, the discrete insulating structure DIS can include an oxide.

[0066] The fourth insulating layer 140 and the source structure SOS can be penetrated by the through-insulation structure PIS and the through contact PCT. The through-insulation structure PIS can be surrounded by the source structure SOS. The through-insulation structure PIS can contact the third insulating layer 130. The through-insulation structure PIS can be arranged at substantially the same height as the separate insulating structure DIS. The through-insulation structure PIS can include an insulating material. In an embodiment, the through-insulation structure PIS can include an oxide.

[0067] The through contact PCT may include a third contact CT3 defined as a first through contact and a fourth contact CT4 defined as a second through contact.

[0068] The third contact CT3 may be disposed between the second interconnect IC2 and the fourth contact CT4. The third contact CT3 may contact the second interconnect IC2 and may extend toward the fourth contact CT4 in a third direction D3. The third contact CT3 may pass through a portion of the second insulating layer 120 and the third insulating layer 130. The third contact CT3 may include a conductive material. In one embodiment, the third contact CT3 may include tungsten.

[0069] The fourth contact CT4 can pass through the source structure SOS. The fourth contact CT4 can be insulated from the source structure SOS by passing through the insulating structure PIS. The fourth contact CT4 can be connected to the top line TML. The fourth contact CT4 can include a conductive material. In an embodiment, the fourth contact CT4 can include tungsten.

[0070] Some top lines TML can be electrically connected to some transistors TR of the peripheral circuit via through contact PCT, second interconnect IC2, second bonding pad BP2, first bonding pad BP1 and first interconnect IC1.

[0071] In the following text, reference will be made to Figures 2A to 2C The layout of the source structure SOS, select conductive layer SSL, word line WL, and drain select line DSL of a semiconductor memory device according to an embodiment of the present invention is described.

[0072] Figure 2A It is along Figure 1B A plan view of a semiconductor memory device cut along line A-A'.

[0073] Reference Figure 2AThe source structure SOS can have the shape of a plate extending in the first direction D1 and the second direction D2. The source structure SOS can surround the separate insulating structure DIS. The source structure SOS can surround the through insulating structure PIS. The through insulating structure PIS can surround the fourth contact CT4, and the source structure SOS can surround the fourth contact CT4, with the through insulating structure PIS inserted between the source structure SOS and the fourth contact CT4.

[0074] The separation insulation structure DIS, the fourth contact CT4, and the through insulation structure PIS can extend on the third direction D3.

[0075] Figure 2B It is along Figure 1B A plan view of a semiconductor memory device cut along line B-B'.

[0076] Reference Figure 2B Because of the first slit structure SLS1, the second slit structure SLS2, and the third slit structure SLS3, the selectively conductive layers (SSLs) can be mutually insulated. The selectively conductive layers (SSLs) can be arranged at substantially the same height. The selectively conductive layers (SSLs) can be... Figure 2A The source structure shown is SOS overlap. Each selective conductive layer (SSL) can be penetrated by multiple cell plugs (CPL). Each selective conductive layer (SSL) can be penetrated by a first dummy plug (DPL1). Each selective conductive layer (SSL) can be penetrated by a second dummy plug (DPL2). Each selective conductive layer (SSL) can have a sidewall extending along the third insulating layer 130.

[0077] Selective conductive layers SSL may include a first selective conductive layer SSL1 and a second selective conductive layer SSL2 located between the third slit structures SLS3. The first selective conductive layer SSL1 and the second selective conductive layer SSL2 may be spaced apart from each other in the second direction D2. The first selective conductive layer SSL1 and the second selective conductive layer SSL2 may be arranged at substantially the same height. Due to the first slit structure SLS1, the second slit structure SLS2, and the separation insulation structure DIS, the first selective conductive layer SSL1 may not only be spaced apart from the second selective conductive layer SSL2, but also insulated from it.

[0078] The third slit structure SLS3 can be spaced apart from each other in the second direction D2. The first slit structure SLS1, the second slit structure SLS2, and the separation insulation structure DIS can be arranged between the third slit structure SLS3. The first slit structure SLS1, the second slit structure SLS2, and the separation insulation structure DIS can be arranged between the first selective conductive layer SSL1 and the second selective conductive layer SSL2.

[0079] The first slit structure SLS1, the second slit structure SLS2 to the third slit structure SLS3 can be... Figure 2A The source structure shown is covered by an SOS. The first to third slit structures SLS1, SLS2, and SLS3 may include insulating material. In an embodiment, the first to third slit structures SLS1, SLS2, and SLS3 may include oxides.

[0080] The separation insulation structure DIS can be arranged between the first slit structure SLS1 and the second slit structure SLS2, which are spaced apart from each other along the first direction D1. The separation insulation structure DIS may include a side connected to the first slit structure SLS1 and a side connected to the second slit structure SLS2.

[0081] The width of the separation insulation structure DIS can be greater than the width of the first slit structure SLS1 and the second slit structure SLS2. In an embodiment, if the width of the separation insulation structure DIS in the second direction D2 is defined as a first width W1, the width of the first slit structure SLS1 in the second direction D2 is defined as a second width W2, and the width of the second slit structure SLS2 in the second direction D2 is defined as a third width W3, then the first width W1 can be greater than the second width W2 and the third width W3.

[0082] The third insulating layer 130 can cover... Figure 2A The source structure SOS is shown. The second slit structure SLS2 can be connected to the third insulating layer 130. The second slit structure SLS2 can extend from the separated insulating structure DIS along the first direction D1 and can pass through the third insulating layer 130.

[0083] The through-contact PCT and through-insulation structure PIS can extend into a portion of the third insulation layer 130. Figure 1C Either the third contact CT3 or the fourth contact CT4 of the through contact PCT shown can be arranged at the same height as the selective conductive layer SSL, or a portion of the third contact CT3 and a portion of the fourth contact CT4 can extend to the height at which the selective conductive layer SSL is arranged.

[0084] Figure 2C It is along Figure 1B A plan view of a semiconductor memory device cut along line C-C'. Figure 2D It is along Figure 1B A plan view of a semiconductor memory device cut along line D-D'.

[0085] Reference Figure 2C and Figure 2DEach of the first slit structure SLS1, the second slit structure SLS2, the cell plug CPL, the first dummy plug DPL1, and the second dummy plug DPL2 may extend in a third direction D3 through the stacked conductive layers WL and DSL. Each of the stacked conductive layers WL and DSL may have a sidewall extending along the third insulating layer 130. The third insulating layer 130 may be penetrated by the gate contact GCT.

[0086] Reference Figure 2C Each word line WL of the stacked conductive layer WL and DSL may include a first conductive extension CEP1, a second conductive extension CEP2, and a conductive connector CCP. The first conductive extension CEP1, the second conductive extension CEP2, and the conductive connector CCP may be arranged between third slit structures SLS3 that are adjacent to each other in the second direction D2.

[0087] Each of the first conductive extension CEP1 and the second conductive extension CEP2 can have the shape of a plate extending in the first direction D1 and the second direction D2. The first conductive extension CEP1 can be connected to the plate in the third direction D3. Figure 2B The first selective conductive layer SSL1 shown overlaps with the second conductive extension CEP2 on the third-direction D3. Figure 2B The second selective conductive layer SSL2 shown overlaps. The first slit structure SLS1 and the second slit structure SLS2 can be arranged between the first conductive extension CEP1 and the second conductive extension CEP2. In other words, the first conductive extension CEP1 and the second conductive extension CEP2 can be spaced apart from each other in the second direction D2 due to the first slit structure SLS1 and the second slit structure SLS2. The first conductive extension CEP1 and the second conductive extension CEP2 can be electrically connected to each other via a conductive connector CCP.

[0088] The conductive connector CCP can be used with third-party D3. Figure 2B The separated insulating structures DIS shown overlap. A conductive connector CCP can be arranged between the first slit structure SLS1 and the second slit structure SLS2. The conductive connector CCP can extend from the first conductive extension CEP1 toward the second conductive extension CEP2 in the second direction D2.

[0089] Each character line WL can be formed as a line in the first direction D1 that is larger than... Figure 2B The selected conductive layer SSL shown is short. Each word line WL may have a sidewall extending along the third insulating layer 130. The third insulating layer 130 may extend to be similar to... Figure 2BThe ends of each selected conductive layer SSL shown overlap. At the height at which each word line WL is positioned, the third insulating layer 130 may surround some of the first dummy plugs DPL1 adjacent to the third contact CT3.

[0090] Reference Figure 2D The drain selection lines of the stacked conductive layer WL and DSL can be arranged at essentially the same height. Due to the first slit structure SLS1, the third slit structure SLS3, and the drain separation insulation structure DSS, the drain selection lines DSL can not only be spaced apart from each other, but also be insulated from each other.

[0091] The drain separation insulation structure DSS can overlap with the second dummy plugs DPL2 arranged in a row in the first direction D1, and can also overlap with some of the first dummy plugs DPL1. The drain separation insulation structure DSS can separate the conductive layer between the first slit structures SLS1 and the third slit structures SLS3 that are adjacent to each other in the second direction D2 into two or more drain selection lines DSL. In an embodiment, the drain selection lines DSL may include a first group of first drain selection lines DSL11, a first group of second drain selection lines DSL12, a second group of first drain selection lines DSL21, and a second group of second drain selection lines DSL22, which are arranged between adjacent third slit structures SLS3.

[0092] The first group of first drain selection lines DSL11 and the first group of second drain selection lines DSL12 can be arranged between the first slit structure SLS1 and a third slit structure SLS3 adjacent to the first slit structure SLS1. Due to the drain separation insulation structure DSS, the first group of first drain selection lines DSL11 can not only be spaced apart from the first group of second drain selection lines DSL12, but also can be insulated from the first group of second drain selection lines DSL12. The drain separation insulation structure DSS between the first group of first drain selection lines DSL11, the first group of second drain selection lines DSL12, and the first group of first drain selection lines DSL11 and the first group of second drain selection lines DSL12 can be... Figure 2C The first conductive extension CEP1 shown overlaps.

[0093] The second group of first drain selection lines DSL21 and the second group of second drain selection lines DSL22 can be arranged between the first slit structure SLS1 and another third slit structure SLS3 adjacent to the first slit structure SLS1. Due to the drain separation insulation structure DSS, the second group of first drain selection lines DSL21 can not only be spaced apart from the second group of second drain selection lines DSL22, but also can be insulated from the second group of second drain selection lines DSL22. The drain separation insulation structure DSS between the second group of first drain selection lines DSL21, the second group of second drain selection lines DSL22, and the second group of first drain selection lines DSL21 and second group of second drain selection lines DSL22 can be arranged with... Figure 2C The second conductive extension CEP2 shown overlaps.

[0094] Each drain-separated insulation structure (DSS) can extend further than the drain selection line (DSL). In this embodiment, each drain-separated insulation structure (DSS) can extend further than the drain selection line (DSL) in the first direction (D1).

[0095] The first slit structure SLS1 can extend longer than each drain select line DSL. In an embodiment, the first slit structure SLS1 can extend further than each drain select line DSL in the first direction D1.

[0096] Each drain selection line DSL can be configured to be more efficient than the first direction D1. Figure 2C The word line WL shown is short. Each drain select line DSL can have a sidewall extending along the third insulating layer 130. The third insulating layer 130 can extend to be similar to... Figure 2C The ends of the word line WL shown overlap. The third insulating layer 130 may include an extension 130EP that extends between the first slit structure SLS1 and the second slit structure SLS2. The extension 130EP may be disposed at the arrangement height of the drain selection line DSL and may be connected with... Figure 2C The conductive connectors CCP shown are overlapped.

[0097] In the above embodiments of this disclosure, such as Figure 1C The isolated insulating structure DIS, shown as passing through the source structure SOS, can extend to the arrangement height of the selective conductive layer SSL. Therefore, as... Figure 2B As shown, the first selective conductive layer SSL1 and the second selective conductive layer SSL2 can be separated from each other due to the separation insulation structure DIS. Figure 1CAs shown, the selective conductive layer SSL is disposed between the stacked conductive layers WL and DSL and the source structure SOS. The first selective conductive layer SSL1 and the second selective conductive layer SSL2 can be located on the same plane created based on the first direction D1 and the second direction D2. According to embodiments of this disclosure, the depth of the separation insulation structure DIS can be controlled so that it does not penetrate through the stacked conductive layers WL and DSL, thereby allowing the selective conductive layer SSL to be separated from the stacked conductive layers WL and DSL as a distinct unit.

[0098] Hereinafter, a method for manufacturing a semiconductor memory device according to embodiments of the present disclosure will be described.

[0099] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7A , Figure 7B , Figure 8 , Figure 9 , Figure 10A , Figure 10B and Figure 11 This is a diagram illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure. Hereinafter, repeated explanations will be omitted if they are deemed redundant. In the following text, the cross-sectional views primarily show... Figure 1C The structure shown.

[0100] Figure 3 The substrate 100 is shown corresponding to Figure 1A A cross-sectional view of some areas of the first contact area AR1 and the second contact area AR2 shown in the figure. Figure 3 A cross-sectional view showing the process of forming transistor TR is shown.

[0101] Reference Figure 3 Transistors TR can be formed on substrate 100. The steps of forming transistor TR may include: forming an isolation layer IS that separates the active regions of substrate 100; and forming a sludge region IR for each transistor TR in the active regions. Before forming the sludge region IR, as... Figure 1B As shown, the gate insulating layer GI and gate electrode GM of each transistor TR can be formed on the active region of the substrate 100. This can be achieved by implanting at least one of n-type and p-type impurities into the active region of the substrate. Figure 1B The gate electrode GM shown is used to define the impurity region IR in the active region where they do not overlap.

[0102] Subsequently, a first insulating layer 110 covering the transistor TR, a first interconnect IC1 electrically connected to the transistor TR, and a first bonding pad BP1 contacting the first interconnect IC1 can be formed. The process of forming the first insulating layer 110, the first contact CT1 and the first line ML1 of the first interconnect IC1, and the first bonding pad BP1 may include multiple deposition processes and multiple etching processes.

[0103] Figure 4 Cross-sectional views are shown of some regions in the source structure SOS and the stack 200, which correspond to Figure 1A The first contact area AR1 and the second contact area AR2 are shown in the figure.

[0104] Reference Figure 4 It can provide a source structure SOS having a first surface SU1 and a second surface SU2 facing opposite directions. The source structure SOS can be a doped semiconductor.

[0105] Subsequently, a preliminary laminate 200 can be formed on the first surface SU1 of the source structure SOS. The formation of the preliminary laminate 200 may include alternatingly laminating an insulating layer IL and a sacrificial layer FL on the first surface SU1 of the source structure SOS. The insulating layer IL and the sacrificial layer FL may comprise different materials. In one embodiment, the insulating layer IL may comprise an oxide, and the sacrificial layer FL may comprise a nitride.

[0106] Figure 5 and Figure 6 This is a cross-sectional view showing an embodiment of the process after the formation of the preliminary laminate 200.

[0107] Reference Figure 5 It can be etched in a stepped manner. Figure 4 The preliminary laminate 200 shown consists of a laminated insulating layer IL and a laminated sacrificial layer FL. Therefore, a stepped laminate 200ST with a stepped structure STE can be defined.

[0108] The stacked insulating layer IL and the stacked sacrificial layer FL can be etched to open up certain regions of the source structure SOS. In an embodiment, some regions of the source structure SOS corresponding to the second contact region AR2 may not overlap with the stepped stack 200ST, but may be exposed.

[0109] Reference Figure 6 The stepped laminate 200ST and the source structure SOS can be covered by a third insulating layer 130. The third insulating layer 130 can cover the stepped structure STE of the stepped laminate 200ST.

[0110] Subsequently, a first dummy plug DPL1 can be formed through the stepped laminate 200ST. The first dummy plug DPL1 can be connected with... Figure 1A and Figure 1B The unit plug CPL and the second dummy plug DPL2 shown are formed simultaneously.

[0111] The formation of the first dummy plug DPL1, the unit plug CPL, and the second dummy plug DPL2 may include: forming plug holes through the stepped laminate 200ST; forming a dummy storage layer DML or in each plug hole. Figure 1B The cell storage layer CML; and the virtual channel layer DCH and Figure 1B The cell channel layer CCH is shown in the diagram. The formation of the dummy channel layer DCH and the cell channel layer CCH may include: forming a contact with the source structure SOS and dummy storage layer DML and along... Figure 1B The cell storage layer CML shown extends into a channel layer; and the upper end of the central region of each plug hole opened by the channel layer is filled with a doped semiconductor pattern. Before filling the upper end of the central region of each plug hole with the doped semiconductor pattern, a portion of the central region of each plug hole can be filled with a dummy filling layer DFI or Figure 1B The cell filling layer CFI shown is filled. Doped semiconductor patterns can be formed on the dummy filling layer DFI or... Figure 1B The cell-filled layer CFI shown is shown.

[0112] Figure 7A This is a cross-sectional view illustrating an embodiment of the process for forming the gate stack STA. Figure 7B It is along Figure 7A A plan view cut by line E-E'.

[0113] Reference Figure 7A and Figure 7B It can form a passage Figure 6 The stepped stack 200ST shown includes a first trench ST1, a second trench ST2, and a third trench ST3. Each of the first trench ST1, the second trench ST2, and the third trench ST3 can extend in a first direction D1. Due to the third trench ST3, the stepped stack 200ST can be separated into a preliminary gate stack. The third trench ST3 can be arranged to be spaced apart from each other in a second direction D2. The first trench ST1 and the second trench ST2 can be arranged between the third trench ST3. The first trench ST1 and the second trench ST2 can be spaced apart from each other in the first direction D1.

[0114] Subsequently, it can be removed via the first trench ST1, the second trench ST2, and the third trench ST3. Figure 6The stacked sacrificial layer FL is shown. The empty spaces where the stacked sacrificial layer FL has been removed can then be filled with a conductive material. The conductive material in each of the first trench ST1, the second trench ST2, and the third trench ST3 can be removed by an etching process. Afterwards, a... Figure 1A and Figure 2D The drain-separated insulating structure DSS is shown. Therefore, the conductive material can be separated into a preliminary selective conductive layer pSSL and stacked conductive layers WL and DSL, and can define gate stack bodies STA. Each gate stack body STA can surround a cell plug CPL, a first dummy plug DPL1, and a second dummy plug DPL2.

[0115] The initially selected conductive layer pSSL and the stacked conductive layers WL and DSL can be alternately arranged on the stacked insulating layer IL and the first surface SU1 of the source structure SOS. The initially selected conductive layer pSSL and the stacked conductive layers WL and DSL can be insulated from each other by the stacked insulating layer IL. Due to the stacked insulating layer IL between the stacked conductive layers WL and DSL and the source structure SOS, the initially selected conductive layer pSSL can be insulated from the source structure SOS.

[0116] The initially selected conductive layer pSSL can be disposed between the source structure SOS and the structure formed by alternating layers of insulating layer IL and conductive layers WL and DSL. The initially selected conductive layer pSSL can be formed to extend further than the stacked conductive layers WL and DSL in a first direction D1 parallel to the first surface SU1 of the source structure SOS.

[0117] The initial selection conductive layer pSSL may include a first selection extension SEP1, a second selection extension SEP2, and a selection connector SCP. Each of the first selection extension SEP1 and the second selection extension SEP2 may have a plate shape extending in a first direction D1 and a second direction D2. The first selection extension SEP1 may be spaced apart from the second selection extension SEP2 in the second direction D2 due to a first trench ST1 and a second trench ST2. The selection connector SCP may be disposed between the first selection extension SEP1 and the second selection extension SEP2. The selection connector SCP can extend from the first selection extension SEP1 along the second direction D2 to connect with the second selection extension SEP2. In other words, the first selection extension SEP1 and the second selection extension SEP2 can be interconnected by means of the selection connector SCP between the first selection extension SEP1 and the second selection extension SEP2.

[0118] The stacked conductive layer WL and DSL may include a drain selection line DSL and a word line WL.

[0119] Each word line WL may include a first conductive extension CEP1, a second conductive extension CEP2, and a conductive connector CCP (as shown in reference). Figure 2C (as described). In Figure 7A and Figure 7B In the process shown, Figure 2C The first conductive extension CEP1 shown can overlap with the first selective extension SEP1. Figure 2C The second conductive extension CEP2 shown can overlap with the second selective extension SEP2, and Figure 2C The conductive connector CCP shown may overlap with the selected connector SCP.

[0120] The first trench ST1, the second trench ST2, and the third trench ST3 can be filled with the first slit structure SLS1, the second slit structure SLS2, and the third slit structure SLS3, respectively. The first selection extension SEP1, the second selection extension SEP2, and the selection connector SCP of the initial selection conductive layer pSSL can be arranged between the third slit structure SLS3. The first slit structure SLS1 and the second slit structure SLS2 can be arranged between the first selection extension SEP1 and the second selection extension SEP2. The first slit structure SLS1 and the second slit structure SLS2 can be spaced apart from each other by the selection connector SCP.

[0121] Figure 8 This is a cross-sectional view illustrating an embodiment of the subsequent process after the formation of the gate stack STA.

[0122] Reference Figure 8 The second insulating layer 120 may be formed to cover the gate stack STA and the third insulating layer 130. The second insulating layer 120 may include two or more insulating layers.

[0123] The gate contact GCT, the second contact CT2 and the second line ML2 of the second interconnect IC2, the third contact CT3 and the second bonding pad BP2 can be embedded into the second insulating layer 120 by means of various processes.

[0124] Gate contact GCT can penetrate the third insulating layer 130 to contact the stacked conductive layers WL and DSL of each gate stack STA and the initial selected conductive layer pSSL. Third contact CT3 can penetrate the third insulating layer 130 to contact the source structure SOS.

[0125] It can be formed by using some of the second contacts CT2 and the second line ML2 that form the second interconnect IC2. Figure 1B The bit line contact BCT and bit line BL are shown in the diagram.

[0126] In one embodiment, after forming the first lower layer of the second insulating layer 120, gate contacts GCT and third contacts CT3 can be formed, penetrating the first lower layer of the second insulating layer 120 and the third insulating layer 130. Subsequently, after forming the second lower layer of the second insulating layer 120, a lowermost second contact CT2 can be formed, contacting the gate contacts GCT and third contacts CT3. The lowermost second contact CT2 can penetrate the second lower layer of the second insulating layer 120. Figure 1B The bit line contact BCT shown can pass through the second lower layer and the first lower layer of the second insulating layer 120 to interact with... Figure 1B The cell channel layer CCH of the cell plug CPL shown is in contact. Subsequently, after forming the third lower layer of the second insulating layer 120, a lowermost second line ML2 that contacts the lowermost second contact CT2 can be formed. The lowermost second line ML2 can pass through the third lower layer of the second insulating layer 120. Figure 1B The bit line BL shown can pass through the third lower layer of the second insulating layer 120 to interact with... Figure 1B The bit line contact BCT shown is in contact with the bit line. Afterwards, after forming the intermediate layer of the second insulating layer 120, the remaining second contact CT2 and the remaining second line ML2 can be formed through the intermediate layer of the second insulating layer 120. Subsequently, after forming the upper layer of the second insulating layer 120, the second bonding pad BP2 can be formed through the upper layer of the second insulating layer 120.

[0127] Figure 9 An implementation method for the process of combining the peripheral circuit structure and the memory cell array structure is shown. This can be understood by referring to... Figure 3 The described process setup includes the peripheral circuit structure, and can be referenced... Figure 4 , Figure 5 , Figure 6 , Figure 7A , Figure 7B and Figure 8 The described process sets up the memory cell array structure.

[0128] Reference Figure 9 The memory cell array structure with gate stack STA can be aligned with the peripheral circuit structure with transistor TR, such that the second bonding pad BP2 faces the first bonding pad BP1 on the third direction D3. Subsequently, the second bonding pad BP2 can be bonded to the first bonding pad BP1, and the second insulating layer 120 can be bonded to the first insulating layer 110.

[0129] Subsequently, a fourth insulating layer 140 can be formed to cover the source structure SOS. In an embodiment, the thickness of the source structure SOS can be reduced before forming the fourth insulating layer 140. The thickness of the source structure SOS can be reduced by a planarization process or an etching process. Embodiments of this disclosure are not limited thereto, and the step of reducing the thickness of the source structure SOS can be omitted.

[0130] Figure 10A This is a cross-sectional view illustrating an embodiment of the process for forming a separated structured hole (DSH) and a through structured hole (PSH). Figure 10B It is along Figure 10A The plan view shown is cut by line F-F'.

[0131] Reference Figure 10A and Figure 10B A mask pattern (not shown) can be formed having openings corresponding to the split-structure hole (DSH) and the through-structure hole (PSH). Subsequently, the split-structure hole (DSH) and the through-structure hole (PSH) can be formed simultaneously by an etching process using the mask pattern as an etching barrier. After forming the split-structure hole (DSH) and the through-structure hole (PSH), the mask pattern can be removed.

[0132] The split-through via (DSH) can overlap with the word line (WL). The through-through via (PSH) can overlap with the third contact (CT3). Each of the split-through via (DSH) and the through-through via (PSH) can pass through the fourth insulating layer (140). Each of the split-through via (DSH) and the through-through via (PSH) can pass through the second surface (SU2) of the source structure (SOS) of the source structure (SOS).

[0133] The separated structure via DSH can penetrate the stacked insulating layer IL adjacent to the source structure SOS. For example... Figure 7A and Figure 7B As shown, the split structure hole DSH can pass through the select connector SCP of the initial selection conductive layer pSSL. The split structure hole DSH can be defined as... Figure 7B The selected connector SCP shown has a wider area. While forming the separation structure hole DSH, not only can it remove... Figure 7B The selected connector SCP is shown, and it can be removed. Figure 7B A portion of each of the first selective extension SEP1 and the second selective extension SEP2 shown. Due to the separation structure hole DSH, Figure 7A and Figure 7BThe preliminary selective conductive layer pSSL shown can be separated into selective conductive layers SSL. In an embodiment, the preliminary selective conductive layer pSSL located between the third slit structures SLS3 can be separated into a first selective conductive layer SSL1 and a second selective conductive layer SSL2. The first slit structure SLS1 and the second slit structure SLS2 located between the third slit structures SLS3 can be exposed via the separation structure aperture DSH. The separation structure aperture DSH can be connected to... Figure 2C The conductive connectors CCP shown are overlapped.

[0134] When forming the separation via DSH and the through-hole PSH, a portion of the third contact CT3 and a portion of the third insulating layer 130 can be etched. The through-hole PSH can be formed to expose the third contact CT3.

[0135] As described above, even without performing a separate etching process to separate the first selective conductive layer SSL1 and the second selective conductive layer SSL2, a separation structural hole DSH can be formed simultaneously with the formation of the through structural hole PSH, so that the first selective conductive layer SSL1 and the second selective conductive layer SSL2 can be separated from each other.

[0136] Figure 11 This is a cross-sectional view illustrating an embodiment of the process for forming a separated insulating structure DIS and a through insulating structure PIS.

[0137] Reference Figure 11 The discrete insulating structure DIS can fill the discrete structure hole DSH. The through insulating structure PIS can extend along the sidewall of the through structure hole PSH to cover the sidewall of the source structure SOS. The third contact CT3 can be exposed through the bottom of the through structure hole PSH.

[0138] When the diameter of the through-hole PSH is limited to twice the diameter of the separation structure hole DSH, the separation insulation structure DIS and the through-hole insulation structure PIS can be formed simultaneously. In an embodiment, the formation of the separation insulation structure DIS and the through-hole insulation structure PIS may include: forming insulating material in the separation structure hole DSH and the through-hole PSH; and etching the insulating material by a back-etching process to expose the third contact CT3. Before the back-etching process, the insulating material may completely fill the separation structure hole DSH, but may not completely fill the through-hole PSH with a diameter larger than that of the separation structure hole DSH, and may be formed conformally along the surface of the separation structure hole DSH.

[0139] After forming the aforementioned separated insulation structure DIS and through insulation structure PIS, as Figure 1C As shown, the central region of the through structural hole PSH can be filled with the fourth contact CT4 of the through contact PCT.

[0140] Subsequently, it can form Figure 1C The fifth insulating layer 150 and the top line TML are shown.

[0141] According to embodiments of this disclosure, before forming the discrete insulation structure DIS, it can be used Figure 7A The preliminary selection of conductive layer pSSL replacement shown Figure 6 Some of the sacrificial layers FL are shown in the diagram. Therefore, the process of replacing the sacrificial layer FL with a preliminary selected conductive layer pSSL can be carried out stably without interference from the separation insulation structure DIS.

[0142] Unlike the embodiments of this disclosure, a separate insulating structure can be formed before the sacrificial layer is replaced with a preliminary selected conductive layer. In this case, due to the separate insulating structure, pattern defects in the preliminary selected conductive layer may occur, or it may be difficult to smoothly expel dust from the preliminary selected conductive layer. According to the embodiments of this disclosure, because the separate insulating structure DIS is formed in... Figure 6 Some of the sacrifice layers FL shown are Figure 7A The initial selected conductive layer pSSL shown is formed after replacement, so the pattern failure of the initial selected conductive layer pSSL can be reduced, and the smoke and dust can be discharged smoothly.

[0143] According to embodiments of this disclosure, since the through-hole PSH and the split-hole DSH can be formed simultaneously, the number of process steps can be reduced. Therefore, according to embodiments of this disclosure, the manufacturing time and cost of semiconductor memory devices can be reduced.

[0144] Figure 12 This is a block diagram illustrating the configuration of a storage system according to an embodiment of the present disclosure.

[0145] Reference Figure 12 The storage system 1100 according to an embodiment of the present disclosure includes a storage device 1120 and a storage controller 1110.

[0146] Storage device 1120 may include a semiconductor storage device according to embodiments of the present disclosure. Storage device 1120 may be a multi-chip package formed of a plurality of flash memory chips. Storage device 1120 may include a first selective conductive layer and a second selective conductive layer, the first selective conductive layer and the second selective conductive layer being disposed between a source structure and stacked conductive layers and spaced apart from each other. The first selective conductive layer may be insulated from the second selective conductive layer by means of a separation insulating structure. The separation insulating structure may extend through the source structure.

[0147] The storage controller 1110 controls the storage device 1120 and includes a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction code (ECC) circuit 1114, and a storage interface 1115. The SRAM 1111 can be used as the operating memory of the CPU 1112. The CPU 1112 can perform overall control operations for data exchange with the storage controller 1110. The host interface 1113 can provide a data exchange protocol with a host connected to the storage system 1100. Furthermore, the ECC circuit 1114 can detect and correct errors included in the data read from the storage device 1120, and the storage interface 1115 can interface with the storage device 1120. Additionally, the storage controller 1110 may further include a read-only memory (ROM) for storing code data for interfacing with the host.

[0148] The aforementioned storage system 1100 may be a memory card or solid-state drive (SSD) equipped with a storage device 1120 and a storage controller 1110. For example, when the storage system 1100 is an SSD, the storage controller 1110 may communicate with an external device (e.g., a host) via one of various interface protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Interconnect-Express (PCI-E), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE) protocols.

[0149] Figure 13 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure.

[0150] Reference Figure 13 The computing system 1200 according to embodiments of this disclosure may include a CPU 1220, random access memory (RAM) 1230, user interface 1240, modem 1250, and storage system 1210 electrically connected to a system bus 1260. Furthermore, if the computing system 1200 is a mobile device, it may further include units for supplying operating voltage to the computing system 1200. It may further include an application chipset, camera image processor, mobile DRAM, etc.

[0151] Reference above Figure 12 Similarly, the storage system 1210 may consist of a storage device 1212 and a storage controller 1211.

[0152] According to embodiments of this disclosure, the select conductive layers can be separated from each other using a separation insulating structure that passes through the source structure. Therefore, pattern defects in the select conductive layers can be reduced, and soot in the select conductive layers can be reduced. Thus, embodiments of this disclosure can improve the operational reliability of semiconductor memory devices.

[0153] Cross-reference to related applications

[0154] This application claims priority to Korean Patent Application No. 10-2020-0150833, filed with the Korean Intellectual Property Office on November 12, 2020, and Korean Patent Application No. 10-2021-0022705, filed with the Korean Intellectual Property Office on February 19, 2021, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: Source structure; A stacked conductive layer, wherein the stacked conductive layer overlaps with the source structure; A first selective conductive layer and a second selective conductive layer are disposed between the source structure and the stacked conductive layers. A stacked insulating layer is disposed between a first selective conductive layer and the stacked conductive layer and between a second selective conductive layer and the stacked conductive layer; A first slit structure and a second slit structure, the first slit structure and the second slit structure passing through the stacked conductive layer and the stacked insulating layer; as well as A separate insulating structure is provided that extends through the source structure and to the arrangement height of the first selective conductive layer and the second selective conductive layer without extending through the stacked conductive layers. The first slit structure, the second slit structure, and the separated insulating structure are arranged between the first selective conductive layer and the second selective conductive layer. The separation insulation structure is arranged between the first slit structure and the second slit structure.

2. The semiconductor memory device according to claim 1, wherein, The separate insulation structure is in contact with the stacked insulation layer.

3. The semiconductor memory device according to claim 1, wherein, Each of the first slit structure and the second slit structure extends in a first direction, and The first slit structure and the second slit structure are spaced apart from each other in the first direction, and the separation insulation structure is inserted between the first slit structure and the second slit structure.

4. The semiconductor memory device according to claim 3, wherein, The first selective conductive layer and the second selective conductive layer are spaced apart from each other in a second direction intersecting the first direction.

5. The semiconductor memory device according to claim 3, wherein, The width of the separation insulation structure in the second direction intersecting the first direction is greater than the widths of the first slit structure and the second slit structure in the second direction.

6. The semiconductor memory device according to claim 1, wherein, The stacked conductive layer includes: A first conductive extension, which overlaps with the first selective conductive layer; A second conductive extension, which overlaps with the second selective conductive layer; and A conductive connector that connects the first conductive extension and the second conductive extension.

7. The semiconductor memory device according to claim 6, wherein, The conductive connector overlaps with the separate insulating structure.

8. The semiconductor memory device according to claim 6, wherein, The conductive connector is disposed between the first slit structure and the second slit structure.

9. A semiconductor memory device, the semiconductor memory device comprising: Source structure; A stacked conductive layer, wherein the stacked conductive layer overlaps with the source structure; A first selective conductive layer and a second selective conductive layer are disposed between the source structure and the stacked conductive layers. A stacked insulating layer is disposed between a first selective conductive layer and the stacked conductive layer and between a second selective conductive layer and the stacked conductive layer; as well as A separate insulating structure passes through the source electrode structure. The separation insulation structure is arranged between the first selective conductive layer and the second selective conductive layer, and The stacked conductive layer includes: a first conductive extension overlapping the first selective conductive layer; a second conductive extension overlapping the second selective conductive layer; and a conductive connector overlapping the separate insulating structure.

10. The semiconductor memory device of claim 9, further comprising: Through-through contact through the source structure.

11. The semiconductor memory device of claim 10, further comprising: A through-insulation structure, the through-insulation structure surrounding the through-contact element. The through-insulation structure is arranged at the same height as the separate insulation structure.

12. The semiconductor memory device according to claim 9, wherein, The source structure surrounds the separated insulating structure.

13. The semiconductor memory device according to claim 9, wherein the semiconductor memory device further comprises: A first slit structure and a second slit structure are spaced apart from each other, and the separating insulating structure is inserted between the first slit and the second slit. Wherein, the first selective conductive layer and the second selective conductive layer are separated from each other due to the first slit structure, the second slit structure, and the separated insulating structure, and The first slit structure and the second slit structure extend between the first conductive extension and the second conductive extension.

14. The semiconductor memory device according to claim 13, wherein, The source structure covers the first slit structure and the second slit structure.

15. A semiconductor memory device, the semiconductor memory device comprising: Source structure; A stacked conductive layer, wherein the stacked conductive layer overlaps with the source structure; A first selective conductive layer and a second selective conductive layer are disposed between the source structure and the stacked conductive layers. A stacked insulating layer is disposed between a first selective conductive layer and the stacked conductive layer and between a second selective conductive layer and the stacked conductive layer; A first slit structure and a second slit structure, the first slit structure and the second slit structure passing through the stacked conductive layer and the stacked insulating layer, and spaced apart from each other along a first direction; as well as A separate insulation structure is provided, which is arranged between the first slit structure and the second slit structure. The first selective conductive layer and the second selective conductive layer are spaced apart from each other by the first slit structure, the second slit structure, and the separated insulating structure. The width of the separation insulation structure is greater than the widths of the first slit structure and the second slit structure, and the separation insulation structure passes through the source structure and extends to the arrangement height of the first selective conductive layer and the second selective conductive layer without passing through the stacked conductive layer.

16. The semiconductor memory device according to claim 15, wherein, The first selective conductive layer and the second selective conductive layer are spaced apart from each other in a second direction intersecting the first direction. The width of the separation insulation structure in the second direction is greater than the width of the first slit structure and the second slit structure in the second direction.

17. The semiconductor memory device of claim 15, further comprising: A through-insulation structure that passes through the source structure.

18. The semiconductor memory device of claim 17, further comprising: A through-contact, which is insulated from the source structure by the through-insulation structure and is surrounded by the through-insulation structure.

19. The semiconductor memory device according to claim 15, wherein, Each of the first selective conductive layer and the second selective conductive layer extends further in the first direction than the stacked conductive layer.

20. A method for manufacturing a semiconductor memory device, the method comprising the following steps: A source structure having a first surface and a second surface is formed, wherein the first surface and the second surface face opposite directions; A stack is formed on the first surface of the source structure, the stack comprising a preliminary selected conductive layer, a stacked conductive layer, and a stacked insulating layer; A unit plug is formed through the stack, and the unit plug is connected to the source structure; A separation structure hole is formed, the separation structure hole passing through the source structure from the second surface of the source structure; as well as A separation insulation structure is formed in the separation structure hole. The step of forming the separated structural pore includes separating the preliminary selective conductive layer into a first selective conductive layer and a second selective conductive layer. The separate insulating structure extends to the arrangement height of the first selective conductive layer and the second selective conductive layer without penetrating the stacked conductive layers.

21. The method of claim 20, further comprising the following steps: An insulating layer is formed that covers the first surface of the source structure and the laminate. A first through-contact is formed through the insulating layer, and the first through-contact contacts the source structure; as well as A through-hole is formed, the through-hole extending from the second surface of the source structure through the source structure, and The through-hole structure exposes the first through-contact element.

22. The method according to claim 21, wherein, The through-hole and the separation hole are formed simultaneously.

23. The method of claim 20, further comprising the following steps: Forming transistors; Form first bonding pads that are electrically connected to the transistors respectively; A second bonding pad is formed that is electrically connected to the unit plug and the stacked conductive layer, respectively; as well as The second bonding pad is bonded to the first bonding pad respectively.

24. The method of claim 20, wherein, The initially selected conductive layer is arranged between the source structure and the structure formed by alternately stacking the stacked conductive layers and the stacked insulating layers, and The preliminary selected conductive layer extends further than the stacked conductive layer in a first direction parallel to the first surface.

25. The method according to claim 20, wherein, The preliminary selected conductive layer includes a first selected extension, a second selected extension, and a selected connector, wherein the selected connector connects the first selected extension and the second selected extension.

26. The method of claim 25, wherein, The stacked conductive layer includes word lines, and The word line includes: a first conductive extension overlapping the first selectable extension; a second conductive extension overlapping the second selectable extension; and a conductive connector overlapping the selectable connector, the conductive connector connecting the first conductive extension and the second conductive extension.

27. The method of claim 26, further comprising the following steps: A first slit structure and a second slit structure are formed, and the first slit structure and the second slit structure are arranged between the first selection extension and the second selection extension, which are spaced apart from each other by the selection connector. The first slit structure and the second slit structure extend between the first conductive extension and the second conductive extension.

28. The method according to claim 27, wherein, The separation structure hole is formed to pass through the selector connector and overlap with the conductive connector, and The first slit structure and the second slit structure are exposed via the separation structure hole.

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