Semiconductor structure and method of manufacturing the same, three-dimensional memory and storage system

Abstract

The disclosure provides a semiconductor structure and a preparation method thereof, a three-dimensional memory and a storage system, and relates to the technical field of semiconductor chips, and aims to solve the problems of poor uniformity of deep hole etching and easy over-etching. The preparation method comprises the following steps: forming a stop block extending at least partially into a substrate, leaving a spacing between the stop block and the surface of the substrate away from the stop block; forming a first laminated structure comprising a plurality of insulating layers and a plurality of sacrificial layers on the side of the stop block away from the substrate; etching to form a first channel hole, the first channel hole penetrating through the first laminated structure and extending into the stop block, and the etching selectivity ratio of the stop block is smaller than that of the first laminated structure; and removing the stop block to form a second channel hole.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and its fabrication method, a three-dimensional memory and a storage system. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of the process, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed memory with a three-dimensional structure (3D NAND, three-dimensional memory), which increases storage density by arranging storage cells three-dimensionally on a substrate.

[0004] As the number of stacked layers in 3D memory continues to increase, the total thickness of the stacked film layers continues to increase, making the etching process for forming deep holes such as channel holes increasingly difficult. At the same time, the uniformity of the formed deep holes is poor, which has an adverse effect on the subsequent back-side lead-out process. Summary of the Invention

[0005] This disclosure provides a semiconductor structure and its fabrication method, a three-dimensional memory and a storage system, relating to the field of semiconductor chip technology, and aims to solve the problems of poor uniformity and easy over-etching in deep hole etching.

[0006] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions: On one hand, a method for fabricating a semiconductor structure is provided, comprising: forming a stop block on a substrate, at least a portion of the stop block extending into the substrate, and a gap being left between the stop block and a surface of the substrate away from the stop block; forming a first stacked structure located on the side of the stop block away from the substrate, the first stacked structure including a plurality of alternately stacked insulating layers and a plurality of sacrificial layers; etching to form a first channel hole, the first channel hole penetrating the first stacked structure and extending into the stop block, the etching selectivity of the stop block being less than the etching selectivity of the first stacked structure; and removing the stop block to form a second channel hole.

[0007] In some embodiments, forming a stop block on the substrate includes forming a stop block embedding layer on the substrate, wherein the stop block is embedded in the stop block embedding layer, and a portion of the stop block extends into the substrate.

[0008] In some embodiments, forming a stop block embedding layer on one side of a substrate includes: forming a stop block defining layer on the substrate; forming a groove on the side of the stop block defining layer away from the substrate, and the bottom of the groove extending into the substrate; and embedding the stop block in the groove.

[0009] In some embodiments, forming a stop block defining layer on a substrate includes: forming a second stacked structure on the substrate, the second stacked structure including at least one insulating layer and at least one sacrificial layer alternately stacked; and / or forming a first etch barrier layer on the substrate; wherein the second stacked structure is located on the side of the first etch barrier layer away from the substrate.

[0010] In some embodiments, the layer furthest from the substrate in the second stacked structure is an insulating layer.

[0011] In some embodiments, in the first stacked structure, the thickness of the first insulating layer is greater than the thickness of the other insulating layers, and the first insulating layer is the insulating layer in the first stacked structure that is in contact with the second stacked structure.

[0012] In some embodiments, forming a stop block on the substrate includes: forming a groove on the substrate; and embedding the stop block in the groove.

[0013] In some embodiments, prior to forming the first stacked structure, the method further includes forming a second etch barrier layer located on the side of the stop block away from the substrate.

[0014] In some embodiments, embedding the stop block in the groove includes: forming a stop material layer that covers the groove; planarizing the stop material layer to form the stop block; wherein the stop block is flush with the edge of the groove away from the substrate on the surface of the substrate.

[0015] In some embodiments, the first channel hole extends into a portion of the stop block, with a gap between it and the sidewall of the stop block at all points.

[0016] In some embodiments, the substrate includes: a first sub-substrate, a release layer, and a second sub-substrate stacked sequentially, and forming a stop block on the substrate includes: forming a stop block on the second sub-substrate, at least a portion of the stop block extending into the second sub-substrate, and a gap being left between the stop block and the release layer.

[0017] In some embodiments, the substrate further includes a third barrier etching layer disposed on the side of the second sub-sub ...

[0018] In some embodiments, removing the stop block to form a second channel hole includes: forming the second channel hole by heat treatment; or, etching to form the second channel hole.

[0019] In some embodiments, forming the second channel hole by heat treatment includes: providing a combustion accelerant, causing the combustion accelerant to chemically react with the stop block to form a gaseous compound.

[0020] In some embodiments, the method for fabricating the semiconductor structure further includes: sequentially forming a storage functional layer and a channel layer within the channel via to obtain a channel structure; removing the substrate to expose a portion of the channel structure extending into the substrate; removing the storage functional layer from the exposed channel structure to expose a portion of the channel layer; and ion doping at least the exposed portion of the channel layer.

[0021] In some embodiments, ion doping of at least a portion of the exposed portion of the channel layer includes ion doping of at least a portion of the channel layer located between a doping site and the bottom, wherein the doping site corresponds to a sacrificial layer in the semiconductor structure closest to the substrate.

[0022] On the other hand, a semiconductor structure is provided, comprising: a source layer; a first memory stack structure located on one side of the source layer, including a plurality of alternately stacked gate conductive layers and a plurality of insulating layers; a channel structure including a first sub-channel structure and a second sub-channel structure in contact with each other, the first sub-channel structure being located on the side of the second sub-channel structure away from the source layer; the first sub-channel structure extending through the first memory stack structure, and the end of the second sub-channel structure away from the first sub-channel structure contacting the source layer; wherein, along a thickness direction perpendicular to the first memory stack structure, the critical dimension of the first sub-channel structure is smaller than the critical dimension of the second sub-channel structure.

[0023] In some embodiments, a gap is left everywhere between the edge of the first sub-channel structure projected onto the source layer and the edge of the second sub-channel structure projected onto the source layer.

[0024] In some embodiments, the semiconductor structure further includes: a second memory stack structure disposed between the source layer and the first memory stack structure, the second memory stack structure including at least one gate conductive layer and at least one insulating layer; and a second sub-channel structure extending through the second memory stack structure.

[0025] In some embodiments, in the second storage stack structure, the layer furthest from the source layer is an insulating layer.

[0026] In some embodiments, in the first storage stack structure, the thickness of the first insulating layer is greater than the thickness of other insulating layers, and the first insulating layer is an insulating layer in the first storage stack structure that is in contact with the second storage stack structure.

[0027] In some embodiments, in the first storage stack structure, the thickness of the first insulating layer is 3 to 5 times the thickness of the other insulating layers.

[0028] In some embodiments, the semiconductor structure further includes: a first etch barrier layer located on the side of the second memory stack structure near the source layer; and a second sub-channel structure extending through the first etch barrier layer.

[0029] In some embodiments, the second sub-channel structure is entirely located within the source layer.

[0030] In some embodiments, the semiconductor structure further includes a second etch barrier layer located on the side of the first memory stack structure near the source layer.

[0031] In another aspect, a three-dimensional memory is provided, including a semiconductor structure as described in some of the embodiments above, and further including peripheral circuitry coupled to the semiconductor structure.

[0032] In another aspect, a storage system is provided, including a three-dimensional memory as described in some of the embodiments above, and further including: a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

[0033] The semiconductor structure fabrication method provided in the above embodiments of this disclosure sets the etch selectivity of the stop block to be less than that of the first stacked structure. That is, under the same etching process conditions, the etch rate of the stop block is less than that of the first stacked structure. Thus, when etching to form the first channel hole, the formed first channel hole will penetrate the first stacked structure but will not penetrate the stop block; only a portion will extend into the stop block, thereby ensuring that the etching stops effectively within the stop block and avoiding over-etching. Furthermore, multiple stop blocks are formed together through the same process steps, and their positions and shapes are basically the same. Correspondingly, the position, shape, aperture, and depth of the second channel hole formed by removing the stop blocks are also basically the same. Multiple second channel holes are connected to multiple first channel holes to form multiple channel holes. The depth, shape, and contour of the ends near the substrate of the multiple channel holes are basically the same, improving the uniformity and consistency of the process, and resulting in a semiconductor structure with better structural performance.

[0034] It is understood that the beneficial effects of the semiconductor structure, three-dimensional memory and storage system provided in the above embodiments of this disclosure can be referred to the beneficial effects of the semiconductor structure preparation method described above, and will not be repeated here. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0036] Figure 1 A perspective view of a semiconductor structure according to some embodiments; Figure 2 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments; Figure 3 This is a flowchart of a method for fabricating a stop block on a substrate according to some embodiments; Figure 4 This is a flowchart of a method for preparing a stop block in a groove according to some embodiments; Figure 5 This is a flowchart of a method for fabricating gate lines according to some embodiments; Figure 6 This is a flowchart of a method for preparing a stop block embedding layer according to some embodiments; Figures 7A to 7O This is a process flow diagram for fabricating a semiconductor structure according to some embodiments; Figure 8 This is a structural diagram of an ion implantation window according to some embodiments; Figure 9 This is a structural diagram of the stop block defining layer, the stop block embedding layer, and the semiconductor structure according to some other embodiments; Figure 10 This is a structural diagram of the stop block defining layer, the stop block embedding layer, and the semiconductor structure according to some other embodiments; Figures 11A to 11M This is a process flow diagram for fabricating a semiconductor structure according to some embodiments; Figure 12 This is a structural diagram of an ion implantation window according to some other embodiments; Figure 13 This is a structural diagram of a storage system according to some embodiments; Figure 14 This is a structural diagram of a storage system according to some other embodiments. Detailed Implementation

[0037] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0038] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0039] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0040] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0041] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0042] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0043] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0044] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0045] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0046] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0047] The term "three-dimensional memory" refers to a semiconductor device formed by strings of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on the main surface of a substrate and extending in a direction perpendicular to the substrate. As used herein, the term "perpendicularly" means nominally perpendicular to the main surface of the substrate (i.e., the lateral surface).

[0048] Figure 1 This is a perspective view of a semiconductor structure prepared according to the semiconductor structure preparation method provided in some embodiments of this disclosure. The cross-sectional view of the semiconductor structure can be as follows: Figure 7O , Figure 9 (c) Figure 10 (c) or Figure 11M As shown. Figures 2-6 A flowchart illustrating a method for fabricating a semiconductor structure provided in some embodiments of this disclosure; Figures 7A to 7O and Figures 11A to 11M This is a process flow diagram for fabricating a semiconductor structure according to some embodiments. It should be understood that... Figures 2-6 , Figures 7A to 7O and Figures 11A to 11M The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Furthermore, some steps may be performed simultaneously, or they may be performed in a sequence different from the steps described. Figure 2 The process is performed in the sequence shown. The fabrication methods of the semiconductor structures in some embodiments will now be described with reference to the foregoing accompanying drawings.

[0049] See Figure 2 Some embodiments of this disclosure provide a method for fabricating a semiconductor structure, the method comprising steps S11 to S41.

[0050] S11. A stop block is formed on the substrate.

[0051] In subsequent fabrication processes, the stop block can be removed, and the resulting void can be used to form a channel structure. For example, the stop block is positioned on one side of the substrate, with a gap between the stop block and the substrate surface away from it; that is, the stop block does not penetrate the substrate. Correspondingly, the channel structure formed at the location corresponding to the stop block is also spaced from the substrate surface away from the channel structure. See, for example, [link to documentation]. Figure 7E The stop block SP extends entirely into (or is disposed in) the substrate 1, and the end of the stop block SP away from the substrate 1 does not extend into other film layers.

[0052] For example, substrate 1 can be a single-layer silicon substrate. For instance, the material of substrate 1 can be polycrystalline silicon, which helps to improve the uniformity and consistency of the film formed in subsequent fabrication processes.

[0053] As another example, the substrate in a semiconductor structure may also include multiple film layers adjacent to each other. For example, see Figure 7EThe substrate 1 includes a first sub-substrate 11, a release layer 12, and a second sub-substrate 13 stacked sequentially. A stop block SP is formed on the second sub-substrate 13, at least a portion of which extends into the second sub-substrate 13, and a gap is left between the stop block SP and the release layer 12. The first sub-substrate 11 and the second sub-substrate 13 can be made of the same material, for example, both being polycrystalline silicon. The release layer 12 is made of a different material than the first sub-substrate 11 and the second sub-substrate 13, and can be an oxide, such as silicon oxide.

[0054] In related technologies, during the process steps after the channel structure is formed, at least a portion of the substrate needs to be removed to expose at least a portion of the channel structure near the substrate, facilitating the back-side lead-out process. The substrate removal process typically employs processes such as chemical mechanical polishing (CMP). Under this premise, see [reference needed]. Figure 7E The stop block SP is designed not to penetrate the second sub-substrate 13, ensuring a gap between the end of the stop block SP near the release layer and the release layer 12. Correspondingly, the end of the channel structure formed at the corresponding position of the stop block SP in subsequent processes also has a gap with the release layer 12. This design reduces the risk of damage to the end of the channel structure located in the substrate 1 during the substrate removal process. Furthermore, the release layer 12, located between the first sub-substrate 11 and the second sub-substrate 13 and made of a different material than the first sub-substrate 11 and the second sub-substrate 13, can serve as a stop layer for the CMP process. While removing the first sub-substrate 11 by the CMP process to reduce the thickness of the substrate 1 and facilitate the subsequent exposure of the channel structure, the release layer 12 further helps to reduce the risk of damage to the end of the channel structure located in the substrate 1 during the substrate removal process.

[0055] To expose more of the channel structure and improve the connection between the channel structure and the source layer, the stop block SP can extend further into the substrate 1. However, to avoid increasing the risk of damage to the ends of the channel structure formed at the corresponding locations of the stop block SP, the increased exposed portion of the channel structure is generally not achieved by reducing the spacing between the stop block SP and the release layer 12. Therefore, exemplarily, see... Figure 7EThe substrate 1 may further include a third etch barrier layer 14, which is disposed on the side of the second sub-substrate 13 away from the first sub-substrate 11. The stop block SP penetrates the third etch barrier layer 14 and extends into the second sub-substrate 13. In subsequent fabrication processes, at least part (e.g., all) of the third etch barrier layer 14 can be removed by processes such as room temperature (20-80°C) / low temperature (<-30°C) etching, dry / wet etching, etc., to expose more channel structures. Furthermore, during the above-described etching process, the third etch barrier layer 14 can also be used to protect the various film layers located on its side away from the substrate 1, reducing the risk of damage to these film layers caused by the etching process.

[0056] As another example, if the substrate 1 also includes a third barrier etch layer 14, the end of the stop block SP near the substrate 1 may also extend only into the third barrier etch layer 14, and the embodiments of this disclosure do not impose too many restrictions on this.

[0057] For the sake of simplicity, the following example illustrates the scheme of this disclosure, with substrate 1 comprising a first sub-substrate 11, a release layer 12, a second sub-substrate 13 and a third etch barrier layer 14 stacked sequentially, and a stop block SP penetrating the third etch barrier layer 14 and extending from the end of the stop block SP near substrate 1 into the second sub-substrate 13.

[0058] In some embodiments of this disclosure, see Figure 3 When all or all of the stop blocks SP are disposed in the substrate 1 and do not extend into other film layers on the side of the stop blocks SP away from the substrate 1, step S1 of forming the stop blocks SP on the substrate 1 includes steps S111 to S112.

[0059] S111, A groove is formed on the substrate 1.

[0060] For example, see Figure 7A At least one (e.g., multiple) grooves GR can be formed on the surface of one side of the substrate 1 by an etching process. The cross section of the groove GR along the direction of the stacking of each film layer in the substrate 1 is rectangular. In other examples, the cross section of the groove GR can also be other shapes, such as positive direction, trapezoid, inverted trapezoid, etc.

[0061] S112. Embed the stop block SP in the groove GR.

[0062] For example, see Figure 4 The specific steps for forming the stop block SP in the groove GR may include S1121~S1122.

[0063] S1121, Form a stop material layer.

[0064] For example, see Figure 7BStop material can be deposited into the grooves GR until a certain thickness of stop material is also deposited on the surface of the substrate 1 on the side where the grooves GR are located, to form a stop material layer ML. The stop material layer ML covers multiple grooves GR. The stop material can be tungsten, and the deposition method of the stop material includes, but is not limited to, thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0065] S1122. Planarize the stop material layer ML to form the stop block SP.

[0066] For example, see Figure 7C The surface of the deposited stop material layer ML away from the substrate 1 can be planarized using a CMP process, so that the formed stop block SP is flush with the edge of the groove GR away from the substrate 1, facilitating the subsequent formation of other film structures on this surface. The shape of the stop block SP formed by this process can be cylindrical, prism, frustum, etc., without much limitation. For example, the thickness of the formed stop block SP along the thickness direction (i.e., the Z direction) of the substrate 1 is approximately 150 nm to 200 nm.

[0067] For example, see Figure 7D When all the stop blocks SP are disposed in the substrate 1, the method for fabricating the semiconductor structure after forming the stop blocks SP may further include: forming a second etch barrier layer 22, the second etch barrier layer 22 being located on the side of the stop blocks SP away from the substrate 1. For example, the second etch barrier layer 22 is in contact with the surface of the stop blocks SP away from the substrate 1, and can be formed by a thin film deposition process such as CVD, PVD, or ALD, and its material can be polycrystalline silicon. During the subsequent removal of at least a portion of the substrate 1 to expose the channel structure, the second etch barrier layer 22 can be used to protect the film layers located on its side away from the substrate 1, reducing the risk of damage to these film layers caused by the substrate removal process.

[0068] S21, forming the first layered structure.

[0069] For example, see Figure 7EThe first stacked structure LS1 is located on the side of the stop block SP away from the substrate 1, and includes multiple alternately stacked insulating layers 31 and multiple sacrificial layers 32. The first stacked structure LS1 can be formed by thin film deposition processes such as CVD, PVD, or ALD. The insulating layer 31 can be made of oxide, and the sacrificial layer 32 can be made of nitride. For example, in the first stacked structure LS1, the insulating layer 31 is made of silicon oxide, and the sacrificial layer 32 is made of silicon nitride.

[0070] In addition, see, for example Figure 7E When a first stacked structure LS1 is provided in the semiconductor structure, the thickness of the first insulating layer 311 in the first stacked structure LS1 is greater than the thickness of the other insulating layers 31. The first insulating layer 311 is the insulating layer 31 closest to the substrate 1 in the first stacked structure LS1.

[0071] For example, see Figure 7E The edges of the first stacked structure LS1 can be stepped. This stepped structure can be formed by performing multiple trim-etch cycles on multiple sacrificial layers 32 and multiple insulating layers 31. See also Figure 7E After the above-described process, the region on substrate 1 corresponding to the stepped structure formed by the first stacked structure LS1 can be referred to as step region B, which can be the electrical connection region of the word line (gate layer). The region corresponding to the first stacked structure LS1 without the stepped structure can be referred to as memory region A, which can be used to implement the memory function. The remaining regions on substrate 1 can be referred to as peripheral region C, which can be used to form through-silicon contact structures and source contact structures electrically connected to the peripheral circuit layers in subsequent processes. The steps for forming through-silicon contact structures and source contact structures will be described in detail in some later embodiments.

[0072] For example, see Figure 7F After forming the stepped structure, the method for fabricating the semiconductor structure may further include forming an insulating capping layer 5 covering the first stacked structure LS1, wherein the insulating capping layer 5 is located on the side of the first stacked structure LS1 away from the substrate 1. The insulating capping layer 5 is made of an insulating material, such as silicon oxide, and can be formed by thin film deposition processes such as CVD, PVD, or ALD. After forming the insulating capping layer 5, the surface of the insulating capping layer 5 away from the substrate 1 can be planarized using a CMP process.

[0073] S31, etching to form the first channel hole.

[0074] For example, see Figure 7GThe first channel hole CH1 can be formed using room temperature (20-80℃) / low temperature (<-30℃) etching processes, dry / wet etching processes, etc. The first channel hole CH1 penetrates the first stacked structure LS1 and extends into the stop block SP. The etching selectivity of the stop block SP is less than the etching selectivity of the first stacked structure LS1. Specifically, when all or all of the stop blocks SP are disposed in the substrate 1 (see...), Figure 7G The material of the stop block SP can be tungsten; when a portion of the stop block SP extends into the substrate 1 and the remainder extends into other film layers away from the substrate 1, the material of the stop block SP can be carbon or tungsten. During the etching process to form the first channel hole CH1, because the etching selectivity of the stop block SP is less than that of the first stacked structure LS1, i.e., under the same etching process conditions, the etching rate of the stop block SP is less than that of the first stacked structure LS1, the formed first channel hole CH1 will penetrate the first stacked structure LS1 and partially extend into the stop block SP, thus ensuring that the etching stops well within the stop block SP, reducing the risk of over-etching during the formation of the first channel hole CH1.

[0075] In this context, "the first channel hole CH1 extends into the stop block SP" means that the formed first channel hole CH1 does not penetrate the stop block SP. The orthographic projection of the end of the first channel hole CH1 near the substrate 1 onto the substrate 1 is included in the orthographic projection of the stop block SP onto the substrate 1, and the area of ​​the orthographic projection of the stop block SP onto the substrate 1 is larger than the area of ​​the orthographic projection of the end of the first channel hole CH1 near the substrate 1 onto the substrate 1. In other words, the end of the first channel hole CH1 near the substrate 1 does not exceed the range defined by the stop block SP. Because the area of ​​the orthographic projection of the stop block SP onto the substrate 1 is relatively large, the alignment accuracy required for the end of the first channel hole CH1 near the substrate 1 to extend into the stop block SP is reduced during the etching process, thus reducing the process difficulty and facilitating production cost control.

[0076] If a portion of the first channel hole CH1 near the end of the substrate 1 extends beyond the range defined by the stop block SP, the etching of the portion of the first channel hole CH1 extending beyond the stop block SP cannot be stopped, resulting in a higher risk of over-etching and the inability to guarantee the uniformity of the formed first channel hole CH1. Therefore, by way of example, see Figure 7GThe portion of the first channel hole CH1 extending into the stop block SP is spaced apart from the sidewall of the stop block SP at all points. That is, the orthographic projection of the etched first channel hole CH1 onto the substrate 1 is included in the orthographic projection of the stop block SP onto the substrate 1, and a gap is maintained between the edge of the orthographic projection of the first channel hole CH1 onto the substrate 1 and the edge of the orthographic projection of the stop block SP onto the substrate 1 at all points. The portion of the first channel hole CH1 extending into the stop block SP is surrounded by the stop block SP, and the stop block SP constitutes the hole wall of the portion of the first channel hole CH1 extending into the stop block SP. This allows the stop block SP to stop the etching of the first channel hole CH1, reducing the likelihood of the aforementioned problems.

[0077] S41. Remove the stop block SP to form a second channel hole.

[0078] For example, see Figure 7H Depending on the material of the stop block SP, the stop block SP can be removed by an appropriate method (such as heat treatment or etching) to form a second channel hole CH2. The second channel hole CH2 is connected to the first channel hole CH1 and together they form the channel hole CH of the semiconductor structure.

[0079] For example, when the stop block SP is made of tungsten, it can be removed by etching to form the second channel hole CH2. Alternatively, wet etching can be used to remove the stop block SP.

[0080] For example, when the stop block SP is made of carbon, it can be removed by heat treatment to form the second channel hole CH2. Specifically, a combustion-supporting agent can be provided to react chemically with the stop block SP, forming a gaseous compound to remove the stop block SP. For example, the provided combustion-supporting agent can be oxygen. By controlling the process temperature and oxygen concentration, carbon and oxygen react chemically to form gaseous compounds of carbon and oxygen, such as carbon monoxide and carbon dioxide, thereby removing the stop block SP. The process temperature of the heat treatment can be set as needed. For example, the process temperature of the heat treatment can be set not to exceed 300°C, specifically, it can be 200°C. Alternatively, hot oxygen can be directly provided to react with the stop block SP to form a gaseous compound, thereby removing the stop block SP and forming the second channel hole CH2. The temperature of the hot oxygen can not exceed 300°C, for example, it can be 220°C.

[0081] In summary, the setting of stop blocks SP not only helps to reduce the difficulty of aligning the etching position of the first channel hole CH1, but also reduces the risk of over-etching during the formation of the first channel hole CH1. Multiple stop blocks SP are formed together through the same process steps, and their setting positions and shapes are basically the same. Correspondingly, the position, shape, aperture and depth of the second channel hole CH2 formed by removing the stop blocks SP are also basically the same. Multiple second channel holes CH2 are connected to multiple first channel holes CH1 to form multiple channel holes. The depth, shape and contour of the ends near the substrate 1 of the multiple channel holes are basically the same, resulting in good uniformity and consistency of the process and good structural performance.

[0082] In some embodiments, see Figure 2 The method for preparing the semiconductor structure also includes steps S51 to S91.

[0083] S51, forming a channel structure.

[0084] For example, forming a channel structure includes: sequentially forming a storage function layer and a channel layer within a channel hole CH to obtain a channel structure.

[0085] For example, see Figure 7I Thin-film deposition processes such as CVD, PVD, or ALD can be used to sequentially deposit a charge blocking layer 411, a charge trapping layer 412, a tunneling layer 413, and a channel layer 42 on the inner walls (including the bottom and sidewalls) of the channel hole CH. The charge blocking layer 411, charge trapping layer 412, and tunneling layer 413 constitute the storage functional layer 41. The channel layer 42 can be made of polycrystalline silicon, the charge blocking layer 411 can be made of silicon oxide, the charge trapping layer 412 can be made of silicon nitride, and the tunneling layer 413 can be made of silicon oxide, forming an "ONO" structure.

[0086] For example, see Figure 7I In the formed channel structure 4, the part of the channel structure 4 corresponding to the location of the first channel hole is the first sub-channel structure 410, and the part of the channel structure 4 corresponding to the location of the second channel hole is the second sub-channel structure 420. The first sub-channel structure 410 and the second sub-channel structure 420 are in contact and together constitute the channel structure 4.

[0087] For example, see Figure 7JAfter step S51, the method for fabricating the semiconductor structure may further include: forming at least one (e.g., multiple) virtual channel vias (not shown in the figure) in the step region B, penetrating the first stacked structure LS1 and partially extending into the substrate 1. It should be noted that the depth to which the virtual channel vias extend into the substrate 1 may be the same as or different from the depth to which the channel vias extend into the substrate 1. The virtual channel vias and the channel vias can be formed under the same process or under different processes; there are no excessive restrictions on this.

[0088] For example, see Figure 7J After forming the virtual channel via, the method for fabricating the semiconductor structure may further include filling the virtual channel via with a dielectric material to form a virtual channel structure 4'. In subsequent processes, a dielectric material, such as silicon oxide, can be filled into the virtual channel via using thin-film deposition processes such as CVD, PVD, or ALD to form the virtual channel structure 4'. Exemplarily, by controlling the filling process, one or more air gaps can be formed during the filling process to alleviate structural stress. In embodiments of this disclosure, the virtual channel structure 4' can be used to provide mechanical support without forming a storage functional layer 41 and a channel layer 42 with storage functionality.

[0089] For example, see Figure 7K After forming the virtual channel structure 4', the method for fabricating the semiconductor structure may further include: forming a first capping layer 6 on the side of the first stacked structure LS1 away from the substrate 1 using a thin film deposition process. The first capping layer 6 may cover the end face of the channel structure 4 away from the substrate 1 and the end face of the virtual channel structure 4' away from the substrate 1. Exemplarily, the first capping layer 6 may be made of the same material (e.g., silicon oxide) as the insulating capping layer 5 and the insulating layer 31.

[0090] For example, see Figure 7K After forming the first capping layer 6, the method for fabricating the semiconductor structure may further include forming at least one (e.g., multiple) isolation trenches U. Each isolation trench U extends in a direction perpendicular to the extension direction of the channel via and penetrates the first stacked structure LS1, the insulating capping layer 5, and the first capping layer 6. The number of isolation trenches U can be adaptively adjusted according to the circuit design or integration level of the semiconductor structure.

[0091] For example, after the isolation trench is formed, the sacrificial layer 32 is divided into multiple sacrificial portions by the isolation trench. In subsequent fabrication processes, each sacrificial portion can be replaced with a gate line. The insulating layer 31 is divided into multiple gate insulating layers by the isolation trench. The multiple sacrificial layers 32 and insulating layers 31 are alternately stacked along a first direction (i.e., the Z direction). Each sacrificial portion is replaced with a gate line, and the same gate conductive layer 33 includes multiple gate lines. Each gate line extends along a second direction (i.e., the X direction), and the multiple gate lines in the same gate conductive layer 33 are arranged along a third direction (i.e., the Y direction). Any two of the X, Y, and Z directions intersect each other (e.g., perpendicularly).

[0092] See Figure 5 Forming gate lines may specifically include the following steps: S10. Remove the sacrificial part to form a sacrificial gap.

[0093] For example, a wet etching process can be used to remove the sacrificial portion; for instance, hydrofluoric acid can be used to remove the sacrificial portion to form a sacrificial gap.

[0094] S20, An interface layer is formed in the sacrificial gap.

[0095] Specifically, see Figure 7L An interface layer can be formed on the surface of the insulating layer 31 exposed through the sacrificial gap and on the surface of the insulating capping layer 5 using an ALD process or a sputtering process. The material of the interface layer may include a metal compound, such as one or more combinations of titanium nitride, tantalum nitride, and tungsten carbide.

[0096] S30, forming grid lines.

[0097] For example, the gate lines are all formed of a conductive material, and multiple gate lines are made of the same material. The gate line materials may include, but are not limited to, tungsten, aluminum, copper, titanium, tantalum, or their metal nitrides. See, for example, [link to relevant documentation]. Figure 7L Conductive material can be filled into the isolation trench U and the sacrificial gaps where the interface layer is formed using processes such as CVD, PECVD, ALD, PVD, and sputtering. After the conductive material is filled, the conductive material in the isolation trench U is removed by etching back to form multiple mutually insulated gate lines. The multiple gate conductive layers 33 and insulating layers 31 corresponding to the location of the first stacked structure constitute the first memory stack structure D1.

[0098] For example, see Figure 7L After forming multiple grid lines, dielectric material can be filled into the isolation trench U to form a slot structure Ux.

[0099] For example, see Figure 7LThe method for fabricating this semiconductor structure may further include: forming at least one (e.g., one) through-silicon contact structure 71 and at least one (e.g., one) source contact structure 72 in the peripheral region C, wherein the through-silicon contact structure 71 and the source contact structure 72 penetrate the insulating capping layer 5 and extend at least partially into the substrate 1 for electrical connection with peripheral circuits, and their number and arrangement can be fabricated according to actual needs. In this step, a dry / wet etching process can be used to form through-silicon contact holes and source contact holes that vertically penetrate the first capping layer 6 and the insulating capping layer 5 and extend partially into the substrate 1. Then, a thin film deposition process can be used to fill the through-silicon contact holes with a conductive material, such as at least one of tungsten, cobalt, copper, aluminum, etc., to form the through-silicon contact structure 71 and the source contact structure 72.

[0100] For example, prior to the step of filling the through-hole and source contact hole with conductive material, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to deposit, for example, titanium nitride on the inner walls of the through-hole and source contact hole to form a spacer layer (not shown) through the silicon contact structure 71 and the source contact structure 72. Furthermore, the shape of the through-hole and source contact structure 72 can be cylindrical, prismatic, or other shapes.

[0101] For example, see Figure 7L After forming multiple gate lines, the method for fabricating this semiconductor structure may further include forming multiple contacts 73. Each contact 73 is coupled to one gate line. Specifically, multiple contact holes may be formed in the step region B, penetrating the insulating capping layer 5 and exposing at least a portion of the gate lines. The contact holes may be formed using an etching process, such as wet etching. After forming the multiple contact holes, see [link to documentation]. Figure 7L Multiple contacts 73 can be formed by filling each contact hole with conductive material using sputtering or ALD processes. The depth to which the multiple contacts 73 extend into the substrate 1 can be the same as or different from the depth to which the through-silicon contact structure 71 and the source contact structure 72 extend into the substrate 1. The through-silicon contact structure 71 and the source contact structure 72 and the multiple contacts 73 can be formed using the same process or different processes, without much restriction.

[0102] For example, see Figure 7L While making the aforementioned multiple contacts 73, at least one (e.g. multiple) channel conductive structures 74 can also be made, each channel conductive structure 74 penetrating the first capping layer 6 and coupled to a channel structure 4.

[0103] S61. Remove substrate 1 to expose the portion of the channel structure 4 that extends into substrate 1.

[0104] For example, in this step, the substrate can be removed by dry / wet etching, CMP process or mechanical stripping.

[0105] For example, when the substrate is a single-layer silicon substrate, the silicon substrate can be removed by dry / wet etching to expose the portion of the channel structure extending into the substrate. Alternatively, the substrate can be thinned first using a CMP process, and then the remaining substrate portion can be removed by dry / wet etching to expose the portion of the channel structure extending into the substrate. When thinning the substrate using a CMP process, the thinned substrate is far from the surface of the first stacked structure, and a gap needs to exist between it and the end of the channel structure extending into the substrate, thereby reducing the risk of damage to the channel structure caused by the CMP process.

[0106] For example, when the substrate includes a first sub-substrate, a release layer and a second sub-substrate, and the channel structure extends into the second sub-substrate near the end of the substrate, the first sub-substrate and the release layer can be removed first by dry / wet etching, CMP process or mechanical stripping, and then the second sub-substrate can be removed by wet etching to expose the portion of the channel structure extending into the second sub-substrate.

[0107] For example, see Figure 7M When the substrate includes a first sub-substrate, a release layer, a second sub-substrate and a third etch barrier layer 14, and the channel structure 4 extends into the second sub-substrate near the end of the substrate, similar to the above, the first sub-substrate and the release layer can be removed first by dry / wet etching, CMP process or mechanical stripping, and then the second sub-substrate can be removed by wet etching to expose the portion of the channel structure 4 extending into the second sub-substrate.

[0108] S71. Remove the storage function layer in the exposed channel structure to expose a portion of the channel layer.

[0109] For example, in this step, the storage function layer in the exposed channel structure 4 can be removed by dry / wet etching.

[0110] For example, when the substrate is a single-layer silicon substrate or the substrate includes a first sub-substrate, a release layer, and a second sub-substrate, and the first stacked structure is disposed on the substrate and in contact with the second sub-substrate, and the channel structure extends into the second sub-substrate near the end of the substrate, after removing the single-layer silicon substrate or removing the first sub-substrate, the release layer, and the second sub-substrate to expose the portion of the channel structure extending into the second sub-substrate, the storage functional layer in the exposed channel structure can be removed by wet etching. Because the first insulating layer in the first stacked structure is relatively thick, the etching can be stopped in the first insulating layer, avoiding damage to other film layers in the first stacked structure.

[0111] For example, when the substrate includes a first sub-substrate, a release layer, a second sub-substrate, and a third etch stop layer, and the first stacked structure is disposed on the substrate and in contact with the third etch stop layer, and the channel structure extends into the second sub-substrate near the end of the substrate, after removing the first sub-substrate, the release layer, and the second sub-substrate to expose the portion of the channel structure extending into the second sub-substrate, the storage functional layer in the exposed channel structure can be removed by wet etching. Simultaneously, since the material of the third etch stop layer is all oxide, it will also be etched. After removing the storage functional layer in the exposed channel structure, the third etch stop layer may remain or may be completely removed; there are no strict limitations on this. When the third etch stop layer is completely removed, because the first insulating layer in the first stacked structure is relatively thick, the etching can also stop within the first insulating layer, reducing the risk of damage to other film layers in the first stacked structure.

[0112] For example, see Figure 7N When the substrate includes a first sub-substrate, a release layer, a second sub-substrate, and a third etch barrier layer, and the semiconductor structure also includes a second etch barrier layer 22, the first stacked structure LS1 is disposed on the substrate and in contact with the second etch barrier layer 22. The end of the channel structure 4 near the substrate penetrates the third etch barrier layer 14 and extends into the second sub-substrate. After removing the first sub-substrate, the release layer, and the second sub-substrate, exposing the portion of the channel structure extending into the second sub-substrate, the storage functional layer and the third etch barrier layer in the exposed channel structure can be removed by wet etching. Since the material of the second etch barrier layer 22 is different from that of the storage functional layer 41, it has a different etching selectivity than the storage functional layer 41. When removing the storage functional layer 41 in the exposed channel structure 4, the etching can be stopped at the second etch barrier layer 22, which is beneficial to improving the uniformity of the etching process. At the same time, it can also protect the stacked structure located on the side of the second etch barrier layer 22 away from the substrate.

[0113] S81, At least the exposed portion of the channel layer 42 is ion-doped.

[0114] For example, see Figure 7O Ion doping of at least the exposed portion of the channel layer 42 includes: ion doping of at least the portion of the channel layer 42 located between the doping site and the bottom end, wherein the doping site corresponds to the sacrificial layer 32 closest to the substrate in the semiconductor structure. The type of ion doping can be N-type doping or P-type doping. Ion doping of the portion of the channel layer 42 located between the doping site and the bottom end can improve the conductivity of the channel layer 42 and also improve its conductivity stability. Specifically, when the semiconductor structure is as follows... Figure 7OAs shown, the doping position corresponds to the sacrificial layer closest to the substrate in the first stacked structure, which is also the gate conductive layer 33 closest to the second sub-channel structure 420 in the first memory stacked structure D1.

[0115] See Figure 7O Because the areas of the first channel hole and the stop block projected onto the substrate are different, the areas of the first sub-channel structure 410 formed in the first channel hole and the second sub-channel structure 420 formed in the second channel hole formed by removing the stop block are also different. Furthermore, since the first sub-channel structure 410 and the second sub-channel structure 420 are in contact, a corner exists at their contact point. The channel layer at the corner will block ion implantation at other locations, thus affecting the size of the ion implantation window.

[0116] As described in the foregoing embodiments, when all stop blocks are disposed in the substrate, the ion implantation window is as follows: Figure 8 As shown in the diagram. L1 is the line connecting the corner of the channel layer near the doped site and the doped site; L2 is the line connecting the edge of the etch barrier layer near the channel layer and the doped site when an etch barrier layer is present in the semiconductor structure; and L3 is the line connecting the edge of the channel layer away from the doped site in an adjacent channel structure and the doped site. When an etch barrier layer is present in the semiconductor structure, the angle between L1 and L2 is α1, and the size of α1 is the ion implantation window size, approximately 6°. When no etch barrier layer is present in the semiconductor structure, the angle between L1 and L3 is α2, and the size of α2 is the ion implantation window size, approximately 15°. It can be seen that the stop block configuration in this embodiment can reduce the risk of over-etching during channel hole formation while ensuring the formed semiconductor structure has a reasonable ion implantation window size and achieves a smaller ion implantation angle value (i.e., the sizes of α1 and α2), which is beneficial for improving the conductivity stability of the channel structure 4 through ion implantation. In addition, the first channel hole extends into the stop block, and there is a gap between it and the side wall of the stop block. This allows the channel layer at the corner to block ion implantation at other locations to have a roughly the same area of ​​obstruction, resulting in a more uniform size of the ion implantation window, which helps to improve the uniformity of ion implantation.

[0117] S91, forming the source layer.

[0118] For example, see Figure 7OFollowing step S81, the method for fabricating the semiconductor structure may further include: forming a source layer 101 covering the exposed portion of the channel layer 42 to achieve coupling between the channel structure 4 and the source layer 101. The source layer 101 surrounds the exposed portion of the channel layer 42, enabling a larger contact area between the source layer 101 and the channel structure 4, which is beneficial for increasing the reliability of the contact connection and improving the performance of the fabricated semiconductor structure.

[0119] Specifically, see Figure 7O First, a source material layer can be formed by depositing a source material using a thin-film deposition process. The formed source material covers the exposed portion of the channel layer 42. The source material can be polycrystalline silicon, including P-type or N-type doped materials. The doping type of the source layer 101 is the same as that of the channel layer 42. Next, the surface of the source material layer away from the channel structure 4 is planarized to form the source layer 101. This planarization can be achieved using a CMP process. The formed source layer 101 is positioned away from the channel structure 4, leaving a gap between it and the channel structure 4. This facilitates the subsequent formation of other film layers on this surface while ensuring a large contact area between the source layer 101 and the channel structure 4, and also reduces the risk of damage to the channel structure 4 caused by the CMP process.

[0120] Exemplarily, after step S91, the method for fabricating the semiconductor structure may further include: using dry / wet etching to remove the portion of the source layer 101 corresponding to the through-silicon contact structure 71 and the source contact structure 72. Subsequently, the method for fabricating the semiconductor structure may further include: forming an interlayer dielectric layer 102 on the side of the source layer 101 away from the channel structure 4, the formed interlayer dielectric layer 102 covering the exposed through-silicon contact structure 71, the source contact structure 72, and the source layer 101. In this step, see [reference needed]. Figure 7O A dielectric material, such as silicon oxide, can be filled on the side of the source layer 101 away from the channel structure 4 using, for example, high-density plasma chemical vapor deposition (HDCVD) to form a dielectric material layer. Based on this, a CMP process can be used to planarize the surface of the interlayer dielectric material layer away from the channel structure 4 to form an interlayer dielectric layer 102. The interlayer dielectric layer 102 (also referred to as the intermetallic dielectric layer) may include one or more spaced dielectric material regions that provide insulating space for the metal interconnect layers formed in subsequent processes.

[0121] For example, see Figure 7OThe method for fabricating this semiconductor structure may further include: forming a first source contact A1 coupled to the source layer 101, forming a second source contact A2 coupled to the source contact structure 72, and forming a peripheral contact A3 coupled to the through-silicon contact structure 71. The methods for forming the first source contact A1, the second source contact A2, and the peripheral contact A3 include, but are not limited to, thin film deposition processes such as CVD, PVD, and ALD.

[0122] For example, see Figure 7O The interlayer dielectric layer 102 separates the source layer 101 from the source contact structure 72 and the through silicon contact structure 71, preventing any two of the three from directly contacting each other, thereby preventing crosstalk when receiving and transmitting signals.

[0123] For example, see Figure 7O The method for fabricating the semiconductor structure may further include: forming a metal interconnect layer 103 on the side of the interlayer dielectric layer 102 away from the stacked structure, wherein the metal interconnect layer 103 is electrically connected to the first source contact A1.

[0124] In this step, thin film deposition processes such as CVD, PVD, and ALD can be used to form a metal thin film. The metal thin film is then patterned (e.g., exposed or developed) to form the metal interconnect layer 103. See also... Figure 7O The metal interconnect layer 103 can be coupled to both the first source contact A1 and the second source contact A2 simultaneously, thereby enabling the transmission of source signals.

[0125] For example, see Figure 7O During the formation of the metal interconnect layer 103, a connection pad 103' is also formed on the side of the interlayer dielectric layer 102 away from the channel structure 4. The connection pad 103' is electrically connected to the peripheral contact A3. The connection substrate 1 and the connection pad 103' are used for connection with external circuitry.

[0126] For example, see Figure 7O The method for fabricating the semiconductor structure may further include: forming a barrier layer 104, wherein the barrier layer 104 blocks the connection pad 103' from the metal interconnect layer 103, thereby making it less likely for signal interference to occur between the connection pad 103' and the metal interconnect layer 103.

[0127] In other embodiments of this disclosure, a method for fabricating a semiconductor structure is provided, see [link to relevant documentation]. Figure 2 The preparation method includes steps S12 to S42.

[0128] S12, Form a stop block on the substrate.

[0129] For example, a portion of the stop block extends into the substrate, while the end of the stop block away from the substrate extends into other film layers located on the side of the stop block away from the substrate. As previously mentioned, the substrate can be a single-layer silicon substrate or can include multiple film layers adjacent to each other.

[0130] For example, see Figure 9 In (a), the substrate 1 includes a first sub-substrate 11, a release layer 12 and a second sub-substrate 13 stacked in sequence. A stop block SP is formed on the second sub-substrate 13. A portion of the stop block SP extends into the second sub-substrate 13. The end of the stop block SP away from the substrate 1 extends into other film layers located on the side of the stop block away from the substrate. A gap is left between the stop block SP and the release layer 12.

[0131] For example, see Figure 9 In (a), substrate 1 includes a first sub-substrate 11, a release layer 12, a second sub-substrate 13, and a third etch barrier layer 14 stacked sequentially. The stop block SP penetrates the third etch barrier layer 14 and extends into the second sub-substrate 13. Similarly, the arrangement of the stop block SP in substrate 1 can reduce the risk of damage to the ends of the channel structure located in substrate 1 during the substrate removal process.

[0132] For the sake of simplicity, the following example illustrates the scheme of this disclosure, with substrate 1 comprising a first sub-substrate 11, a release layer 12, a second sub-substrate 13 and a third etch barrier layer 14 stacked sequentially, and a stop block SP penetrating the third etch barrier layer 14 and extending from the end of the stop block SP near substrate 1 into the second sub-substrate 13.

[0133] When a portion of the stop block SP extends into the substrate 1, and the end of the stop block SP away from the substrate 1 is located in another film layer on the side of the stop block SP away from the substrate 1, forming the stop block SP on the substrate 1 includes: forming a stop block embedding layer EL on the substrate 1, embedding the stop block SP in the stop block embedding layer EL, and a portion of the stop block SP extending into the substrate 1. See also... Figure 6 The process of forming a stop block embedding layer EL on substrate 1 includes steps S121 to S123.

[0134] S121. A stop block defining layer DF is formed on substrate 1.

[0135] For example, there is no strict limit on the number of film layers included in the stop block defining layer DF. The stop block defining layer DF may include only a single film layer or multiple film layers that are adjacent to each other.

[0136] For example, see Figure 9In (a), the stop block defining layer DF may consist only of a second stacked structure LS2 located on one side of the substrate 1. The second stacked structure LS2 includes at least one (e.g., multiple) insulating layers 31 and at least one (e.g., multiple) sacrificial layers 32 alternately stacked. The sacrificial layers 32 can be removed by a subsequent process to provide space for forming gate lines. In this case, forming the stop block defining layer DF includes forming the second stacked structure LS2 on the substrate 1. Specifically, the second stacked structure LS2 can be formed by a thin film deposition process such as CVD, PVD, or ALD. The material of the second stacked structure LS2 can be the same as the material of the first stacked structure LS1. In the second stacked structure LS2, the material of the insulating layer 31 can be silicon oxide, and the material of the sacrificial layer 32 can be silicon nitride.

[0137] For example, see Figure 10 In (a), the stop block defining layer DF may consist only of a first etch barrier layer 21. The first etch barrier layer 21 is located on one side of the substrate 1. During subsequent fabrication, the first etch barrier layer 21 protects the film layers located away from the substrate 1, preventing damage to these film layers from the etching process. When the stop block defining layer DF includes the first etch barrier layer 21, forming the stop block defining layer DF includes forming the first etch barrier layer 21 on the substrate 1. Specifically, the first etch barrier layer 21 can be formed by a thin film deposition process such as CVD, PVD, or ALD, and the material of the first etch barrier layer 21 can be polycrystalline silicon.

[0138] For example, see Figure 11A The stop block defining layer DF may include both a first etch barrier layer 21 and a second stacked structure LS2, wherein the second stacked structure LS2 is located on the side of the first etch barrier layer 21 away from the substrate 1. In this case, forming the stop block defining layer DF includes sequentially forming the first etch barrier layer 21 and the second stacked structure LS2 on the substrate 1. The materials and processes for forming the first etch barrier layer 21 and the second stacked structure LS2 are the same as described above and will not be repeated here.

[0139] It should be noted that when the stop block defining layer comprises only a portion of the multiple layers disposed on one side of the substrate in the semiconductor structure, the layers included in the semiconductor structure but not in the stop block defining layer still need to be fabricated during the semiconductor structure fabrication process. For example, a first etch stop layer and a second stacked structure are disposed on the substrate, with the first etch stop layer located on the side of the second stacked structure closer to the substrate. The stop block defining layer only includes the first etch stop layer, meaning that part of the stop block extends into the first etch stop layer but not into the second stacked structure. In this case, the process of forming the stop block defining layer includes forming the first etch stop layer on the substrate. After the stop block defining layer is fabricated, the semiconductor structure fabrication method still needs to include forming the second stacked structure.

[0140] For the sake of simplicity, the stop block defining layer will be described below as including both the first etch barrier layer and the second stacked structure (i.e., the structure of the stop block defining layer is as follows). Figure 11A Taking the example shown, the solution of this disclosure will be explained. When the structure of the stop block delimitation layer is as follows... Figure 9 (a) or Figure 10 As shown in (a), the stop block SP and the stop block embedding layer EL embedded with the stop block SP can also be formed by the following preparation method.

[0141] S122. A groove is formed on the side of the stop block defining layer away from the substrate, and the bottom of the groove extends into the substrate.

[0142] For example, see Figure 11A Similarly, at least one (e.g., multiple) grooves GR can be formed on the surface of the stop block defining layer DF away from the substrate 1 by an etching process. The cross-section of the groove GR along the direction of the stacking of each film layer in the substrate 1 is rectangular. In other examples, the cross-section of the groove GR can also be other shapes, such as positive direction, trapezoid, inverted trapezoid, etc.

[0143] S123. Embed the stop block in the groove GR.

[0144] For example, the method steps for embedding the stop block SP in the groove GR on the stop block defining layer DF are the same as the aforementioned steps S1121~S1122, and will not be repeated here. The material of the stop block can be carbon or tungsten, etc.

[0145] For example, according to the above method steps S121~S123, Figure 9 The structure of the stop block embedding layer EL, which is formed by the stop block delimiting layer DF shown in (a), and the stop block SP is embedded in it, is as follows: Figure 9 As shown in (b), the thickness of the stop block SP ranges from 550 nm to 1000 nm along the Z direction. Figure 10The structure of the stop block embedding layer EL, which is formed by the stop block delimiting layer DF shown in (a), and the stop block SP is embedded in it, is as follows: Figure 10 As shown in (b), the thickness of the stop block SP ranges from 200 nm to 400 nm along the Z direction. Figure 11A The structure of the stop block embedding layer EL, which is formed by the stop block delimiting layer DF and contains the stop block SP, is shown below. Figure 11B As shown, along the Z direction, the thickness of the stop block SP ranges from 550 nm to 1000 nm.

[0146] For example, see Figure 11B When the stop block defining layer DF includes a second stacked structure LS2, the layer furthest from the substrate 1 in the formed second stacked structure LS2 is an insulating layer 31 (hereinafter referred to as the protective insulating layer). Thus, during the planarization of the stop material layer ML to form the stop block SP, the protective insulating layer can protect the sacrificial layer 32, which is in contact with the surface closest to the substrate 1. This prevents the thickness of the gate layer formed by replacing the sacrificial layer 32 in subsequent processes from being uneven with the thickness of other gate layers due to the thinning of the sacrificial layer 32 during the planarization process, thereby avoiding adverse effects on structural performance. After the planarization process, the insulating protective layer can be completely removed, or some may remain. The remaining insulating protective layer, on the surface furthest from the substrate 1, is a flat surface. The following explanation uses the example of a partially remaining insulating protective layer after the planarization process.

[0147] S22, forming the first layered structure.

[0148] For example, see Figure 11C The first stacked structure LS1 is located on the side of the stop block SP away from the substrate 1, and includes multiple insulating layers 31 and multiple sacrificial layers 32 stacked alternately.

[0149] For example, see Figure 11C In the second stacked structure LS2, the layer closest to the substrate 1 is an insulating layer 31, and the thickness of this insulating layer 31 is greater than the thickness of the other insulating layers 31 in the second stacked structure LS2. The first stacked structure LS1 and the second stacked structure LS2 are referred to as the stacked structure LS. The edges of the stacked structure LS can be stepped. The fabrication process and material selection for the stacked structure LS can be found in step S21 above. (Continue to see...) Figure 11C The region corresponding to the step-like structure formed by the stacked structure LS on substrate 1 can be called step region B, the region corresponding to the stacked structure LS without the step-like structure can be called storage region A, and the region corresponding to the rest of the substrate 1 can be called peripheral region C.

[0150] For example, see Figure 11DAfter forming the stepped structure, the method for fabricating the semiconductor structure may further include forming an insulating capping layer 5 covering the stacked structure LS, wherein the insulating capping layer 5 is located on the side of the stacked structure LS away from the substrate 1. The fabrication process and materials of the insulating capping layer 5 can also be found in the aforementioned step S21, and will not be repeated here.

[0151] S32, etching to form the first channel hole.

[0152] For example, see Figure 11E The first channel hole CH1 can be formed using room temperature (20-80℃) / low temperature (<-30℃) etching processes, dry / wet etching processes, etc. The first channel hole CH1 penetrates the first stacked structure LS1 and extends into the stop block SP. The etching selectivity of the stop block SP is less than the etching selectivity of the first stacked structure LS1. Figure 11E In the semiconductor structure shown, since the material of the second stacked structure LS2 is the same as that of the first stacked structure LS1, the second stacked structure LS2 and the first stacked structure LS1 have the same etch selectivity. Correspondingly, the etch selectivity of the stop block SP is also less than that of the stacked structure LS. For example, the material of the stop block SP (i.e., the stop material layer ML) can be carbon or tungsten. Similarly, when etching to form the first channel hole CH1, the placement of the stop block SP can also ensure that the etching stops well within the stop block SP, reducing the risk of over-etching when forming the first channel hole CH1.

[0153] For example, see Figure 11E The first channel hole CH1 extends into a portion of the stop block SP, with spacing maintained between it and the sidewall of the stop block SP. This arrangement also helps reduce the risk of over-etching and improves the uniformity of the formed first channel hole CH1.

[0154] S42. Remove the stop block SP to form a second channel hole.

[0155] For example, see Figure 11F When the material of the stop block SP is tungsten, the stop block SP can be removed by an etching process (e.g., wet etching) to form the second channel hole CH2.

[0156] When the stop block SP is made of carbon, it can be removed by heat treatment to form the second channel hole CH2. The specific method of heat treatment is as described above and will not be repeated here.

[0157] In some embodiments, see Figure 2 The method for preparing the semiconductor structure also includes steps S52 to S92.

[0158] Step S52 (forming the channel structure) is the same as step S51 described above, and will not be repeated here. The semiconductor structure obtained after step S52 is as follows: Figure 11G As shown.

[0159] For example, see Figure 11H After step S52, the method for fabricating the semiconductor structure may further include: forming at least one (e.g., multiple) virtual channel vias (not shown) in the step region B that penetrate the stacked structure LS and partially extend into the substrate 1; forming the virtual channel structure 4'; and forming the first capping layer 6 (see [reference]). Figure 11I ), forming at least one (e.g., multiple) isolation trenches U (see Figure 11I The preparation methods for each structure can be found above, and will not be repeated here.

[0160] For example, see Figure 11J After forming multiple isolation trenches U, the method for fabricating this semiconductor structure may further include forming multiple gate lines, which constitute multiple gate conductive layers 33. The multiple gate conductive layers 33 and insulating layers 31 corresponding to the location of the first stacked structure constitute a first memory stacked structure D1, and the multiple gate conductive layers 33 and insulating layers 31 corresponding to the location of the second stacked structure constitute a second memory stacked structure D2. The specific method for forming multiple gate lines is as described in steps SS10~S30, and will not be repeated here.

[0161] For example, see Figure 11J The method for fabricating this semiconductor structure can also form a slot structure Ux, form at least one (e.g., one) through-silicon contact structure 71 and at least one (e.g., one) source contact structure 72 in the peripheral region C, form multiple contacts 73, and form at least one (e.g., multiple) channel conductive structure 74. The fabrication methods for each structure can also be found above, and will not be repeated here.

[0162] S62. Remove substrate 1 to expose the portion of the channel structure 4 that extends into substrate 1.

[0163] Specifically, step S62 is the same as step S61 described above, and will not be repeated here. The semiconductor structure obtained after step S62 is as follows: Figure 11K As shown.

[0164] S72. Remove the storage function layer 41 in the exposed channel structure 4 to expose a portion of the channel layer 42.

[0165] For example, in this step, the storage function layer 41 in the exposed channel structure 4 can be removed by dry / wet etching.

[0166] For example, when the substrate is a single-layer silicon substrate or the substrate includes a first sub-substrate, a release layer, and a second sub-substrate, and the second stacked structure is disposed on the substrate and in contact with the second sub-substrate, and the channel structure extends into the second sub-substrate near the end of the substrate, after removing the single-layer silicon substrate or removing the first sub-substrate, the release layer, and the second sub-substrate to expose the portion of the channel structure extending into the second sub-substrate, the storage functional layer in the exposed channel structure can be removed by wet etching. Because the protective insulating layer in the second stacked structure is relatively thick, etching can be stopped within the protective insulating layer, avoiding damage to other film layers in the second stacked structure.

[0167] For example, see Figure 9 In (b), when the substrate includes a first sub-substrate 11, a release layer 12, a second sub-substrate 13, and a third etch barrier layer 14, the second stacked structure LS2 is disposed on the substrate 1 and in contact with the third etch barrier layer 14. When the channel structure extends into the second sub-substrate 13 near the end of the substrate, after removing the first sub-substrate 11, the release layer 12, and the second sub-substrate 13 to expose the portion of the channel structure extending into the second sub-substrate 13, the storage functional layer in the exposed channel structure can be removed by wet etching. At the same time, since the material of the third etch barrier layer 14 is all oxide, the third etch barrier layer 14 will also be etched. After removing the storage functional layer in the exposed channel structure, the third etch barrier layer 14 may still remain or may be completely removed; there are no strict limitations on this. When the third etch barrier layer 14 is completely removed, since the protective insulating layer 31 in the second stacked structure LS2 is relatively thick, the etching can also stop in the protective insulating layer 31, reducing the risk of damage to other film layers in the second stacked structure LS2. See 9(c) in the figure for an example where the third etch barrier layer 14 is completely removed.

[0168] For example, see Figure 10 (b) or Figure 11LWhen the substrate includes a first sub-substrate, a release layer, a second sub-substrate, and a third etch barrier layer, and the semiconductor structure also includes a first etch barrier layer 21, the second stacked structure LS2 is disposed on the substrate and in contact with the first etch barrier layer 21. The end of the channel structure 4 near the substrate penetrates the third etch barrier layer 14 and extends into the second sub-substrate. After removing the first sub-substrate, the release layer, and the second sub-substrate, exposing the portion of the channel structure extending into the second sub-substrate, the storage functional layer and the third etch barrier layer in the exposed channel structure can be removed by wet etching. Since the material of the first etch barrier layer 21 is different from that of the storage functional layer 41, it has a different etch selectivity than the storage functional layer 41. When removing the storage functional layer 41 in the exposed channel structure 4, the etching can be stopped at the first etch barrier layer 21, which is beneficial to improving the uniformity of the etching process. At the same time, it can also protect the stacked structure located on the side of the first etch barrier layer 21 away from the substrate.

[0169] S82, At least the exposed portion of the channel layer 42 is ion-doped.

[0170] For example, see Figure 11M Ion doping of at least the exposed portion of the channel layer 42 includes ion doping of at least the portion of the channel layer 42 located between the doping site and the bottom end, wherein the doping site corresponds to the sacrificial layer 32 closest to the substrate in the semiconductor structure. When only the first stacked structure is provided in the semiconductor structure, the doping site corresponds to the sacrificial layer closest to the substrate in the first stacked structure, that is, it corresponds to the gate conductive layer 33 closest to the second sub-channel structure 420 in the first memory stacked structure D1; when the semiconductor structure has both the first stacked structure and the second stacked structure, the doping site corresponds to the sacrificial layer closest to the substrate in the second stacked structure, that is, it corresponds to the gate conductive layer 33 closest to the second sub-channel structure 420 in the second memory stacked structure D2.

[0171] S92, forming the source layer.

[0172] Specifically, step S92 is the same as step S91 described above, and will not be repeated here.

[0173] For example, after step S92, the method for fabricating the semiconductor structure may further include: forming an interlayer dielectric layer 102, forming a first source contact A1, forming a second source contact A2, forming a peripheral contact A3, forming a metal interconnect layer 103, forming a barrier layer 104, etc. The method steps for forming each structure after step S92 are consistent with the method steps for forming each structure in the foregoing embodiments, and the beneficial effects are similar. The formed semiconductor structure is as follows: Figure 11M As shown.

[0174] Furthermore, by way of example, in Figure 9 Based on the stop block SP and stop block embedding layer EL structure shown in (b), the semiconductor structure prepared according to the aforementioned preparation method is as follows: Figure 9 As shown in (c); in Figure 10 Based on the stop block SP and stop block embedding layer EL structure shown in (b), the semiconductor structure prepared according to the aforementioned preparation method is as follows: Figure 10 As shown in (c) in the figure.

[0175] For example, when the end of the stop block near the substrate extends into the substrate, the end of the stop block away from the substrate extends into other film layers located on the side of the substrate near the first stacked structure (e.g., extending into the etching barrier layer; the specific arrangement of the stop block is as follows). Figure 10 As shown in (b) in the figure, the ion implantation window is as follows: Figure 12 As shown in the diagram. L4 is the line connecting the corner of the channel layer near the doped site and the doped site; L5 is the line connecting the edge of the etch barrier layer near the channel layer and the doped site when an etch barrier layer is present in the semiconductor structure; and L6 is the line connecting the edge of the channel layer furthest from the doped site in an adjacent channel structure and the doped site. When an etch barrier layer is present in the semiconductor structure, the angle between L1 and L2 is α3, and the size of α3 is the ion implantation window size, approximately 12°. When no etch barrier layer is present in the semiconductor structure, the angle between L4 and L6 is α4, and the size of α4 is the ion implantation window size, approximately 18°. Similar to the aforementioned method, this stop block arrangement reduces the risk of over-etching during channel hole formation while ensuring the formed semiconductor structure has a reasonable ion implantation window size, which is beneficial for improving the conductivity stability of the channel structure through ion implantation. The first channel hole extends into the stop block, with gaps left between it and the sidewall of the stop block. This allows the channel layer at the corner to block ion implantation at other locations to have roughly the same area of ​​obstruction, resulting in a more uniform ion implantation window size, which helps improve the uniformity of ion implantation.

[0176] When the stop block is set as follows Figure 11B As shown, the ion implantation window formed also has the aforementioned beneficial effects, which will not be repeated here.

[0177] This disclosure provides a semiconductor structure according to some embodiments. This semiconductor structure can be fabricated using the fabrication method provided in any of the foregoing embodiments. A three-dimensional view of the fabricated semiconductor structure is shown below. Figure 1 As shown, a cross-sectional view of the semiconductor structure is as follows: Figure 7O , Figure 9 (c) Figure 10 (c) or Figure 11M As shown. For the sake of simplicity, the following will use... Figure 11M The semiconductor structure shown is used as an example for illustration, but it should be understood that the following descriptions apply to all the semiconductor structures described above in this disclosure.

[0178] For example, see Figure 11M The semiconductor structure includes a source layer 101, a first memory stack structure D1 disposed on one side of the source layer 101, and multiple channel structures 4. The arrangement of the source layer 101 is described above and will not be repeated here. The first memory stack structure D1 includes multiple gate conductive layers 33 and multiple insulating layers 31 stacked alternately. Referring to the previous description, the sacrificial layer 32 in the first stack structure D1 is divided into multiple sacrificial portions by a slot structure Ux. An interface layer and a gate conductive layer 33 are formed in the sacrificial gaps formed by removing the multiple sacrificial portions, resulting in the first memory stack structure D1. The gate conductive layer 33 includes multiple gate lines, and the insulating layer 31 includes multiple gate insulating layers. Specifically, the multiple gate conductive layers 33 and insulating layers 31 are stacked alternately along a first direction (i.e., the Z direction), the gate lines extend along a second direction (i.e., the X direction), and the multiple gate lines in the same gate conductive layer 33 are arranged along a third direction (i.e., the Y direction). Any two of the X, Y, and Z directions intersect each other (e.g., perpendicularly).

[0179] For example, see Figure 11M Each channel structure 4 is coupled to a gate line to form a memory cell. Multiple memory cells are connected together through a channel structure 4 to form a memory cell string. The first memory stack structure and the multiple channel structures 4 form multiple memory cell strings. The multiple memory cell strings are arranged in an array to form a memory string array layer. Each memory cell can be equivalent to a transistor, which is coupled to a gate line and turns on or off under the control of the gate line.

[0180] For example, see Figure 11M In a string of gate lines, at least one gate line located at the bottom along the Z-direction (e.g., one) is constructed as a source selection gate, controlling the connection between the source channels and the source end of the memory cell string; at least one gate line located at the top along the Z-direction (e.g., one) is constructed as a drain selection gate, controlling the connection between the drain channels and the source end of the memory cell string; the gate lines in the middle are constructed as multiple word lines. By writing different voltages onto the word lines, data writing, reading, and erasing of individual memory cells in the memory cell string can be accomplished.

[0181] In some embodiments, see Figure 1The semiconductor structure may also include an array interconnect layer. The array interconnect layer may be coupled to a memory cell string. The array interconnect layer may include the drain (i.e., bit line) of the memory cell string, which may be coupled to the semiconductor channel of each transistor in at least one memory cell string.

[0182] The array interconnect layer may include one or more interlayer insulating layers (not shown in the figure), and may also include multiple interconnect contacts insulated from each other by these interlayer insulating layers. These interconnect contacts may include, for example, bit line contacts coupled to bit lines; and drain select gate contacts coupled to drain select gates. The array interconnect layer may also include multiple interconnect lines, such as bit lines, and word line interconnects coupled to word lines. The interconnect lines and interconnect contacts may be made of conductive materials, such as tungsten, cobalt, copper, aluminum, and combinations of one or more metal silicides, or other suitable materials. The interlayer insulating layers may be made of insulating materials, such as silicon oxide, silicon nitride, and combinations of one or more high-dielectric-constant insulating materials, or other suitable materials.

[0183] For example, see [link to previous article] Figure 11M The channel structure 4 includes a first sub-channel structure 410 and a second sub-channel structure 420 that are in contact with each other. The first sub-channel structure 410 is located on the side of the second sub-channel structure 420 away from the source layer 101 and penetrates the first memory stack structure D1. The end of the second sub-channel structure 420 away from the first sub-channel structure 410 is in contact with the source layer 101. For the first sub-channel structure 410, its critical dimension is the average value of its dimensions in one direction (i.e., the average size). For the second sub-channel structure 420, its critical dimension is also the average value of its dimensions in one direction (i.e., the average size). For example, along the thickness direction perpendicular to the first memory stack structure D1 (i.e., along the X or Y direction), the critical dimension of the first sub-channel structure 410 is smaller than the critical dimension of the second sub-channel structure 420. That is, the orthographic projection of the first sub-channel structure 410 onto the source layer 101 is included within the orthographic projection of the second sub-channel structure 420 onto the source layer 101. For example, see... Figure 11M There is a gap between the edge of the first sub-channel structure 410 projected onto the source layer 101 and the edge of the second sub-channel structure 420 projected onto the source layer 101. The specific arrangement of the first sub-channel structure 410 and the second sub-channel structure 420 can be found in the foregoing content, and will not be repeated here.

[0184] For example, see Figure 11MThe semiconductor structure also includes a second memory stack structure D2 disposed between the source layer 101 and the first memory stack structure D1. The second memory stack structure D2 includes at least one (e.g., two) gate conductive layers 33 and at least one (e.g., multiple) insulating layers 31, and a second sub-channel structure 420 penetrates the second memory stack structure D2. The specific configuration of the second memory stack structure D2 can be found in the foregoing description and will not be repeated here. When the semiconductor structure includes both the first memory stack structure D1 and the second memory stack structure D2, the first memory stack structure D1 may include at least one (e.g., one) drain select gate and multiple word lines, while the second memory stack structure D2 may include two source select gates. When one of the multiple drain select gates fails, the other drain select gates can still control the on / off state of the memory cell string drain channels, improving the reliability of the device. Based on this, since the second sub-channel structure 420 penetrates the second memory stack structure D2, and the first sub-channel structure 410 and the second sub-channel structure 420 are in contact, the layer furthest from the source layer 101 in the second memory stack structure D2 is set as an insulating layer 31. This allows the corner formed by the contact between the first sub-channel structure 410 and the second sub-channel structure 420 to be located on the side of the source selection gate furthest from the source layer 101. Thus, during ion implantation, the channel layer 42 in the end of the second sub-channel structure 420 near the first sub-channel structure 410 can be prevented from blocking ion implantation, resulting in a larger ion implantation window and a more uniform ion implantation effect, which is beneficial to improving the conductivity stability of the channel structure 4.

[0185] For example, see Figure 11M In the first memory stack structure D1, the thickness of the first insulating layer 311 is greater than the thickness of the other insulating layers 31. The first insulating layer 311 is the insulating layer 31 in the first memory stack structure D1 that contacts the second memory stack structure D2. For example, the thickness of the first insulating layer 311 is 3 to 5 times the thickness of the other insulating layers 31 in the first memory stack structure D1. This thickness setting allows the corner formed by the contact between the first sub-channel structure 410 and the second sub-channel structure 420 to have a certain distance (hereinafter referred to as the reserved distance) from the gate line closest to the source layer in the first memory stack structure D1. The reserved distance can reduce the risk of damage to the first stack structure or the film layers in the first memory stack structure D1 when removing the stop block and forming the corresponding second sub-channel structure 420 in the second channel hole. The specific setting of the first insulating layer 311 in the first memory stack structure D1 can be found in the foregoing content, and will not be repeated here.

[0186] For example, see Figure 11MThe semiconductor structure also includes a first etch barrier layer 21, wherein the first etch barrier layer 21 is located on the side of the second memory stack structure D2 near the source layer 101, and the second sub-channel structure 420 penetrates the first etch barrier layer 21. The specific arrangement of the first etch barrier layer 21 can be found in the foregoing content, and will not be repeated here.

[0187] For example, when the semiconductor structure is as follows Figure 7O As shown, the second sub-channel structure 420 is entirely located within the source layer 101. That is, during the fabrication of the semiconductor structure, the stop block is entirely disposed within the substrate, thereby enabling the formation of the second sub-channel structure 420 entirely located within the source layer 101 through subsequent fabrication processes. The specific arrangement of the second sub-channel structure 420 can be found in the foregoing description and will not be repeated here.

[0188] For example, when the semiconductor structure is as follows Figure 7O As shown, the semiconductor structure also includes a second etch barrier layer 22, wherein the second etch barrier layer 22 is located on the side of the first memory stack structure D1 near the source layer 101.

[0189] For example, see Figure 11M The semiconductor structure also includes an insulating capping layer 5 and a plurality of contacts 73 extending along the Z direction and penetrating the insulating capping layer 5, each contact 73 being coupled to a gate line. The plurality of contacts 73 may include at least one (e.g., one) drain select gate contact, at least one (e.g., one) source select gate contact, and a plurality of word line contacts. Specifically, the drain select gate contacts are coupled to each other, the source select gate contacts are coupled to each other, and the word line contacts are coupled to each other. The specific arrangement of the insulating capping layer 5 and the plurality of contacts 73 can be found in the foregoing description and will not be repeated here.

[0190] For example, see Figure 11M Along the X direction, the semiconductor structure can be divided into a memory region A, a peripheral region C, and a step region B located between memory region A and peripheral region C. Memory region A contains the aforementioned multiple memory cell strings. A first memory stack structure D1 is provided in both memory region A and step region B, wherein the first memory stack structure D1 located in step region B is a step-shaped structure. Furthermore, step region B also contains at least one (e.g., multiple) virtual channel structures 4' and channel structures 4, and peripheral region C contains at least one (e.g., one) through-silicon contact structure 71 and at least one (e.g., one) source contact structure 72. The specific arrangements of the virtual channel structure 4', through-silicon contact structure 71, and source contact structure 72 can be found in the foregoing description and will not be repeated here.

[0191] For example, see Figure 11MThe semiconductor structure may also include a first capping layer 6, a channel conductive structure 74, an interlayer dielectric layer 102, a first source contact A1, a second source contact A2, a peripheral contact A3, a metal interconnect layer 103, a connecting pad 103', a barrier layer 104, and other film layer structures. The specific configuration of each of the above film layer structures can be found in the foregoing content, and will not be repeated here.

[0192] This disclosure provides a three-dimensional memory in some embodiments, which may include the semiconductor structure provided in any of the above embodiments. Furthermore, the three-dimensional memory may also include peripheral circuitry coupled to the semiconductor structure, the coupling method being bonding or the like.

[0193] The peripheral circuitry is configured to control and sense the semiconductor structure. The peripheral circuitry can be any suitable digital, analog, and / or mixed-signal control and sensing circuitry used to support the operation of the three-dimensional memory, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry may also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and programmable logic devices (PLDs)) or memory circuitry (e.g., static random access memory (SRAM)).

[0194] This disclosure provides a storage system in some embodiments that may include the three-dimensional memory provided in any of the above embodiments. Furthermore, the storage system may also include a controller coupled to the three-dimensional memory to control the storage of data in the three-dimensional memory.

[0195] The storage system can be integrated into various types of storage devices, for example, within the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system can be applied to and packaged into different types of electronic products, such as mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0196] In some embodiments, see Figure 13 The storage system 10 includes a controller 500 and a three-dimensional memory 300, and the storage system 10 can be integrated into a memory card.

[0197] Among them, memory cards include any one of the following: PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0198] In other embodiments, see Figure 14 The storage system 10 includes a controller 500 and multiple three-dimensional storage devices 300, and the storage system 10 is integrated into a solid state drive (SSD).

[0199] In some embodiments of the storage system 10, the controller 500 is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0200] In other embodiments, the controller 500 is configured to operate in a high duty cycle environment using SSDs or eMMCs, which are used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0201] In some embodiments, the controller 500 may be configured to manage data stored in the 3D memory 300 and to communicate with an external device (e.g., a host). In some embodiments, the controller 500 may also be configured to control the operation of the 3D memory 300, such as read, erase, and program operations. In some embodiments, the controller 500 may also be configured to manage various functions relating to data stored or to be stored in the 3D memory 300, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, the controller 500 is also configured to process error correction codes relating to data read from or written to the 3D memory 300.

[0202] Of course, the controller 500 can also perform any other suitable functions, such as formatting the three-dimensional memory 300. For example, the controller 500 can communicate with external devices (e.g., a host) through at least one of various interface protocols.

[0203] It should be noted that interface protocols include USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, and PCI High Speed ​​(PCI) protocol. E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, Firewire protocol, or at least one of these protocols.

[0204] It is understood that the beneficial effects of the semiconductor structure, three-dimensional memory and storage system provided in the above embodiments of this disclosure can be referred to the beneficial effects of the relevant film layers and structures in the semiconductor structure preparation method described above, and will not be repeated here.

[0205] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A stop block is formed on a substrate, the substrate comprising a first sub-substrate, a release layer and a second sub-substrate stacked sequentially, wherein forming the stop block on the substrate comprises: forming a stop block on the second sub-substrate, at least a portion of the stop block extending into the second sub-substrate, and a gap being left between the stop block and the release layer; A first stacked structure is formed, the first stacked structure being located on the side of the stop block away from the substrate, comprising a plurality of alternately stacked insulating layers and a plurality of sacrificial layers; The etching process forms a first channel hole that penetrates the first stacked structure and extends into the stop block. The etching selectivity of the stop block is less than that of the first stacked structure. Remove the stop block to form a second channel hole; the size of the first channel hole is smaller than the size of the second channel hole along the thickness direction perpendicular to the first stacked structure; A storage functional layer and a channel layer are sequentially formed within the channel hole to obtain a channel structure, wherein the channel hole includes a first channel hole and a second channel hole; Remove the substrate to expose the portion of the channel structure that extends into the substrate; Remove the storage function layer from the exposed channel structure to expose a portion of the channel layer; A source layer is formed, and the channel layer is in contact with the source layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, Forming a stop block on the substrate includes: A stop block embedding layer is formed on the substrate, in which the stop block is embedded, and a portion of the stop block extends into the substrate.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, Forming a stop block embedding layer on one side of the substrate includes: A stop block defining layer is formed on the substrate; A groove is formed on the side of the stop block defining layer away from the substrate, and the bottom of the groove extends into the substrate; The stop block is embedded in the groove.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, Forming a stop block delimiting layer on the substrate includes: A second stacked structure is formed on the substrate, the second stacked structure comprising at least one insulating layer and at least one sacrificial layer alternately stacked; and / or, a first etch barrier layer is formed on the substrate; The second stacked structure is located on the side of the first etch barrier layer away from the substrate.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, In the second stacked structure, the layer furthest from the substrate is an insulating layer.

6. The method for preparing a semiconductor structure according to claim 4, characterized in that, In the first stacked structure, the thickness of the first insulating layer is greater than the thickness of the other insulating layers, and the first insulating layer is the insulating layer in the first stacked structure that is in contact with the second stacked structure.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, Forming a stop block on the substrate includes: A groove is formed on the substrate; The stop block is embedded in the groove.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, Before the formation of the first layered structure, it also includes: A second etch barrier layer is formed, which is located on the side of the stop block away from the substrate.

9. The method for preparing a semiconductor structure according to claim 3, characterized in that, Embedding the stop block in the groove includes: A stop material layer is formed, the stop material layer covering the groove; The stop material layer is planarized to form the stop block; The stop block is located on the surface of the substrate and is flush with the edge of the groove away from the substrate.

10. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first channel hole extends into a portion of the stop block, with a gap between it and the sidewall of the stop block at all points.

11. The method for preparing a semiconductor structure according to claim 1, characterized in that, The substrate further includes a third barrier etching layer disposed on the side of the second sub-sub ...

12. The method for preparing a semiconductor structure according to claim 1, characterized in that, Removing the stop block to form the second channel hole includes: The second channel hole is formed by heat treatment; Alternatively, the second channel hole can be formed by etching.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that, Forming the second channel hole through heat treatment includes: An oxidizing agent is provided, which reacts chemically with the stop block to form a gaseous compound.

14. The method for preparing a semiconductor structure according to any one of claims 1 to 13, characterized in that, Before the source layer is formed, it also includes: At least the exposed portion of the channel layer is ion-doped.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that, Ion doping of at least the exposed portion of the channel layer includes: At least the portion of the channel layer located between the doping site and the bottom end is ion-doped, the doping site corresponding to the sacrificial layer closest to the substrate in the semiconductor structure.

16. A semiconductor structure, characterized in that, include: Source layer; A first memory stack structure, located on one side of the source layer, includes multiple gate conductive layers and multiple insulating layers stacked alternately; A channel structure, comprising a first sub-channel structure and a second sub-channel structure in contact with each other, wherein the first sub-channel structure is located on the side of the second sub-channel structure away from the source layer; the channel structure includes a storage function layer and a channel layer. The first sub-channel structure penetrates the first memory stack structure. The end of the second sub-channel structure away from the first sub-channel structure contacts the source layer. The channel layer of the second sub-channel structure is exposed from the memory functional layer and contacts the source layer. The channel layer is at least partially located within the source layer, and the source layer contacts the memory functional layer. Wherein, along the thickness direction perpendicular to the first storage stack structure, the size of the first sub-channel structure is smaller than the size of the second sub-channel structure, the size of the channel layer of the second sub-channel structure located in the source layer is larger than the size of the channel layer of the first sub-channel structure, and the size of the portion of the channel layer of the second sub-channel structure exposed from the storage functional layer is larger than the size of the channel layer of the first sub-channel structure.

17. The semiconductor structure according to claim 16, characterized in that, There is a gap between the edge of the first sub-channel structure projected onto the source layer and the edge of the second sub-channel structure projected onto the source layer at all points.

18. The semiconductor structure according to any one of claims 16-17, characterized in that, Also includes: A second memory stack structure is disposed between the source layer and the first memory stack structure, the second memory stack structure including at least one gate conductive layer and at least one insulating layer; The second sub-channel structure extends through the second memory stack structure.

19. The semiconductor structure according to claim 18, characterized in that, In the second storage stack structure, the layer furthest from the source layer is an insulating layer.

20. The semiconductor structure according to claim 18, characterized in that, In the first storage stack structure, the thickness of the first insulating layer is greater than the thickness of the other insulating layers, and the first insulating layer is an insulating layer in the first storage stack structure that is in contact with the second storage stack structure.

21. The semiconductor structure according to claim 20, characterized in that, In the first storage stack structure, the thickness of the first insulating layer is 3 to 5 times the thickness of the other insulating layers.

22. The semiconductor structure according to claim 18, characterized in that, Also includes: A first etch barrier layer is located on the side of the second memory stack structure near the source layer; The second sub-channel structure penetrates the first etch barrier layer.

23. The semiconductor structure according to any one of claims 16-17, characterized in that, The second sub-channel structure is entirely located within the source layer.

24. The semiconductor structure according to claim 23, characterized in that, Also includes: The second etch barrier layer is located on the side of the first memory stack structure near the source layer.

25. A three-dimensional memory, characterized in that, The semiconductor structure included in any one of claims 16 to 24 further includes: Peripheral circuitry coupled to the semiconductor structure.

26. A storage system, characterized in that, Including the three-dimensional memory as described in claim 25, further comprising: A controller, coupled to the three-dimensional memory, controls the storage of data in the three-dimensional memory.

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