Three-dimensional memory, methods of making three-dimensional memory, and three-dimensional memory systems

Abstract

The application provides a three-dimensional memory, a method for manufacturing the three-dimensional memory, and a three-dimensional memory system. The method for manufacturing the three-dimensional memory comprises: forming a stack structure by alternately stacking dielectric layers and sacrificial layers on a substrate; removing at least a part of the sacrificial layers to form gaps, and filling the gaps with gate layers; forming preset holes on a side of the stack structure away from the substrate, wherein at least a part of the preset holes is in contact with the gate layers; forming a first conductive layer connected with the gate layers in the preset holes, and forming a filling layer in the remaining space of the preset holes; and forming a fourth conductive layer connected with the first conductive layer on a side of the filling layer away from the substrate.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and manufacturing, and more specifically, to the structure, fabrication method, and system of a three-dimensional memory (3D NAND). Background Technology

[0002] 3D NAND flash memory is a type of flash memory device constructed by stacking memory cells in three dimensions. The structure of a 3D NAND flash memory typically includes a stacked structure with storage functionality and an external circuit structure that interconnects with each other. The stacked structure can be formed by alternating gate layers and dielectric layers. Generally, conductive structures are needed to bring out word lines to achieve electrical connections between the memory cells and the external circuitry.

[0003] It should be understood that the content described in the background section is only for the purpose of helping to understand the technical solutions disclosed in this application, and is not necessarily prior art before the filing date of this application. Summary of the Invention

[0004] This application provides a method for fabricating a three-dimensional memory. The method includes: alternately stacking dielectric layers and sacrificial layers on a substrate to form a stacked structure; removing at least a portion of the sacrificial layers to form gaps, and filling the gaps with gate layers; forming a predetermined via on the side of the stacked structure away from the substrate, wherein at least a portion of the predetermined via contacts the gate layer; forming a first conductive layer connected to the gate layer within the predetermined via, and forming a filling layer in the remaining space of the predetermined via; and forming a fourth conductive layer connected to the first conductive layer on the side of the filling layer away from the substrate.

[0005] In one embodiment, the gate layer comprises multiple layers, each of which is alternately stacked with the dielectric layer, and the preset via contacts at most one of the gate layers.

[0006] In one embodiment, after the gate layer is formed, the dielectric layer and the gate layer are alternately stacked to form a first stacked structure, the portion of the dielectric layer and the sacrificial layer that has not been removed are alternately stacked to form a second stacked structure, and the first stacked structure and the second stacked structure are arranged along a first direction, wherein the first direction includes a direction perpendicular to the stacking direction of the dielectric layer and the gate layer.

[0007] In one embodiment, the method of forming the preset hole includes: forming a first portion of the preset hole on the side of the second stacked structure away from the substrate; and forming a second portion of the preset hole on the side of the first portion of the preset hole close to the substrate, wherein the second portion of the preset hole is in contact with the gate layer.

[0008] In one embodiment, before forming the second portion of the preset hole, the method further includes forming an isolation layer on the sidewall of the first portion of the preset hole.

[0009] In one embodiment, the step of forming the fourth conductive layer includes: forming a third conductive layer connected to the first conductive layer on the side of the fill layer away from the substrate; and removing the portion of the third conductive layer that is not in contact with the fill layer to form the fourth conductive layer.

[0010] In one embodiment, the step of forming a first conductive layer connected to the gate layer within the preset hole further includes forming a second conductive layer on the side of the first stacked structure and the second stacked structure away from the substrate.

[0011] In one embodiment, the distance from the side of the third conductive layer closest to the substrate to the substrate is less than the distance from the side of the second conductive layer closest to the substrate to the substrate. The method further includes removing the second conductive layer to expose a first side of the first stacked structure and the second stacked structure, wherein the side of the fourth conductive layer furthest from the substrate is coplanar with the first side.

[0012] In one embodiment, the method further includes forming a conductive portion connected to the fourth conductive layer on the side of the fourth conductive layer away from the substrate.

[0013] In one embodiment, the method further includes forming voids within the filling layer.

[0014] In one embodiment, the material forming the filler layer includes an insulating material.

[0015] This application also provides a three-dimensional memory, comprising: a semiconductor layer; a stacked structure located on the semiconductor layer, including a gate layer; and a conductive structure located on the side of the stacked structure away from the semiconductor layer, including a first conductive layer, a fill layer, and a fourth conductive layer, wherein the first conductive layer is connected to the gate layer and the fourth conductive layer respectively, the first conductive layer and the fourth conductive layer cover the fill layer, and the fourth conductive layer is located on the side of the fill layer away from the semiconductor layer.

[0016] In one embodiment, the gate layer comprises multiple layers, the stacked structure further includes dielectric layers alternately stacked with each of the gate layers, and the first conductive layer contacts at most one of the gate layers.

[0017] In one embodiment, the first conductive layer includes a first portion located between the two dielectric layers and connected to the gate layer, and a second portion located between the fill layer and the stacked structure and connected to the first portion, wherein the first portion of the first conductive layer and the fourth conductive layer surround the fill layer.

[0018] In one embodiment, the three-dimensional memory further includes an isolation layer located between the stacked structure and the second portion of the first conductive layer, and covering the portion of the second portion of the first conductive layer near the stacked structure.

[0019] In one embodiment, the three-dimensional memory includes a core region and a dummy step region. The core region has a channel structure penetrating the stacked structure, the dummy step region has a dummy channel structure penetrating the stacked structure, and the conductive structure is located in the dummy step region, wherein the critical dimension of the dummy channel structure is smaller than the critical dimension of the conductive structure.

[0020] In one embodiment, the three-dimensional memory further includes a conductive portion located on the side of the fourth conductive layer away from the substrate and connected to the fourth conductive layer.

[0021] In one embodiment, the three-dimensional memory further includes: a gate gap structure located on the side of the conductive structure near the dummy channel structure, and extending along the stacking direction of the dielectric layer and the gate layer, and along the arrangement direction of the core region and the dummy step region, respectively.

[0022] In one embodiment, the interior of the filling layer has voids.

[0023] In another aspect, this application provides a three-dimensional memory system, comprising: a three-dimensional memory as described in any of the above embodiments, wherein the three-dimensional memory includes a storage string for storing data; and a controller electrically connected to the three-dimensional memory and configured to control the operation of the storage string.

[0024] The method for fabricating the three-dimensional memory provided in this application can have at least one of the following beneficial effects:

[0025] The conductive structure formed according to some embodiments of this application connects the word line to the conductive part, thereby realizing the interconnection between the stacked structure with storage function and the external circuit.

[0026] According to some embodiments of this application, a conductive structure can be formed by filling, for example, a tungsten metal-coated insulating layer. Compared with a conductive structure formed by a single tungsten metal, this can improve the stress on the wafer and prevent defects introduced by stress.

[0027] According to some embodiments of this application, the effect of significantly increasing the landing window of the conductive part on the conductive structure can be achieved without significantly increasing costs. Attached Figure Description

[0028] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings:

[0029] Figure 1 A flowchart illustrating a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application is shown schematically;

[0030] Figures 2 to 11 This is a schematic diagram of the fabrication method of a three-dimensional memory according to an exemplary embodiment of this application;

[0031] Figure 12 This is a schematic diagram of the structure of a three-dimensional memory according to an exemplary embodiment of this application; and

[0032] Figure 13 This is a schematic diagram of a three-dimensional memory system according to an exemplary embodiment of this application. Detailed Implementation

[0033] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0034] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first stacked structure discussed herein may also be referred to as the second stacked structure, and the first conductive layer may also be referred to as the second conductive layer, and vice versa.

[0035] In the accompanying drawings, the thickness, dimensions, and shapes of the components have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. For example, the thickness of the second conductive layer shown in the drawings of this application is not proportional to actual production. Terms such as “approximately,” “about,” and similar terms used herein are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by those skilled in the art.

[0036] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0037] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0038] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0039] The features, principles and other aspects of this application are described in detail below.

[0040] The inventors of this application have discovered that in some exemplary embodiments, it is necessary to use conductive structures to bring out the word lines in the 3D NAND memory to achieve electrical connection between the memory cells and external circuits. These conductive structures are typically formed from a relatively thick conductive material (e.g., tungsten). When a thick conductive structure is formed using a single material, it can lead to large stress variations, severely deteriorating the stress state of the wafer and even causing defects such as cracks.

[0041] The inventors have also discovered that, in some exemplary embodiments, a conductive layer and an insulating layer can be used to form the conductive structure to reduce the stress effects caused by a single material forming a thicker conductive structure. In such a conductive structure, the insulating layer is located at the center of the conductive layer, and the conductive layer can form a ring surrounding the insulating layer. Since the insulating layer is non-conductive, during the formation of the conductive portion connecting the conductive structure and the external circuit, the conductive portion can only land on the ring-shaped conductive layer; the presence of the insulating layer obstructs the landing window of the conductive portion. In cases where the conductive layer deposition is insufficient, a portion of the conductive portion will land on the insulating layer, causing an increase in its contact resistance. Exemplarily, the above-mentioned conductive structure can be formed using, for example, tungsten metal and an oxide layer.

[0042] This application proposes a three-dimensional memory and a method for manufacturing the same, which can at least partially improve or solve the above-mentioned problems. It can reduce wafer stress and device defects caused by increased stress without significantly increasing costs, and can significantly increase the landing window of conductive parts on conductive structures.

[0043] Figure 1 This is a flowchart of a method 1000 for fabricating a three-dimensional memory according to an embodiment of this application. For example... Figure 1 As shown, this application provides a method 1000 for fabricating a three-dimensional memory, comprising:

[0044] Step S1100: Alternately stack dielectric layers and sacrificial layers on the substrate to form a stacked structure;

[0045] Step S1200: Remove at least a portion of the sacrificial layer to form a gap, and fill the gap with the gate layer;

[0046] Step S1300: A preset hole is formed on the side of the stacked structure away from the substrate, wherein at least a portion of the preset hole is in contact with the gate layer;

[0047] Step S1400: A first conductive layer connected to the gate layer is formed in the preset via, and a filling layer is formed in the remaining space of the preset via; and

[0048] In step S1500, a fourth conductive layer connected to the first conductive layer is formed on the side of the filling layer away from the substrate.

[0049] It should be understood that the steps shown in method 1000 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. Furthermore, some of the steps shown may be performed simultaneously or in a sequence different from the steps described. Figure 1 The execution is performed in the order shown.

[0050] Figures 2 to 11 This is a schematic diagram of the fabrication method 1000 of the three-dimensional memory according to an embodiment of this application. The following is in conjunction with... Figures 2 to 11 The above steps S1100 to S1500 are further described.

[0051] Step S1100: Dielectric layers and sacrificial layers are alternately stacked on the substrate to form a stacked structure.

[0052] like Figure 2As shown, in step S1100, a stacked structure 120' can be formed on the substrate 110. The stacked structure 120' can be formed by sequentially stacking a dielectric layer 130 and a sacrificial layer 140. In some embodiments, the material of the substrate 110 may include, for example, silicon (e.g., single-crystal silicon, polycrystalline silicon), silicon-germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or any combination thereof. In some examples, the substrate 110 may include a substrate 111 and a composite layer 112 located on the substrate, wherein the substrate 111 has a certain thickness and can serve as a structural support for the device structure (e.g., the stacked structure 120) formed thereon. Alternatively, the substrate 111 may be removed in some subsequent process steps.

[0053] In some embodiments, the stacked structure 120' may include a plurality of dielectric layers 130 and a plurality of sacrificial layers 140 alternately stacked in a direction perpendicular or substantially perpendicular to the substrate 110 (y-direction). Under the same etching conditions, the sacrificial layer 140 and the dielectric layer 130 may have a high etch selectivity ratio so that the dielectric layer 130 is hardly removed when the sacrificial layer 140 is removed in a subsequent process. In some examples, the material for the sacrificial layer 140 includes, for example, silicon nitride, and the material for the dielectric layer 130 includes silicon oxide.

[0054] For example, a stacked structure 120' can be formed on substrate 110 by alternately forming a plurality of sacrificial layers 140 and dielectric layers 130 through thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0055] It should be understood that the number of layers in the stacking structure 120' is not limited to the number of layers shown in the figure. Rather, the number of stacking layers and the stacking height of the stacking structure 120' can be designed according to actual needs. This application does not make any specific limitations in this regard.

[0056] In some embodiments, multiple dummy channel structures 150 may be formed in the stacked structure 120'. Exemplarily, the method of forming the dummy channel structures 150 may include first forming a channel via within the stacked structure 120', followed by sequentially forming a barrier layer, a charge trapping layer, a tunneling layer, and a channel layer within the dummy channel via to form the dummy channel structure 150. Exemplarily, the barrier layer, charge trapping layer, and tunneling layer may be sequentially deposited using, for example, one or more thin film deposition processes (e.g., ALD, CVD, PVD, or combinations thereof), after which the channel layer may be deposited on the side of the tunneling layer away from the channel via. In other embodiments, the dummy channel structures 150 may be filled only with an insulating material. The dummy channel structures 150 may provide mechanical support for subsequent sacrificial layer 140 removal processes.

[0057] In some embodiments, the formation of a channel structure (not shown) is also included, which may be aligned with the dummy channel structure 150 along the z-direction. The channel structure may be located within the core region of the 3D memory, and the dummy channel structure 250 may be located within a dummy step region of the 3D memory, which may also be aligned with the core region along the y-direction. The method of forming the channel structure may include, for example, first forming a channel via within the stacked structure 120', and then sequentially forming a barrier layer, a charge trapping layer, a tunneling layer, and a channel layer within the channel via to form the channel structure. Exemplarily, the barrier layer, charge trapping layer, and tunneling layer may be a silicon oxide-silicon nitride-silicon oxide (ONO) structure. In some examples, the channel layer may be used to transport the desired charge (electrons or holes). The material of the channel layer may include p-type doped polysilicon. The space defined by the channel layer may be filled with a channel filler layer, the material of which may include, for example, silicon oxide or silicon oxynitride.

[0058] Step S1200: Remove at least a portion of the sacrificial layer to form a gap, and fill the gap with the gate layer.

[0059] Figure 3 This is a schematic diagram illustrating the process of forming a stacked structure 120 of a three-dimensional memory according to an embodiment of this application. Figure 3 As shown, a gate line slot 160' can be formed through the stacked structure 120' and extend into the substrate 110. The gate line slot 160' can be formed by repeated etch-trimming processes, such as photolithography and etching. Then, the sacrificial layer 140 is etched multiple times through the gate line slot 160' to remove a portion of the sacrificial layer 140, and the gate layer 170 is filled in the gap formed after the removal of this portion. At this time, a channel structure and a dummy channel structure 150 are respectively passed through the gate layer 170. The gate layer 170 is located above the first dielectric layer 131 (along the y direction), and the unetched sacrificial layer 140 is located above the second dielectric layer 132.

[0060] For example, a portion of the sacrificial layer 140 may be removed using a wet etching process, and the gate layer 170 may be formed using one or more thin film deposition processes (e.g., ALD, CVD, PVD, or combinations thereof).

[0061] In some embodiments, the gate layer 170 replaces a portion of the sacrificial layer 140 to form a stacked structure 120. The stacked structure 120 may include a first stacked structure 121 and a second stacked structure 122. Exemplarily, the first stacked structure 121 may include a first dielectric layer 131 and a gate layer 170 stacked sequentially, and the second stacked structure 122 may include a second dielectric layer 133 and a sacrificial layer 140 stacked sequentially. The first stacked structure 121 and the second stacked structure 122 are connected and arranged along the x-direction. It is understood that the gate layer 170 in the first stacked structure 121 and the sacrificial layer 140 in the second stacked structure 122 are connected and arranged along the x-direction.

[0062] In some embodiments, a high-dielectric-constant layer 171 may be formed in the voids created by removing a portion of the sacrificial layer 140 using, for example, a thin-film deposition process, and then a gate layer 170 may be formed inside the high-dielectric-constant layer 171. The high-dielectric-constant layer 171 covers the gate layer 170 and is in contact with the sacrificial layer 140 located in the same layer.

[0063] In other embodiments, a high-dielectric-constant layer 171, an adhesive layer (not shown), and a gate layer 170 may be sequentially formed in the voids created by removing a portion of the sacrificial layer 140 using, for example, a thin-film deposition process. Exemplarily, the high-dielectric-constant layer 171 may be formed of a high-dielectric-constant material, such as hafnium dioxide, lanthanum oxide, aluminum oxide, tantalum pentoxide, yttrium oxide, hafnium silicate oxide, silicon oxide, silicon nitride, zirconium dioxide, strontium titanate, or zirconium silicate oxide. The high-dielectric-constant layer 171, using a high-dielectric-constant material, can effectively reduce gate capacitance. The adhesive layer material may include, for example, titanium, titanium nitride, tantalum, tantalum nitride, or any combination thereof. The gate layer 170 may be formed of a conductive material, such as tungsten, cobalt, copper, aluminum, or any combination thereof.

[0064] The adhesive layer according to an exemplary embodiment of this application can provide deposition sites during the deposition of the gate layer 170, and can also be used to bond the gate layer 170 to the high dielectric constant layer 171, and can prevent the diffusion of the conductive material forming the gate layer 170.

[0065] Step S1300: A preset hole is formed on the side of the stacked structure away from the substrate, wherein the preset hole... At least a portion of it is in contact with the gate layer.

[0066] Figure 4 and Figure 5 This is a schematic diagram illustrating the formation of a preset hole 180 and an isolation layer 190 in a three-dimensional memory according to an embodiment of this application. Figure 4As shown, a first portion 181 of a preset via can be formed on the upper side (along the y-direction) of the second stacked structure 122, and an isolation layer 190 is formed on the sidewall of the preset via 181. The first portion 181 of the preset via penetrates a portion of the second dielectric layer 132 and the sacrificial layer 140 in the opposite y-direction, exposing the sacrificial layer 140. A portion of the exposed sacrificial layer 140 can then be removed via the first portion 181 of the preset via to form a second portion 182 of the preset via that is connected to the gate layer 170 (e.g., ...). Figure 5 (As shown). The first part 181 and the second part 182 of the preset hole together constitute the preset hole 180.

[0067] In some embodiments, the isolation layer 190 can be formed by a thin film deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The material for forming the isolation layer 190 may be, for example, silicon oxide.

[0068] In some embodiments, processes such as photolithography and etching can be used to form a first portion 181 of a preset hole on the upper side of the second stacked structure 122. The lower side of the first portion 181 of the preset hole may be a sacrificial layer 140 that has not been removed. A portion of the sacrificial layer 140 is etched away through the first portion 181 of the preset hole to form a second portion 182 of the preset hole that communicates with the gate layer 170.

[0069] In some embodiments, the process of forming the second portion 182 of the preset via further includes etching away the high dielectric constant layer 171 located on the surface of the gate layer 170. In other embodiments, the process of forming the second portion 182 of the preset via further includes etching away the high dielectric constant layer 171 and the adhesive layer located on the surface of the gate layer 170 to expose at least a portion of the gate layer 170, the exposed portion of the gate layer 170 serving as an electrical connection portion for leading out word lines in subsequent processes.

[0070] In some embodiments, the method for removing a portion of the sacrificial layer 140 located below the first portion 181 of the preset via may include, but is not limited to, etching. For example, dry etching such as deep ion reactive etching may be used, or wet etching (e.g., using hot concentrated sulfuric acid, phosphoric acid, etc. as etchants) may be used to etch the exposed sacrificial layer 140 through the first portion 181 of the preset via to form the second portion of the preset via. During this process, the isolation layer 190 can protect the sacrificial layer 140 of the second stacked structure 122 near the first portion 181 of the preset via, thereby preventing the sacrificial layers 140 located on both sides of the first portion 181 of the preset via from being etched away, achieving the purpose of etching only a single sacrificial layer 140, and forming a first conductive layer 200 connected only to a gate layer 170 in subsequent processes. Figure 6 (As shown).

[0071] In some embodiments, the gate line slots 160' are further filled to form a gate line slot structure 160. A single filler material, such as an oxide, may be sequentially filled into the gate line slots 160'. Alternatively, a composite material may be filled into the gate line slots 160', for example, first filling a layer of insulating material, and then filling the interior of the insulating material with a conductive material. This application does not limit this approach.

[0072] It should be noted that, Figure 4 The shape of the first portion 181 of the preset hole shown is merely illustrative and is not a limitation on the configuration of the first portion 181 of the preset hole. Those skilled in the art can design a suitable shape of the first portion 181 of the preset hole according to the specific structural requirements of different storage devices, and this application does not limit it in this regard.

[0073] Step S1400: A first conductive layer connected to the gate layer is formed in the preset hole, and in the remaining space of the preset hole... An internal filling layer is formed.

[0074] Figure 6 This is a schematic diagram illustrating the formation of a first conductive layer 200 in a three-dimensional memory according to an embodiment of this application. Figure 6 As shown, a first conductive layer 200 is formed within the second portion 182 of the preset hole, and also forms on the sidewall of the first portion 181 of the preset hole. One end of the first conductive layer 200 located within the second portion 182 of the preset hole is connected to the gate layer 170, forming an electrical connection structure when an external voltage is applied. It can be understood that by controlling the filling amount of the first conductive layer 200, it is possible to ensure that at least a portion of the first portion 181 of the preset hole remains unfilled when the second portion 182 of the preset hole is completely filled.

[0075] In some embodiments, a second conductive layer 210 is formed on the upper side (along the y direction) of the stacked structure 120, and the second conductive layer 210 is connected to the first conductive layer 200.

[0076] In some embodiments, a filling layer 220 is formed in the space remaining after the first conductive layer 200 is formed in the first portion 181 of the preset hole. Exemplarily, the filling layer 220 can fill the unfilled area of ​​the first portion 181 of the preset hole. Exemplarily, the filling layer 220 can also cover the second conductive layer 210. The material of the filling layer 220 is different from that of the first conductive layer to mitigate the large stress changes caused by forming a structure from a single material. The material of the filling layer 220 can be, for example, an insulating material.

[0077] For example, one or more thin-film deposition processes (e.g., ALD, CVD, PVD, or combinations thereof) can be used to sequentially form a first conductive layer 200 and a filling layer 220 within a predetermined hole 180. In some embodiments, the method for forming the second conductive layer 210 may be the same as the method for forming the first conductive layer 200. The material used to form the first conductive layer 200 may be the same as or different from the material used to form the second conductive layer 210, and may include, for example, tungsten, aluminum, silver, copper, tungsten alloys, aluminum alloys, silver alloys, copper alloys, or any combination thereof. The material used to form the filling layer 220 may include, for example, silicon oxide.

[0078] In other implementations, such as Figure 7 As shown, gaps 260 can be reserved inside the filling layer 220 during its formation process to relieve internal stress in the device.

[0079] In step S1500, a fourth conductive layer connected to the first conductive layer is formed on the side of the filling layer away from the substrate.

[0080] Figures 8 to 9 This is a schematic diagram of the formation of a third conductive layer 230 in a three-dimensional memory according to an embodiment of this application. Figure 8 As shown, a portion of the fill layer 220 can be etched from the side away from the substrate 110, such that the upper surface (along the y-direction) of the etched fill layer 220 is located below the lower surface (in the opposite y-direction) of the second conductive layer 210. Exemplarily, the aforementioned portion of the fill layer 220 can be removed using wet etching, dry etching, and / or other processes.

[0081] like Figure 9 As shown, a conductive material can be deposited on the upper surface of the filler layer 220 and the upper surface of the second conductive layer 210. A portion of this conductive material on the upper surface of the filler layer 220 forms a third conductive layer 230, and at least a portion of the third conductive layer 230 is connected to the first conductive layer 200. Exemplarily, the method for forming the third conductive layer 230 can be the same as the method for forming the first conductive layer 200. The material used to form the third conductive layer 200 can be the same as or different from the material used to form the first conductive layer 230, and may include, for example, tungsten, aluminum, silver, copper, tungsten alloys, aluminum alloys, silver alloys, copper alloys, or any combination thereof.

[0082] In some embodiments, the second conductive layer 210 and the portion above the second conductive layer 210 may be removed to form a structure as shown in the figure. Figure 10 The structure is shown. In this process, at least a portion of the third conductive layer 230 is retained, and the retained portion forms the fourth conductive layer 240. It should be noted that at least a portion of the fourth conductive layer 240 is connected to the first conductive layer 200, thereby enabling connection with the conductive portion 250 formed in subsequent processes. Figure 11 (As shown) and the peripheral circuit form a conductive path.

[0083] Exemplarily, the second conductive layer 210 and the portion above it can be removed using, for example, a chemical mechanical polishing (CMP) process. In the context of this invention, some steps, such as planarization, surface cleaning, and removal of scum, are omitted from the methods for fabricating the pre-drilled hole 180, the second conductive layer 210, and the third conductive layer 240. These are not the focus of this invention and will not be described further here. Those skilled in the art can add or omit steps in the fabrication method of this invention as needed.

[0084] In some embodiments, a conductive portion 250 is also formed on the upper side of the fourth conductive layer 240 (e.g., Figure 11 As shown, one side of the conductive portion 250 is connected to the fourth conductive layer 240, and the other side can be connected to an external interconnection structure. For example, the material of the conductive portion 250 may include tungsten, aluminum, silver, copper, tungsten alloy, aluminum alloy, silver alloy, copper alloy, or any combination thereof.

[0085] Another aspect of this application provides a three-dimensional memory. This three-dimensional memory can be fabricated using the fabrication methods described in any of the above embodiments.

[0086] refer to Figure 12 As shown, the three-dimensional memory includes a semiconductor layer 110', a stacked structure 120, and a conductive structure 300. In some embodiments, the stacked structure 120 is located on the semiconductor layer 110' and has a gate layer 170. The conductive structure 300 is located on the side of the stacked structure 120 away from the semiconductor layer 110' and includes a first conductive layer 200, a fill layer 220, and a fourth conductive layer 240. The first conductive layer 200 is connected to the gate layer 170 and the fourth conductive layer 240, respectively. The first conductive layer 200 and the fourth conductive layer 240 cover the fill layer 220, and the fourth conductive layer 240 is located above the fill layer 220 (along the y-direction).

[0087] In some embodiments, the gate layer 170 includes multiple layers, the stacked structure 120 further includes dielectric layers 130 alternately stacked with each of the gate layers 170, and a first conductive layer 200 connected to one of the gate layers 170.

[0088] In some embodiments, the conductive structure 300 is located within the second stacked structure 122 and includes a first conductive layer 200, a fill layer 220, and a fourth conductive layer 240. The first conductive layer 200 is connected to the gate layer 170, and the fourth conductive layer 240 is connected to the first conductive layer 200. The fill layer 220 is located within the remaining space of the conductive structure 300 after the first conductive layer 200 is filled, and the fourth conductive layer 240 is located above the fill layer 220. Exemplarily, the conductive structure 300 penetrates the sacrificial layer 140 and the dielectric layer 130 located above the second stacked structure 122 in the opposite direction of y. An isolation layer 190 is provided between the conductive structure 300 and the stacked structure 120, the isolation layer 190 contacting the first conductive layer 200 and surrounding a second portion of the first conductive layer 200.

[0089] In some embodiments, the three-dimensional memory includes a dummy step region and a core region (not shown) arranged along the z-direction. A channel structure runs through the core region, and a dummy channel structure 150 and a conductive structure 300 run through the dummy step region. The dummy channel structure 150 and the conductive structure 300 may be arranged along the x-direction and connected via a gate layer 170. The channel structure 251 and the conductive structure 300 may be arranged along the z-direction and also connected via a gate layer 330. The critical dimension of the dummy channel structure 150 is smaller than the critical dimension of the conductive structure 300.

[0090] In some embodiments, a first portion of the first conductive layer 200 is located between two dielectric layers 130 and is connected to the gate layer 170, and a second portion of the first conductive layer 200 penetrates the dielectric layer 130 and the sacrificial layer 140 on the side of the stacked structure 120 away from the semiconductor layer 110' and is connected to the first portion of the first conductive layer 200.

[0091] In some embodiments, the three-dimensional memory further includes a gate slot structure 160 and a dummy channel structure 150 penetrating the dummy step region. The dummy channel structure 150 is located on both sides of the gate slot structure 160 along the x-direction. The critical dimension of the channel structure 150 is smaller than the critical dimension of the conductive structure 300. In other words, the dimension of the conductive structure 300 in the x-direction is larger than the dimension of the channel structure 150 in the same direction.

[0092] In some embodiments, the first conductive layer 200 includes a first portion located between two dielectric layers 130 and connected to the gate layer 170, and a second portion located on the outer wall of the fill layer 220 and connected to the first portion. The first portion of the first conductive layer 200 and the fourth conductive layer 240 surround the fill layer 220. The material of the first conductive layer 200 may be the same as the material of the fourth conductive layer 240, while the material of the fill layer 200 may be different from the materials of the first conductive layer 200 and the fourth conductive layer 240. The structure formed by using composite materials can alleviate stress changes in structures formed by single materials. The material of the fill layer 220 may be, for example, an insulating material, while the materials of the first conductive layer 200 and the fourth conductive layer 240 may be, for example, conductive materials.

[0093] In some embodiments, the three-dimensional memory also includes a conductive portion 250 located above the fourth conductive layer 240. One side of the conductive portion 250 is connected to the fourth conductive layer 240, and the other side can be connected to an external interconnect structure, so that external circuitry can control the (word line) gate layer 170 through the conductive portion 250 and the conductive structure 300.

[0094] In other embodiments, a void 260 is provided inside the filler layer 220. Figure 7 The presence of the 260mm gap can buffer stress, thereby protecting the stability of the device.

[0095] Since the content and structure described in the preparation method 1000 above can be fully or partially applied to the three-dimensional memory described here, related or similar content will not be repeated.

[0096] Another aspect of this application provides a three-dimensional memory system, such as Figure 13 As shown, the three-dimensional storage system includes a three-dimensional memory 301 and a controller 302 as described in any embodiment of this application. The three-dimensional memory 301 includes multiple memory strings with storage functions, each memory string being composed of multiple memory cells. The controller 302 is electrically connected to the three-dimensional memory 301 via peripheral circuitry and is configured to control the operation of the memory strings.

[0097] In some embodiments, memory 301 is electrically connected to and controlled by controller 302. Controller 302 may, for example, control the application of different voltage signals to memory cells (not shown) in memory 301 to control memory 301 to perform at least one of, for example, read operations, programming operations, and erase operations.

[0098] In some implementations, controller 302 may be configured to control operations of memory 301, such as read, program, and erase operations. Controller 302 may also be configured to manage various functions related to data stored in or to be stored in memory 301, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.

[0099] In some embodiments, the 3D memory 301 includes a 3D NAND memory, which comprises a plurality of memory cells arranged in a three-dimensional stacked manner. In some embodiments, the 3D memory system also includes a connector 303, which can be connected to a device such as a host computer for transmitting data.

[0100] In some embodiments, the three-dimensional memory system includes a solid-state drive (SSD), a memory card, or any combination thereof. In some embodiments, the controller 302 and the memory 301 may be integrated onto the SSD to form the three-dimensional memory system. The storage capacity and / or operating speed of the SSD may be higher than that of the memory card. The three-dimensional memory 301 of any embodiment of this application can be applied to storage devices or memory cards such as memory sticks, PC cards, compact flash (CF) cards, smart media (SM) cards, multimedia cards, SD cards, and universal flash memory (UFS).

[0101] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for fabricating a three-dimensional memory, comprising: A stacked structure is formed by alternately stacking dielectric layers and sacrificial layers along the stacking direction on a substrate; A portion of the sacrificial layer is removed to form a gap, and a gate layer is filled in the gap. After the gate layer is formed, the dielectric layer and the gate layer are alternately stacked to form a first stacked structure. The portion of the dielectric layer and the sacrificial layer that has not been removed are alternately stacked to form a second stacked structure. The first stacked structure and the second stacked structure are arranged along a first direction, wherein the first direction is perpendicular to the stacking direction. A predetermined hole extending in the second stacked structure is formed along the stacking direction on the side of the second stacked structure away from the substrate, wherein at least a portion of the predetermined hole contacts the gate layer; A first conductive layer connected to the gate layer is formed within the preset hole, and a filling layer is formed in the remaining space of the preset hole; and A fourth conductive layer, connected to the first conductive layer, is formed on the side of the fill layer away from the substrate.

2. The method according to claim 1, wherein, The gate layer comprises multiple layers, each of which is alternately stacked with the dielectric layer. The preset hole contacts at most one of the gate layers.

3. The method according to claim 1, wherein, The method for forming the preset hole includes: A first portion of a predetermined hole is formed on the side of the second stacked structure away from the substrate; and A second portion of the preset hole is formed on the side of the first portion of the preset hole that is close to the substrate, wherein the second portion of the preset hole is in contact with the gate layer.

4. The method according to claim 3, wherein, Before forming the second part of the preset hole, it also includes: An isolation layer is formed on the sidewall of the first part of the preset hole.

5. The method according to claim 1, wherein, The steps for forming the fourth conductive layer include: A third conductive layer, connected to the first conductive layer, is formed on the side of the fill layer away from the substrate; and The portion of the third conductive layer that does not contact the filling layer is removed to form the fourth conductive layer.

6. The method according to claim 5, wherein, The step of forming a first conductive layer connected to the gate layer within the preset hole further includes: A second conductive layer is formed on the side of the first and second stacked structures away from the substrate.

7. The method according to claim 6, wherein, The distance from the side of the third conductive layer closest to the substrate to the substrate is less than the distance from the side of the second conductive layer closest to the substrate to the substrate, wherein the method further includes: Remove the second conductive layer to expose the first side of the first stacked structure and the second stacked structure. The side of the fourth conductive layer away from the substrate is coplanar with the first side.

8. The method according to claim 5, further comprising: A conductive portion connected to the fourth conductive layer is formed on the side of the fourth conductive layer away from the substrate.

9. The method according to claim 1, further comprising: Voids are formed inside the filling layer.

10. The method according to claim 1, wherein, The material forming the filler layer includes insulating materials.

11. A three-dimensional memory, comprising: Semiconductor layer; A stacked structure, located on the semiconductor layer, includes a first stacked structure and a second stacked structure. The first stacked structure includes a first dielectric layer and a gate layer stacked sequentially. The second stacked structure includes a second dielectric layer and a sacrificial layer stacked sequentially. The first stacked structure and the second stacked structure are arranged along a first direction, wherein the first direction includes a direction perpendicular to the stacking direction of the dielectric layer and the gate layer. A conductive structure extends in the second stacked structure and includes a first conductive layer, a filler layer, and a fourth conductive layer. The first conductive layer is connected to the gate layer and the fourth conductive layer, the first conductive layer and the fourth conductive layer cover the filling layer, and the fourth conductive layer is located on the side of the filling layer away from the semiconductor layer.

12. The three-dimensional memory according to claim 11, wherein, The gate layer comprises multiple layers, and the first stacked structure further comprises dielectric layers alternately stacked with each of the gate layers, and The first conductive layer is in contact with at most one of the gate layers.

13. The three-dimensional memory according to claim 12, wherein, The first conductive layer includes a first portion located between the two dielectric layers and connected to the gate layer, and This includes a second portion located between the filler layer and the second stacked structure, and connected to the first portion. The first portion of the first conductive layer and the fourth conductive layer surround the filling layer.

14. The three-dimensional memory according to claim 13, further comprising: An isolation layer is located between the second stacked structure and the second portion of the first conductive layer, and covers the portion of the second portion of the first conductive layer that is close to the second stacked structure.

15. The three-dimensional memory according to claim 13, wherein, The three-dimensional memory includes a core region and a dummy step region. The core region has a channel structure penetrating the first stacked structure, and the dummy step region has a dummy channel structure penetrating the second stacked structure. The conductive structure is located within the dummy step region. The critical dimension of the dummy channel structure is smaller than the critical dimension of the conductive structure.

16. The three-dimensional memory according to claim 11, further comprising: The conductive portion is located on the side of the fourth conductive layer away from the semiconductor layer and is connected to the fourth conductive layer.

17. The three-dimensional memory according to claim 15, further comprising: The gate gap structure is located on the side of the conductive structure close to the dummy channel structure, and extends along the stacking direction of the dielectric layer and the gate layer, as well as along the arrangement direction of the core region and the dummy step region.

18. The three-dimensional memory according to claim 11, wherein, The filling layer has voids inside.

19. A three-dimensional memory system, comprising: The three-dimensional memory as described in any one of claims 11-18, wherein the three-dimensional memory includes a storage string for storing data; and A controller, electrically connected to the three-dimensional memory, is configured to control the operation of the memory string.

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