Three-dimensional memory and methods of making the same, memory systems

Abstract

The present disclosure provides three-dimensional memory and methods of making the same, as well as memory systems. One method of making a three-dimensional memory according to the present disclosure includes forming a dielectric stack on a side of a substrate, the dielectric stack including a core region; forming a channel structure through the dielectric stack at the core region; forming an auxiliary dummy structure, at least a portion of the auxiliary dummy structure located at an edge of the core region; and forming a common source structure through the dielectric stack, the auxiliary dummy structure electrically isolating the channel structure and the common source structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and manufacturing, and more specifically, to the structure of three-dimensional memory and its fabrication method and storage system. Background Technology

[0002] Three-dimensional storage devices (e.g., 3D NAND type memory) have high storage density and high storage capacity, and have been continuously developed in recent years. For example, 3D NAND type memory has been used more and more widely.

[0003] The 3D NAND memory structure includes a core region, which houses an array of channel structures. These channel structures are the memory strings within the 3D NAND type memory. In related technologies, during the gate gap formation process, the gate gap can deform due to internal loads, such as bending towards the channel structure. Consequently, during the subsequent common-source structure formation process, because the gate gap is filled with highly doped polysilicon, it is highly susceptible to contact with the channel structure in the deformed area, leading to short circuits or leakage. This severely impacts the electrical performance and product yield of the 3D NAND device. Summary of the Invention

[0004] This application provides a three-dimensional memory and a method for its fabrication that can at least partially solve the aforementioned problems existing in related technologies.

[0005] One aspect of this application provides a method for fabricating a three-dimensional memory, the method comprising: forming a dielectric stack structure on one side of a substrate, the dielectric stack structure including a core region; forming a channel structure penetrating the dielectric stack structure in the core region; forming an auxiliary virtual structure, at least a portion of the auxiliary virtual structure being located at the edge of the core region; and forming a common source structure penetrating the dielectric stack structure, the auxiliary virtual structure electrically isolating the channel structure and the common source structure.

[0006] In one embodiment of this application, forming the auxiliary virtual structure includes: forming at least two auxiliary virtual structures, each having at least a portion located at the edge of the core region and spaced apart from each other; wherein forming a common source structure penetrating the dielectric stack structure includes: forming a common source structure penetrating the dielectric stack structure and extending through the space, wherein the direction of extension is perpendicular to the direction of penetration.

[0007] In one embodiment of this application, forming the common source structure that penetrates the dielectric stack structure and extends through the interval includes: forming a gate gap that penetrates the dielectric stack structure and extends through the interval, wherein a portion of the sidewall of the gate gap is formed by the auxiliary virtual structure; and forming the common source structure within the gate gap.

[0008] In one embodiment of this application, forming the auxiliary virtual structure includes: forming a mask having an auxiliary virtual hole pattern on the side of the dielectric stack structure away from the substrate; etching the dielectric stack structure via the auxiliary virtual hole pattern to form an auxiliary virtual hole; and filling the auxiliary virtual hole with a first material.

[0009] In one embodiment of this application, the first material includes an insulating material.

[0010] In one embodiment of this application, the dielectric stack structure includes alternately stacked insulating layers and gate sacrificial layers, wherein the etching rate of the first material under the same etching conditions is lower than the etching rates of the insulating layer and the gate sacrificial layer.

[0011] In one embodiment of this application, the first material includes at least one of alumina, hafnium oxide, and atomic layer deposited silicon oxide.

[0012] In one embodiment of this application, the auxiliary dummy via penetrates the dielectric stack structure and extends to the substrate.

[0013] In one embodiment of this application, the auxiliary dummy hole penetrates the dielectric stack structure.

[0014] In one embodiment of this application, the dielectric stack structure further includes a stepped region located around the core region, and the mask template further has a virtual channel pattern; wherein, the method further includes: when forming the auxiliary dummy hole via the auxiliary dummy hole pattern, simultaneously etching the dielectric stack structure through the virtual channel pattern to form a virtual channel penetrating the dielectric stack structure in the stepped region; and when filling the auxiliary dummy hole with a first material to form the auxiliary virtual structure, simultaneously filling the virtual channel with the first material to form a virtual channel structure.

[0015] In one embodiment of this application, the dielectric stack structure includes alternating insulating layers and gate sacrificial layers, wherein, before forming the common source structure within the gate gap, the method further includes: removing the gate sacrificial layer via the gate gap to form a sacrificial gap; and forming a gate layer within the sacrificial gap.

[0016] Another aspect of this application provides a three-dimensional memory comprising: a substrate; a stacked structure located on one side of the substrate and including a core region; a channel structure located in the core region and extending through the stacked structure; a common source structure extending through the stacked structure; and an auxiliary virtual structure, at least a portion of which is located at the edge of the core region, wherein the auxiliary virtual structure electrically isolates the channel structure and the common source structure.

[0017] In one embodiment of this application, the three-dimensional memory includes: at least two auxiliary virtual structures, each having at least a portion located at the edge of the core region and spaced apart from each other; the common source structure penetrates the stacked structure and extends through the gap, wherein the direction of extension is perpendicular to the direction of penetration.

[0018] In one embodiment of this application, a portion of the sidewall of the common source structure is in contact with the auxiliary virtual structure.

[0019] In one embodiment of this application, the material forming the auxiliary virtual structure includes an insulating material.

[0020] In one embodiment of this application, the stacked structure includes alternating insulating layers and gate layers, wherein the etching rate of the insulating material under the same etching conditions is lower than the etching rate of the insulating layer.

[0021] In one embodiment of this application, the insulating material includes at least one of silicon oxide, aluminum oxide, and hafnium oxide.

[0022] In one embodiment of this application, the auxiliary virtual structure extends through the stacked structure and to the substrate, or the auxiliary virtual structure extends through a portion of the stacked structure.

[0023] In one embodiment of this application, the stacked structure further includes a stepped area located around the core area, wherein a plurality of virtual channel structures are formed in the stepped area, wherein the auxiliary virtual structure includes a first portion extending along the extending direction, the length of the first portion being greater than or equal to the length of a single virtual channel structure along the extending direction.

[0024] In one embodiment of this application, the auxiliary virtual structure further includes a second portion that protrudes relative to the first portion in a second direction perpendicular to the direction of extension toward a side away from the common source structure.

[0025] In one embodiment of this application, on the first side of the common source structure along the second direction, the three-dimensional memory includes M auxiliary virtual structures spaced apart along the extending direction, where M is a positive integer; and on the second side of the common source structure along the second direction, the three-dimensional memory includes N auxiliary virtual structures spaced apart along the extending direction, where N is a positive integer.

[0026] In one embodiment of this application, M≥2 and M=N, the M auxiliary virtual structures located on the first side and the N auxiliary virtual structures located on the second side correspond one-to-one with each other along the second direction.

[0027] Another aspect of this application provides a storage system comprising: at least one three-dimensional memory as described above; and a controller electrically connected to at least one of the three-dimensional memories for controlling at least one of the three-dimensional memories.

[0028] This application pre-sets auxiliary virtual structures at locations prone to deformation during gate slot formation, allowing the gate slot etching to proceed downwards along these structures. Specifically, the auxiliary virtual structures prevent the gate slot from bending and deforming towards the channel structure during etching, resulting in a well-defined gate slot morphology. The subsequent common-source structure formed within the gate slot also exhibits a favorable morphology. Furthermore, the auxiliary virtual structures separate the common-source structure and the channel structure, effectively preventing short circuits or leakage caused by the common-source structure contacting the channel structure due to bending deformation, thus improving the electrical performance and production yield of 3D memory devices. Attached Figure Description

[0029] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Embodiments of this application are illustrated in the accompanying drawings by way of example rather than limitation, in which the same reference numerals indicate similar elements. Wherein: Figure 1 This is a flowchart of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application; Figure 2 These are scanning electron microscope images showing the deformation of the common-source structure of a three-dimensional memory located at the edge of the core region in related technologies. Figure 3 This is a schematic diagram of the process layout for fabricating three-dimensional memory in related technologies; Figure 4 This is a schematic process layout diagram of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application; Figure 5A three-dimensional memory according to an exemplary embodiment of this application is in the corresponding Figure 4 The cross-sectional view at the R-R' position shown; Figure 6 A three-dimensional memory according to another exemplary embodiment of this application in the corresponding Figure 4 The cross-sectional view at the R-R' position shown; Figures 7 to 13 These are schematic diagrams of process layouts of different design schemes for auxiliary virtual structures according to different exemplary embodiments of this application; Figure 14 This is a top view of a three-dimensional memory prepared according to an exemplary embodiment of this application; Figure 15 yes Figure 14 The cross-sectional view of the three-dimensional memory shown is located at Z-Z'. Figure 16 This is a schematic diagram of a storage system according to an exemplary embodiment of this application; and Figure 17 This is a schematic diagram of a storage system according to another exemplary embodiment of this application. Detailed Implementation

[0030] The present application will now be described in detail with reference to the accompanying drawings. The exemplary embodiments mentioned herein are for illustrative purposes only and are not intended to limit the scope of the application. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] The accompanying drawings are for illustrative purposes only and are not strictly to scale. As used herein, the terms “approximately,” “about,” and similar expressions are used to indicate approximation, not degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art. It should be understood that in this specification, the terms “first,” “second,” etc., are used only to distinguish one feature from another and do not imply any limitation on the features, or in particular any order of precedence.

[0032] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprise" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the term "exemplary" is intended to refer to examples or illustrations.

[0033] Furthermore, when terms such as “connection,” “covering,” and / or “formed on” are used in this application, they may indicate that the corresponding components are in direct or indirect contact, unless there are other explicit limitations or can be inferred from the context.

[0034] As used in this article, the term "layer" refers to a portion of material with a certain thickness.

[0035] As used herein, the term "three-dimensional memory" refers to a semiconductor device having vertically oriented strings of memory cell transistors on a laterally oriented substrate, such that the strings of memory cell transistors extend in a direction perpendicular or substantially perpendicular to the substrate. As used herein, the term "vertical" means perpendicular or substantially perpendicular to the lateral surface of the substrate.

[0036] The shapes of, for example, channel structures, auxiliary virtual structures, and virtual channel structures shown in the “process layouts” included in the accompanying drawings are shown as squares or rectangles. However, it should be understood that such illustrations are for illustrative purposes only and are not restrictive. For example, in the corresponding view of the actual product corresponding to each “process layout”, the shapes of these structures may be approximately circular or elliptical, i.e., the corresponding structures in the corresponding view of the actual product usually do not have the sharp corners shown in the layout.

[0037] Many specific details of this application, such as the structure, materials, dimensions, processing techniques, and methods of the devices, are described below to provide a clearer understanding of the application. However, as those skilled in the art will understand, this application may be implemented without adhering to these specific details.

[0038] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be executed in any order or in parallel.

[0039] Based on the description in the background section, in the fabrication process of three-dimensional memory, when forming the gate gap, the portion of the gate gap located at the edge region adjacent to the core region and the step region often deforms due to internal loads and other reasons (e.g. Figure 2 As shown in the figure, this causes it to come into contact with the adjacent channel structure. In the subsequent process of forming the common source structure, since the common source structure is filled with highly doped polysilicon, it is very easy for electrical connections to occur with the channel structure in the above-mentioned deformation area, which leads to problems such as short circuits or leakage, seriously affecting the electrical performance and product yield of the three-dimensional memory device.

[0040] Figure 2These are scanning electron microscope images showing the deformation of the common-source structure of a three-dimensional memory located at the edge of the core region in related technologies. Figure 2 Area A, as indicated in the text, is the core area, and area B is the stepped area; Figure 2 230 indicates a common-source pole structure; 210 and 240 indicate the channel structure located in the core region and the virtual channel structure located in the step region, respectively. Figure 2 As can be seen, near the edge of the step region in the core region A, the common source electrode structure 230 undergoes bending deformation and comes into contact with both adjacent channel structures 210, such as... Figure 2 The part circled in the middle is shown.

[0041] Figure 3 This is a schematic diagram of the fabrication process of a three-dimensional memory in related technologies. As can be seen from this process layout, although the common-source structure 230 shown in the layout extends along a straight line and can separate multiple channel structures 210 in the core region (region A), in actual production, the final common-source structure usually produces... Figure 2 The deformation shown.

[0042] To address the above situation, this application provides an auxiliary virtual structure in the region where the common source structure is prone to deformation. The auxiliary virtual structure is located between the channel structure and the common source structure. The auxiliary virtual structure can separate the channel structure and the common source structure to achieve electrical isolation between them, thereby effectively preventing the common source structure and the channel structure from becoming electrically connected as described above. This is beneficial to improving the electrical performance and product yield of the three-dimensional memory device.

[0043] This application will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0044] This application provides a method 1000 for fabricating a three-dimensional memory. Figure 1 A flowchart of method 1000 is shown.

[0045] like Figure 1 As shown, the method 1000 for fabricating a three-dimensional memory may include the following steps: S1: A dielectric stack structure 200 is formed on one side of the substrate 100. The dielectric stack structure 200 may include a core region A. S2: A channel structure 210 is formed in the core region A, penetrating the dielectric stack structure 200; S3: Forming an auxiliary virtual structure 220, at least a portion of which is located at the edge of the core region A; and S4: Forming a common source structure 230 that penetrates the dielectric stack structure 200, the common source structure 230 along the first direction D1 ( Figure 4Extending this, the auxiliary virtual structure 220, the electrically isolated channel structure 210, and the common source structure 230 are provided.

[0046] The following will combine Figures 4 to 13 The specific processes for each step in the above preparation method 1000 are described in detail.

[0047] Figure 4 This is a schematic diagram of the process layout for fabricating a three-dimensional memory according to an exemplary embodiment of this application. Figure 5 and Figure 6 In two different exemplary embodiments, respectively, along Figure 4 A cross-sectional view obtained from the R-R' line.

[0048] In various embodiments of this application, the substrate 100 may be, for example, a single-crystal silicon (Si) substrate, a single-crystal germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or a substrate comprising other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC. The substrate 100 may also be a stacked structure, such as Si / SiGe. In one embodiment, the semiconductor substrate 100 is, for example, a doped single-crystal silicon substrate. The semiconductor substrate 100 may be a P-type substrate or an N-type substrate, and may further include N-wells and / or P-wells. It is understood that this application is not limited thereto, and the material and doping type of the semiconductor substrate may be selected according to actual needs.

[0049] According to step S1, a dielectric stack structure 200 is formed on one side of the substrate 100. The dielectric stack structure 200 may include a plurality of alternately stacked insulating layers 201 and a plurality of gate sacrificial layers 202, such as... Figure 5 or Figure 6 As shown. The dielectric stack structure 200 can be implemented by one or more deposition processes. These deposition processes include, but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof. The materials for the insulating layer 201 and the gate sacrificial layer 202 can be selected from suitable materials known in the art. For example, the insulating layer 201 can be an oxide layer (such as silicon oxide), and the gate sacrificial layer 202 can be a nitride layer (such as silicon nitride). It should be understood that the number and thickness of the insulating layer 201 and the gate sacrificial layer 202 are not limited to... Figure 5 or Figure 6The quantities and thicknesses shown can be varied by those skilled in the art, without departing from the concept of this application, to allow for the creation of any number and thickness of insulating layers 201 and gate sacrificial layers 202 as needed. According to one embodiment of this application, a dielectric stack structure 200 may be formed on one side of the substrate 100. According to another embodiment of this application, multiple sequentially stacked dielectric stack structures 200 may be formed on one side of the substrate 100. For clarity and conciseness, the process is described herein using a three-dimensional memory including a dielectric stack structure 200 as an example.

[0050] The dielectric stack structure 200 may include a core region A, such as Figure 4 As shown. Core region A may be located, for example, in the central region of dielectric stack structure 200. Core region A may be a region including memory cells, and multiple memory cell strings (channel structures described herein) may be formed in core region A, for example.

[0051] According to step S2, a channel structure 210 is formed in the core region A, which penetrates the dielectric stack structure 200.

[0052] First, multiple channel vias can be formed in the core region A of the dielectric stack structure 200 using, for example, a dry / wet etching process. These channel vias can extend through the entire dielectric stack structure 200 and into the substrate 100. Then, a functional layer and a channel layer can be sequentially formed within the channel vias using, for example, one or more thin-film deposition processes (e.g., ALD, CVD, PVD, or combinations thereof). The functional layer can sequentially include, for example, a barrier layer, a charge trapping layer, and a tunneling layer. The materials of the charge barrier layer, charge trapping layer, and tunneling layer can sequentially include, for example, silicon oxide, silicon nitride, and silicon oxide to form an "ONO" (Oxide-Nitride-Oxide) structure. The material of the channel layer can include, for example, but not limited to, p-type doped polysilicon.

[0053] According to step S3, an auxiliary virtual structure 220 is formed, at least a portion of which is located at the edge of the core region A. According to one embodiment of this application, the method of forming the auxiliary virtual structure 220 may include: forming a mask with an auxiliary virtual via pattern on the side of the dielectric stack structure 200 away from the substrate 100; etching the dielectric stack structure 200 via the formed auxiliary virtual via pattern to form auxiliary virtual vias; and filling the formed auxiliary virtual vias with a first material to form the auxiliary virtual structure 220.

[0054] The processes for forming the aforementioned auxiliary dummy vias include, but are not limited to, photolithography, etching, and wet cleaning. In the formation of the auxiliary dummy via, the critical dimension (CD) of the auxiliary dummy via can be relatively large, for example, similar to the critical dimension of a virtual channel via located in step region B. The auxiliary dummy via can, for example, penetrate the dielectric stack structure 200 and extend into the substrate 100. In some embodiments, an etching process such as deep ion reactive etching (RIDE) can be used to form the auxiliary dummy via penetrating the dielectric stack structure 200 and extending into the substrate 100 in a single etching step. In other embodiments, wet etching, for example using phosphoric acid as an etchant, can be used to form the auxiliary dummy via penetrating the dielectric stack structure 200 and extending into the substrate 100 in a single etching step. In still other embodiments, the etching process can be stopped before the auxiliary dummy via reaches the substrate 100, and a stamping process can be performed subsequently to extend the auxiliary dummy via into the substrate 100.

[0055] In one exemplary embodiment, auxiliary dummy holes can be formed by performing photolithography and etching. For example, a mask layer and photoresist can be formed in the adjacent region of the core region A and the step region B of the dielectric stack structure 200. The photoresist is photolithographically etched to obtain patterned photoresist. Then, a hard mask layer is etched based on the patterned photoresist to obtain a patterned hard mask layer, on which an opening pattern for forming the shape and position of the auxiliary dummy hole is provided. The dielectric stack structure 200 is then etched using a dry etching process or a wet etching process to transfer the pattern into the dielectric stack structure 200. Afterward, the patterned hard mask layer is removed to form the auxiliary dummy hole in the region adjacent to the core region A and the step region B. During the formation of the auxiliary dummy hole, micro-over-etching (e.g., penetrating 0.2 nm to 1 nm into the substrate surface) can be performed to ensure complete removal of various defects on the surface of the substrate 100, such as native oxides, cracks, contaminant particles, etc.

[0056] In other embodiments, the critical dimension (CD) of the auxiliary dummy via can also be smaller. For example, the dimension of the auxiliary dummy via along the second direction D2 can be smaller than the dimension of the virtual channel via located in the step region along the second direction D2. The auxiliary dummy via may, for example, only penetrate a portion of the upper part of the dielectric stack structure 200, including several insulating layers 201 and gate sacrificial layers 202, without extending into the substrate 100. For example, the auxiliary dummy via may only penetrate a dozen or several dozen layers of insulating layers 201 and gate sacrificial layers 202 of the dielectric stack structure 200. The dry or wet etching process described above can also be used, and this application does not specifically limit it.

[0057] Next, the formed auxiliary dummy holes can be filled with the first material to form an auxiliary virtual structure 220. Thin film deposition processes such as CVD, PVD, ALD, or any combination thereof can be used. Depending on the depth to which the auxiliary dummy holes penetrate the dielectric stack structure 200, the formed auxiliary virtual structure 220 can, for example, penetrate the entire dielectric stack structure 200 and extend to the substrate 100, such as... Figure 5 As shown. This auxiliary virtual structure can provide good support and act as a guide during subsequent gate gap etching, allowing the etching to proceed downwards along the sidewalls of the auxiliary virtual structure 220 and preventing etching bends. In some embodiments, the formed auxiliary virtual structure 220 may, for example, only penetrate a portion of the upper part of the dielectric stack structure 200, including several insulating layers 201 and gate sacrificial layers 202, without extending into the substrate 100, such as... Figure 6 As shown. In one embodiment, the number of layers penetrated by the auxiliary virtual structure 220 may be less than half the total number of layers of the dielectric stack structure 200, for example, penetrating a dozen or several dozen layers at the top of the dielectric stack structure 200. This auxiliary virtual structure 220 can also play a good guiding role in the subsequent gate gap etching process. Since the bending deformation generated during the gate gap formation process mentioned above is mainly formed in the part including several insulating layers 201 and gate sacrificial layers 202 at the top of the dielectric stack structure 200, the formed auxiliary virtual structure 220 only penetrates the part of the upper part of the dielectric stack structure 200 including several insulating layers 201 and gate sacrificial layers 202, and can also effectively block the bending deformation that occurs during gate gap etching. In this case, the process of forming the auxiliary virtual structure 220 is relatively simple. For example, the etching depth required for the auxiliary virtual via is shallower, and the etching process and filling process can be relatively simplified. In some embodiments, a virtual channel structure 240 can also be appropriately added in this area as needed to provide sufficient support for the three-dimensional memory. The virtual channel structure 240 located in step area B will be further described below.

[0058] The three-dimensional memory may further include a stepped region B located around the core region A along the first direction D1. The fabrication method 1000 of the three-dimensional memory may further include forming a virtual channel structure 240 through the dielectric stack structure 200 in the stepped region B. The virtual channel structure 240 can provide support and protection for the stepped region B.

[0059] In one embodiment, the method of forming the virtual channel structure 240 may include: forming a virtual channel hole through the dielectric stack structure 200 in the step region B; and filling the formed virtual channel hole to form the virtual channel structure 240.

[0060] In one embodiment, the virtual channel via and the auxiliary virtual via can be formed in the same process step, for example, by etching using the same mask. Combining the method for forming the auxiliary virtual via described above, the virtual channel via can also be formed using, for example, dry / wet etching processes. Since the virtual channel via and the auxiliary virtual via can be formed simultaneously in the same process, there is no need to change the process flow of the original 3D memory fabrication method, thus saving costs. Of course, in another embodiment, the virtual channel via and the auxiliary virtual via can also be formed separately.

[0061] In one embodiment, the first material can simultaneously fill the auxiliary dummy vias and virtual channel vias in the same process step to form the auxiliary virtual structure 220 and the virtual channel structure 240. This filling process can be performed using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. Since the auxiliary virtual structure 220 and the virtual channel structure 240 are formed simultaneously in the same process, it is not necessary to change the process flow of the original 3D memory fabrication method, thus saving costs. Of course, in another embodiment, the auxiliary virtual structure 220 and the virtual channel structure 240 can also be formed separately in different processes. In yet another embodiment, the virtual channel structure 240 can also be filled with a different material than the auxiliary virtual structure 220; for example, insulating materials such as silicon oxide or silicon nitride can be used to fill the virtual channel structure 240.

[0062] In one embodiment, the first material may include an insulating material. In one embodiment, the etching rate of the first material may be lower than the etching rates of the insulating layer 201 and the gate sacrificial layer 202 under the same etching conditions. In one embodiment, the etching selectivity ratio of the insulating layer 201 to the first material and the etching selectivity ratio of the gate sacrificial layer 202 to the first material may both be not less than 1.6:1. In one embodiment, the first material may include atomic layer deposited silicon oxide under high temperature conditions. In another embodiment, the first material may include aluminum oxide. In yet another embodiment, the first material may also include hafnium oxide. It should be understood that the auxiliary virtual structure 220 may, during the formation of the gate gap, allow the etching of the dielectric stack structure 200 to proceed downwards along the sidewall of the auxiliary virtual structure 220 to prevent bending deformation of the gate gap at that location. The formation morphology of the auxiliary gate gap is such that, while the insulating layer 201 and the gate sacrificial layer 202 included in the dielectric stack structure 200 are etched away, the auxiliary virtual structure 220 cannot be etched. Furthermore, the auxiliary virtual structure 220 is located between the channel structure 210 and the common source structure 230 subsequently formed in the gate gap. In other words, the auxiliary virtual structure 220 separates the channel structure 210 and the common source structure 230 to prevent undesirable electrical connections between the channel structure 210 and the common source structure 230, which could lead to short circuits or leakage. Therefore, the auxiliary virtual structure 220 should have good insulation properties. Thus, the first material included in the auxiliary virtual structure 220 can be selected from suitable materials that meet the above conditions, and this application does not limit its application.

[0063] According to step S4, a common source structure 230 is formed through the dielectric stack structure 200. The common source structure 230 extends along the first direction D1, and the auxiliary virtual structure 220 electrically isolates the channel structure 210 and the common source structure 230.

[0064] In one embodiment, two auxiliary virtual structures 220 spaced apart from each other can be formed in a second direction D2 perpendicular to the first direction D1, according to the method described in step S3 above; then, a common source structure 230 is formed through the gap between the two auxiliary virtual structures 220. The method of forming the common source structure 230 may include: forming a gate gap that can penetrate the dielectric stack structure 200, extend along the first direction D1 and through the gap between the two auxiliary virtual structures 220; and forming the common source structure 230 within the formed gate gap.

[0065] In one embodiment, a mask with a gate slot pattern can be formed on the side of the dielectric stack structure 200 away from the substrate 100. Then, an etchant can be used to etch the dielectric stack structure 200 through the gate slot pattern to form the gate slots. The selected etchant has a lower etching rate for the auxiliary virtual structure 220 than for the dielectric stack 200, so that the etching proceeds downwards along the sidewalls of the auxiliary virtual structure 220, thereby creating a self-aligned effect within a small area, and ultimately resulting in a portion of the sidewalls of the gate slots being formed by the auxiliary virtual channel structure 220.

[0066] In this embodiment, there is no need to change the pattern of the mask used to form the gate slot pattern. Instead, an auxiliary virtual structure 220 is formed near the channel structure 210 at the edge of the core region A before forming the gate slot pattern. This auxiliary virtual structure 220 acts as a barrier layer, reducing or preventing the gate slot from shifting towards the channel structure 210 due to internal loads or other factors. Simultaneously, the gate slot pattern has a consistent width in the first direction, and the etching rate of each region of the stacked structure is relatively consistent, which helps improve the uniformity of the gate slot.

[0067] In one embodiment, before forming the common-source structure 230 within the gate gap, the method 1000 for fabricating a three-dimensional memory may further include: removing each gate sacrificial layer 202 in the dielectric stack structure 200 via the gate gap to form a sacrificial gap; and forming a gate layer 203 within the formed sacrificial gap. This further forms a stacked structure 200' including the gate layer 203 and an insulating layer 201, such as... Figure 15 As shown.

[0068] In this step, the gate gap can be used as an etchant channel to remove the gate sacrificial layer 202 in the dielectric stack structure 200 using, for example, isotropic etching. Isotropic etching can be performed using selective wet etching or vapor phase etching. In wet etching, an etching solution is used as the etchant, and the semiconductor structure is immersed in the etching solution. In vapor phase etching, an etching gas is used as the etchant, and the semiconductor structure is exposed to the etching gas. The insulating layer 201 and the gate sacrificial layer 202 in the dielectric stack structure 200 are silicon oxide (SiO2) and silicon dioxide (SiO2), respectively. X ) and silicon nitride (SiN) X In the case of wet etching, phosphoric acid solution can be used as the etchant, while in vapor phase etching, one or more of C4F8, C4F6, H2F2, and O2 can be used as the etchant. During the etching step, the etchant fills the gate gaps and gradually etches the gate sacrificial layer 202 into the dielectric stack structure 200. Due to the selectivity of the etchant, this etching removes the gate sacrificial layer 202 from the stack structure 200 while retaining the insulating layer 201.

[0069] After removing the gate sacrificial layer 202, a gate layer 203, comprising a gate barrier layer, an adhesive layer, and a metal layer, can be formed on the inner wall of the gate gap using one or more deposition processes such as CVD, PVD, and ALD. The gate barrier layer may include, but is not limited to, a high-dielectric-constant material such as alumina (Al2O3); the adhesive layer may be made of, but is not limited to, at least one of, tantalum nitride (TaN), titanium nitride (TiN), or Ti / TiN; and the metal layer may be made of, but is not limited to, tungsten (W).

[0070] In one embodiment, before forming the common source structure 230 within the formed gate gap, the corresponding region of the gate gap in the substrate 100 may be doped via the formed gate gap to form a common source region. For example, the common source region may be formed by implanting dopant atoms into the corresponding position of the substrate 100 via the gate gap using an ion implantation process.

[0071] Next, excess gate barrier layer, adhesive layer, and metal layer formed on the inner wall of the gate gap can be removed by, for example, wet etching, exposing the formed common source region. Then, an insulating layer 230-1 and a conductive layer 230-2 are sequentially formed within the gate gap to form a common source structure 230. The insulating layer 230-1 can contact the auxiliary virtual structure 220. The conductive layer 230-2 can contact the common source region. The conductive layer 230-2 can be formed using a conductive material, including but not limited to polysilicon or tungsten. The insulating layer 230-1 can be made of an insulating material, including but not limited to oxides. The insulating layer 230-1 serves to separate the conductive layer 230-2 from other structures, reducing the leakage risk of the 3D memory. In conjunction with the above, due to the blocking and guiding effect of the auxiliary virtual structure 220, the etching of the gate gap can have a good morphology without severe bending deformation; therefore, the formed common source structure 230 can also have a good morphology without severe bending deformation. Furthermore, the auxiliary virtual structure 220 formed by insulating material is located between the channel structure 210 and the formed common source structure 230, which can better play the role of spacing and insulation, and more effectively ensure that there will be no electrical connection between the channel structure 210 and the common source structure 230, and will not cause problems such as short circuit or leakage.

[0072] In summary, during the fabrication process of 3D memory, when forming the gate gap, the portion of the gate gap located at the edge region adjacent to the core region and the step region often deforms due to internal loads and other reasons, causing it to come into contact with the adjacent channel structure. Consequently, in the subsequent process of forming the common source structure, since the common source structure is filled with highly doped polysilicon, it is very easy for electrical connections to occur with the channel structure in the aforementioned deformed region, leading to problems such as short circuits or leakage, which seriously affects the electrical performance and product yield of 3D memory devices. The method for fabricating a three-dimensional memory provided in this application forms an auxiliary virtual structure in a deformable region near the step area of ​​the core region. Utilizing the principle that the etching rate of the internal filler is relatively slower than that of the dielectric stack structure, the etching of the gate gap proceeds downwards along the formed auxiliary virtual structure, thus playing a role in assisting morphology and avoiding the aforementioned deformation. It also achieves a certain degree of self-alignment within a small area of ​​its location, thereby preventing short circuits or leakage after filling the gate gap with highly doped polysilicon in subsequent processes. This effectively improves the reliability of the three-dimensional memory and is beneficial for increasing product yield.

[0073] It is understood that the design concept of this application, which uses auxiliary virtual structures to help openings or structures in three-dimensional storage to have a good morphology in areas prone to deformation, is not only applicable to areas such as the core area and the step area described in the text, but also to other areas of the three-dimensional storage, such as situations where other structures or other openings located or partially located in adjacent areas are prone to deformation due to structural differences between two adjacent parts. In such cases, auxiliary virtual structures can be set in the area, and the morphological function of the auxiliary structures or openings can be similar to that described in the text, and also fall within the scope of the concept of this application.

[0074] On the other hand, this application also provides a three-dimensional memory. This three-dimensional memory can be, but is not limited to, dynamic random access memory (DRAM) and flash memory (Flash). Flash memory includes NOR flash and NAND flash. In this embodiment, NAND flash is used as an example for description. The three-dimensional memory can be applied to communication products, consumer electronics, automotive products, aerospace products, artificial intelligence products, or big data, etc. Consumer electronics include, but are not limited to, mobile phones, computers, tablets, cameras, smart glasses, or gaming products, etc.

[0075] like Figure 14 and Figure 15As shown, according to one embodiment of this application, a three-dimensional memory may include: a substrate 100 and a stacked structure 200' located on one side of the substrate 100. The stacked structure 200' may include a core region A, which may be provided with a plurality of channel structures 210 penetrating the stacked structure 200'. The three-dimensional memory may further include an auxiliary virtual structure 220 and a common source structure 230, wherein at least a portion of the auxiliary virtual structure 220 may be located at the edge of the core region A; the common source structure 230 may penetrate the stacked structure 200' and extend along a first direction D1. The auxiliary virtual structure 220 may space the channel structures 210 and the common source structure 230.

[0076] In one embodiment, the three-dimensional memory may include at least two of the auxiliary virtual structures 220, wherein at least a portion of the auxiliary virtual structures 220 is located at the edge of the core region A and is spaced apart from each other. A common-source structure 230 penetrates the stacked structure and extends through the aforementioned spacing, wherein the direction of extension (i.e., the first direction D1) is perpendicular to the direction in which the channel structure 210 and the common-source structure 230 penetrate the stacked structure 200'. Figure 14 In the illustrated embodiment, the common source structure 230 can be divided into multiple channel structures 210. Multiple channel structures 210 can be provided on both sides of the common source structure 230 along the second direction D2, which is perpendicular to the first direction D1. At least one auxiliary virtual structure 220 can be provided on each side of the common source structure 230 along the second direction D2.

[0077] In one embodiment, a portion of the sidewall of the common source structure 230 may contact the auxiliary virtual structure 220. The common source structure 230 may include a conductive layer 230-2 and an insulating layer 230-1 located outside the conductive layer 230-2, wherein a portion of the insulating layer 230-1 of the common source structure 230 may contact the auxiliary virtual structure 220.

[0078] In one embodiment, the three-dimensional memory may further include a stepped region B located around the core region A along the first direction D1, and a plurality of virtual channel structures 240 located in the stepped region B that penetrate the stacked structure 200'.

[0079] In one embodiment, a portion of the auxiliary virtual structure 220 may be located in the step region B; that is, the auxiliary virtual structure 220 may be positioned across the boundary between the core region A and the step region B, with a portion located in the core region A and a portion located in the step region B, such as... Figure 4 or Figure 9 The process layout is shown in the diagram. In other embodiments, the auxiliary virtual structure 220 may be located only in the core region A, such as... Figure 13 As shown in the process layout diagram, the entire structure of the auxiliary virtual structure 220 is located at the edge adjacent to the core area A and the step area B.

[0080] In one embodiment, the virtual channel structure 240 may include the same first material as the auxiliary virtual structure 220.

[0081] In one embodiment, the first material may include an insulating material. The auxiliary virtual structure 220 can serve to separate the channel structure 210 and the common source structure 230 to prevent electrical connection between the channel structure 210 and the common source structure 230, which could lead to leakage or short circuit problems.

[0082] In one embodiment, the stacked structure 200' may include alternately stacked insulating layers 201 and gate layers 203. The etching rate of the first material under the same etching conditions may be lower than the etching rate of the insulating layer 201 in the stacked structure 200'.

[0083] Furthermore, the etching selectivity ratio of the insulating layer 201 to the first material in the stacked structure 200' can satisfy not less than 1.6:1.

[0084] Specifically, in one embodiment, for example, the insulating layer 201 in the stacked structure 200' is made of silicon oxide. The first material may include, for example, aluminum oxide or hafnium oxide, or may include atomic layer deposited silicon oxide formed under high temperature conditions.

[0085] In one embodiment, the auxiliary virtual structure 220 may have a large critical dimension, for example, its critical dimensions along the first direction D1 and the second direction D2 may be similar to the critical dimensions of the virtual channel structure 240 of the stepped region B along the first direction D1 and the second direction D2. The auxiliary virtual structure 220 may penetrate the stacked structure 200' and extend into the substrate 100. In this case, the auxiliary virtual structure 220 can effectively assist in the formation of the gate gap (see the description in the preceding method section) and can provide good support for this region of the stacked structure 200'.

[0086] In one embodiment, the auxiliary virtual structure 220 can have a smaller critical dimension; for example, its critical dimension in the second direction D2 can be smaller than the critical dimension of the virtual channel structure 240 in the step region B along the second direction D2. In this case, the auxiliary virtual structure 220 can penetrate only a portion of the stacked structure 200'; for example, the number of layers penetrated by the auxiliary virtual structure 220 is less than half the total number of layers in the stacked structure 200', penetrating only the insulating layer 201 and gate layer 203 included in a dozen or several dozen layers of the stacked structure 200'. In this case, the auxiliary virtual structure 220 can also better assist in the formation of the gate gap (see the description in the method section above), and since the depth of the auxiliary virtual via that needs to be etched is shallower, the process is simpler and easier to implement.

[0087] In one embodiment, the auxiliary virtual structure 220 may include a first portion extending along a first direction D1, the length of which may be greater than or equal to the length of a single virtual channel structure 240 along the first direction D1. Figure 9 or Figure 11 The process layout is shown in the diagram. The first part has a sufficient length along the first direction D1, which not only better assists in the formation of the gate gap and better blocks the contact between the common source structure 230 and the channel structure 210, but also provides a larger process window during the formation of the auxiliary virtual structure 220.

[0088] In one embodiment, the auxiliary virtual structure 220 may further include a second portion protruding relative to the first portion along the second direction D2 toward a side away from the common source structure 230. For example... Figure 12 The process layout is shown in the diagram. The protruding second portion can locally enhance the auxiliary virtual structure 220. For the auxiliary virtual structure 220 that penetrates the stacked structure 200' and extends to the substrate 100, the protruding second portion allows the auxiliary virtual structure 220 to provide greater support and protection for the stacked structure 200'. Specifically, in one embodiment, the second portion can be located at the center of the first portion along the first direction D1.

[0089] In one embodiment, the dimension of the first portion of the auxiliary virtual structure 220 along the second direction D2 can be less than or equal to the dimension of the single virtual channel structure 240 along the second direction D2. Similarly, the dimension of the second portion of the auxiliary virtual structure 220 along the second direction D2 can also be less than or equal to the dimension of the single virtual channel structure 240 along the second direction D2. The first or second portion needs to have sufficient dimensions along the second direction D2 to enable the auxiliary virtual structure 220 to better assist in the formation of the gate gap morphology and to provide a more guaranteed insulation gap between the channel structure 210 and the common source structure 230. Of course, it can also provide a larger process window during the formation of the auxiliary virtual structure 220. However, for the sake of saving space in the three-dimensional memory, especially the core region A of the three-dimensional memory, and for the sake of not affecting the normal layout of the channel structure 210 and the virtual channel structure 240, the dimension of the first or second portion of the auxiliary virtual structure 220 along the second direction D2 should not be too large.

[0090] The design of the number and arrangement of the auxiliary virtual structures 220 can be varied, and this application does not impose specific limitations on them. For example, in one embodiment, on the first side of the common source structure 230 along the second direction D2, M auxiliary virtual structures 220 can be arranged at intervals along the first direction D1, where M is a positive integer; on the second side of the common source structure 230 along the second direction D2, N auxiliary virtual structures 220 can be arranged at intervals along the first direction D1, where N is a positive integer.

[0091] Specifically, in one implementation, M ≥ 2 and M = N, such as Figure 7 and Figure 10 As shown in the process layout diagram, in Figure 7 In the middle, M = N = 4; in Figure 10 In this case, M = N = 2. Furthermore, in... Figure 7 and Figure 10 In the design shown, the M auxiliary virtual structures 220 located on the first side can correspond one-to-one with the N auxiliary virtual structures 220 located on the second side in the second direction D2. It is understood that in other embodiments, the M auxiliary virtual structures 220 located on the first side may also be partially or completely offset from the N auxiliary virtual structures 220 located on the second side in the second direction D2; this application does not limit this. It is understood that M and N may not be equal; for example, in another embodiment, M ≥ 2 and M ≠ N. Figure 8 As shown in the process layout, one of M and N has a value of 1, and the other has a value of 3.

[0092] In the three-dimensional memory provided according to this application, the auxiliary virtual structure 220 can help achieve a better morphology for the common source structure 230, so that the common source structure 230 does not produce or produces only small bending deformation at the edge of the core region A adjacent to the step region B. Furthermore, the auxiliary virtual structure 220 can space the channel structure 201 and the common source structure 230, which helps prevent electrical connection between the channel structure 201 and the common source structure 230 that could lead to leakage or short circuit, thus improving the electrical performance of the three-dimensional memory.

[0093] In another aspect, this application also provides a storage system. Figure 16 and Figure 17 These are schematic diagrams of storage systems 2000a and 2000b according to embodiments of this application. Figure 16 and Figure 17 As shown, storage system 2000a or 2000b may include at least one three-dimensional memory 2100 and controller 2200, wherein the three-dimensional memory 2100 may be a three-dimensional memory provided according to any of the embodiments described above in this application, and may accordingly include the structure described according to any of the exemplary embodiments described above in this application, which will not be repeated here.

[0094] The controller 2200 can be electrically connected to and control the three-dimensional memory 2100 via, for example, a channel (not shown), and the three-dimensional memory 2100 can perform operations based on the control of the controller 2200. Exemplarily, the three-dimensional memory 2100 can receive commands and addresses from the controller 2200 via, for example, a channel and access a region of a channel structure in response to the address. In other words, the three-dimensional memory 2100 can perform internal operations corresponding to commands on a region selected by an address.

[0095] In some examples, the controller 2200 and one or more three-dimensional memories 2100 can be integrated into various types of storage devices; in other words, storage systems 2000a and 2000b can be implemented and packaged into different types of final electronic products. Figure 16 In one example shown, the controller 2200 and a single three-dimensional memory 2100 may be integrated into a memory card-based storage system 2200a. The memory card may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a universal flash memory card (UFS), etc. The memory card-based storage system 2200a may also include a memory card connector 2300a that couples it to a host (not shown).

[0096] In such Figure 17 In another example shown, the controller 2200 and multiple three-dimensional memories 2100 may be integrated into a storage system 2000b, such as a solid-state drive (SSD). The solid-state drive (SSD) may also include an SSD connector 2300b that couples it to the host.

[0097] Although exemplary fabrication methods and structures of three-dimensional memories have been described herein, it is understood that one or more features may be omitted, substituted, or added to the structure of the three-dimensional memory. Furthermore, the layers and materials described are merely exemplary.

[0098] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, The method includes: A dielectric stack structure is formed on one side of a substrate, the dielectric stack structure including a core region; A channel structure is formed in the core region that penetrates the dielectric stack structure; Forming an auxiliary virtual structure, at least a portion of which is located at the edge of the core region; and A common source structure is formed, wherein the auxiliary virtual structure electrically isolates the channel structure and the common source structure; wherein forming the common source structure includes: forming a gate gap penetrating the dielectric stack structure, wherein a portion of the sidewall of the gate gap is formed by the auxiliary virtual structure; forming the common source structure within the gate gap, wherein a portion of the sidewall of the common source structure is in contact with the auxiliary virtual structure.

2. The method according to claim 1, wherein, Forming the auxiliary virtual structure includes: Form at least two auxiliary virtual structures, each having at least a portion located at the edge of the core area and spaced apart from each other; The common source structure forming the dielectric stack structure includes: A common source structure is formed that penetrates the dielectric stack structure and extends through the interval, wherein the direction of extension is perpendicular to the direction of penetration.

3. The method according to claim 1, wherein, Forming the auxiliary virtual structure includes: A mask template with an auxiliary dummy hole pattern is formed on the side of the dielectric stack structure away from the substrate; The dielectric stack structure is etched via the auxiliary dummy via pattern to form auxiliary dummy vias; and The auxiliary dummy hole is filled with the first material.

4. The method according to claim 3, wherein, The first material includes insulating material.

5. The method according to claim 4, wherein, The dielectric stack structure includes alternating insulating layers and gate sacrificial layers, wherein, The etching rate of the first material under the same etching conditions is lower than that of the insulating layer and the gate sacrificial layer.

6. The method according to claim 5, wherein, The first material includes at least one of alumina, hafnium oxide, and atomic layer deposited silicon oxide.

7. The method according to claim 3, wherein, The auxiliary dummy via penetrates the dielectric stack structure and extends to the substrate.

8. The method according to claim 3, wherein, The auxiliary dummy hole penetrates the dielectric stack structure.

9. The method according to claim 3, wherein, The dielectric stack structure also includes a stepped area located around the core area, and the mask template also has a virtual channel pattern; The method further includes: When forming the auxiliary dummy via the auxiliary dummy via pattern, the dielectric stack structure is simultaneously etched using the virtual channel pattern to form a virtual channel penetrating the dielectric stack structure in the step region; and When the auxiliary virtual structure is formed by filling the auxiliary dummy hole with the first material, the first material is also filled into the virtual channel at the same time to form a virtual channel structure.

10. The method of claim 1, wherein the dielectric stack structure comprises alternately stacked insulating layers and gate sacrificial layers, wherein, Before forming the common source structure within the gate gap, the method further includes: The gate sacrificial layer is removed via the gate gap to form a sacrificial gap; and A gate layer is formed within the sacrificial gap.

11. A three-dimensional memory, characterized in that, include: Substrate; A stacked structure is located on one side of the substrate and includes a core region; A channel structure is located in the core area and extends through the stacked structure; A common source electrode structure extends through the stacked structure, the common source electrode structure comprising a conductive layer and an insulating layer; An auxiliary virtual structure, at least a portion of which is located at the edge of the core region, wherein the auxiliary virtual structure electrically isolates the channel structure and the common source structure, and the auxiliary virtual structure is located on the side of the insulating layer away from the conductive layer and in contact with a portion of the sidewall of the insulating layer.

12. The three-dimensional memory according to claim 11, wherein, The three-dimensional memory includes: At least two of the auxiliary virtual structures are located at least partially at the edge of the core area and are spaced apart from each other; The common source structure penetrates the stacked structure and extends through the interval, wherein the direction of extension is perpendicular to the direction of penetration.

13. The three-dimensional memory according to claim 11, wherein, The materials forming the auxiliary virtual structure include insulating materials.

14. The three-dimensional memory according to claim 13, wherein, The stacked structure includes alternating insulating layers and gate layers. The etching rate of the insulating material under the same etching conditions is lower than that of the insulating layer.

15. The three-dimensional memory according to claim 14, wherein, The insulating material includes at least one of silicon oxide, aluminum oxide, and hafnium oxide.

16. The three-dimensional memory according to claim 11, wherein, The auxiliary virtual structure extends through the stacked structure and into the substrate, or the auxiliary virtual structure extends through a portion of the stacked structure.

17. The three-dimensional memory according to claim 12, wherein, The layered structure also includes a stepped area located around the core area, where multiple virtual channel structures are formed. The auxiliary virtual structure includes a first portion extending along the extending direction, the length of which is greater than or equal to the length of a single virtual channel structure along the extending direction.

18. The three-dimensional memory according to claim 17, wherein, The auxiliary virtual structure further includes a second portion, which protrudes relative to the first portion in a second direction perpendicular to the direction of extension toward a side away from the common source structure.

19. The three-dimensional memory according to claim 18, wherein, On the first side of the common source structure along the second direction, the three-dimensional memory includes M auxiliary virtual structures spaced apart along the extending direction, where M is a positive integer; as well as On the second side of the common source structure along the second direction, the three-dimensional memory includes N auxiliary virtual structures spaced apart along the extending direction, where N is a positive integer.

20. The three-dimensional memory according to claim 19, wherein, M≥2 and M=N, the M auxiliary virtual structures located on the first side and the N auxiliary virtual structures located on the second side correspond one-to-one with each other along the second direction.

21. A storage system, characterized in that, include: At least one three-dimensional memory as described in any one of claims 11-20; as well as A controller, electrically connected to at least one of the three-dimensional memories, is used to control at least one of the three-dimensional memories.

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