Image sensors and the electronic systems that include them

Abstract

An image sensor and an electronic system including the image sensor are provided. The image sensor includes a substrate having pixel regions defining a plurality of active regions. A first transistor includes a first gate electrode having a buried gate portion. The buried gate portion is buried in the substrate within the first active region selected from the plurality of active regions. A second transistor includes a second gate electrode that overlaps in a vertical direction with the buried gate portion on the first active region.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0151279, filed with the Korean Intellectual Property Office on November 12, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present invention relate to image sensors and electronic systems including image sensors, and more specifically, to image sensors including multiple transistors and electronic systems including image sensors. Background Technology

[0004] Image sensors, which acquire images and convert them into electrical signals, have been used in various fields to enable a wide range of devices such as digital cameras, portable video cameras, personal communication systems (PCS), gaming devices, security cameras, and medical miniature cameras. Summary of the Invention

[0005] An embodiment of the present invention provides an image sensor having a structure that can improve integration density while ensuring stable electrical characteristics of transistors even when the image sensor becomes highly integrated and pixel size is miniaturized.

[0006] Embodiments of the present invention also provide an electronic system including an image sensor having a structure that can improve integration density while ensuring stable electrical characteristics of the transistors even when the image sensor becomes highly integrated and the pixel size is miniaturized.

[0007] According to one aspect of the present invention, an image sensor is provided, including a substrate having pixel regions defining a plurality of active regions. A first transistor includes a first gate electrode having a buried gate portion. The buried gate portion is buried in the substrate in the first active region selected from the plurality of active regions. A second transistor includes a second gate electrode that overlaps in a vertical direction with the buried gate portion on the first active region.

[0008] According to one aspect of the present invention, an image sensor is provided, comprising: a substrate including a front side and a back side, the front side and the back side being opposing surfaces. The substrate includes a plurality of active regions defined between the front side and the back side at a location adjacent to the front side. A photodiode is formed in the substrate. A source follower transistor is located in a first active region selected from the plurality of active regions. The source follower transistor includes a first gate electrode. The first gate electrode includes a buried gate portion buried in the substrate and an upper gate portion contacting the buried gate portion. The upper gate portion overlaps with a first region of the buried gate portion in a vertical direction. A second transistor includes a second gate electrode overlapping with a second region of the buried gate portion in the first active region in the vertical direction. A transfer transistor is formed in a second active region selected from the plurality of active regions. A floating diffusion region is formed in the second active region. The floating diffusion region is connected to the upper gate portion of the source follower transistor. A microlens covers the back side of the substrate.

[0009] According to one aspect of the present invention, an electronic system is provided, including at least one camera module, the at least one camera module including an image sensor. A processor processes image data received from the at least one camera module. The image sensor includes a substrate having pixel regions defining a plurality of active regions. A first transistor includes a first gate electrode having a buried gate portion. The buried gate portion is buried in the substrate in the first active region selected from the plurality of active regions. A second transistor includes a second gate electrode overlapping the buried gate portion on the first active region in a vertical direction. Attached Figure Description

[0010] The above and other features of the present invention will become more readily understood by referring to the accompanying drawings, which describe embodiments of the invention in detail.

[0011] Figure 1 This is a block diagram of an image sensor according to an embodiment;

[0012] Figure 2 This is an example circuit diagram of a unit pixel included in an image sensor according to an embodiment;

[0013] Figure 3 This is an example circuit diagram of a unit pixel included in an image sensor according to an embodiment;

[0014] Figure 4 This is a planar layout illustrating an example structure of a unit pixel included in the pixel array of an image sensor according to an embodiment;

[0015] Figure 5A It is based on along Figure 4 A cross-sectional view of an example configuration of the section intercepted by line X1-X1';

[0016] Figure 5B It is based on along Figure 4 A cross-sectional view of an example configuration of the section intercepted by line X2-X2';

[0017] Figure 5C It is based on along Figure 4 A cross-sectional view of an example configuration of the section intercepted by line Y1-Y1';

[0018] Figures 6A to 6C This is a cross-sectional view showing an image sensor according to an embodiment;

[0019] Figure 7 This is a cross-sectional view showing an image sensor according to an embodiment;

[0020] Figure 8 This is a cross-sectional view showing an image sensor according to an embodiment;

[0021] Figure 9 This is a cross-sectional view showing an image sensor according to an embodiment;

[0022] Figure 10 This is a cross-sectional view showing an image sensor according to an embodiment;

[0023] Figures 11A to 20C This is a diagram illustrating a method for manufacturing an image sensor according to an embodiment, wherein, Figure 11A , Figure 12A ,……,and Figure 20A It is shown according to the process sequence and along Figure 4 A cross-sectional view of the region of the image sensor corresponding to the section intercepted by line X1-X1'. Figure 11B , Figure 12B ,……,and Figure 20B It is shown according to the process sequence and along Figure 4 The cross-sectional view of the image sensor region corresponding to the section intercepted by line X2-X2', and Figure 11C , Figure 12C ,……,and Figure 20C It is shown according to the process sequence and along Figure 4 A cross-sectional view of the region of the image sensor corresponding to the section intercepted by line Y1-Y1';

[0024] Figure 21A This is a block diagram of an electronic system according to an embodiment of the present invention; and

[0025] Figure 21B yes Figure 21AA detailed block diagram of the camera module included in the electronic system. Detailed Implementation

[0026] Embodiments of the inventive concept will be described more fully below with reference to the accompanying drawings. Throughout the drawings, the same reference numerals may refer to the same elements, and repeated descriptions may be omitted.

[0027] It should be understood that the terms "first," "second," "third," etc., are used herein to distinguish one element from another, and these elements are not limited by these terms. Thus, an element that is "first" in one embodiment may be described as a "second" element in another embodiment.

[0028] It should be understood that the description of features or aspects in each embodiment should generally be considered applicable to other similar features or aspects in other embodiments, unless the context clearly indicates otherwise.

[0029] As used in this article, the singular forms “a,” “one,” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0030] Figure 1 This is a block diagram of the image sensor 100 according to an embodiment.

[0031] Reference Figure 1 The image sensor 100 according to an embodiment may include a pixel array 10 and circuitry configured to control the pixel array 10. In an example embodiment, the circuitry configured to control the pixel array 10 may include a column driver 20, a row driver 30, a timing controller 40, and a readout circuitry 50.

[0032] Image sensor 100 can operate according to control commands received from image processor 70, and can convert light emitted from an external object into an electrical signal and output the electrical signal to image processor 70. Image sensor 100 may be a complementary metal-oxide-semiconductor (CMOS) image sensor.

[0033] The pixel array 10 may include a plurality of unit pixels PXU having a two-dimensional array structure arranged in a matrix along multiple rows and columns.

[0034] Each of the multiple unit pixel PXUs can have a photodiode. A photodiode can generate charge by receiving light emitted from an object. The image sensor 100 can perform autofocus by using the phase difference between pixel signals generated from the multiple photodiodes included in the multiple unit pixel PXUs. Each of the multiple unit pixel PXUs can include pixel circuitry for generating pixel signals from the charge generated by the photodiodes.

[0035] Column driver 20 may include, for example, a correlated double sampler (CDS), an analog-to-digital converter (ADC), etc. The CDS can be connected to the row selected by a row selection signal supplied by row driver 30, and performs correlated double sampling to detect the reset voltage and pixel voltage. The ADC can convert the reset voltage and pixel voltage, both detected by the CDS, into digital signals and send them to readout circuit 50.

[0036] The readout circuit 50 may include latches or buffer circuits, amplifier circuits, etc., capable of temporarily storing digital signals, and may temporarily store or amplify digital signals received from the column driver 20 to generate image data. The operating timing of the column driver 20, the row driver 30, and the readout circuit 50 may be determined by the timing controller 40, and the timing controller 40 may operate based on control commands sent from the image processor 70.

[0037] The image processor 70 can perform signal processing on the image data output from the readout circuit 50 and output the processed image data to a display device, or store the processed image data in a storage device such as a memory. When the image sensor 100 is installed on an autonomous vehicle, the image processor 70 can perform signal processing on the image data and send the processed image data to the main controller that controls the autonomous vehicle.

[0038] Figure 2 According to the embodiments Figure 1 An example circuit diagram of the unit pixel PXU included in the image sensor 100.

[0039] Reference Figure 2 , Figure 1 The pixel array 10 of the image sensor 100 shown includes multiple unit pixels PXU, each of which can constitute a 2-shared pixel including two photodiodes (i.e., the first photodiode PD1 and the second photodiode PD2).

[0040] In a unit pixel PXU, the first photodiode PD1 and the second photodiode PD2 can share a floating diffusion region FD by using the first transmission transistor TX1 and the second transmission transistor TX2. That is, the first transmission transistor TX1 corresponding to the first photodiode PD1 and the second transmission transistor TX2 corresponding to the second photodiode PD2 can share a floating diffusion region FD as a common drain region.

[0041] In a single pixel PXU, the first photodiode PD1 and the second photodiode PD2 can share the reset transistor RX, the source follower transistor SF, and the select transistor SX. The gate electrode of the reset transistor RX, the gate electrode of the first transmission transistor TX1, the gate electrode of the second transmission transistor TX2, and the gate electrode of the select transistor SX can be connected to drive signal lines RG, TG1, TG2, and SG, respectively. The first photodiode PD1 and the second photodiode PD2 can respectively constitute the source regions of the first transmission transistor TX1 and the second transmission transistor TX2. The floating diffusion region FD can constitute the common drain region of the first transmission transistor TX1 and the second transmission transistor TX2. The floating diffusion region FD can be connected to each of the source region of the reset transistor RX and the gate electrode of the source follower transistor SF. The drain regions of the reset transistor RX and the source follower transistor SF can be connected to the power supply voltage Vpix. The source region of the source follower transistor SF and the drain region of the select transistor SX can be shared. The output voltage Vout can be connected to the source region of the select transistor SX.

[0042] The first photodiode PD1 and the second photodiode PD2 can generate and accumulate charge proportionally to the amount of light incident from the outside. The gate electrode of the first transmission transistor TX1 and the gate electrode of the second transmission transistor TX2 can transfer the charge accumulated in the first photodiode PD1 and the second photodiode PD2 to the floating diffusion region FD. Complementary signals can be applied to the gate electrodes of the first transmission transistor TX1 and the second transmission transistor TX2 from drive signal lines TG1 and TG2, respectively, and charge can be transferred from either the first photodiode PD1 or the second photodiode PD2 to the floating diffusion region FD. The floating diffusion region FD can receive and store the charge generated by the first photodiode PD1 and the second photodiode PD2.

[0043] The floating diffusion region FD can be periodically reset by the reset transistor RX. When the reset transistor RX is turned on by a reset signal, the power supply voltage Vpix supplied to the reset transistor RX can be transferred to the floating diffusion region FD, and the charge accumulated in the floating diffusion region FD can be dissipated. Therefore, the floating diffusion region FD can be reset.

[0044] The gate electrode of the source follower transistor SF can be connected to the floating diffusion region FD. The source follower transistor SF can be used as a source follower buffer amplifier and can amplify the potential change of the floating diffusion region FD. The pixel signal amplified by the source follower transistor SF can be output to the output line Vout through the select transistor SX. The drain region of the source follower transistor SF can be connected to the power supply voltage Vpix, and the source region of the source follower transistor SF can be connected to the drain region of the select transistor SX.

[0045] The selector transistor SX can select the unit pixel PXU to be read in rows. When the selector transistor SX is turned on, the supply voltage Vpix connected to the drain region of the source follower transistor SF can be transferred to the drain region of the selector transistor SX.

[0046] Figure 3 This is an example circuit diagram of a unit pixel PXU that may be included in an image sensor 100 according to an embodiment.

[0047] Reference Figure 3 , Figure 1 The pixel array 10 of the image sensor 100 shown includes multiple unit pixels PXU, each of which can constitute a 4-shared pixel comprising four photodiodes (i.e., first to fourth photodiodes PD1, PD2, PD3, and PD4). Within a single unit pixel PXU, the first to fourth photodiodes PD1, PD2, PD3, and PD4 can share a floating diffusion region FD using first to fourth transmission transistors TX1, TX2, TX3, and TX4. The first transmission transistor TX1 corresponding to the first photodiode PD1, the second transmission transistor TX2 corresponding to the second photodiode PD2, the third transmission transistor TX3 corresponding to the third photodiode PD3, and the fourth transmission transistor TX4 corresponding to the fourth photodiode PD4 can share a floating diffusion region FD as a common drain region. Within a single unit pixel PXU, the first to fourth photodiodes PD1, PD2, PD3, and PD4 can share a reset transistor RX, a source follower transistor SF, and a select transistor SX. In response to signals applied to the first to fourth transfer transistors TX1, TX2, TX3 and TX4 via drive signal lines TG1, TG2, TG3 and TG4, charge can be transferred from one of the first to fourth photodiodes PD1, PD2, PD3 and PD4 to the floating diffusion region FD.

[0048] According to an embodiment, the image sensor 100 can have images that are all... Figure 2 or Figure 3The circuit configuration shown detects the reset voltage and pixel voltage for each unit pixel in the unit pixel PXU, and obtains the pixel signal by calculating the difference between the reset voltage and the pixel voltage. The pixel voltage can reflect the signal generated by the reset voltage and the pixel voltage. Figure 1 The voltage of the charge generated by the photodiode included in each of the multiple unit pixels PXU shown.

[0049] Although Figure 2 and Figure 3 Examples are shown of unit pixels (PXUs) in image sensor 100 constituting 2-shared pixels or 4-shared pixels, but embodiments of the present invention are not limited thereto. For example, unit pixels (PXUs) according to embodiments may constitute N-shared pixels comprising N photodiodes (where N is an integer of 2 or greater). For example, multiple unit pixels (PXUs) included in image sensor 100 may each comprise 2-shared pixels having two photodiodes, 4-shared pixels having four photodiodes, or 8-shared pixels having eight photodiodes.

[0050] Figure 4 This is a planar layout illustrating an example structure of a plurality of unit pixels (PXUs) included in an image sensor 100 according to an embodiment. Figure 5A It is based on along Figure 4 A cross-sectional view of an example configuration of the section cut by line X1-X1'. Figure 5B It is based on along Figure 4 A cross-sectional view of an example configuration of the section intercepted by line X2-X2'. Figure 5C It is based on along Figure 4 A cross-sectional view of an example configuration of the section intercepted by line Y1-Y1'. For ease of illustration, in Figure 4 and Figures 5A to 5C It shows Figure 1 The image sensor 100 shown includes some components of multiple unit pixels (PXU), and some components are omitted.

[0051] Reference Figure 4 and Figures 5A to 5C The image sensor 100 may include a substrate 102 having a plurality of pixel regions (PXRs). Within the substrate 102, the plurality of pixel regions (PXRs) may be defined by a pixel isolation insulating film 120. Each of the plurality of pixel regions (PXRs) may include a photodiode (PD) formed in the substrate 102. The plurality of pixel regions (PXRs) may be regions configured to sense light incident from outside the image sensor. In an example embodiment, the photodiode (PD) may be... Figure 2 Either the first photodiode PD1 or the second photodiode PD2 shown, or Figure 3 Any one of the first to fourth photodiodes PD1, PD2, PD3 and PD4 shown.

[0052] Substrate 102 may include a semiconductor layer. In an example embodiment, substrate 102 may include a semiconductor layer doped with p-type impurities. For example, substrate 102 may include a semiconductor layer comprising silicon (Si), germanium (Ge), silicon-germanium (SiGe), group II-VI compound semiconductors, group III-V compound semiconductors, or combinations thereof, or may include a silicon-on-insulator (SOI) substrate. In an example embodiment, substrate 102 may include a p-type epitaxial semiconductor layer epitaxially grown from a p-type bulk silicon substrate. Substrate 102 may have a front side 102A and a back side 102B as opposing surfaces.

[0053] The pixel isolation insulating film 120 may have a planar structure surrounding the photodiode PD. The pixel isolation insulating film 120 may extend from the front side 102A to the back side 102B of the substrate 102 in the thickness direction of the substrate 102. In an example embodiment, the pixel isolation insulating film 120 may include silicon oxide, silicon nitride, silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), polycrystalline silicon, metal, metal nitride, metal oxide, borosilicate glass (BSG), silicon phosphosilicate glass (PSG), borosilicate-phosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PE-TEOS), fluorosilicone glass (FSG), carbon-doped silicon oxide (CDO), organosilicon glass (OSG), air, or combinations thereof. Hereinafter, the term "air" may refer to other gases that may be present in the atmosphere or during the manufacturing process. For example, tungsten (W), copper (Cu), or combinations thereof may be provided as metals that can be included in the pixel isolation insulating film 120. The metal nitrides that can be included in the pixel isolation insulating film 120 may include, for example, titanium nitride (TiN), tantalum nitride (TaN), or combinations thereof. The metal oxides that can be included in the pixel isolation insulating film 120 may include, for example, indium tin oxide (ITO), aluminum oxide (Al2O3), or combinations thereof.

[0054] In each pixel region PXR, multiple active regions (e.g., first to third active regions AC1, AC2, and AC3) may be defined by device isolation trench 114. Device isolation trench 114 may be filled with device isolation insulating film 116. Device isolation insulating film 116 may include, for example, a silicon oxide film, a silicon nitride film, or a combination thereof.

[0055] Multiple transistors and wiring structures MS may be located on the front side 102A of the substrate 102. In an example embodiment, the multiple transistors may include those referenced above. Figure 2 The description includes a first transfer transistor TX1, a second transfer transistor TX2, a reset transistor RX, a source follower transistor SF, and a select transistor SX. In an example embodiment, the plurality of transistors may include those referenced above. Figure 3 The first to fourth transmission transistors TX1, TX2, TX3, and TX4, the reset transistor RX, the source follower transistor SF, and the select transistor SX are described. Multiple unit pixels PXU may include the source follower transistor SF, the select transistor SX, and the transmission transistor TX.

[0056] In a plurality of unit pixels (PXU), a plurality of active regions (e.g., first to third active regions AC1, AC2, and AC3) may be defined in a substrate 102. A first trench T1 and a second trench T2, which may intersect each other, may be formed in the first active region AC1 selected from the first to third active regions AC1, AC2, and AC3. The first active region AC1 of the substrate 102 may include a fin region 102F, which protrudes upward from the substrate 102 in a vertical direction (Z direction). The bottom surface of the first trench T1 may have a rough shape to define the fin region 102F of the substrate 102, and the width of the fin region 102F in a second lateral direction (Y direction) may be defined by the bottom surface of the first trench T1.

[0057] The lowest portion of the bottom surface of the first trench T1 can be at a first horizontal height LV1, which is spaced apart from the front surface 102A of the substrate 102 facing inwards by a first vertical distance. The portion of the bottom surface of the first trench T1 that contacts the top surface of the fin region 102F can be at a second horizontal height LV2, which is spaced apart from the front surface 102A of the substrate 102 facing inwards by a second vertical distance. The second vertical distance can be less than the first vertical distance. The second trench T2 can be closer to the front surface 102A of the substrate 102 than the first trench T1. The lowest portion of the second trench T2 can be at a third horizontal height LV3, which is higher than the second horizontal height LV2 and lower than the horizontal height of the front surface 102A of the substrate 102. In the first lateral direction (X direction), the width W11 of the first trench T1 can be less than the width W12 of the second trench T2.

[0058] A source follower transistor SF can be formed in a first active region AC1. The source follower transistor SF may include a gate dielectric film 122 buried in a substrate 102 within the first active region AC1, and a gate electrode SFG formed on the gate dielectric film 122. The gate dielectric film 122 of the source follower transistor SF may conformally cover the inner surface of the first trench T1. The gate electrode SFG of the source follower transistor SF may include a buried gate portion 126 and an upper gate portion 136. The buried gate portion 126 may be buried in the substrate 102 within the first active region AC1. The upper gate portion 136 may protrude upwards from the top surface of the buried gate portion 126 in a vertical direction (Z direction) to a horizontal height higher than the horizontal height of the front surface 102A of the substrate 102. The buried gate portion 126 of the source follower transistor SF may fill the first trench T1 on the gate dielectric film 122. A gate dielectric film 122 may be located between the first active region AC1 and the buried gate portion 126. The top surface of the buried gate portion 126 may extend laterally at a third horizontal height LV3 located between the horizontal height of the front side 102A of the substrate 102 and the second horizontal height LV2. A portion of the upper gate portion 136 of the source follower transistor SF may be buried in the substrate 102 and fill a portion of the second trench T2. The bottom surface of the upper gate portion 136 may contact the top surface of the buried gate portion 126 at a horizontal height lower than the horizontal height of the front side 102A of the substrate 102. The buried gate portion 126 and the upper gate portion 136 of the source follower transistor SF may overlap with the photodiode PD in the vertical direction (Z direction).

[0059] The selector transistor SX may include a gate dielectric film 132 and a gate electrode SXG sequentially stacked on the first active region AC1. The gate electrode SXG of the selector transistor SX may overlap with the buried gate portion 126 of the source follower transistor SF in the vertical direction (Z direction). The lowest surface of the gate electrode SXG of the selector transistor SX may be at a horizontal height below the horizontal height of the front surface 102A of the substrate 102 and facing the buried gate portion 126 of the source follower transistor SF, with the gate dielectric film 132 located between the lowest surface of the gate electrode SXG and the buried gate portion 126. The gate electrode SXG of the selector transistor SX may include a portion buried in the substrate 102 to partially fill the second trench T2, and a portion protruding upward in the vertical direction (Z direction) to a horizontal height above the horizontal height of the front surface 102A of the substrate 102.

[0060] A pair of impurity regions 150 may be formed in the first active region AC1. The pair of impurity regions 150 may be separated from each other in a first lateral direction (X direction), with the gate electrode SXG of the select transistor SX and the gate electrode SFG of the source follower transistor SF located between the pair of impurity regions 150. The pair of impurity regions 150 may serve as the source and drain of each of the select transistor SX and the source follower transistor SF, respectively.

[0061] In the gate electrode SFG of the source follower transistor SF, the upper gate portion 136 can be separated from the gate electrode SXG of the select transistor SX in a second lateral direction (Y direction) perpendicular to the first lateral direction (X direction). In the second lateral direction (Y direction), the upper gate portion 136 of the source follower transistor SF can face the gate electrode SXG of the select transistor SX. The gate electrode SFG of the source follower transistor SF and the gate electrode SXG of the select transistor SX can overlap with the photodiode PD in the vertical direction (Z direction).

[0062] In the example embodiment, both the gate electrode SFG of the source follower transistor SF and the gate electrode SXG of the select transistor SX can comprise doped polysilicon. For example, both the gate electrode SFG and the gate electrode SXG can comprise polysilicon doped with N-type impurities such as phosphorus (P) or arsenic (As). In the example embodiment, the first doping concentration of the gate electrode SXG and the second doping concentration of the upper gate portion 136 of the gate electrode SFG can both be higher than the third doping concentration of the buried gate portion 126 of the gate electrode SFG. The first doping concentration and the second doping concentration can be approximately equal to or similar to each other. For example, the first to third doping concentrations can all be approximately 1 × 10⁻⁶. 11 / cm 3 To approximately 1×10 15 / cm 3 The concentration can be selected within the range of the third doping concentration, and both the first and second doping concentrations can be about 1.1 to about 1.3 times the third doping concentration.

[0063] The gate dielectric film 122 of the source follower transistor SF may be located between the first active region AC1 and the buried gate portion 126. The gate dielectric film 132 of the selector transistor SX may include a portion located between the first active region AC1 and the gate electrode SXG, and a portion located between the gate electrode SXG and the gate electrode SFG of the source follower transistor SF. The gate electrode SXG of the selector transistor SX may be separated from the buried gate portion 126 of the source follower transistor SF in the vertical direction (Z direction), and the gate dielectric film 132 is located between the gate electrode SXG and the buried gate portion 126.

[0064] The gate dielectric film 122 of the source follower transistor SF and the gate dielectric film 132 of the select transistor SX can both include, but are not limited to, a silicon oxide film.

[0065] The thickness of the gate dielectric film 132 of the selector transistor SX can be greater than the thickness of the gate dielectric film 122 of the source follower transistor SF. For example, the thickness of the gate dielectric film 132 of the selector transistor SX can be about 1.1 to about 2.5 times the thickness of the source follower transistor SF, but is not limited thereto.

[0066] like Figure 5A As shown, in the first lateral direction (X direction), the width WG1 of the buried gate portion 126 of the source follower transistor SF can be smaller than the width WG2 of the gate electrode SXG of the select transistor SX.

[0067] like Figure 5C As shown, the fin region 102F formed in the first active region AC1 can protrude upward in the vertical direction (Z direction) toward the buried gate portion 126, which constitutes the gate electrode SFG of the source follower transistor SF. The buried gate portion 126 may include a protrusion 126P that protrudes toward the interior of the substrate 102 in the vertical direction (Z direction) away from the front side of the substrate 102. The protrusion 126P included in the buried gate portion 126 of the source follower transistor SF can cover the sidewalls of the fin region 102F. The sidewalls and top surface of the fin region 102F can be surrounded by the buried gate portion 126 of the source follower transistor SF, and the gate dielectric film 122 is located between the sidewalls and top surface of the fin region 102F and the buried gate portion 126. The channel length of the source follower transistor SF can be increased due to the fin region 102F formed in the first active region AC1. Therefore, even when the image sensor 100 becomes highly integrated and the size of the pixel region PXR is miniaturized, problems caused by the short-channel effect (SCE) of the source follower transistor SF can be prevented. Furthermore, even if noise is generated in the gate dielectric film 122 due to random charge trapping or releasing caused by current fluctuations in the channel of the source follower transistor SF, noise-induced characteristic degradation can be prevented. Moreover, by maintaining linearity between low-light and high-light signals during signal synthesis, pixel response characteristic degradation can be prevented.

[0068] In the first active region AC1, the select transistor SX can overlap with the buried gate portion 126 of the source follower transistor SF in the vertical direction (Z direction). The select transistor SX can have a dual-gate transistor structure, wherein channels are formed on both sides of the buried gate portion 126 in the first lateral direction (X direction). Therefore, the amount of current flowing through the select transistor SX can be increased. Therefore, even when the select transistor SX is reduced in size, problems caused by leakage current can be prevented, and thus, the performance of the select transistor SX will not degrade.

[0069] The top surface of the upper gate portion 136 of the source follower transistor SF and the top surface of the gate electrode SXG of the select transistor SX can be covered by multiple insulating masking patterns 134. The sidewalls of the upper gate portion 136 of the source follower transistor SF, the sidewalls of the gate electrode SXG of the select transistor SX, and the sidewalls of the multiple insulating masking patterns 134 can be covered by multiple insulating spacers 140. In the second lateral direction (Y direction), the space between the upper gate portion 136 of the source follower transistor SF and the gate electrode SXG of the select transistor SX can be filled with insulating spacers 140. For ease of explanation, Figure 4 A portion of the insulating spacer 140 is shown (i.e., only the portion of the insulating spacer 140 located between the upper gate portion 136 of the source follower transistor SF and the gate electrode SXG of the select transistor SX). Both the plurality of insulating masking patterns 134 and the plurality of insulating spacers 140 may comprise, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof.

[0070] Contact plug 164 can be connected to each of the top surface of the upper gate portion 136 of the source follower transistor SF and the top surface of the gate electrode SXG of the select transistor SX.

[0071] The transfer transistor TX may be located in the second active region AC2 among the first to third active regions AC1, AC2 and AC3. The transfer transistor TX may include a gate electrode TXG. A portion of the gate electrode TXG may be buried in the substrate 102, and a recessed channel may be formed in the transfer transistor TX along the recessed surface of the portion of the second active region AC2 surrounding the gate electrode TXG buried in the substrate 102.

[0072] like Figure 5C As shown, the impurity region 152 can be formed in the second active region AC2 on one side of the transfer transistor TX. The impurity region 152 can be a floating diffusion region FD. A contact plug 164 can be connected to the impurity region 152. The transfer transistor TX can form a reference. Figure 2 The first transmission transistor TX1 and the second transmission transistor TX2 described herein may constitute a reference. Figure 3Any one of the first to fourth transmission transistors TX1, TX2, TX3 and TX4 described.

[0073] Impurity region (reference) Figure 4 Impurity region 154 can be formed in the third active region AC3 among the first to third active regions AC1, AC2 and AC3, and contact plug 164 can be connected to this impurity region 154. Impurity region 154 can be a grounded region, and contact plug 164 connected to impurity region 154 can be a grounded contact plug. The plurality of impurity regions 150, 152 and 154 formed in the first to third active regions AC1, AC2 and AC3 can be N-type impurity regions.

[0074] Multiple transistors, including a source follower transistor SF, a select transistor SX, and a transfer transistor TX, located on the front side 102A of the substrate 102, can be covered by an interlayer insulating film 160.

[0075] The electrical signal converted by the photodiode PD can be processed by a plurality of transistors and a wiring structure MS located on the front side 102A of the substrate 102. The wiring structure MS may include: a plurality of contact plugs 164 selectively connected to a plurality of transistors including a source follower transistor SF, a select transistor SX, and a transmit transistor TX; a plurality of wires 168 and 172 selectively connected to the plurality of transistors via the contact plugs 164; and a plurality of interlayer insulating films 170 and 174 covering the plurality of wires 168 and 172. In an example embodiment, the upper gate portion 136 of the gate electrode SFG of the source follower transistor SF and the floating diffusion region FD can be electrically connected to each other via the plurality of contact plugs 164 and wires 168.

[0076] The plurality of contact plugs 164 and the plurality of wires 168 and 172 may each comprise a metal, a conductive metal nitride, or a combination thereof. For example, the plurality of contact plugs 164 and the plurality of wires 168 and 172 may each comprise copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), zirconium nitride (ZrN), tungsten nitride (WN), or a combination thereof, but are not limited thereto. The plurality of interlayer insulating films 160, 170, and 174 may each comprise, for example, an oxide film, a nitride film, or a combination thereof.

[0077] The number and arrangement of interlayer insulating films 160, 170, and 174, and the number and arrangement of multiple conductors 168 and 172 are not limited to... Figures 5A to 5CThe examples shown are for illustrative purposes only and can be modified in various ways according to the embodiments. The multiple conductors 168 and 172 in the wiring structure MS may include wiring connected to multiple transistors electrically connected to photodiodes PD formed in the pixel region PXR. The multiple transistors may include reference... Figure 2 The first transfer transistor TX1 and the second transfer transistor TX2, the reset transistor RX, the source follower transistor SF, and the select transistor SX are described, or may include references. Figure 3 The description includes first to fourth transmission transistors TX1, TX2, TX3, and TX4, a reset transistor RX, a source follower transistor SF, and a select transistor SX. In the example embodiment, the reset transistor RX can be arranged along the row or column direction around multiple pixel regions PXR. The electrical signal converted by the photodiode PD can be processed by the wiring structure MS. Regardless of the arrangement of the photodiode PD, the arrangement of the multiple conductors 168 and 172 can be freely changed.

[0078] A light-transmitting structure LTS can be disposed on the back side 102B of substrate 102. The light-transmitting structure LTS may include a first planarization film 182, a color filter CF, a second planarization film 184, a microlens ML, and a protective cover film 188, sequentially stacked on the back side 102B. The microlens ML may be protected by the protective cover film 188. The light-transmitting structure LTS can converge and filter light incident from the outside and provide the converged and filtered light to the pixel region PXR. A photodiode PD in a pixel region PXR can be covered by a microlens ML. The microlens ML may have an outwardly convex shape to converge light incident on the photodiode PD. A unit pixel PXU may have a back illumination (BSI) structure that receives light from the back side 102B of substrate 102.

[0079] In the light-transmitting structure LTS, the first planarization film 182 can serve as a buffer film, which can prevent or reduce damage to the substrate 102 during the manufacturing process of the image sensor 100. The first planarization film 182 and the second planarization film 184 may each include, for example, a silicon oxide film, a silicon nitride film, a resin, or a combination thereof, but are not limited thereto.

[0080] In an example embodiment, the color filter CF may include a red color filter, a green color filter, a blue color filter, or a white color filter. The white color filter may be a transparent color filter that transmits light in the visible wavelength range. Figure 1 The pixel array 10 shown may include multiple color filter groups, wherein red, green, blue, and white color filters are arranged in a 2×2 two-dimensional array to form a color filter group. Multiple color filter groups may be arranged in a matrix along multiple rows and columns. In the example embodiment, the color filter CF may have other colors, such as cyan, magenta, or yellow.

[0081] The light-transmitting structure LTS may further include an anti-reflective film 186 formed on the first planarization film 182. The anti-reflective film 186 may be disposed on the edge portion of the pixel region PXR at a location overlapping the pixel isolation insulating film 120 defining the pixel region PXR in the vertical direction (Z direction). The top surface and sidewalls of the anti-reflective film 186 may be covered by a color filter CF. The anti-reflective film 186 can prevent incident light passing through the color filter CF from being laterally reflected or scattered. For example, the anti-reflective film 186 can prevent photons reflected or scattered at the interface between the color filter CF and the first planarization film 182 from moving to another pixel region. The anti-reflective film 186 may include a metal. For example, the anti-reflective film 186 may include tungsten (W), aluminum (Al), copper (Cu), or combinations thereof.

[0082] Although Figure 4 and Figures 5A to 5C The image sensor 100 shows a partial region of multiple unit pixel PXUs, but in an embodiment, the substrate 102 of the image sensor 100 may include: having a reference Figure 1 The description includes a region of multiple unit pixels (PXUs), a peripheral circuitry region surrounding the multiple unit pixels (PXUs), and a pad region (not shown). The peripheral circuitry region can include various types of circuitry configured to control the multiple unit pixels (PXUs). For example, the peripheral circuitry region can include multiple transistors that can be driven to provide a constant signal to a photodiode (PD) formed in the pixel region (PXR) or to control an output signal from the photodiode (PD). For example, the multiple transistors can constitute various types of logic circuitry such as a timing generator, a row decoder, a row driver, a CDS, an ADC, a latch, and a column decoder. The pad region can include conductive pads electrically connected to the multiple unit pixels (PXUs) and the circuitry in the peripheral circuitry region. The conductive pads can serve as connection terminals configured to supply power and signals from the outside to the multiple unit pixels (PXUs) and the circuitry in the peripheral circuitry region.

[0083] Figures 6A to 6C This is a diagram illustrating an image sensor 200 according to an embodiment. Figure 6A Is along Figure 4 A cross-sectional view of an example configuration of the region of the image sensor 200 corresponding to the section intercepted by line X1-X1'. Figure 6B Is along Figure 4 A cross-sectional view of an example configuration of the region of the image sensor 200 corresponding to the section intercepted by line X2-X2'. Figure 6C Is along Figure 4 A cross-sectional view of an example configuration of the image sensor 200 region corresponding to the section intercepted by line Y1-Y1'. For ease of illustration, the description... Figures 6A to 6CWhen, the reference to the previous reference can be omitted. Figures 1 to 5C Further description of the components and technologies described.

[0084] Reference Figures 6A to 6C The image sensor 200 has a reference Figures 1 to 5C The image sensor 100 described has a substantially the same configuration. However, in the image sensor 200, the source follower transistor SF2 may include: a gate dielectric film 222 buried in the substrate 102 in the first active region AC1, and a gate electrode SFG2 formed on the gate dielectric film 222. The gate dielectric film 222 of the source follower transistor SF2 may conformally cover the inner surface of the first trench T21. The gate electrode SFG2 of the source follower transistor SF2 may include a buried gate portion 226 buried in the substrate 102 in the first active region AC1 and an upper gate portion 136 in contact with the top surface of the buried gate portion 226.

[0085] The first trench T21, the gate dielectric film 222, and the buried gate portion 226 may have the same characteristics as referenced. Figures 5A to 5C The first trench T1, gate dielectric film 122, and buried gate portion 126 are described to have substantially the same configuration. However, the bottom surface of each of the first trench T21, gate dielectric film 222, and buried gate portion 226 may extend substantially flat in the lateral direction. The bottom surface of the first trench T21 may extend substantially flat at a first horizontal height LV21 at a location remote from the front side 102A of the substrate 102. In this embodiment, the first active region AC1 does not include the fin region (see reference). Figure 5C (102F in the middle).

[0086] In the first lateral direction (X direction), the width W21 of the first trench T21 can be smaller than the width W12 of the second trench T2. In the first lateral direction (X direction), the width WG21 of the buried gate portion 226 of the source follower transistor SF2 can be smaller than the width WG2 of the gate electrode SXG of the select transistor SX.

[0087] Figure 7 This is a cross-sectional view of the image sensor 300 according to an embodiment. Figure 7 It shows the relationship with along Figure 4 The cross-sectional configuration of the image sensor 300 region corresponding to the cross-section intercepted by line X1-X1'. For ease of explanation, in the description Figure 7 When, the reference to the previous reference can be omitted. Figures 1 to 5C Further description of the components and technologies described.

[0088] Reference Figure 7 The image sensor 300 has a reference Figures 1 to 5CThe image sensor 100 described has a substantially the same configuration. However, in the image sensor 300, the source follower transistor SF3 may include: a gate dielectric film 322 buried in the substrate 102 in the first active region AC1, and a gate electrode SFG3 formed on the gate dielectric film 322. The dielectric film 322 of the source follower transistor SF3 may conformally cover the inner surface of the first trench T31. The gate electrode SFG3 of the source follower transistor SF3 may include: a buried gate portion 326 buried in the substrate 102 in the first active region AC1, and an upper gate portion (see reference ) contacting the top surface of the buried gate portion 326. Figure 5C (136 in the middle).

[0089] The first active region AC1 may include a fin region 302F that protrudes upward in the vertical direction (Z direction) toward the gate electrode SFG3 of the source follower transistor SF3. The width of the fin region 302F in the lateral direction may be defined by a first trench T31. The buried gate portion 326 of the source follower transistor SF3 may include a protrusion 326P that protrudes in the vertical direction (Z direction) toward the interior of the substrate 102 in a direction away from the front side 102A of the substrate 102. The protrusion 326P may cover two sidewalls of the fin region 302F in the first lateral direction (X direction). The sidewalls and top surface of the fin region 302F may be surrounded by the buried gate portion 326 of the source follower transistor SF3, and a gate dielectric film 322 is located between the sidewalls and top surface of the fin region 302F and the buried gate portion 326. The channel length of the source follower transistor SF3 may be increased due to the fin region 302F. Therefore, even when the image sensor 300 becomes highly integrated and the size of the pixel region PXR is miniaturized, problems caused by SCE of the source follower transistor SF3 can be prevented, and characteristic degradation due to noise in the channel of the source follower transistor SF3 can be prevented. Furthermore, pixel response characteristic degradation can be prevented by maintaining linearity between the low-light and high-light signals during signal synthesis.

[0090] In the first lateral direction (X direction), the width WG31 of the buried gate portion 326 of the source follower transistor SF3 can be smaller than the width WG2 of the gate electrode SXG of the select transistor SX. The detailed configuration of the first trench T31, the gate dielectric film 322, and the buried gate portion 326 can be referenced. Figures 5A to 5C The detailed configurations of the first trench T1, the gate dielectric film 122, and the buried gate portion 126 are substantially the same.

[0091] Figure 8 This is a cross-sectional view of the image sensor 400 according to an embodiment. Figure 8 It shows the relationship with along Figure 4The cross-sectional configuration of the image sensor 400 corresponding to the cross-section intercepted by line X1-X1'. For ease of explanation, in the description... Figure 8 At that time, the reference to the previous point can be omitted. Figures 1 to 6C Further description of the components and technologies described.

[0092] Reference Figure 8 The image sensor 400 has a reference Figures 6A to 6C The image sensor 200 described has a substantially the same configuration. However, in the image sensor 400, the source follower transistor SF4 may include: a gate dielectric film 422 buried in the substrate 102 in the first active region AC1, and a gate electrode SFG4 formed on the gate dielectric film 422. The gate dielectric film 422 of the source follower transistor SF4 may conformally cover the inner surface of the first trench T41. The gate electrode SFG4 of the source follower transistor SF4 may include: a buried gate portion 426 buried in the substrate 102 in the first active region AC1, and an upper gate portion (see reference ) contacting the top surface of the buried gate portion 426. Figure 5C (136 in the middle).

[0093] The first trench T41, the gate dielectric film 422, and the buried gate portion 426 may have the same characteristics as referenced. Figures 6A to 6C The first trench T21, gate dielectric film 222, and buried gate portion 226 are described in substantially the same configuration. However, in the first lateral direction (X direction), the width W4 of the first trench T41 can be the same as the width of the second trench T2 (see reference). Figure 6A The widths of the buried gate portion 426 of the source follower transistor SF4 (WG41) are approximately equal to or similar to those of the gate electrode SXG of the select transistor SX. In the first lateral direction (X direction), the width of the buried gate portion 426 of the source follower transistor SF4 (WG41) may be smaller than the width of the gate electrode SXG of the select transistor SX (WG2).

[0094] Figure 9 This is a cross-sectional view of the image sensor 500 according to an embodiment. Figure 9 It shows the relationship with along Figure 4 The cross-sectional configuration of the image sensor 500 region corresponding to the cross-section intercepted by line Y1-Y1'. For ease of explanation, in the description... Figure 9 When, the reference to the previous reference can be omitted. Figures 1 to 6C Further description of the components and technologies described.

[0095] Reference Figure 9 The image sensor 500 has a reference Figures 6A to 6CThe image sensor 200 described has a substantially the same configuration. However, in the image sensor 500, the gate electrode SFG5 of the source follower transistor SF5 may include a buried gate portion 526 instead of a buried gate portion 226. The buried gate portion 526 may include polysilicon doped with N-type impurities. The doping concentration of each of the buried gate portion 526 and the upper gate portion 136 of the gate electrode SFG5 may be approximately equal to or similar to the doping concentration of the gate electrode SXG of the select transistor SX. The doping concentration of each of the buried gate portion 526 and the upper gate portion 136 of the gate electrode SFG and the gate electrode SXG of the select transistor SX may be approximately 1 × 10⁻⁶. 11 / cm 3 To approximately 1×10 15 / cm 3 Choose from the range.

[0096] A detailed description of the buried gate portion 526 of the source follower transistor SF5 can be found in the reference. Figures 6A to 6C The detailed description of the buried gate portion 226 is essentially the same. Therefore, further repetitive descriptions are omitted.

[0097] Figure 10 This is a cross-sectional view of the image sensor 600 according to an embodiment. Figure 10 It shows the relationship with along Figure 4 The cross-sectional configuration of the image sensor 600 corresponding to the cross-section intercepted by line Y1-Y1'. For ease of explanation, in the description... Figure 10 When, the reference to the previous reference can be omitted. Figures 1 to 6C Further description of the components and technologies described.

[0098] Reference Figure 10 The image sensor 600 has a reference Figures 6A to 6C The image sensor 200 described has a substantially the same configuration. However, in the image sensor 600, the source follower transistor SF6 may include: a gate dielectric film 622 conformally covering the inner surface of a first trench T61 formed in a first active region AC1 of the substrate 102, and a gate electrode SFG6 formed on the gate dielectric film 622. The gate electrode SFG6 may include a buried gate portion 626 filling the first trench T61 on the gate dielectric film 622 and an upper gate portion 636 contacting the top surface of the buried gate portion 636 and located on the front side 102A of the substrate 102. The horizontal height of the top surface of the buried gate portion 626 may be approximately equal to or similar to the horizontal height of the front side 102A of the substrate 102. In an embodiment, the upper gate portion 636 of the source follower transistor SF6 does not include the portion buried in the substrate 102.

[0099] The selector transistor SX6 may include a gate dielectric film 632 and a gate electrode SXG6 that sequentially cover the buried gate portion 626 of the source follower transistor SF6 and the front side 102A of the substrate 102. The gate electrode SXG6 of the selector transistor SX6 may overlap with the buried gate portion 636 of the source follower transistor SF6 in the vertical direction (Z direction). The horizontal height of the lowest surface of the gate electrode SXG6 of the selector transistor SX6 may be approximately equal to or similar to the horizontal height of the front side 102A of the substrate 102. The gate electrode SXG6 of the selector transistor SX6 may face the buried gate portion 626 of the source follower transistor SF6, with the gate dielectric film 632 located between the gate electrode SXG6 and the buried gate portion 626. In an embodiment, the gate electrode SXG6 of the selector transistor SX6 does not include a portion buried in the substrate 102.

[0100] The detailed configuration of the gate dielectric film 622 of the source follower transistor SF6, the gate electrode SFG6 including the buried gate portion 636 and the upper gate portion 636, and the detailed configuration of the gate dielectric film 632 and the gate electrode SXG6 of the select transistor SX6 can be compared with the reference. Figures 5A to 5C and Figures 6A to 6C The provided source follower transistor SF2 and select transistor SX are configured in a basically similar manner.

[0101] In reference Figures 1 to 10 In the described image sensors 100, 200, 300, 400, 500, and 600, the two gate electrodes of two transistors among the multiple transistors included in a unit pixel PXU (i.e., the gate electrodes SFG, SFG2, SFG3, SFG4, SFG5, or SFG6 of the follower transistor SF, SF2, SF3, SF4, SF5, or SF6 and the gate electrode SXG or SXG6 of the select transistor SX or SX6) can overlap in the vertical direction (Z direction). Therefore, even when the size of the unit pixel PXU in image sensors 100, 200, 300, 400, 500, and 600 decreases, the transistors included in image sensors 100, 200, 300, 400, 500, and 600 can maintain stable electrical characteristics by ensuring sufficient channel length and current. Thus, the integration density and fill factor in the image sensor can be improved while maintaining excellent sensitivity and color filtering.

[0102] Figures 11A to 20C This is a cross-sectional view illustrating a method for manufacturing an image sensor according to an embodiment. Figure 11A , Figure 12A ,……,and Figure 20A It is shown according to the process sequence and along Figure 4 A cross-sectional view of the region of the image sensor corresponding to the section intercepted by line X1-X1'. Figure 11B , Figure 12B ,……,and Figure 20B It is shown according to the process sequence and along Figure 4 A cross-sectional view of the region of the image sensor corresponding to the section intercepted by line X2-X2'. Figure 11C , Figure 12C ,……,and Figure 20C It is shown according to the process sequence and along Figure 4 A cross-sectional view of the image sensor region corresponding to the section intercepted by line Y1-Y1'. (Refer to...) Figures 11A to 20C Description of manufacturing reference Figure 4 and Figures 5A to 5C Example methods of the image sensor 100 described.

[0103] Reference Figures 11A to 11C A photodiode PD can be formed in the substrate 102, and a buffer oxide film 112 and a mask pattern MP1 can be formed on the front side 102A of the substrate 102. The mask pattern MP1 can be used as an etching mask to anisotropically etch the substrate 102 to form a device isolation trench 114. Multiple active regions (e.g., ...) can be defined in the substrate through the device isolation trench 114. Figure 4 The first to third active regions AC1, AC2 and AC3 in the middle.

[0104] In an example embodiment, in order to form a photodiode PD, regions corresponding to multiple pixels (see reference) can be formed on the front side 102A of the substrate 102. Figure 4 A to Figure 4 An ion implantation mask pattern with multiple openings in the PXR (photodiode in D) can be used to dope N-type impurities into the substrate 102. After the photodiode PD is formed, the ion implantation mask pattern can be removed.

[0105] In an example embodiment, the mask pattern MP1 may include a silicon nitride film or a silicon oxynitride film. The lowest surface of the device isolation trench 114 may be separate from the photodiode PD. In an example embodiment, the process of forming the device isolation trench 114 may be performed before the process of forming the photodiode PD. In an example embodiment, the process of forming the device isolation trench 114 may be performed after the process of forming the photodiode PD.

[0106] Reference Figures 12A to 12C A device isolation insulating film 116 can be formed to fill the device isolation trench 114 and cover the top surface of the mask pattern MP1. A portion of the device isolation insulating film 116 and a portion of the substrate 102 can be etched to form a pixel isolation trench 118. The pixel isolation trench 118 can be formed near the photodiode PD to surround the photodiode PD. A pixel region PXR can be defined in the substrate 102 through the pixel isolation trench 118.

[0107] Reference Figures 13A to 13C It can form an insulating film to cover Figures 12A to 12C The resulting structure is then filled with pixel isolation trench 118. The resulting structure, including the insulating film, can be planarized to remove the mask pattern MP1 and the buffer oxide film 112 and expose the front side 102A of the substrate 102. As a result, the portion of the insulating film that fills the pixel isolation trench 118 can be retained as pixel isolation insulating film 120.

[0108] Reference Figures 14A to 14C Through Figures 13A to 13C In the resulting structure, an etching process is performed on the front side 102A of the substrate 102 to etch a portion of the substrate 102 to form a first trench T1. A gate dielectric film 122 and a first conductive pattern 126A can be formed inside the first trench T1.

[0109] The first trench T1 can be formed to include steps in its bottom surface. Therefore, after forming the first trench T1, a fin region 102F can be formed in the first active region AC1 of the substrate 102. The lowest portion of the bottom surface of the first trench T1 can be located at a first horizontal height LV1, which is separated from the front surface 102A of the substrate 102 by a first vertical distance towards the interior of the substrate 102. The portion of the bottom surface of the first trench T1 corresponding to the top surface of the fin region 102F can be located at a second horizontal height LV2, which is separated from the front surface 102A of the substrate 102 by a second vertical distance towards the interior of the substrate 102. Here, the second vertical distance can be smaller than the first vertical distance.

[0110] In an example embodiment, to form the gate dielectric film 122 and the first conductive pattern 126A, firstly, a process of oxidizing the exposed surface of the substrate 102 in which the first trench T1 is formed can be performed to form a gate dielectric film 122 that conformally covers the inner surface of the first trench T1. Subsequently, a polysilicon film can be formed on the gate dielectric film 122 to fill the first trench T1. A planarization process can be performed on the resulting structure to expose the front side 102A of the substrate 102, thus removing unwanted portions of the gate dielectric film 122 and the polysilicon film. N-type impurities can be doped into the polysilicon film retained inside the first trench T1 to form the first conductive pattern 126A comprising doped polysilicon. However, according to the embodiment, the process for forming the gate dielectric film 122 and the first conductive pattern 126A is not limited to the above description and various modifications and changes can be made according to embodiments conceived in the present invention.

[0111] Reference Figures 15A to 15C ,exist Figures 14A to 14CIn the resulting structure, a mask pattern MP2 can be formed on the substrate 102, including an opening H2 exposing the gate dielectric film 122 and the first conductive pattern 126A. The mask pattern MP2 can be used as an etching mask to etch a portion of each of the gate dielectric film 122, the first conductive pattern 126A, and the substrate 102 to form the second trench T2. In an example embodiment, the mask pattern MP2 may include a photoresist pattern. However, the embodiments are not limited thereto.

[0112] During the formation of the second trench T2, a portion of each of the gate dielectric film 122 and the first conductive pattern 126A may be removed. After the formation of the second trench T2, the first conductive pattern 126A remaining in the first trench T1 may constitute the buried gate portion 126 of the source follower transistor SF.

[0113] The lowest portion of the second trench T2 may extend laterally at a third horizontal height LV3, which is higher than the second horizontal height LV2 and lower than the horizontal height of the front side 102A of the substrate 102. The gate dielectric film 122 and the buried gate portion 126 may be exposed at the bottom surface of the second trench T2.

[0114] Reference Figures 16A to 16C It can be seen from Figures 15A to 15C The resulting structure removes the mask pattern MP2 to expose the top surface of each of the front side 102A of the substrate 102, the device isolation insulating film 116, and the pixel isolation insulating film 120.

[0115] Mask pattern 130 can be formed on the resulting structure after mask pattern MP2 has been removed. Mask pattern 130 may have an opening 130H on a portion of each of the exposed gate dielectric film 122, the buried gate portion 126, and the substrate 102 on the first active region AC1. In an example embodiment, mask pattern 130 may include a silicon nitride film.

[0116] A gate dielectric film 132 can be formed to cover the surface of the buried gate portion 126 exposed by the opening 130H of the mask pattern 130 and the surface of the substrate 102. In an example embodiment, to form the gate dielectric film 132, an oxidation process can be performed on the surface of the buried gate portion 126 exposed by the opening 130H of the mask pattern 130 and the surface of the substrate 102. In an example embodiment, the gate dielectric film 132 can be formed using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

[0117] The gate dielectric film 132 can conformally cover the surface of the buried gate portion 126 and the surface of the substrate 102. The thickness of the gate dielectric film 132 can be greater than the thickness of the gate dielectric film 122 of the source follower transistor SF.

[0118] In an example embodiment, during the formation of the gate dielectric film 132, a plurality of gate dielectric films may also be formed on the second active region AC2 and the third active region AC3 of the substrate 102. The plurality of gate dielectric films formed on the second active region AC2 and the third active region AC3 may include those constituting a reference. Figure 2 The gate dielectric film of the first transmission transistor TX1, the second transmission transistor TX2, and the reset transistor RX described herein, or including the components constituting the reference. Figure 3 The gate dielectric film of the first to fourth transmission transistors TX1, TX2, TX3 and TX4 and the reset transistor RX are described.

[0119] Reference Figures 17A to 17C It can be seen from Figures 16A to 16C The resulting structure removes the mask pattern 130 to expose the front side 102A of the substrate 102 and the top surface of the buried gate portion 126. A second conductive layer can be formed in contact with the top surface of the buried gate portion 126 and the top surface of the gate dielectric film 132. Subsequently, a plurality of insulating masking patterns 134 can be formed on the second conductive layer. In the example process for forming the second conductive layer, from... Figures 16A to 16C After removing the mask pattern 130 from the obtained structure, a doped polysilicon film can be formed to cover the obtained structure.

[0120] Multiple insulating masking patterns 134 can be used as etching masks to remove a portion of each of the second conductive layer and the gate dielectric film 132. Thus, the upper gate portion 136 of the source follower transistor SF and the gate electrode SXG of the select transistor SX can be formed, including the portion of the second conductive layer retained on the first active region AC1.

[0121] like Figure 17C As shown, the upper gate portion 136 of the source follower transistor SF and the gate electrode SXG of the select transistor SX can be separated from each other in the second lateral direction (Y direction) by a gap region GA located therebetween. The top surface of the buried gate portion 126 can be exposed through the gap region GA.

[0122] exist Figures 17A to 17C In the resulting structure, the buried gate portion 126 and the upper gate portion 136 can constitute a source follower transistor (see reference). Figures 5A to 5C The gate electrode SFG of SF).

[0123] In the example embodiment, in reference Figures 17A to 17CDuring the formation of the upper gate portion 136 and the gate electrode SXG in the described process, the gate structure constituting the MOS transistor included in the readout circuit can be formed on the front side 102A of the substrate 102 together with the upper gate portion 136 and the gate electrode SXG. For example, during the formation of the upper gate portion 136 and the gate electrode SXG, a reference structure can be formed simultaneously. Figure 2 The gate structures of the first transfer transistor TX1, the second transfer transistor TX2, and the reset transistor RX described herein, or constituting a reference, are as follows. Figure 3 The gate structures of the first to fourth transmission transistors TX1 and TX2, TX3 and TX4, and the reset transistor RX are described.

[0124] Reference Figures 18A to 18C ,exist Figures 17A to 17C In the resulting structure, multiple insulating spacers 140 can be formed to cover the sidewalls of the upper gate portion 136, the gate electrode SXG, and multiple insulating masking patterns 134. Impurity ions can be implanted into the first to third active regions (see reference). Figures 5A to 5C AC1, AC2, and AC3 in the reference (to form multiple impurity regions). These multiple impurity regions may include reference (to...) Figure 4 and Figures 5A to 5C The impurity regions 150, 152, and 154 are described. A pair of impurity regions 150 formed in the first active region AC1 can be used as the source and drain of each of the source follower transistor SF and the select transistor SX. The impurity region 152 formed in the second active region AC2 can constitute a floating diffusion region FD.

[0125] like Figure 18C As shown, in the second lateral direction (Y direction), the gap region between the upper gate portion 136 of the source follower transistor SF and the gate electrode SXG of the select transistor SX (refer to...) Figure 17C The GA in the middle can be filled with insulating spacer 140. The filling gap area (refer to...) Figure 17C The insulating spacer 140 of the GA in the buried gate portion 126 can contact the top surface of the buried gate portion 126.

[0126] Reference Figures 19A to 19C ,exist Figures 18A to 18C In the resulting structure, an interlayer insulating film 160 can be formed to cover the front side 102A of the substrate 102 and a plurality of transistors, including a source follower transistor SF and a select transistor SX. Subsequently, a plurality of contact plugs 164 can be formed to pass through the interlayer insulating film 160 and connect to the plurality of transistors. A plurality of wires 168 can be formed on the interlayer insulating film 160. The plurality of wires 168 can be connected to the plurality of transistors through the plurality of contact plugs 164.

[0127] Multiple contact plugs 164 may include an upper gate portion 136 of the source follower transistor SF, a gate electrode SXG of the select transistor SX, and multiple impurity regions (e.g., Figure 4 Multiple contact plugs 164 (150, 152, and 154). In an embodiment, the multiple contact plugs 164 may further include connections respectively connected to the reference. Figure 2 The described gate structures of the first transfer transistor TX1 and the second transfer transistor TX2, as well as the contact plugs of the impurity region, may also include connections respectively to the reference. Figure 3 The gate structure of the first to fourth transmission transistors TX1, TX2, TX3 and TX4 and the reset transistor RX, as well as the contact plugs of the impurity region, are described.

[0128] Reference Figures 20A to 20C , can Figures 19A to 19C Multiple interlayer insulating films (e.g., 170 and 174) and multiple conductive lines 172 are formed on the resulting structure. The multiple interlayer insulating films (e.g., 170 and 174) and multiple conductive lines 172 can, together with interlayer insulating film 160 and multiple conductive lines 168, form a wiring structure MS covering the front side 102A of the substrate 102.

[0129] After forming the wiring structure MS, the thickness of the substrate 102 can be reduced when the support substrate is adhered to the wiring structure MS. To reduce the thickness of the substrate 102, mechanical polishing, chemical mechanical polishing (CMP), wet etching, or a combination thereof can be used. As a result, the pixel isolation insulating film 120 can be exposed at the back surface 102B, which is the opposite surface of the front surface 102A of the substrate 102. A first planarization film 182 can be formed on the exposed back surface 102B of the substrate 102 and the exposed surface of the pixel isolation insulating film 120.

[0130] After that, as Figures 5A to 5C As shown, an anti-reflective film 186, a color filter CF, a second planarization film 184, a microlens ML, and a protective cover film 188 can be sequentially formed on the first planarization film 182 to form a light-transmitting structure LTS. Subsequently, the supporting substrate covering the wiring structure MS can be removed to fabricate the structure. Figures 5A to 5C The image sensor 100 shown is shown.

[0131] Although it has been referenced Figures 11A to 20C Describes manufacturing Figure 4 and Figures 5A to 5C The method of the image sensor 100 shown is not limited to this embodiment, and various modifications and changes can be made within the scope of the inventive concept to produce the above-described embodiments of the inventive concept. Figures 6A to 10 The image sensors described are 200, 300, 400, 500 and 600.

[0132] Figure 21A This is a block diagram of an electronic system 1000 according to an embodiment of the present invention. Figure 21B yes Figure 21A Detailed block diagram of the camera module included in the electronic system 1000.

[0133] Reference Figure 21A The electronic system 1000 may include a camera module group 1100, an application processor 1200, a power management integrated circuit (PMIC) 1300, and an external memory 1400.

[0134] Camera module group 1100 may include multiple camera modules 1100a, 1100b, and 1100c. Although in Figure 21A The diagram shows three camera modules 1100a, 1100b, and 1100c, but embodiments of the present invention are not limited thereto. In some embodiments, the camera module group 1100 may be modified to include only two camera modules. In some embodiments, the camera module group 1100 may be modified to include "n" camera modules, where "n" is a natural number of at least 4.

[0135] The following will refer to Figure 21B This describes the detailed configuration of camera module 1100b. The following description can also be applied to other camera modules 1100a and 1100c.

[0136] Reference Figure 21B The camera module 1100b may include a prism 1105, an optical path folding element (OPFE) 1110, an actuator 1130, an image sensing device 1140, and a storage device 1150.

[0137] The prism 1105 may include a reflective surface 1107 of reflective material and may change the path of light L incident from the outside.

[0138] In some embodiments, the prism 1105 can direct the energy along the first direction ( Figure 21B The path of the incident light L (in the X direction) is changed to a second direction perpendicular to the first direction (in the X direction). Figure 21B (Y direction in the image). Prism 1105 can rotate the reflective surface 1107 of the reflective material about the central axis 1106 in direction A, or rotate the central axis 1106 in direction B to change the path of the light L incident along the first direction (X direction) to a second direction (Y direction) perpendicular to the first direction (X direction). In this case, OPFE 1110 can rotate in a third direction (Y direction) perpendicular to the first direction (X direction) and the second direction (Y direction). Figure 21B Move in the Z direction.

[0139] In some embodiments, such as Figure 21B As shown, the maximum rotation angle of prism 1105 in direction A can be less than or approximately equal to 15 degrees in the positive (+)A direction, and greater than 15 degrees in the negative (-)A direction. However, the embodiments of the present invention are not limited thereto.

[0140] In some embodiments, the prism 1105 can move by an angle of about 20 degrees in the positive B direction or the negative B direction, or within a range of about 10 degrees to about 20 degrees or from about 15 degrees to about 20 degrees. In this case, the angle by which the prism 1105 moves in the positive B direction can be the same as or similar to the angle by which the prism 1105 moves in the negative B direction (difference of about 1 degree).

[0141] In some embodiments, the prism 1105 can move the reflective surface 1107 of the reflective material in a third direction (Z direction) parallel to the extension direction of the central axis 1106.

[0142] OPFE 1110 may include, for example, "m" optical lenses, where "m" is a natural number. These "m" lenses can be moved in a second direction (Y direction) and change the optical zoom ratio of camera module 1100b. For example, when the default optical zoom ratio of camera module 1100b is Z, the optical zoom ratio of camera module 1100b can be changed to 3Z, 5Z, or greater by moving the "m" optical lenses included in OPFE 1110.

[0143] Actuator 1130 can move OPFE 1110 or optical lens to a specific position. For example, actuator 1130 can adjust the position of optical lens so that image sensor 1142 is located at the focal length of optical lens for accurate sensing.

[0144] Image sensing device 1140 may include image sensor 1142, control logic 1144, and memory 1146. Image sensor 1142 can sense an image of an object using light L provided through an optical lens. Control logic 1144 can control all operations of camera module 1100b. For example, control logic 1144 can control the operation of camera module 1100b according to control signals provided through control signal line CSLb.

[0145] Memory 1146 may store information for the operation of camera module 1100b (e.g., calibration data 1147). Calibration data 1147 may include information for camera module 1100b to generate image data using light L provided externally. For example, calibration data 1147 may include information about the degree of rotation, information about the focal length, information about the optical axis, etc. When camera module 1100b is implemented as a polymorphic camera where the focal length varies with the position of the optical lens, calibration data 1147 may include the focal length value for each position (or state) of the optical lens and information about autofocus.

[0146] Storage device 1150 can store image data sensed by image sensor 1142. Storage device 1150 can be disposed externally to image sensing device 1140 and can be stacked with the sensor chip of image sensing device 1140. In some embodiments, although storage device 1150 may include electrically erasable programmable read-only memory (EEPROM), embodiments of the present invention are not limited thereto.

[0147] Image sensor 1142 may include reference Figures 1 to 10 The image sensor described is 100, 200, 300, 400, 500 or 600, or an image sensor that is modified and altered in various ways within the scope of the inventive concept.

[0148] Reference Figure 21A and Figure 21B In some embodiments, camera modules 1100a, 1100b, and 1100c may each include an actuator 1130. Therefore, camera modules 1100a, 1100b, and 1100c may include calibration data 1147, which may be the same as or different from each other depending on the operation of the actuator 1130 included in each of the camera modules 1100a, 1100b, and 1100c.

[0149] In some embodiments, one of the camera modules 1100a, 1100b, and 1100c (e.g., camera module 1100b) may be a folding lens type including prism 1105 and OPFE 1110, while the other camera modules (e.g., camera modules 1100a and 1100c) may be a vertical type excluding prism 1105 and OPFE 1110. However, embodiments of the present invention are not limited thereto.

[0150] In some embodiments, one of the camera modules 1100a, 1100b, and 1100c (e.g., camera module 1100c) may include a vertical depth camera that extracts depth information using infrared (IR) rays. In this case, the application processor 1200 can generate a three-dimensional (3D) depth image by merging image data provided from the depth camera with image data provided from the other camera modules (e.g., camera modules 1100a or 1100b).

[0151] In some embodiments, at least two camera modules (e.g., 1100a and 1100b) among camera modules 1100a, 1100b, and 1100c may have different fields of view. In this case, for example, two camera modules (e.g., 1100a and 1100b) among camera modules 1100a, 1100b, and 1100c may each have different optical lenses. However, embodiments of the present invention are not limited thereto.

[0152] In some embodiments, camera modules 1100a, 1100b, and 1100c may have different fields of view from each other. In this case, although camera modules 1100a, 1100b, and 1100c may each have different optical lenses, the embodiments of the present invention are not limited thereto.

[0153] In some embodiments, camera modules 1100a, 1100b, and 1100c may be physically separated from each other. In other words, the sensing area of ​​image sensor 1142 is not divided and used by camera modules 1100a, 1100b, and 1100c, but image sensor 1142 may be independently included in each of camera modules 1100a, 1100b, and 1100c.

[0154] Return to reference Figure 21A The application processor 1200 may include an image processing unit 1210, a memory controller 1220, and internal memory 1230. The application processor 1200 may be implemented separately from the camera modules 1100a, 1100b, and 1100c. For example, the application processor 1200 and the camera modules 1100a, 1100b, and 1100c may be implemented on different semiconductor chips.

[0155] Image processing unit 1210 may include multiple subprocessors 1212a, 1212b, and 1212c, image generator 1214, and camera module controller 1216. Image processing unit 1210 may include as many subprocessors 1212a, 1212b, and 1212c as camera modules 1100a, 1100b, and 1100c.

[0156] Multiple image data streams generated by camera modules 1100a, 1100b, and 1100c can be provided to subprocessors 1212a, 1212b, and 1212c respectively via separate image signal lines ISLa, ISLb, and ISLc. For example, image data generated by camera module 1100a can be provided to subprocessor 1212a via image signal line ISLa, image data generated by camera module 1100b can be provided to subprocessor 1212b via image signal line ISLb, and image data generated by camera module 1100c can be provided to subprocessor 1212c via image signal line ISLc. This image data transmission can be performed using, for example, a Camera Serial Interface (CSI) based on a Mobile Industrial Processor Interface (MIPI). However, embodiments of the present invention are not limited thereto.

[0157] In some embodiments, a single sub-processor can be provided for multiple camera modules. For example, with Figure 21A In contrast, in this embodiment, subprocessors 1212a and 1212c may not be separate but may be integrated into a single subprocessor, and image data provided from camera module 1100a or camera module 1100c may be selected by a selection element (e.g., a multiplexer) and then provided to the integrated subprocessor.

[0158] Image data provided to each of the subprocessors 1212a, 1212b, and 1212c can be provided to the image generator 1214. The image generator 1214 can generate an output image using the image data provided from each of the subprocessors 1212a, 1212b, and 1212c, based on image generation information or pattern signals.

[0159] For example, image generator 1214 can generate an output image by merging at least a portion of each image data generated by camera modules 1100a, 1100b, and 1100c, which have different fields of view, based on image generation information or a pattern signal. Alternatively, image generator 1214 can generate an output image by selecting one of multiple image data generated by camera modules 1100a, 1100b, and 1100c, which have different fields of view, based on image generation information or a pattern signal.

[0160] In some embodiments, image generation information may include a zoom signal or a zoom factor. In some embodiments, the mode signal may be based on a user-selected mode.

[0161] When the image generation information includes a zoom signal or zoom factor and camera modules 1100a, 1100b, and 1100c have different fields of view, image generator 1214 can perform different operations based on different types of zoom signals. For example, when the zoom signal is a first signal, image generator 1214 can merge the image data output from camera module 1100a and the image data output from camera module 1100c, and then generate an output image using the merged image signal and image data output from camera module 1100b that is not used for merging. When the zoom signal is a second signal different from the first signal, image generator 1214 can generate an output image by selecting one of the multiple image data output from camera modules 1100a, 1100b, and 1100c respectively, without performing merging. However, embodiments of the present invention are not limited thereto, and the method of processing image data can be changed according to the embodiments.

[0162] In some embodiments, the image generator 1214 may receive multiple image data with different exposure times from at least one of the subprocessors 1212a, 1212b and 1212c, and perform high dynamic range (HDR) processing on the multiple image data to generate merged image data with increased dynamic range.

[0163] The camera module controller 1216 can provide control signals to each of the camera modules 1100a, 1100b, and 1100c. The control signals generated by the camera module controller 1216 can be provided to the respective camera modules 1100a, 1100b, and 1100c via the corresponding control signal lines in the separate control signal lines CSLa, CSLb, and CSLc.

[0164] One camera module (e.g., camera module 1100b) can be designated as the master camera based on a mode signal or an image generation signal including a zoom signal, while other camera modules (e.g., camera modules 1100a and 1100c) can be designated as slave cameras. This designation information can be included in control signals and provided to each of the camera modules 1100a, 1100b, and 1100c via corresponding control signal lines CSLa, CSLb, and CSLc, which are separate from each other.

[0165] The camera module can be configured as either a master or slave device based on the zoom factor or operating mode signal. For example, when the field of view of camera module 1100a is larger than that of camera module 1100b and the zoom factor indicates a low zoom ratio, camera module 1100a can be used as the master device, while camera module 1100b can be used as the slave device. Conversely, when the zoom factor indicates a high zoom ratio, camera module 1100b can be used as the master device, while camera module 1100a can be used as the slave device.

[0166] In some embodiments, control signals provided from camera module controller 1216 to each of camera modules 1100a, 1100b, and 1100c may include a synchronization enable signal. For example, when camera module 1100b is the main camera and camera module 1100a is the slave camera, camera module controller 1216 may send a synchronization enable signal to camera module 1100b. Camera module 1100b, which is provided with the synchronization enable signal, may generate a synchronization signal based on the synchronization enable signal and may provide the synchronization signal to camera modules 1100a and 1100c via the synchronization signal line SSL. Camera modules 1100a, 1100b, and 1100c may synchronize with the synchronization signal and may send image data to application processor 1200.

[0167] In some embodiments, control signals provided from camera module controller 1216 to each of camera modules 1100a, 1100b, and 1100c may include mode information based on mode signals. Camera modules 1100a, 1100b, and 1100c may operate in a first operating mode or a second operating mode related to sensing speed based on the mode information.

[0168] In the first operating mode, camera modules 1100a, 1100b, and 1100c can generate image signals at a first speed (e.g., at a first frame rate), encode the image signals at a second speed higher than the first speed (e.g., at a second frame rate higher than the first frame rate), and send the encoded image signals to application processor 1200. In this case, the second speed can be about 30 times or less than the first speed.

[0169] Application processor 1200 can store received image signals (e.g., encoded image signals) in its internal memory 1230 or in external memory 1400 outside of application processor 1200. Subsequently, application processor 1200 can read the encoded image signals from internal memory 1230 or external memory 1400, decode the encoded image signals, and display image data generated based on the decoded image signals. For example, the corresponding subprocessors in subprocessors 1212a, 1212b, and 1212c of image processing unit 1210 can perform decoding or image processing on the decoded image signals.

[0170] In the second operating mode, camera modules 1100a, 1100b, and 1100c can generate image signals at a third speed lower than the first speed (e.g., a third frame rate lower than the first frame rate) and send the image signals to application processor 1200. The image signals provided to application processor 1200 have not yet been encoded. Application processor 1200 can perform image processing on the image signals or store the image signals in internal memory 1230 or external memory 1400.

[0171] PMIC 1300 can provide power (e.g., supply voltage) to each of camera modules 1100a, 1100b, and 1100c. For example, under the control of application processor 1200, PMIC 1300 can provide a first power supply to camera module 1100a via power signal line PSLa, a second power supply to camera module 1100b via power signal line PSLb, and a third power supply to camera module 1100c via power signal line PSLc.

[0172] PMIC 1300 can respond to a power control signal PCON from application processor 1200 to generate and adjust the power corresponding to each of camera modules 1100a, 1100b, and 1100c. The power control signal PCON can include a power adjustment signal for each operating mode of camera modules 1100a, 1100b, and 1100c. For example, the operating mode can include a low-power mode. In this case, the power control signal PCON can include information about the camera module operating in low-power mode and the power level to be set. The same or different levels of power can be provided to camera modules 1100a, 1100b, and 1100c respectively. The power level can be changed dynamically.

[0173] As is conventional in the field of the present invention, embodiments are described and illustrated in the accompanying drawings from the perspective of functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuitry such as logic circuits, discrete components, microprocessors, hardwired circuits, storage elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, units, and / or modules are implemented by microprocessors or the like, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein and can optionally be driven by firmware and / or software. Alternatively, each block, unit, and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware performing some functions and processors performing other functions (e.g., one or more programmed microprocessors and associated circuitry).

[0174] While the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made herein without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Claims

1. An image sensor, comprising: A substrate having a pixel region defining a plurality of active regions; A first transistor, the first transistor including a first gate electrode, the first gate electrode including a buried gate portion. The buried gate portion is buried in the substrate in a first active region selected from the plurality of active regions; as well as The second transistor includes a second gate electrode that overlaps with the buried gate portion on the first active region in a vertical direction.

2. The image sensor according to claim 1, further comprising: A first impurity region and a second impurity region, located within the first active region. The first impurity region and the second impurity region are spaced apart from each other in the lateral direction by the first gate electrode and the second gate electrode located between the first impurity region and the second impurity region. The first impurity region and the second impurity region serve as the source and drain of each of the first transistor and the second transistor, respectively.

3. The image sensor according to claim 1, wherein, The first gate electrode further includes an upper gate portion that protrudes from the top surface of the buried gate portion along the vertical direction to a horizontal height higher than the front surface of the substrate. Wherein, the upper gate portion of the first gate electrode is spaced apart from the second gate electrode in the lateral direction, and the upper gate portion of the first gate electrode faces the second gate electrode in the lateral direction.

4. The image sensor according to claim 1, wherein, The first transistor further includes a first gate dielectric film located between the first active region and the buried gate portion. The second transistor further includes a second gate dielectric film located between the first active region and the second gate electrode, and located between the first gate electrode and the second gate electrode. The thickness of the second gate dielectric film is greater than the thickness of the first gate dielectric film.

5. The image sensor according to claim 1, wherein, The first transistor further includes a first gate dielectric film located between the first active region and the buried gate portion. The second transistor further includes a second gate dielectric film located between the first active region and the second gate electrode, and located between the first gate electrode and the second gate electrode. The second gate electrode and the buried gate portion are separated in the vertical direction by a second gate dielectric film located between the second gate electrode and the buried gate portion.

6. The image sensor according to claim 1, wherein, In the lateral direction, the width of the buried gate portion of the first gate electrode is smaller than the width of the second gate electrode.

7. The image sensor according to claim 1, wherein, The first active region includes a fin-like region protruding toward the buried gate portion, and The buried gate portion includes protrusions covering the sidewalls of the fin region.

8. The image sensor according to claim 1, further comprising: A photodiode, wherein the photodiode is formed in the substrate, The first gate electrode and the second gate electrode overlap with the photodiode in the vertical direction.

9. The image sensor according to claim 1, wherein, Both the first gate electrode and the second gate electrode comprise doped polysilicon, and The doping concentration of the second gate electrode is higher than the doping concentration of the buried gate portion of the first gate electrode.

10. The image sensor according to claim 1, further comprising: A floating diffusion region, which is formed in the second active region. The second active region is selected from the plurality of active regions and is spaced apart from the first active region. The first gate electrode and the floating diffusion region are electrically connected to each other.

11. The image sensor according to claim 1, further comprising: The upper gate portion, which forms part of the first gate electrode, The upper gate portion protrudes from the top surface of the buried gate portion along the vertical direction to a horizontal height higher than the front surface of the substrate; A floating diffusion region is formed in a second active region selected from the plurality of active regions and spaced apart from the first active region; A first contact plug is connected to the upper gate portion; A second contact plug, the second contact plug being connected to the floating diffusion region; and A wire is disposed on and connected to each of the first contact plug and the second contact plug.

12. An image sensor, comprising: Substrate, the substrate comprising a front side and a back side, Wherein, the front side and the back side are opposing surfaces, and the substrate includes a plurality of active regions defined between the front side and the back side at a position adjacent to the front side; A photodiode, wherein the photodiode is formed in the substrate; A source follower transistor, wherein the source follower transistor is disposed in a first active region selected from the plurality of active regions. The source follower transistor includes a first gate electrode, which includes a buried gate portion buried in the substrate and an upper gate portion in contact with the buried gate portion, and the upper gate portion overlaps with a first region of the buried gate portion in the vertical direction. The selection transistor includes a second gate electrode that overlaps with a second region of the buried gate portion on the first active region in the vertical direction; A transmission transistor, the transmission transistor being formed in a second active region selected from the plurality of active regions; A floating diffusion region is formed in the second active region. Wherein, the floating diffusion region is connected to the upper gate portion of the source follower transistor; and A microlens that covers the back side of the substrate.

13. The image sensor according to claim 12, further comprising: A first impurity region and a second impurity region are disposed in the first active region. The first impurity region and the second impurity region are spaced apart from each other in the lateral direction by the first gate electrode and the second gate electrode located between the first impurity region and the second impurity region. The first impurity region and the second impurity region serve as the source and drain of each of the source follower transistor and the select transistor.

14. The image sensor according to claim 12, further comprising: A first impurity region and a second impurity region are disposed in the first active region. The first impurity region and the second impurity region are spaced apart from each other in the first lateral direction by the first gate electrode and the second gate electrode located between the first impurity region and the second impurity region. Wherein, the upper gate portion of the source follower transistor and the second gate electrode of the select transistor are spaced apart from each other in a second lateral direction, the second lateral direction being perpendicular to the first lateral direction, and In the first lateral direction, the width of the buried gate portion is smaller than the width of the second gate electrode.

15. The image sensor according to claim 12, wherein, The first active region includes a fin-like region having a top surface and sidewalls facing the buried gate portion, and The source follower transistor also includes a gate dielectric film located between the buried gate portion and the fin region.

16. The image sensor according to claim 12, wherein, The buried gate portion overlaps with the photodiode in the vertical direction.

17. The image sensor according to claim 12, wherein, The buried gate portion and the upper gate portion of the source follower transistor, as well as the second gate electrode of the select transistor, all comprise doped polysilicon, and The doping concentration of each of the second gate electrode and the upper gate portion is higher than the doping concentration of the buried gate portion.

18. The image sensor according to claim 12, wherein, The selection transistor has a dual-gate structure, in which channels are formed on both sides of the buried gate portion.

19. The image sensor according to claim 12, wherein, A portion of the upper gate portion and a portion of the second gate electrode are buried in the substrate.

20. An electronic system comprising: At least one camera module, said at least one camera module including an image sensor; as well as A processor, configured to process image data received from the at least one camera module, The image sensor includes: A substrate having a pixel region defining a plurality of active regions; A first transistor, the first transistor including a first gate electrode having a buried gate portion. Wherein, the buried gate portion is buried in the substrate in a first active region selected from the plurality of active regions; and The second transistor includes a second gate electrode that overlaps with the buried gate portion on the first active region in a vertical direction.

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