Display device

Abstract

A display device is disclosed. The display device includes a substrate including an opening region, a peripheral region surrounding the opening region, and a display region surrounding the peripheral region; a transistor overlapping with the display region and provided over the substrate; a first electrode electrically connected to the transistor; an intermediate layer and a second electrode provided over the first electrode and extending to the peripheral region; and a first metal layer overlapping with the intermediate layer and the second electrode in the peripheral region, wherein an end portion of the first metal layer and an end portion of the second electrode are aligned, and an end portion of the intermediate layer protrudes more than the end portion of the first metal layer.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2020-0141330, filed on October 28, 2020, which is incorporated herein by reference for all purposes, as fully set forth herein. Technical Field

[0002] The embodiments of the invention generally relate to a display device. Background Technology

[0003] Recently, as various portable electronic devices have incorporated camera functionality, the number of users carrying only one electronic device with a built-in camera function has rapidly increased, compared to situations where camera functionality is not a feature of the electronic device and therefore users must carry a separate camera to take pictures.

[0004] In conventional technologies, because cameras, flashes, speakers, photoelectric sensors, etc., are located outside the image display area of ​​electronic devices, there is a trend to reduce the space for electronic devices to display images so that cameras can be housed in the non-image display area of ​​electronic devices.

[0005] The information disclosed in this background section is only for understanding the background of the inventive concept, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0006] The device constructed according to an exemplary embodiment of the invention can improve the reliability of an electronic device with display functionality by including a metal layer with ends aligned with the ends of electrodes in the peripheral region of an opening region inside the display area of ​​the electronic device, thereby reducing the chance of cracks forming in the peripheral region that would negatively affect the operational effectiveness (i.e., display capability) of the electronic device.

[0007] The embodiment provides a display device with improved device reliability in the peripheral region of an opening region surrounding the display area of ​​the display device.

[0008] Additional features of the inventive concept will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practice of the inventive concept.

[0009] The display device according to an embodiment includes: a substrate including an opening region, a peripheral region surrounding the opening region, and a display region surrounding the peripheral region; a transistor stacked on the display region and disposed on the substrate; a first electrode electrically connected to the transistor; an intermediate layer and a second electrode disposed on the first electrode and extending to the peripheral region; and a first metal layer stacked on the intermediate layer and the second electrode in the peripheral region, wherein the ends of the first metal layer and the ends of the second electrode are aligned, and the ends of the intermediate layer protrude beyond the ends of the first metal layer.

[0010] The intermediate layer can cover the end of the first metal layer.

[0011] The display device may further include an encapsulation layer disposed on the second electrode, and the encapsulation layer may include: a first encapsulation inorganic layer disposed on the second electrode; an encapsulation organic layer disposed on the first encapsulation inorganic layer; and a second encapsulation inorganic layer disposed on the encapsulation organic layer.

[0012] The end of the second electrode can be stacked with the encapsulating organic layer.

[0013] The display device may also include at least two dams located in the peripheral area.

[0014] The dam may include a first dam and a second dam that are separate from each other, and the display device may include: a first layer superimposed on the first dam; and a first second layer superimposed on the second dam.

[0015] The display device may also include a first to a third layer disposed between the second dam and the opening area.

[0016] The display device may also include a second-first layer disposed between the second dam and the opening area.

[0017] The display device may also include a second metal layer superimposed on at least one of the first dam and the second dam.

[0018] The second metal layer may be stacked with at least one of the first-first layer and the first-second layer, and the display device may further include a second-second layer stacked with the second metal layer and disposed on the same layer as the second electrode.

[0019] The display device may include: an inorganic insulating layer disposed on a substrate; an organic insulating layer disposed on the inorganic insulating layer; and a pixel defining layer and spacers disposed on the organic insulating layer.

[0020] The first metal layer can be disposed between the inorganic insulating layer and the organic insulating layer.

[0021] The display device may include multiple organic insulating layers, and a first metal layer may be positioned between two adjacent organic insulating layers.

[0022] The first metal layer can be disposed between the organic insulating layer and the pixel defining layer.

[0023] The first metal layer can be disposed between the pixel limiting layer and the spacer.

[0024] The display device according to an embodiment includes: a substrate including an opening region, a peripheral region surrounding the opening region, and a display region surrounding the peripheral region; a transistor stacked on the display region and disposed on the substrate; a first electrode electrically connected to the transistor; an intermediate layer and a second electrode disposed on the first electrode and extending into the peripheral region; a first metal layer stacked on the intermediate layer and the second electrode in the peripheral region; and an encapsulation layer disposed on the second electrode and including an encapsulation organic layer, wherein the ends of the first metal layer and the ends of the second electrode are aligned, the ends of the intermediate layer cover the ends of the first metal layer, and the ends of the first metal layer are stacked on the encapsulation organic layer.

[0025] The end of the second electrode can have a flat shape.

[0026] The first metal layer may include silver (Ag) or aluminum (Al).

[0027] The display device may further include: a dam disposed in the peripheral region; and a first-first layer superimposed on the dam, wherein the distance between the end of the first metal layer and the end of the adjacent first metal layer of the first-first layer may be about 35 micrometers or greater.

[0028] The ends of the intermediate layer extending into the peripheral region and the ends of the first-first layer can be separated.

[0029] The intermediate layer may include a functional layer, and the functional layer may include at least one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.

[0030] The first layer may be made of the same material as at least one of the hole injection layer, hole transport layer, electron transport layer and electron injection layer.

[0031] According to an embodiment, the reliability of the stacked structure in the peripheral region adjacent to the opening region can be improved by easily controlling the shape of the end of the second electrode. By forming a flat end of the electrode, the occurrence of cracks in the inorganic layer and the infiltration of foreign particles can be prevented.

[0032] It will be understood that the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0033] The accompanying drawings illustrate exemplary embodiments of the invention and, together with the description, serve to explain the inventive concept. The drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification.

[0034] Figure 1 This is an exploded perspective view of a display device according to an embodiment.

[0035] Figure 2 This is a schematic cross-sectional view of a display device according to an embodiment.

[0036] Figure 3 This is a top plan view of some of the constituent elements of the display panel according to an embodiment.

[0037] Figure 4 yes Figure 1 and Figure 3 Enlarged top view of region A.

[0038] Figure 5A This is a cross-sectional view of the display panel corresponding to the display area. Figure 5B This is a circuit diagram of a display device according to an embodiment. Figure 5C This is a cross-sectional view of the display panel, which has a defined outer area and an opening area. Figure 5D This is an enlarged view of the region at the end where the second electrode is located.

[0039] Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 These are cross-sectional views of some areas of the display panel based on the manufacturing process.

[0040] Figure 12A , Figure 12B , Figure 12C and Figure 12D These are cross-sectional views of the display panel according to the embodiment.

[0041] Figure 13A , Figure 13B , Figure 13C , Figure 13D and Figure 13E These are cross-sectional views of the display panel according to the embodiment.

[0042] Figure 14 This is a cross-sectional view of the display panel according to an embodiment. Detailed Implementation

[0043] In the following description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of various embodiments or implementations of the invention. As used herein, “embodiment” and “implementation” are interchangeable terms as non-limiting examples of apparatuses or methods employing one or more of the inventive concepts disclosed herein. However, it will be apparent that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various embodiments. Furthermore, the various embodiments may differ, but are not necessarily exclusive. For example, a particular shape, construction, and characteristic of one embodiment may be used or implemented in another embodiment without departing from the inventive concept.

[0044] Unless otherwise stated, the embodiments shown are to be understood as exemplary features providing different details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise stated, features, components, modules, layers, films, panels, regions and / or aspects (hereinafter individually or collectively referred to as “elements”) of various embodiments may be combined, separated, interchanged and / or rearranged in other ways without departing from the inventive concept.

[0045] Crosshairs and / or shading are typically used in accompanying drawings to clearly define the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, scale, commonalities between the elements shown, or any other characteristics, properties, etc. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. When embodiments can be implemented differently, a particular process sequence may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Moreover, the same reference numerals denote the same elements.

[0046] When a component or layer is referred to as being "on," "connected to," or "bonded to" another component or layer, the component or layer may be directly on, directly connected to, or directly bonded to the other component or layer, or there may be intermediate components or layers present. However, when a component or layer is referred to as being "directly on," "directly connected to," or "directly bonded to" another component or layer, there are no intermediate components or layers present. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection, with or without intermediate components. Furthermore, the DR1 axis ("DR1 direction"), DR2 axis ("DR2 direction"), and DR3 axis ("DR3 direction") are not limited to the three axes of a Cartesian coordinate system such as the x-axis, y-axis, and z-axis, but can be interpreted in a broader sense. For example, the DR1 axis, DR2 axis, and DR3 axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0047] Although the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the publicly stated teachings, the first element discussed below may be referred to as the second element.

[0048] Spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side” (e.g., as in “sidewall”) may be used herein for descriptive purposes to describe the relationship of one element to another, as shown in the accompanying drawings. Spatial relative terms are intended to cover not only the orientation depicted in the drawings but also different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features would then be positioned “above” said other elements or features. Thus, the term “below” can cover both above and below orientations. Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0049] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms. Furthermore, the terms “comprising,” “including,” “having,” and / or variations thereof, when used in this specification, indicate the presence of the stated features, integrals, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than terms of degree, and thus are used to explain the inherent biases in measured, calculated, and / or provided values ​​that will be recognized by those skilled in the art.

[0050] Various embodiments are described herein with reference to sectional views and / or exploded views, which are schematic diagrams of idealized embodiments and / or intermediate structures. Thus, variations in the illustrated shapes will be anticipated, for example, due to manufacturing techniques and / or tolerances. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes shown, but will include deviations in shape caused, for example, by manufacturing processes. In this way, the areas shown in the drawings can be schematic in nature, and the shapes of these areas may not reflect the actual shapes of the areas of the device, thus not intended to be limiting.

[0051] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms (such as those defined in general dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly stated otherwise herein.

[0052] Furthermore, throughout the instruction manual, the phrase "on a plane" indicates viewing the target portion from the top, while the phrase "on a cross-section" indicates viewing a cross-section formed by vertically cutting the target portion from the side.

[0053] In the following text, refer to Figures 1 to 3 A display device according to an embodiment is illustrated. Figure 1 This is an exploded perspective view of the display device according to an embodiment. Figure 2 This is a schematic cross-sectional view of a display device according to an embodiment. Figure 3 This is a top plan view of some of the constituent elements of the display panel according to an embodiment.

[0054] First, refer to Figure 1 and Figure 2The display device 1000 displays an image on a plane defined by a first direction DR1 and a second direction DR2, facing a third direction DR3 (wherein, the first direction DR1 is orthogonal to the second direction DR2, and the third direction DR3 is orthogonal to both the first direction DR1 and the second direction DR2, thereby forming a {xyz} three-dimensional coordinate system). The front (or top) and back (or bottom) of each component are distinguished by the third direction DR3. The directions indicated from the first direction to the third directions DR1, DR2, and DR3 are relative concepts and can be converted to other directions.

[0055] The display device 1000 includes a cover window WU, a display panel DP, and a housing member HM. In an embodiment, the cover window WU, the display panel DP, and the housing member HM are combined to form the display device 1000.

[0056] A cover window (WU) is disposed on the display panel (DP) to protect the display panel (DP). The cover window (WU) may include a transmissive area (TA) and a blocking area (BA). The transmissive area (TA) is an optically transparent area and may be an area that transmits incident light. The blocking area (BA) may be an area with relatively low light transmittance compared to the transmissive area (TA). The blocking area (BA) defines the shape of the transmissive area (TA). The blocking area (BA) may surround the transmissive area (TA). The blocking area (BA) may display a predetermined color. The blocking area (BA) is superimposed on the non-display area (PA) of the display panel (DP) to prevent the non-display area (PA) from being identified from the outside.

[0057] The coverage window WU may include a first aperture region HA1 and a second aperture region HA2. Each of the first aperture region HA1 and the second aperture region HA2 may be superimposed with an electronic module EM, which will be described later. The electronic module EM can be operated by receiving external signals provided through the first aperture region HA1 and the second aperture region HA2.

[0058] According to an embodiment, the first aperture region HA1 can be located in the transmission region TA, and the second aperture region HA2 can be located in the blocking region BA. However, this is only exemplary; the first aperture region HA1 and the second aperture region HA2 can be located in opposite regions, both in the transmission region TA, or both in the blocking region BA.

[0059] In each of the first hole region HA1 and the second hole region HA2, a predetermined recess may be defined that extends from the rear surface of the cover window WU. The recess may include a groove or opening region having a depth smaller than the thickness of the cover window WU.

[0060] The first hole region HA1 and the second hole region HA2 can have different shapes. The first hole region HA1 can be circular in the plane, and the second hole region HA2 can be elliptical in the plane with a major axis extending along the first direction DR1. However, the shapes of the first hole region HA1 and the second hole region HA2 are not limited to these, and their dimensions and shapes can be modified differently.

[0061] The display panel DP can be a flat, rigid display panel, but is not limited thereto, or it can be a flexible display panel. The display panel DP according to embodiments can be a light-emitting display panel, but is not particularly limited thereto. For example, the display panel DP can be an organic light-emitting panel or a quantum dot light-emitting display panel. The intermediate layer of an organic light-emitting panel may include organic light-emitting materials. The intermediate layer of a quantum dot light-emitting display panel may include quantum dots and / or quantum rods. Hereinafter, the display panel DP is described as an organic light-emitting panel.

[0062] The display panel DP displays the image in front of it. The front of the display panel DP includes a display area DA and a non-display area PA. The image is displayed in the display area DA. The non-display area PA may surround the display area DA.

[0063] A display panel (DP) may include multiple pixels (PX) positioned within a display area (DA). Each pixel (PX) can display light in response to an electrical signal. The light displayed by the pixels (PX) can create an image. The number of transistors and capacitors included in a single pixel (PX) and their interconnections can vary in different ways.

[0064] According to an embodiment, the display panel DP may include an opening region DTA that penetrates the display panel DP. The opening region DTA may be located inside the display region DA. The region A where the opening region DTA is located will be described later. The opening region DTA may be superimposed on the first hole region HA1 of the overlay window WU. Some of the plurality of pixels PX may be arranged around the opening region DTA. Therefore, an image may also be displayed in the region adjacent to the opening region DTA.

[0065] The display panel DP includes a non-display area PA extending from the display area DA and including multiple signal lines and pads (or "solder pads"). A data driver 50 may be positioned within the non-display area PA. According to an embodiment, the pads of the non-display area PA may be electrically connected to a printed circuit board (PCB) including a driver chip 80, and... Figure 3 It is described in more detail.

[0066] like Figure 2As shown, the adhesive layer AD for attaching the display panel DP and the cover window WU can be positioned between the display panel DP and the cover window WU. Furthermore, a touch unit positioned between the display panel DP and the cover window WU may also be included. The touch unit can be disposed on the display panel DP for the touchscreen function of the display device 1000. The touch unit may include touch electrodes of various patterns and may be resistive film type or capacitive type.

[0067] The electronic module EM includes various functional modules to operate the display device 1000. The electronic module EM can be electrically connected to the display panel DP via connectors. For example, the electronic module EM can be a camera, a speaker, or a sensor for detecting light or heat.

[0068] The electronic module EM may include a first electronic module EM1 and a second electronic module EM2. The first electronic module EM1 can detect external targets received through the opening region DTA and the first aperture region HA1. The first electronic module EM1 can receive external input transmitted through the opening region DTA and the first aperture region HA1, or provide output through the opening region DTA and the first aperture region HA1.

[0069] For example, the first electronic module EM1 can be at least any one of a light-emitting module, a photosensitive module, and an imaging module. For example, the first electronic module EM1 can include at least one of a light-emitting module that outputs infrared light, a CMOS sensor for infrared detection, and a camera module for imaging external objects.

[0070] The second electronic module EM2 can collect sound signals, such as speech, through the second aperture region HA2, or provide sound signals, such as processed speech, to the outside. For example, the second electronic module EM2 may include at least one of an acoustic input module and an acoustic output module. The acoustic input module may include a microphone capable of receiving acoustic signals. The acoustic output module may include a speaker that outputs sound data as a sound signal.

[0071] However, this is shown by way of example that the electronic module EM can consist of a single module or include a greater number of electronic modules, can be arranged in various arrangements, and is not limited to any one embodiment.

[0072] The housing component HM is disposed below the display panel DP. The housing component HM, together with the cover window WU, forms the exterior of the display device 1000. The housing component HM may contain a material with relatively high rigidity. For example, the housing component HM may include multiple frames and / or panels made of glass, plastic, and metal.

[0073] The housing component HM provides a predetermined housing space. The display panel DP can be housed within this housing space to be protected from external impacts.

[0074] Next, refer to Figure 3 The display panel DP includes a base SUB containing the display area DA and a non-display area PA. The non-display area PA may be defined along the boundary of the display area DA.

[0075] The display panel (DP) includes multiple pixels (PX). These pixels (PX) can be arranged on a substrate (SUB) within a display area (DA). Each pixel (PX) includes a light-emitting element and driving circuitry connected to that element. Each pixel (PX) emits light, for example, red, green, blue, or white light, and may include an organic light-emitting element (organic light-emitting diode) as an example.

[0076] The display panel DP may include multiple signal lines and pads. The multiple signal lines may include a scan line SL extending in the first direction DR1 and a data line DL and a drive voltage line PL extending in the second direction DR2.

[0077] The scan driver 20 generates a scan signal and transmits the scan signal to each pixel PX via the scan line SL. According to an embodiment, the scan driver 20 may be disposed on the left and right sides of the display area DA. This specification shows a structure in which the scan driver 20 is disposed on both sides of the substrate SUB; however, in another embodiment, the scan driver 20 may be disposed on only one side of the substrate SUB.

[0078] The pad PAD is located at one end of the display panel DP and includes multiple terminals P1, P2, P3, and P4. The pad PAD is exposed and not covered by an insulating layer, and can be electrically connected to the printed circuit board (PCB). The pad PAD can be electrically connected to the pad PCB_P of the PCB. The PCB can transmit signals or power from the IC driver chip 80 to the pad PAD.

[0079] The controller converts multiple image signals transmitted from the outside into multiple image data signals, and transmits the converted image data signals to the data driver 50 via terminal P1. Additionally, the controller can receive vertical synchronization signals, horizontal synchronization signals, and clock signals, generate control signals for controlling the scan driver 20 and the data driver 50, and transmit these control signals to each pixel PX via terminals P3 and P1. The controller transmits the drive voltage ELVDD (see...) via terminal P2. Figure 5B The controller transmits the common voltage ELVSS (see [reference]) to the drive voltage supply wiring 60 via terminal P4. Figure 5B Transmitted to each common voltage supply cabling 70.

[0080] The data driver 50 is disposed in the non-display area PA and generates and transmits data signals to each pixel PX. The data driver 50 may be disposed on one side of the display panel DP, and may be disposed, for example, between the pad PAD and the display area DA.

[0081] The drive voltage supply wiring 60 is disposed in the non-display area PA. For example, the drive voltage supply wiring 60 can be disposed between the data driver 50 and the display area DA. The drive voltage supply wiring 60 provides the drive voltage ELVDD to the pixel PX. The drive voltage supply wiring 60 can be disposed on the first direction DR1 and can be connected to multiple drive voltage lines PL disposed on the second direction DR2.

[0082] A common voltage supply wiring 70 is disposed in the non-display area PA. The common voltage supply wiring 70 may have a shape surrounding the substrate SUB. The common voltage supply wiring 70 transmits the common voltage ELVSS to an electrode (e.g., a second electrode) of the light-emitting element included in the pixel PX.

[0083] Below, refer to Figure 4 describe Figure 3 The region A shown includes the opening region DTA. Figure 4 yes Figure 1 and Figure 3 Enlarged top view of region A.

[0084] Reference Figure 4 As shown in the accompanying drawings, the display panel DP includes multiple signal lines SL and DL disposed on the substrate SUB, and multiple pixels PX. Each of the multiple pixels PX can be connected to multiple signal lines SL and DL. Figure 4 The scan line SL and data line DL among multiple signal lines are described as examples. However, this is shown as an example, and each pixel PX according to the embodiments described herein may be additionally connected to various signal lines, and is not limited to any one embodiment.

[0085] The hole area HA included in the display panel DP includes the opening area DTA and the peripheral area LA surrounding the opening area DTA.

[0086] The peripheral area LA is the region surrounding the opening area DTA. The peripheral area LA prevents damage to the wiring when the laser is used to form the opening area DTA. The peripheral area LA needs to maintain a minimum constant width. Furthermore, the peripheral area LA includes dams D1 and D2.

[0087] The scan lines SL and data lines DL have a semi-circular structure, superimposed on the peripheral region LA, and can bypass the opening region DTA. Multiple scan lines SL extend horizontally along the periphery of the opening region DTA. Here, the multiple scan lines SL can include scan lines, light emission control lines, initialization voltage lines, etc., depending on the signal. Multiple data lines DL extend vertically along the periphery of the opening region DTA. The multiple data lines DL can consist of drive voltage lines and drive low voltage lines, depending on the signal. According to an embodiment, the multiple scan lines SL and multiple data lines DL can be varied.

[0088] Next, refer to Figure 5A , Figure 5C and Figure 5D Describe the region surrounding the opening region DTA. Figure 5A This is a cross-sectional view of the display panel corresponding to the display area. Figure 5B This is a circuit diagram of a display device according to an embodiment. Figure 5C This is a cross-sectional view of the display panel, which has a defined outer area and an opening area. Figure 5D This is an enlarged view of the region at the end where the second electrode is located.

[0089] First, refer to Figure 5A Describes the stacking structure based on the display area (DA).

[0090] The substrate SUB according to embodiments may comprise an inorganic insulating material such as glass or an organic insulating material such as polyimide (PI) plastic. The substrate SUB may be single-layered or multi-layered. The substrate SUB may have a structure in which at least one matrix layer and at least one inorganic layer comprising sequentially stacked polymer resins are alternately stacked.

[0091] Substrate SUBs can have various degrees of flexibility. Substrate SUBs can be rigid substrates or flexible substrates that can be bent, folded, or rolled up.

[0092] A buffer film (BF) can be positioned on a substrate (SUB). The buffer film (BF) prevents impurities from being transported from the substrate (SUB) to the upper layer of the buffer film (specifically, the semiconductor layer (SC)), thereby preventing degradation of the semiconductor layer (SC) and reducing stress. The buffer film (BF) may comprise inorganic or organic insulating materials such as silicon nitride or silicon oxide. Some or all of the components of the buffer film (BF) may be omitted.

[0093] A semiconductor layer SC is positioned on a buffer film BF. The semiconductor layer SC may comprise at least one of polycrystalline silicon and oxide semiconductors. The semiconductor layer SC includes a channel region C, a first region S, and a second region D. The first region S and the second region D are respectively disposed on opposite sides of the channel region C. The channel region C may comprise a semiconductor with fewer impurities or no impurities compared to the first region S and the second region D, while the first region S and the second region D may comprise semiconductors with more impurities compared to the channel region C. The semiconductor layer SC may be made of oxide semiconductors, in which case a separate protective layer (not shown) may be added to protect the oxide semiconductor material from external environmental factors such as high temperatures.

[0094] A first inorganic insulating layer IL1 is disposed on the semiconductor layer SC. The first inorganic insulating layer IL1 may include silicon oxide (SiO2). X ), silicon nitride (SiN) X ) and silicon oxynitride (SiO) X N Y At least one of the following: a single layer or multiple layers.

[0095] The gate electrode GE and the first capacitor electrode CE1 are positioned on the first inorganic insulating layer IL1. The gate electrode GE and the first capacitor electrode CE1 can be multilayer or single-layer in which at least one metal film including copper (Cu), copper alloy, aluminum (Al), aluminum alloy, molybdenum (Mo), and molybdenum alloy is stacked. The gate electrode GE can be stacked with the channel region C of the semiconductor layer SC.

[0096] The second inorganic insulating layer IL2 is positioned on the gate electrode GE and the first inorganic insulating layer IL1. The second inorganic insulating layer IL2 may include silicon oxide (SiO2). X ), silicon nitride (SiN) X ) and silicon oxynitride (SiO) X N Y At least one of the following: a single layer or multiple layers.

[0097] The upper electrode AE ​​and the second capacitor electrode CE2 are positioned on the second inorganic insulating layer IL2. The second capacitor electrode CE2 and the upper electrode AE ​​can be different parts of a conductive pattern. The second capacitor electrode CE2 and the upper electrode AE ​​can be electrically connected.

[0098] The second capacitor electrode CE2 and the upper electrode AE ​​can be multilayer or single-layer in which a metal film including at least one of copper (Cu), copper alloy, aluminum (Al), aluminum alloy, molybdenum (Mo) and molybdenum alloy is stacked.

[0099] The third inorganic insulating layer IL3 is positioned on the upper electrode AE ​​and the second capacitor electrode CE2. The third inorganic insulating layer IL3 may include silicon oxide (SiO2).X ), silicon nitride (SiN) X ) and silicon oxynitride (SiO) X N Y At least one of the following: a single layer or multiple layers.

[0100] The source electrode SE and the drain electrode DE are positioned on the third inorganic insulating layer IL3. The source electrode SE and the drain electrode DE are connected to the first region S and the second region D of the semiconductor layer SC through contact holes formed in the third inorganic insulating layer IL3, the first inorganic insulating layer IL1, and the second inorganic insulating layer IL2, respectively.

[0101] The source electrode SE and drain electrode DE can be made of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), and can be a single-layer or multi-layer structure.

[0102] The first organic insulating layer IL4 and the second organic insulating layer IL5 are sequentially positioned on the third inorganic insulating layer IL3, the source electrode SE, and the drain electrode DE. The first organic insulating layer IL4 and the second organic insulating layer IL5 may comprise organic insulating materials such as general polymers (such as polymethyl methacrylate (PMMA) or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, and siloxane polymers.

[0103] The connecting member CE can be positioned between the first organic insulating layer IL4 and the second organic insulating layer IL5. The connecting member CE can connect the drain electrode DE and the first electrode E1. However, the invention is not limited thereto; according to embodiments, the drain electrode DE and the first electrode E1 can be directly connected without the connecting member.

[0104] The first electrode E1 is positioned on the second organic insulating layer IL5. The first electrode E1 is connected to the connecting member CE through a contact hole in the second organic insulating layer IL5. The first electrode E1 is electrically connected to the drain electrode DE.

[0105] The first electrode E1 may include metals such as silver (Ag), lithium (Li), calcium (Ca), aluminum (Al), magnesium (Mg), and gold (Au), and may also include transparent conductive oxides (TCOs) such as indium tin oxide (ITO) and indium zinc oxide (IZO). The first electrode E1 may consist of a single layer comprising a metallic material or a transparent conductive oxide, or multiple layers comprising a metallic material and a transparent conductive oxide. For example, the first electrode E1 may have a three-layer structure of indium tin oxide (ITO) / silver (Ag) / indium tin oxide (ITO).

[0106] A transistor consisting of a gate electrode GE, a semiconductor layer SC, a source electrode SE, and a drain electrode DE is connected to a first electrode E1 to supply current to the light-emitting element LD.

[0107] The pixel defining layer IL6 and the spacer IL7 are positioned on the second organic insulating layer IL5 and the first electrode E1.

[0108] The pixel defining layer IL6 is superimposed on at least a portion of the first electrode E1 and has an opening defining a light-emitting area. The opening may have a planar shape similar to the planar shape of the first electrode E1. The opening may have a rhomboid or octagonal shape in the plane, but is not limited to these, and may have any shape such as quadrilateral, polygon, circle or ellipse.

[0109] The pixel-defining layer IL6 and the spacer IL7 may include organic insulating materials such as general polymers (such as polymethyl methacrylate (PMMA) or polystyrene (PS)), polymer derivatives with phenolic groups, acrylic polymers, imide polymers and siloxane polymers.

[0110] The intermediate layer EL is positioned on the first electrode E1, stacked with the opening. The intermediate layer EL may include an emitter layer and a functional layer.

[0111] Intermediate layers (ELs) can produce light of a predetermined color. In this specification, intermediate layers (ELs) are shown positioned within the display area DA and the peripheral area LA; however, at least some intermediate layers (ELs) may be positioned only within the display area DA and not within the peripheral area LA. For example, an emission layer can be formed using a mask to be positioned only within the opening of the pixel-defining layer IL6. In this case, the emission layer is positioned within the display area DA and not within the peripheral area LA. Functional layers may be positioned within the display area DA and the peripheral area LA.

[0112] The emitter layer may comprise organic and / or inorganic materials. Furthermore, the functional layer may comprise at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). The functional layer may be positioned between the first electrode E1 and the emitter layer, and / or may be positioned between the emitter layer and the second electrode E2. The functional layer may have a shape that overlaps the entire surface of the substrate SUB. The functional layer may be distributed across multiple pixel PXs.

[0113] In this specification, the intermediate layer EL is stacked over the entire surface of the substrate SUB, illustrating an embodiment in which the functional layer is stacked over the entire surface of the substrate SUB. As described above, the emission layer may be formed only within the opening of the pixel defining layer IL6.

[0114] The second electrode E2 is positioned on the intermediate layer EL. The second electrode E2 may include a reflective metal or a transparent conductive oxide (TCO) such as indium tin oxide (ITO) and indium zinc oxide (IZO). The reflective metal includes calcium (Ca), barium (Ba), magnesium (Mg), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), etc.

[0115] The first electrode E1, the intermediate layer EL, and the second electrode E2 can constitute a light-emitting element (LD). Here, the first electrode E1 can be an anode serving as a hole injection electrode, and the second electrode E2 can be a cathode serving as an electron injection electrode. However, in an embodiment, according to the driving method of the emitting display device, the first electrode E1 can be a cathode, and the second electrode E2 can be an anode.

[0116] Holes and electrons are injected into the organic intermediate layer EL from the first electrode E1 and the second electrode E2, respectively. When the excitons formed by the combination of the injected holes and electrons descend from the excited state to the ground state, light is emitted.

[0117] The encapsulation layer ENC is positioned on the second electrode E2. The encapsulation layer ENC can cover the sides and top surface of the light-emitting element LD, thereby sealing the light-emitting element LD. Since the light-emitting element LD is very susceptible to moisture and oxygen, the encapsulation layer ENC seals the light-emitting element LD to prevent moisture and oxygen from flowing in from the outside.

[0118] The encapsulation layer ENC may include multiple layers and may be formed from a composite film including both inorganic and organic layers (e.g., a first encapsulation inorganic layer EIL1 and an encapsulation organic layer EOL), and the encapsulation layer ENC may be formed from three layers in which the first encapsulation inorganic layer EIL1, the encapsulation organic layer EOL, and the second encapsulation inorganic layer EIL2 are sequentially formed.

[0119] The first encapsulation inorganic layer EIL1 can cover the second electrode E2. The first encapsulation inorganic layer EIL1 can prevent external moisture or oxygen from penetrating into the light-emitting element (LD). For example, the first encapsulation inorganic layer EIL1 can include silicon nitride, silicon oxide, or a combination thereof. The first encapsulation inorganic layer EIL1 can be formed by a deposition process.

[0120] An organic encapsulation layer (EOL) is disposed on and in contact with the first inorganic encapsulation layer (EIL1). Curvature formed on the upper surface of the first inorganic encapsulation layer (EIL1) or particles present on the first inorganic encapsulation layer (EIL1) are covered by the organic encapsulation layer (EOL), thereby preventing the surface condition of the upper surface of the first inorganic encapsulation layer (EIL1) from affecting the component formed on the organic encapsulation layer (EOL). Additionally, the organic encapsulation layer (EOL) can alleviate stress between contact layers. The organic encapsulation layer (EOL) may comprise organic materials and can be formed using solution processes such as spin coating, slot coating, or inkjet printing.

[0121] The second encapsulation inorganic layer EIL2 is disposed on the encapsulation organic layer EOL to cover the encapsulation organic layer EOL. The second encapsulation inorganic layer EIL2 can be stably formed on a relatively flat surface, rather than being disposed on the first encapsulation inorganic layer EIL1. The second encapsulation inorganic layer EIL2 prevents moisture from penetrating to the outside by encapsulating moisture emanating from the encapsulation organic layer EOL. The second encapsulation inorganic layer EIL2 may comprise silicon nitride, silicon oxide, or a combination thereof. The second encapsulation inorganic layer EIL2 can be formed by a deposition process.

[0122] Additionally, a capping layer may be included, positioned between the second electrode E2 and the encapsulation layer ENC. The capping layer may comprise an organic material. The capping layer protects the second electrode E2 from subsequent processes (e.g., sputtering processes) and improves the luminous efficiency of the light-emitting element (LD). The capping layer may have a refractive index greater than that of the first encapsulation inorganic layer EIL1.

[0123] While the above description has covered one transistor included in a single pixel PX, each pixel PX can include multiple transistors. See below for reference. Figure 5B The description includes examples of multiple transistors in each pixel PX.

[0124] like Figure 5B As shown, a pixel PX of the display device according to an embodiment includes a plurality of transistors T1, T2, T3, T4, T5, T6 and T7 connected to a plurality of wirings 127, 128, 151, 152, 153, 154, 155, 171, 172 and 741, a storage capacitor Cst, a boost capacitor Cbt and a light-emitting diode LED.

[0125] Multiple wirings 127, 128, 151, 152, 153, 154, 155, 171, 172, and 741 are connected to a pixel PX. These wirings include a first initialization voltage line 127, a second initialization voltage line 128, a first scan signal line 151, a second scan signal line 152, an initialization control line 153, a bypass control line 154, an emission control line 155, a data line 171, a drive voltage line 172, and a common voltage line 741.

[0126] The first scan signal line 151 is connected to the gate driver and transmits the first scan signal GW to the second transistor T2. A voltage with the opposite polarity to the voltage applied to the first scan signal line 151 can be applied to the second scan signal line 152 in the same timing as the signal applied to the first scan signal line 151. For example, when a negative voltage is applied to the first scan signal line 151, a positive voltage can be applied to the second scan signal line 152. The second scan signal line 152 transmits the second scan signal GC to the third transistor T3.

[0127] Initialization control line 153 transmits the initialization control signal GI to the fourth transistor T4. Bypass control line 154 transmits the bypass signal GB to the seventh transistor T7. Bypass control line 154 can be formed from the first scan signal line 151 of the previous stage. Light emission control line 155 transmits the light emission control signal EM to the fifth transistor T5 and the sixth transistor T6.

[0128] Data line 171 is a wiring that transmits the data voltage DATA generated from the data driver (not shown), and the brightness of the light emitted by the light-emitting diode LED changes according to the data voltage DATA applied to the pixel PX.

[0129] The driving voltage line 172 applies the driving voltage ELVDD. The first initialization voltage line 127 transmits the first initialization voltage VINT, and the second initialization voltage line 128 transmits the second initialization voltage AINT. The common voltage line 741 applies the common voltage ELVSS to the cathode of the light-emitting diode (LED). In the embodiment described herein, the voltages applied to the driving voltage line 172, the first initialization voltage line 127, the second initialization voltage line 128, and the common voltage line 741 can all be constant voltages.

[0130] The plurality of transistors may include a driving transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The plurality of transistors may include oxide transistors comprising oxide semiconductors and silicon transistors comprising polycrystalline silicon semiconductors. For example, the third transistor T3 and the fourth transistor T4 may be made of oxide transistors, and the driving transistors T1, T2, T5, T6, and T7 may be made of silicon transistors. However, the invention is not limited thereto, and the plurality of transistors may all be formed of silicon transistors.

[0131] Above, it has been described that a pixel PX consists of seven transistors T1 to T7, a storage capacitor Cst, and a boost capacitor Cbt, but it is not limited thereto. The number of transistors and capacitors and their connection relationships can be changed in a variety of ways.

[0132] Next, refer to Figure 5C and Figure 5D Describe the opening region DTA and the hole region HA, which includes the opening region DTA and its peripheral region LA. Descriptions of constituent elements identical to those described above are omitted.

[0133] First, in the peripheral region LA, a buffer film BF and a first inorganic insulating layer IL1 can be disposed on the substrate SUB. The buffer film BF and the first inorganic insulating layer IL1 can extend from the display region DA. The embodiment described herein shows the buffer film BF and the first inorganic insulating layer IL1 extending into the peripheral region LA; however, the embodiment is not limited thereto, and at least one of the buffer film BF, the first inorganic insulating layer IL1, the second inorganic insulating layer IL2, and the third inorganic insulating layer IL3 can extend into the peripheral region LA.

[0134] According to an embodiment, a first metal layer MCL can be positioned within a peripheral region LA. The first metal layer MCL can be stacked on a first inorganic insulating layer IL1, overlapping with the peripheral region LA. The first metal layer MCL can be stacked with the ends of the second inorganic insulating layer IL2 and the third inorganic insulating layer IL3 extending into the peripheral region LA. The first metal layer MCL can have a structure including a step difference while being stacked with the upper surfaces of the third inorganic insulating layer IL3 and the first inorganic insulating layer IL1 positioned within the peripheral region LA. However, the first metal layer MCL is not limited to this type; the shape of the first metal layer MCL can be varied according to the shape of the peripheral region LA of the display panel DP.

[0135] The first metal layer MCL may include, but is not limited to, silver (Ag) or aluminum (Al), and may include various metals such as titanium (Ti) or molybdenum (Mo).

[0136] On the first metal layer MCL, a first organic insulating layer IL4, a second organic insulating layer IL5, a pixel defining layer IL6, and a spacer IL7 extending from the display area DA can be provided. The ends of the first organic insulating layer IL4 and the second organic insulating layer IL5 can extend to the peripheral area LA in a shape that covers a portion of the first metal layer MCL, but are not limited thereto.

[0137] The first organic insulating layer IL4, the second organic insulating layer IL5, the pixel defining layer IL6, and the spacer IL7 may extend to the end of the first metal layer MCL. The end of the first metal layer MCL may be separate from the first organic insulating layer IL4, the second organic insulating layer IL5, the pixel defining layer IL6, and the spacer IL7.

[0138] The intermediate layer EL can extend from the display area DA to a portion of the peripheral area LA. (See reference...) Figure 5C and Figure 5D The end EL-E of the intermediate layer EL can cover the end MCL-E of the first metal layer MCL. The end EL-E of the intermediate layer EL can have a shape that protrudes much more toward the opening region DTA than the end MCL-E of the first metal layer MCL.

[0139] The second electrode E2, positioned on the intermediate layer EL, can extend from the display area DA to a portion of the peripheral area LA. For example... Figure 5D As shown, the end E2-E of the second electrode E2 can substantially match the end MCL-E of the first metal layer MCL. The end E2-E of the second electrode E2 can substantially align with the end MCL-E of the first metal layer MCL. In this embodiment and other embodiments described herein, substantially aligned can mean that the end E2-E of the second electrode E2 matches the end MCL-E of the first metal layer MCL, or that one of the ends slightly protrudes.

[0140] The end E2-E of the second electrode E2 can have a flat shape. In the manufacturing process, the second electrode E2 can be formed by laser irradiation of certain areas after the formation of the second electrode material layer. Laser irradiation removes unwanted portions of the second electrode material layer. At this time, the end E2-E of the second electrode E2 will be formed with burrs. That is, the second electrode E2, having a relatively thin thickness, will have an end E2-E that curls up due to heat transferred from the laser. However, according to an embodiment, the second electrode E2 can be stacked with a first metal layer MCL, which can block heat transfer to the second electrode E2 via the laser. This minimizes the shape deformation of the intermediate layer EL stacked with the first metal layer MCL and the second electrode E2. Specifically, the second electrode E2 stacked with the first metal layer MCL can be set to a flat shape without curling up.

[0141] At least two dams, D1 and D2, can be located in the peripheral area LA. For example, the first dam D1 and the second dam D2 can be located in a sequence adjacent to the display area DA. The first dam D1 and the second dam D2 can be located in the peripheral area LA and can be located on the first inorganic insulating layer IL1.

[0142] The first dam D1 may include a first-first sub-dam D1-a, a first-second sub-dam D1-b, and a first-third sub-dam D1-c. The first-first sub-dam D1-a may be located on the same layer as the second organic insulating layer IL5 located in the display area DA, and may contain the same material as the second organic insulating layer IL5. The first-first sub-dam D1-a may be formed in the same process as the second organic insulating layer IL5 located in the display area DA. The first-second sub-dam D1-b may be located on the same layer as the pixel defining layer IL6 located in the display area DA, and may contain the same material as the pixel defining layer IL6. The first-second sub-dam D1-b may be formed in the same process as the pixel defining layer IL6 located in the display area DA. The first-third sub-dam D1-c may be located on the same layer as the spacer IL7 located in the display area DA, and may contain the same material as the spacer IL7. The first-third sub-dam D1-c may be formed in the same process as the spacer IL7 located in the display area DA.

[0143] The second dam D2 may include a second-first sub-dam D2-a, a second-second sub-dam D2-b, a second-third sub-dam D2-c, and a second-fourth sub-dam D2-d. The second-first sub-dam D2-a may be located on the same layer as the first organic insulating layer IL4 located in the display area DA, and may contain the same material as the first organic insulating layer IL4. The second-first sub-dam D2-a may be formed in the same process as the first organic insulating layer IL4 located in the display area DA. The second-second sub-dam D2-b may be located on the same layer as the second organic insulating layer IL5 located in the display area DA, and may contain the same material as the second organic insulating layer IL5. The second-second sub-dam D2-b may be formed in the same process as the second organic insulating layer IL5 located in the display area DA. The second-third sub-dam D2-c may be located on the same layer as the pixel defining layer IL6 located in the display area DA, and may contain the same material as the pixel defining layer IL6. The second-third sub-dam D2-c may be formed in the same process as the pixel defining layer IL6 located in the display area DA. The second-fourth sub-dam D2-d can be positioned on the same layer as the spacer IL7 located in the display area DA, and can include the same material as the spacer IL7. The second-fourth sub-dam D2-d can be formed in the same process as the spacer IL7 located in the display area DA.

[0144] The embodiments described herein illustrate a first dam D1 formed with a three-layer structure and a second dam D2 formed with a four-layer structure. However, the embodiments are not limited to this; the positions can be changed when the first dam D1 is formed with a four-layer structure and the second dam D2 with a three-layer structure, or when both the first dam D1 and the second dam D2 are formed with a three-layer structure, or when both the first dam D1 and the second dam D2 are formed with a four-layer structure. Furthermore, it goes without saying that dams with a double-layer structure comprising only a portion of the aforementioned sub-dams can be provided. Additionally, although this specification shows an embodiment where two dams D1 and D2 are located in the peripheral region LA, the number is not limited; two or more dams can be located in the peripheral region LA.

[0145] Moreover, such as Figure 4 As shown, the dams D1 and D2 described herein have annular shapes surrounding the opening region DTA in a plane. However, this is an exemplary shape, and the first dam D1 and the second dam D2 may have shapes different from the opening region DTA. For example, the first dam D1 and the second dam D2 may have shapes including polygons, ellipses, or closed line shapes containing at least some curves, or may be configured to include multiple partially broken patterns, and are not limited to any one embodiment.

[0146] The first layer EL-1 can be positioned on the first dam D1. The first layer EL-2 can be positioned on the second dam D2. The first layer EL-3 can be positioned between the second dam D2 and the opening area DTA. The first layer EL-1, the first layer EL-2, and the first layer EL-3 can be made of the same material as the intermediate layer EL and can be formed in the same process as the intermediate layer EL.

[0147] The first-first-layer EL-1, the first-second-layer EL-2, and the first-third-layer EL-3 may include at least a portion of the functional layers within the intermediate layer EL. Specifically, the first-first-layer EL-1, the first-second-layer EL-2, and the first-third-layer EL-3 may include at least one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. The intermediate layer EL and the first-first-layer EL-1 may be separate. The first inorganic insulating layer IL1 may be exposed in the region separating the intermediate layer EL and the first-first-layer EL-1 from each other. The gap region between the end EL-E of the intermediate layer EL and the end EL-1-E of the first-first-layer EL-1 may be a first opening region R1.

[0148] Reference Figure 5D The distance W1 between the end EL-E of the intermediate layer EL and the end MCL-E of the first metal layer MCL can be approximately 35 micrometers or greater. When the distance W1 is less than approximately 35 micrometers, it becomes difficult to control the process of separating the sacrificial layer during manufacturing. It also becomes difficult to control the process of separating only the sacrificial layer while maintaining the first metal layer MCL and the second electrode E2.

[0149] The first-first layer EL-1 and the first-second layer EL-2 can be separated from each other. When the first-first layer EL-1 and the first-second layer EL-2 are separated from each other, a portion of the first inorganic insulating layer IL1 can be exposed. The first-first layer EL-1 and the first-second layer EL-2 are separated from each other such that the area exposing the first inorganic insulating layer IL1 can be the second opening region R2.

[0150] The first-second layer EL-2 and the first-third layer EL-3 can be separated from each other. When the first-second layer EL-2 and the first-third layer EL-3 are separated from each other, a portion of the first inorganic insulating layer IL1 can be exposed. The first-second layer EL-2 and the first-third layer EL-3 are separated from each other such that the area exposing the first inorganic insulating layer IL1 can be the third opening region R3.

[0151] The first opening region R1, the second opening region R2, and the third opening region R3 are regions from which the intermediate material layer has been removed, and can block the path of foreign particles from penetrating from the outside along the intermediate material layer.

[0152] A portion of the second electrode E2 extending from the display area DA can be positioned within the peripheral area LA. Additionally, a second-first layer E2-1 can be positioned within the peripheral area LA. The second-first layer E2-1 can comprise the same material as the second electrode E2 and can be formed in the same process as the second electrode E2.

[0153] This specification describes an embodiment in which the second-first layer E2-1 and the first-third layer EL-3 are formed in a region adjacent to the opening region DTA. However, the embodiment is not limited thereto, and the second-first layer E2-1 and the first-third layer EL-3 may be omitted based on the design of the manufacturing process. When the second-first layer E2-1 and the first-third layer EL-3 are omitted, the third opening region R3 may be extended. In the third opening region R3, the substrate SUB, the buffer film BF, the first inorganic insulating layer IL1, the first encapsulation inorganic layer EIL1, and the second encapsulation inorganic layer EIL2 may be stacked.

[0154] In the peripheral region LA, a first encapsulated inorganic layer EIL1 extending from the display region DA can be positioned. Additionally, the end of the encapsulated organic layer EOL extending from the display region DA can be positioned. In the process of forming the encapsulated organic layer EOL, a first dam D1 can control material diffusion. The encapsulated organic layer EOL can have a shape that fills the space between the end of the display region DA and the first dam D1. On the encapsulated organic layer EOL, a second encapsulated inorganic layer EIL2, stacked with the entire surface of the substrate SUB, can be positioned.

[0155] In the first opening region R1, the first encapsulation inorganic layer EIL1, the encapsulation organic layer EIL1, and the second encapsulation inorganic layer EIL2 can be positioned on the first inorganic insulating layer IL1. Furthermore, in the second opening region R2, the first encapsulation inorganic layer EIL1 and the second encapsulation inorganic layer EIL2 can be positioned on the first inorganic insulating layer IL1. Additionally, in the third opening region R3, the first encapsulation inorganic layer EIL1 and the second encapsulation inorganic layer EIL2 can be positioned on the first inorganic insulating layer IL1.

[0156] The aforementioned first electronic module EM1 can be inserted into the region overlapping with the opening region DTA. The inner surface of the opening region DTA can be defined by the ends of the substrate SUB, the buffer film BF, the first inorganic insulating layer IL1, the first-third layer EL-3, the second-first layer E2-1, the first encapsulation inorganic layer EIL1, and the second encapsulation inorganic layer EIL2. The ends of the substrate SUB, the buffer film BF, the first inorganic insulating layer IL1, the first-third layer EL-3, the second-first layer E2-1, the first encapsulation inorganic layer EIL1, and the second encapsulation inorganic layer EIL2 are aligned with each other to form the opening region DTA. However, the embodiment is not limited to this; of course, some of the above-mentioned constituent elements can be omitted or added to form the inner surface of the opening region DTA.

[0157] Next, refer to Figures 6 to 11 A method for manufacturing a display device 1000 according to an embodiment is described. Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 These are cross-sectional views of certain areas of the display panel based on the manufacturing process. Descriptions of structural elements identical to those described above will be omitted.

[0158] First, such as Figure 6 As shown, the display device 1000 according to an embodiment forms a transistor Tr stacked on a display area DA and disposed on a substrate SUB, and a first electrode E1 connected to the transistor Tr. The transistor Tr and the first electrode E1 can be formed by patterning a conductive material.

[0159] A pixel defining layer IL6 and a spacer IL7 can be formed on the first electrode E1. The pixel defining layer IL6 can be formed as an opening including at least a portion of the first electrode E1. Simultaneously, a first dam D1 and a second dam D2 can be formed in the peripheral region LA. The first dam D1 and the second dam D2 can be formed as a multilayer structure containing organic material.

[0160] Then, multiple sacrificial layers S1, S2, and S3 are formed in the peripheral region LA. The sacrificial layers S1, S2, and S3 may comprise metallic materials, and for example, may comprise any of silver (Ag), titanium (Ti), and molybdenum (Mo). When the sacrificial layers S1, S2, and S3 comprise silver (Ag) as an example, the thickness t1 of the sacrificial layers S1, S2, and S3 may be about 800 angstroms to 1000 angstroms. When the sacrificial layers S1, S2, and S3 comprise titanium (Ti) or molybdenum (Mo) as examples, the thickness t1 of the sacrificial layers S1, S2, and S3 may be about 200 angstroms to 300 angstroms. However, the thickness t1 of the sacrificial layers S1, S2, and S3 is not limited to this range and can be varied according to embodiments; the thinner the thickness, the easier it is for the sacrificial layers to be separated by the laser irradiation process described later.

[0161] The first sacrificial layer S1 is positioned between the first metal layer MCL and the first dam D1. The second sacrificial layer S2 is positioned between the first dam D1 and the second dam D2. The third sacrificial layer S3 is positioned between the second dam D2 and the region where the opening region DTA will be formed. Although the embodiments described herein show one sacrificial layer positioned in each region, multiple sacrificial layers can be provided in one region according to the design. For example, multiple third sacrificial layers can be positioned between the second dam D2 and the region where the opening region DTA will be formed.

[0162] Simultaneously, the first metal layer MCL located in the peripheral region LA can be formed concurrently with, but is not limited to, the source electrode SE and the drain electrode DE, and can be formed by separate processes. The first metal layer MCL can include silver (Ag) or aluminum (Al). When the first metal layer MCL includes silver (Ag), the thickness t2 of the first metal layer MCL can be from about 800 angstroms to about 1000 angstroms. The thicker the first metal layer MCL, the more effectively it can block heat.

[0163] The distance W1 between the end of the first sacrificial layer S1 and the end of the first metal layer MCL can vary depending on the materials included in the first sacrificial layer S1 and the first metal layer MCL. For example, when the materials included in the first sacrificial layer S1 and the first metal layer MCL have excellent laser selectivity, the first sacrificial layer S1 and the first metal layer MCL can be arranged in a fairly close configuration. This is because the first sacrificial layer S1 can be removed without excessive laser irradiation or heat transfer to the first metal layer MCL. When the materials included in the first sacrificial layer S1 and the first metal layer MCL are the same, a predetermined interval is required between the first sacrificial layer S1 and the first metal layer MCL. This is because the first metal layer MCL should not have excessive heat transfer when the first sacrificial layer S1 is sufficiently removed by the irradiated laser. In the case of an embodiment, the distance W1 between the first sacrificial layer S1 and the first metal layer MCL can be about 35 micrometers or more. However, the distance W1 is not limited to this distance and can vary depending on various conditions such as the processing precision of the manufacturing equipment, the size of the laser beam, and the spacing of the emission (shots).

[0164] Next, as Figure 7 As shown, an intermediate material layer EL-a and a second electrode material layer E2-a are formed by a deposition process.

[0165] The intermediate material layer EL-a may include an emitter layer and a functional material layer. The emitter layer is formed using a mask to be positioned only within an opening in the pixel-defining layer IL6, and the functional material layer is formed to be superimposed on the entire surface of the substrate SUB. The functional material layer may include a material layer for forming at least one of the hole injection layer (HIL), hole transport layer (HTL), electron transport layer (ETL), and electron injection layer (EIL) as described above.

[0166] Furthermore, the emitter layer, which is positioned only in the opening, is not shown separately; the intermediate material layer EL-a is shown as being superimposed on the entire surface of the substrate SUB. This indicates that the functional material layer is superimposed on the entire surface of the substrate SUB, and the emitter layer, which is positioned only in the opening, is omitted.

[0167] Then, as Figure 8 As shown, the region IRA is illuminated by a laser on the peripheral region LA. According to an embodiment, lasers with different energy densities (ED) can be used to illuminate the region IRA. For example, a laser with a high energy density can illuminate the regions where sacrificial layers S1, S2, and S3 are positioned, while a laser with a low energy density can illuminate other regions. The laser can illuminate from the display region DA toward the region where the opening region DTA will be formed.

[0168] Through this laser irradiation process, such as Figure 9 As shown, sacrificial layers S1, S2, and S3 are separated from the first inorganic insulating layer IL1. Through laser ablation, sacrificial layers S1, S2, and S3 are separated from the first inorganic insulating layer IL1, and the intermediate material layer EL-a and the second electrode material layer E2-a, positioned on sacrificial layers S1, S2, and S3, are also separated. Furthermore, in areas where sacrificial layers S1, S2, and S3 are not positioned but where laser irradiation occurs, the second electrode material layer E2-a is removed, allowing the formation of the second electrode E2 and the second-first layer E2-1.

[0169] Removal via laser irradiation and sacrificial layer, such as Figure 10 As shown, in the peripheral region LA, a first-first layer EL-1, a first-second layer EL-2, and a first-third layer EL-3 are formed. Furthermore, a second-first layer E2-1 is formed positioned on the first-third layer EL-3. In the display region DA, a light-emitting element LD is formed, comprising a first electrode E1, an intermediate layer EL, and a second electrode E2.

[0170] A first opening region R1 can be formed between the intermediate layer EL and the first layer EL-1, a second opening region R2 can be formed between the first layer EL-1 and the first layer EL-2, and a third opening region R3 can be formed between the first layer EL-2 and the first layer EL-3. Each opening region R1, R2, and R3 can expose the first inorganic insulating layer IL1 and can be a region where the intermediate material layer is lacking.

[0171] The ends of the intermediate layer EL and the second electrode E2 can extend into a portion of the peripheral region LA. In this case, because heat is blocked by the first metal layer MCL, the end of the second electrode E2 can be formed into a flat shape without curling. Furthermore, since the intermediate layer EL is removed from the area separated from the sacrificial layer, it can be formed from the shape of the end covering the first metal layer MCL.

[0172] Then, as Figure 11As shown, a first encapsulated inorganic layer EIL1 can be formed on the entire surface of the substrate SUB. Additionally, an encapsulated organic layer EIL1 can be formed and positioned within a portion of the peripheral region LA while being overlaid with the display region DA. During the process of forming the encapsulated organic layer EIL1, dams D1 and D2 can prevent the diffusion of liquid organic material. The encapsulated organic layer EIL1 can be formed by inkjet printing, whereby liquid organic material is coated onto the first encapsulated inorganic layer EIL1. In this case, dams D1 and D2 define the boundaries of the areas coated with liquid organic material and prevent the liquid organic material from overflowing outside of dams D1 and D2. Subsequently, a second encapsulated inorganic layer EIL2 can be formed on the encapsulated organic layer EIL1, such that the second encapsulated inorganic layer EIL2 is overlaid on the entire surface of the substrate SUB. The first encapsulated inorganic layer EIL1 and the second encapsulated inorganic layer EIL2 can be in contact with each other within the peripheral region LA.

[0173] Then, the opening region DTA is formed, thereby forming with Figure 5C A similar structure. The opening region DTA can be formed as a through-display panel DP. The opening region DTA can be formed by laser or drilling processes. The opening region DTA can be equipped with the aforementioned first electronic module EM1. The opening region DTA can be formed by the aligned inner surfaces of the ends of the substrate SUB, the ends of the buffer film BF, the ends of the first inorganic insulating layer IL1, the ends of the first-third layer EL-3, the ends of the second-first layer E2-1, the ends of the first encapsulation inorganic layer EIL1, and the ends of the second encapsulation inorganic layer EIL2.

[0174] In the following text, refer to Figures 12A to 12D A display device 1000 according to an embodiment is described. Figure 12A , Figure 12B , Figure 12C and Figure 12D These are cross-sectional views of the display panel according to the embodiment. Descriptions of components identical to those described above are omitted.

[0175] Reference Figure 12A According to the embodiment, the first metal layer MCL1 can be stacked with a portion of the first organic insulating layer IL4. Specifically, one end of the first metal layer MCL1 can be disposed on the upper surface of the first organic insulating layer IL4, and can have a shape that extends along the side of the first organic insulating layer IL4 while contacting the upper surface of the first inorganic insulating layer IL1 disposed in the peripheral region LA.

[0176] The first metal layer MCL1 can be formed after the formation of the first organic insulating layer IL4 and before the formation of the second organic insulating layer IL5. The first metal layer MCL1 can comprise the same material as the connecting member CE and can be manufactured in the same process as the connecting member CE. However, the first metal layer MCL1 is not limited to this, and even if it is positioned on the same layer as the connecting member CE, it can be manufactured using a process with different masks.

[0177] Next, refer to Figure 12B According to an embodiment, the first metal layer MCL1 can be stacked with a portion of the second organic insulating layer IL5. One end of the first metal layer MCL1 can be disposed between the second organic insulating layer IL5 and the pixel defining layer IL6. Specifically, one end of the first metal layer MCL1 can be positioned on the upper surface of the second organic insulating layer IL5 and can have a shape that extends along the side of the second organic insulating layer IL5 while contacting the first inorganic insulating layer IL1 positioned in the peripheral region LA.

[0178] The first metal layer MCL1 can be formed after the formation of the second organic insulating layer IL5 and before the formation of the pixel defining layer IL6. The first metal layer MCL1 can comprise the same material as the first electrode E1 and can be manufactured in the same process as the first electrode E1. However, the first metal layer MCL1 is not limited to this, and even if it is located on the same layer as the first electrode E1, it can be manufactured using a process with different masks.

[0179] Next, refer to Figure 12C According to an embodiment, the first metal layer MCL1 can be stacked with a portion of the pixel defining layer IL6. One end of the first metal layer MCL1 can be disposed between the pixel defining layer IL6 and the spacer IL7. Specifically, one end of the first metal layer MCL1 can be positioned on the upper surface of the pixel defining layer IL6 and has a shape that extends along the side of the pixel defining layer IL6 and the second organic insulating layer IL5 while contacting the first inorganic insulating layer IL1 positioned in the peripheral region LA.

[0180] The first metal layer MCL1 can be formed after the pixel defining layer IL6 and before the spacer IL7. The first metal layer MCL1 can be fabricated using a separate mask.

[0181] Next, refer to Figure 12D According to the embodiment, the first metal layer MCL1 can be stacked with the spacer IL7. One end of the first metal layer MCL1 can be disposed on the upper surface of the spacer IL7, and has a shape that extends along the side of the spacer IL7, the pixel defining layer IL6, and the second organic insulating layer IL5 while contacting the first inorganic insulating layer IL1 disposed in the peripheral region LA.

[0182] The first metal layer MCL1 can be formed after the spacer IL7 is formed and before the intermediate layer EL is formed. The first metal layer MCL1 can be manufactured using a separate mask.

[0183] In the following text, refer to Figures 13A to 13E A display device 1000 according to an embodiment is described. Figure 13A , Figure 13B , Figure 13C , Figure 13D and Figure 13E These are cross-sectional views of the display panel according to the embodiment. For ease of explanation of this embodiment, descriptions of components identical to those described above have been omitted.

[0184] Reference Figure 13A According to the embodiment, the display device 1000 may further include a second metal layer MCL2 superimposed on the second dam D2 and a third metal layer MCL3 superimposed on the end of the peripheral region LA. The second metal layer MCL2 and the third metal layer MCL3 may be made of the same material as the first metal layer MCL1 and may be formed in the same process as the first metal layer MCL1.

[0185] The second metal layer MCL2 can be positioned between the first inorganic insulating layer IL1 and the bottom surface of the second dam D2. The two ends of the second metal layer MCL2 can have a shape that protrudes beyond the bottom surface of the second dam D2.

[0186] The first and second layers EL-2 can be positioned above the second dam D2. The first and second layers EL-2 can cover the upper and side surfaces of the second dam D2 while also covering the ends of the second metal layer MCL2. The first and second layers EL-2 can contact the first inorganic insulating layer IL1 while covering the upper and side surfaces of the second metal layer MCL2 exposed by the second dam D2.

[0187] The second layer E2-2 can be disposed on the first layer EL-2. The second layer E2-2 can cover the upper and side surfaces of the second dam D2. The ends of the second layer E2-2 can substantially coincide with the ends of the second metal layer MCL2. Here, the fact that the ends of the second layer E2-2 and the ends of the second metal layer MCL2 substantially coincide includes that the two ends are completely aligned or that either end can protrude slightly.

[0188] In the laser irradiation process during manufacturing, the laser can irradiate from the first opening region R1 to the second opening region R2, and can also irradiate the third opening region R3. That is, the laser can be applied without irradiating between the second opening region R2 and the third opening region R3. In this case, the second-second layer E2-2 can be formed while a portion of the second electrode material layer E2-a remains in the un-irradiated region. At this time, when the second metal layer MCL2 is positioned between the substrate SUB and the second-second layer E2-2, the second metal layer MCL2 blocks heat transfer from the laser to the second-second layer E2-2. The ends of the second-second layer E2-2 can be configured as flat shapes. The first encapsulation inorganic layer EIL1 and the second encapsulation inorganic layer EIL2 positioned on the second-second layer E2-2 can be arranged in a stable form.

[0189] However, when laser is applied without the second metal layer MCL2, the rather thin second layer E2-2 will have its ends curled up by the heat generated by the laser. In this case, cracks will form in the inorganic layers EIL1 and EIL2, and the reliability of the display device 1000 will be reduced due to the infiltration of foreign particles.

[0190] The third metal layer MCL3 can be disposed below the first-third layer EL-3 and the second-first layer E2-1. The third metal layer MCL3 can be disposed between the first inorganic insulating layer IL1 and the first-third layer EL-3. The end of the first-third layer EL-3 can cover the end of the third metal layer MCL3.

[0191] The laser may not irradiate the area between the third opening region R3 and the area where the opening region DTA is formed. In this case, the second-first layer E2-1 can be formed while a portion of the second electrode material layer E2-a remains in the area not irradiated by the laser. At this time, when the third metal layer MCL3 is positioned between the substrate SUB and the second-first layer E2-1, the third metal layer MCL3 blocks heat transfer from the laser to the second-first layer E2-1, and the end of the second-first layer E2-1 can be provided in a flat shape. The first encapsulation inorganic layer EIL1 and the second encapsulation inorganic layer EIL2 positioned on the second-first layer E2-1 can be provided in a stable form.

[0192] However, when laser is irradiated without the third metal layer MCL3, the second-first layer E2-1, positioned adjacent to the third opening region R3, has a relatively thin thickness. Therefore, the ends of the second-first layer E2-1 will curl up when irradiated by the laser light reaching the third opening region R3. In this case, cracks will occur in the inorganic layers EIL1 and EIL2 positioned on the second-first layer E2-1, and the reliability of the display device 1000 will be reduced due to the infiltration of foreign particles.

[0193] on the other hand, Figure 13A A second metal layer MCL2 superimposed on the second dam D2 and a third metal layer MCL3 positioned adjacent to the opening region DTA are shown. However, the embodiment is not limited to this position and may also include a metal layer superimposed on the first dam D1, or one of the second metal layer MCL2 and the third metal layer MCL3 may be omitted. Of course, various combinations of the above embodiments are feasible.

[0194] The area where the second electrode material layer E2-a is retained may have an end that is rolled up by laser irradiation. However, according to the embodiment, the display device 1000 can form layers E2-1 and E2-2 with flat ends by positioning the metal layer in the corresponding area to block heat transfer to the second electrode material layer E2-a. According to the embodiment, various combinations of positions are possible, such that the metal layer is positioned in the area where the second electrode material layer E2-a is retained.

[0195] Reference Figure 13B According to the embodiment, the second metal layer MCL2 can be disposed between the second-first sub-dam D2-a and the second-second sub-dam D2-b. The first metal layer MCL1 is positioned such that one end adjacent to the display area DA can be positioned between the first organic insulating layer IL4 and the second organic insulating layer IL5. The third metal layer MCL3 can be positioned between the first inorganic insulating layer IL1 and the first-third layer EL-3.

[0196] The first metal layer MCL1, the second metal layer MCL2, and the third metal layer MCL3 can be formed after the formation of the first organic insulating layer IL4 and before the formation of the second organic insulating layer IL5. The first metal layer MCL1, the second metal layer MCL2, and the third metal layer MCL3 can comprise the same material as the connecting member CE and can be manufactured in the same process as the connecting member CE. However, the first metal layer MCL1, the second metal layer MCL2, and the third metal layer MCL3 are not limited thereto, and even if they are positioned on the same layer as the connecting member CE, they can be manufactured using processes employing different masks.

[0197] Next, refer to Figure 13C According to the embodiment, the second metal layer MCL2 can be disposed between the second-second sub-dam D2-b and the second-third sub-dam D2-c. The first metal layer MCL1 is positioned at one end in the display area DA between the second organic insulating layer IL5 and the pixel defining layer IL6. The third metal layer MCL3 can be positioned between the first inorganic insulating layer IL1 and the first-third layer EL-3.

[0198] The first metal layer MCL1, the second metal layer MCL2, and the third metal layer MCL3 can be formed after the formation of the second organic insulating layer IL5 and before the formation of the pixel defining layer IL6. The first metal layer MCL1, the second metal layer MCL2, and the third metal layer MCL3 can comprise the same material as the first electrode E1 and can be manufactured in the same process as the first electrode E1. However, they are not limited to this, and even if they are located on the same layer as the first electrode E1, they can be manufactured using processes employing different masks.

[0199] Next, refer to Figure 13D According to the embodiment, the second metal layer MCL2 can be disposed between the second-third sub-dam D2-c and the second-fourth sub-dam D2-d. The first metal layer MCL1 can be positioned at one end in the display area DA between the pixel defining layer IL6 and the spacer IL7. The third metal layer MCL3 can be positioned between the first inorganic insulating layer IL1 and the first-third layer EL-3.

[0200] The first metal layer MCL1, the second metal layer MCL2, and the third metal layer MCL3 can be formed after the pixel defining layer IL6 and before the spacer IL7. The first metal layer MCL1, the second metal layer MCL2, and the third metal layer MCL3 can be fabricated using separate masks.

[0201] Next, refer to Figure 13E According to the embodiment, the second metal layer MCL2 can be disposed on the second-fourth sub-dam D2-d. The first metal layer MCL1 can be positioned at one end in the display area DA on the upper surface of the spacer IL7.

[0202] The first metal layer MCL1, the second metal layer MCL2, and the third metal layer MCL3 can be formed after the spacer IL7 and before the intermediate layer EL. The first metal layer MCL1, the second metal layer MCL2, and the third metal layer MCL3 can be fabricated using separate masks.

[0203] Next, refer to Figure 14 The description of the display panel DP according to an embodiment. Figure 14 This is a cross-sectional view of the display panel according to an embodiment. For ease of explanation of this embodiment, descriptions of components that are the same as or similar to those described above have been omitted.

[0204] According to the embodiment, the first dam D1, the second dam D2, and the third dam D3 can be located in the outer area LA.

[0205] The first dam D1 may include a first-first sub-dam D1-a, a first-second sub-dam D1-b, and a first-third sub-dam D1-c. The first-first sub-dam D1-a may be located on the same layer as the second organic insulating layer IL5 located in the display area DA, and may contain the same material as the second organic insulating layer IL5. The first-first sub-dam D1-a and the second organic insulating layer IL5 located in the display area DA may be formed in the same process. The first-second sub-dam D1-b may be located on the same layer as the pixel defining layer IL6 located in the display area DA, and may contain the same material as the pixel defining layer IL6. The first-second sub-dam D1-b and the pixel defining layer IL6 located in the display area DA may be formed in the same process. The first-third sub-dam D1-c may be located on the same layer as the spacer IL7 located in the display area DA, and may contain the same material as the spacer IL7. The first-third sub-dam D1-c and the spacer IL7 located in the display area DA may be formed in the same process.

[0206] The second dam D2 may include a second-first sub-dam D2-a, a second-second sub-dam D2-b, and a second-third sub-dam D2-c. The second dam D2 may be formed in a three-layer structure similar to the first dam D1.

[0207] The third dam D3 may include a third-first sub-dam D3-a and a third-second sub-dam D3-b. The third-first sub-dam D3-a may be located on the same layer as the pixel defining layer IL6 located in the display area DA, and may contain the same material as the pixel defining layer IL6. The third-first sub-dam D3-a may be formed in the same process as the pixel defining layer IL6 located in the display area DA. The third-second sub-dam D3-b may be located on the same layer as the spacer IL7 located in the display area DA, and may contain the same material as the spacer IL7. The third-second sub-dam D3-b may be formed in the same process as the spacer IL7 located in the display area DA.

[0208] This specification shows a first dam D1, a second dam D2, and a third dam D3 located in the peripheral area LA; however, the shape and number of dams can be modified differently depending on the embodiment. For example, the second dam D2 can be omitted, and the first dam D1 and the third dam D3 can be included, or two or more third dams D3 can be included.

[0209] Within the peripheral region LA, the first-first layer EL-1, the first-second layer EL-2, the first-third layer EL-3, and the first-fourth layer EL-4 can be located. The peripheral region LA may also include a first opening region R1 between the intermediate layer EL and the first-first layer EL-1, a second opening region R2 between the first-first layer EL-1 and the first-second layer EL-2, a third opening region R3 between the first-second layer EL-2 and the first-third layer EL-3, a fourth opening region R4 between the first-third layer EL-3 and the first-fourth layer EL-4, and a fifth opening region R5 between the first-fourth layer EL-4 and the opening region DTA. Because the intermediate material layer EL-a has a discontinuous shape in the first to fifth opening regions R1, R2, R3, R4, and R5, it can block the path through which foreign particles can flow in.

[0210] The opening region DTA may have an inner surface formed by the ends of the substrate SUB, the buffer layer BL, the first inorganic insulating layer IL1, the first encapsulation inorganic layer EIL1, and the second encapsulation inorganic layer EIL2. It goes without saying that combinations of the various embodiments described in this specification are feasible.

[0211] While certain embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but is limited to the broader scope of the appended claims and the various obvious modifications and equivalent arrangements that will be apparent to those skilled in the art.

Claims

1. A display device, the display device comprising: The substrate includes an opening region, a peripheral region surrounding the opening region, and a display region surrounding the peripheral region; A transistor, stacked with the display area and disposed on the substrate; The first electrode is electrically connected to the transistor; An intermediate layer and a second electrode are disposed on the first electrode and extend into the peripheral region; as well as A first metal layer is stacked with the intermediate layer and the second electrode in the peripheral region. In this configuration, one end of the first metal layer and one end of the second electrode are aligned. One end of the intermediate layer protrudes beyond the end of the first metal layer, and The intermediate layer directly covers the end of the first metal layer.

2. The display device according to claim 1, wherein, The display device further includes an encapsulation layer disposed on the second electrode, and The encapsulation layer includes: a first encapsulation inorganic layer disposed on the second electrode; an encapsulation organic layer disposed on the first encapsulation inorganic layer; and a second encapsulation inorganic layer disposed on the encapsulation organic layer, wherein... The end of the second electrode is stacked with the encapsulated organic layer.

3. The display device according to claim 1, wherein, The display device also includes two or more dams disposed in the peripheral area. The two or more dams include a first dam and a second dam that are separate from each other, and The display device includes: a first layer superimposed on the first dam; and a first second layer superimposed on the second dam.

4. The display device according to claim 1, wherein, The display device includes: an inorganic insulating layer disposed on the substrate; an organic insulating layer disposed on the inorganic insulating layer; and a pixel defining layer and a spacer disposed on the organic insulating layer.

5. The display device according to claim 4, wherein, The first metal layer is disposed between the inorganic insulating layer and the organic insulating layer.

6. The display device according to claim 4, wherein, The display device includes multiple organic insulating layers, and The first metal layer is positioned between two adjacent organic insulating layers among the plurality of organic insulating layers.

7. The display device according to claim 4, wherein, The first metal layer is disposed between the organic insulating layer and the pixel defining layer.

8. The display device according to claim 4, wherein, The first metal layer is disposed between the pixel defining layer and the spacer.

9. The display device according to claim 3, wherein, The intermediate layer includes a functional layer. The functional layer includes at least one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. The first layer and at least one of the hole injection layer, the hole transport layer, the electron transport layer and the electron injection layer comprise the same material.

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